CN1333344C

CN1333344C - Method for reducing software load of system-on-chip (SoC)

Info

Publication number: CN1333344C
Application number: CNB2005100288880A
Authority: CN
Inventors: 朱建清; 郑世宝; 顾亮; 王峰; 张文军
Original assignee: Shanghai Jiao Tong University
Current assignee: Shanghai Jiao Tong University
Priority date: 2005-08-18
Filing date: 2005-08-18
Publication date: 2007-08-22
Anticipated expiration: 2025-08-18
Also published as: CN1731358A

Abstract

The present invention relates to a method for reducing software load of a system on a chip, which adopts linked list principle. Software organizes a plurality of operating instructions into a linked list in charge, and controls the start and the reset of hardware; each node of the linked list is automatically read in the hardware after the hardware is started to complete operations of pertinent data; an interruption signal is sent after the whole linked list of the instructions is enforced and completed; all parameters of instruction words are combined into one order node; each node is correspondent to one operation; the last NIP is a pointer to point a next node; the initial memory address of the next node is stored; the present invention contracts that if a cell value is 0, the cell value indicates the node is the last node of the linked list; one linked list of the instructions is composed of a plurality of nodes. The present invention packs a plurality of operations into the linked list of the instructions, and the operations of the linked list are enforced automatically by the hardware. The multiple operations are corresponding to only one interruption. The present invention fundamentally solves the problem that the load of the software is weighted because the number of the times of the interruption is too more. Meanwhile, the implementation method is simple, and the universality is high.

Description

Alleviate the method for SOC (system on a chip) software load

Technical field

What the present invention relates to is a kind of method of field of computer technology, specifically a kind of method that alleviates the SOC (system on a chip) software load.

Background technology

A SOC (system on a chip) (SoC) is made up of system framework (comprising CPU, bus, storage unit etc.) and a plurality of I/O (I/O) functional module usually.Wherein, CPU is responsible for the control of each I/O functional module (for example audio-frequency module, video decode module, video processing module, graphics system module etc.), and this control is generally finished by the register that disposes each I/O functional module.These registers are usually located in the master control interface module (HostIF), with the system storage unified addressing, generally comprise control register, order register and parameter register.Control register is finished resetting of I/O functional module and start-up control.The operation that order register indication I/O functional module need be finished.Parameter register provides the work of I/O functional module required parameter.Real-time is that most of SoC are desired, for making CPU each I/O functional module is in time responded, and can take several different methods to control.

Find through literature search prior art, " computer organization and structure one performance design (the 5th edition) " (2001.8 Higher Education Publishing House) the 182nd page to the 209th page introduction that William Stallings is shown mainly contains three kinds of I/O control methods: programmed control I/O, drives interrupts I/O, direct memory visit (DMA).These three kinds of loads that method has alleviated CPU successively.Wherein back two kinds of methods all need to adopt interrupts controlling.But the ability of CPU is quite limited among the SoC usually, and excessively frequent interruption can make the expense of CPU strengthen, and efficient reduces, and has a strong impact on system performance, even system can't normally be moved.The 207th page to the 209 pages notions that propose I/O passage (I/O channel) of this book, the load that can further alleviate CPU on this technical know-how.But concrete I/O passage implementation method is also not mentioned in the book.

Summary of the invention

The present invention is directed to deficiency of the prior art, a kind of method that alleviates the SOC (system on a chip) software load is provided, make it that a plurality of operational orders are organized into instruction link-list, after whole instruction link-list is finished, send a look-at-me, like this, originally need repeatedly to interrupt only need interrupt for 1 time now.Can obviously reduce the CPU interruption times for the module that needs continuous several times to operate, thereby alleviate cpu load.

The present invention is achieved by the following technical solutions, the present invention adopts the chained list principle, a plurality of operational orders are organized into instruction link-list, software and hardware is carried out collaborative design, and software is responsible for instruction is organized into chained list, and the startup of control hardware and resetting, automatically read in each node of chained list after hardware-initiated, finish the operation of corresponding data, after whole instruction link-list is finished, send a look-at-me.

Described a plurality of operational orders are organized into instruction link-list, are meant: the parameter that instruction word and instruction are carried is formed an instruction node, the corresponding operation of node.Last tail node pointer NIP is meant the pointer to next node, deposits the initial memory address of next node, and if agreement this element value be 0 the expression this node be last node of chained list.A plurality of nodes are formed an instruction link-list.

The startup of described software control hardware and resetting, be meant: control register and head pointer register HIP are set in HostIF, and control register is used to control the startup of I/O functional module and reset, and HIP is used to deposit the pointer of the head node of chained list.

The hardware of described I/O functional module mainly is made up of three parts: get finger unit, performance element and control module, get the finger unit and be responsible for taking out instruction node from system storage, be stored in the register in the sheet.Performance element is carried out corresponding operation according to the content of taking out node.The action that refers to unit and performance element is got in control module control.

Get finger and execution sequence and carry out, promptly take out a node, carry out, get next node again, carry out again, be finished up to all nodes.One group of register need be set in sheet, be used to deposit the node content of taking-up.Control module is realized with state machine.This state machine has three states: idle, get and refer to and carry out.Be in idle condition after system powers on, after state machine is received enabling signal, forward to and get the finger-like attitude, otherwise keep idle condition; Getting under the finger-like attitude, getting and enter executing state after finger finishes, otherwise keep getting the finger-like attitude; Under executing state, present node instruction executes the value that NIP is checked in the back, if NIP non-0 then enter again and get the finger-like attitude, otherwise would enter idle condition; After reset signal under any state is effective, all enter idle condition.Getting under the finger-like attitude, getting the finger circuit working, from system storage, take out the content of a node, and assignment is being given relevant register.Under executing state, executive circuit carries out corresponding operating according to the value of the register that upgraded just now.Under idle condition, all circuit are in reset mode.

After described I/O functional module started, at first according to the value of HIP, the data of taking out first node from system storage were carried out first operation.After operation is finished, according to the value of NIP is taken out next node from system storage data, carrying out next one operation, is 0 up to NIP.Whole instruction link-list sends look-at-me after all executing.CPU carries out Interrupt Process after receiving look-at-me, send next operational order chained list.

Described each node that reads in chained list after hardware-initiated is automatically finished the operation of corresponding data, is specially: get the finger counter getting to refer to be provided with in the unit, get and refer to that the unit whenever reads into data and get and refer to that counter adds one automatically, and when executing state, counter O reset.So get the position of the corresponding current data of value in node that refers to counter, can guide data enter corresponding registers, and when the value of counter equals the length of node, show that present node gets finger and finish, can instruct the control state machine redirect.Performance element executes instruction under the control of control state machine, sends " being finished " signal to control state machine when being finished.Because therefore data and the shared chip external memory of instruction need a selector switch in the system, select corresponding signal to deliver to memory controller (MC) under the control of state machine.

The present invention has outstanding substantive distinguishing features and marked improvement, the present invention is packaged into instruction link-list with a plurality of operations, by all operations in the hardware automatic execution instruction chained list, corresponding a plurality of operations have only an interruption, greatly reduced interruption times, thereby alleviated the load of CPU, significant for the real-time that guarantees SoC.In addition, because a large amount of register is moved out of HostIF, organize in the mode of chained list node, and chained list is to be generated by software that be placed among the outer RAM of sheet, whole like this SoC chip area can reduce, the sheet intraconnections also can reduce.The present invention has fundamentally solved interruption times and has too much caused the problem that software load increases the weight of, and it is simple to have implementation method, the characteristics of highly versatile.

Description of drawings

Fig. 1 list structure figure of the present invention

Fig. 2 hardware block diagram of the present invention

Fig. 3 state of a control transition diagram of the present invention

Embodiment

The present invention is further illustrated below in conjunction with accompanying drawing:

The present invention is finished jointly by software and hardware.Software is responsible for instruction is organized into chained list, and the startup of control hardware and resetting.

As shown in Figure 1, instruction link-list is organized as follows: an instruction node is made up of instruction word, all parameters and NIP (being used to deposit the initial memory address of next node), their depositing continuously in internal memory, the address of presumptive instruction word is X, total N parameter, then their address is followed successively by X, X+1, X+2 ... X+N+1.Last NIP is meant the pointer to next node, and if agreement this element value be 0 the expression this node be last node of chained list.The corresponding operation of node, a plurality of nodes are formed an instruction link-list, and the NIP value of last node of chained list is made as 0.

Register HIP and control register are set in HostIF, deposit the pointer of the head node of chained list with HIP, i.e. the address of first node instruction word, control register is provided with start bit and resets, and is used to control the startup of I/O functional module and reset.The step that CPU carries out is as follows:

1) preparation instruction chained list is sent in the system storage;

2) set HIP;

3) under the ready situation of I/O functional module, control register is set, starts the I/O functional module.

Automatically read in each node of chained list after hardware-initiated, finish the operation of corresponding data, after whole instruction link-list is finished, send a look-at-me.

As shown in Figure 2, hardware components of the present invention is got and is referred to unit, performance element, control module, order register group and selector switch.Get the finger unit and be responsible for from system storage, taking out instruction node, be stored in the order register group in the sheet.Performance element is carried out corresponding operation according to the content of order register group.Thereby order register consists of the bridge of getting finger unit and performance element.All work under the control of control module in all unit.This control module is realized by control state machine.

As shown in Figure 3, control state machine has three states: idle, get and refer to and carry out.Be in idle condition after system powers on, after module is received enabling signal, forward to and get the finger-like attitude, otherwise keep idle condition; Getting under the finger-like attitude, getting and enter executing state after finger finishes, otherwise keep getting the finger-like attitude; Under executing state, present node instruction executes the value that NIP is checked in the back, if NIP non-0 then enter again and get the finger-like attitude, otherwise would enter idle condition; After reset signal under any state is effective, all enter idle condition.

Enter after module starts and get the finger-like attitude, get the finger unit and send read request to memory controller (MC), the address of request is HIP, reads the size that number is a chained list node.After the MC response request, send data to and get the finger unit, by the arrival of data useful signal designation data.Get the finger counter getting to refer to be provided with in the unit, get and refer to that the unit whenever reads into data (being that the data useful signal is for high) and get and refer to that counter adds one automatically.According to getting the value that refers to counter, deliver in the order register group in the relevant register reading into data.When getting the value that refers to counter when equaling chained list node big or small, show to get to refer to finish, enter executing state, get the finger counter O reset, performance element is carried out corresponding operating according to the value of order register group, sends the signal that is finished after operation is finished.Check the value of NIP in the order register group simultaneously, if non-0, show to also have instruction to carry out, the value of NIP is composed to getting the finger unit, as the address of getting finger next time, enter and get the finger-like attitude, get next instruction node,, show that whole instruction link-list is finished if NIP is 0, send look-at-me, enter idle condition.Because therefore data and the shared chip external memory of instruction need a selector switch in the system, selector switch is controlled by state machine, is getting under the finger-like attitude, send MC with getting the signal that refers to the unit, under executing state, send MC with the signal of performance element.

The present invention is packaged into instruction link-list with a plurality of operations, by all operations in the hardware automatic execution instruction chained list, corresponding a plurality of operations have only an interruption, have fundamentally solved interruption times and have too much caused the problem that software load increases the weight of, method realizes simple, highly versatile.

Claims

1. A method for alleviating the software load of an on-chip system, characterized in that, the linked list principle is adopted, and the software is responsible for organizing a plurality of operation instructions into a linked list, and controls the startup and reset of the hardware, and automatically reads each node of the linked list after the hardware starts , to complete the operation of the corresponding data, and send an interrupt signal after the entire instruction linked list is executed.

2. The method for alleviating the load of the system-on-chip software according to claim 1, characterized in that said organizing a plurality of operation instructions into a linked list refers to: forming an instruction node with instruction words and parameters carried by the instruction, a A node corresponds to an operation, and the last item tail node pointer refers to the pointer to the next node, which stores the starting memory address of the next node, and agrees that if the value of this unit is 0, it means that the node is the last node of the linked list, and multiple nodes Form a linked list of instructions.

3. The method for alleviating the software load of the system-on-chip according to claim 1, wherein the software controls the start and reset of the hardware, and refers to: setting the control register and the head pointer register in the main control interface, and the control register It is used to control the start and reset of the I/O function module, and the head pointer register is used to store the pointer of the head node of the linked list.

4. The method for alleviating the software load of a system on chip according to claim 1 or 3, wherein the software controls the startup and reset of the hardware, and the CPU executes the steps as follows:

1) Prepare the command chain list and send it into the system memory;

2) Set the head pointer;

3) When the I/O function module is ready, set the control register and start the I/O function module.

5. The method for alleviating the software load of an on-chip system according to claim 3, wherein the hardware of the I/O function module is mainly composed of three parts: an instruction fetch unit, an execution unit and a control unit, and the instruction fetch The unit is responsible for fetching instruction nodes from the system memory and storing them in on-chip registers; the execution unit performs corresponding operations according to the contents of the fetched nodes; the control unit controls the actions of the instruction fetch unit and the execution unit.

6. The method for alleviating the software load of an on-chip system according to claim 5, wherein the control unit is implemented with a state machine, and the state machine has three states: idle, instruction fetch, and execution. After the system is powered on, In the idle state, when the state machine receives the start signal, it turns to the instruction fetching state, otherwise it remains in the idle state; in the fetching state, it enters the execution state after the fetching is completed, otherwise it remains in the fetching state; in the execution state, the current node After the instruction is executed, check the value of the tail node pointer. If the tail node pointer is not 0, it will enter the fetch state, otherwise it will enter the idle state; in any state, after the reset signal is valid, it will enter the idle state.

7. The method for alleviating the software load of a system-on-chip according to claim 6, wherein the state machine, in the fetching state, the fetching circuit works, fetches the content of a node from the system memory, and assigns a value To the corresponding register; in the execution state, the execution circuit performs corresponding operations according to the value of the register just updated; in the idle state, all circuits are in the reset state.

8. The method according to claim 3 or 5 for alleviating the software load of an on-chip system is characterized in that, after the described I/O function module is started, the first one is taken out from the system memory according to the value of the head pointer register. The data of the node, perform the first operation, after the operation is completed, take out the data of the next node from the system memory according to the value of the tail node pointer, and perform the next operation until the tail node pointer is 0, after the entire instruction linked list is executed , send an interrupt signal, after the CPU receives the interrupt signal, it will perform interrupt processing and send the next operation command linked list.

9. The method for alleviating the software load of an on-chip system according to claim 1, characterized in that, after the hardware is started, each node of the linked list is automatically read into, and the operation of corresponding data is completed, specifically: in the fetching unit Set the instruction fetch counter, the instruction fetch unit automatically increments the instruction fetch counter by one every time a data is read in, and the counter is cleared to zero in the execution state, so the value of the instruction fetch counter corresponds to the position of the current data in the node, which can guide the data into the corresponding register , and when the value of the counter is equal to the length of the node, it indicates that the current node fetches instructions and guides the control state machine to jump; the execution unit executes the instruction under the control of the control state machine, and sends "execution completed" to the control state machine "Signal, because the data and instructions in the system share an off-chip memory, so a selector is needed to select the corresponding signal and send it to the memory controller under the control of the state machine.