CN1322577C

CN1322577C - A method to avoid gaps in the upper electrode layer caused by stress in 1T SRAM processing

Info

Publication number: CN1322577C
Application number: CNB031548563A
Authority: CN
Inventors: 涂国基
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2003-08-15
Filing date: 2003-08-15
Publication date: 2007-06-20
Anticipated expiration: 2023-08-15
Also published as: CN1581469A

Abstract

The invention discloses a method for avoiding the generation of stress induced gap of an upper electrode layer in the processing of a single transistor static read-only memory (1T SRAM) capacitor, which is mainly characterized in that an inner dielectric layer for balancing stress is added between the upper electrode layer of the capacitor and an anti-reflection layer thereof. In addition, the isolation effect between the gate and the upper electrode layer and between the gate and the upper electrode layer are also improved, thereby reducing the formation of gaps.

Description

Avoid the method that the upper electrode layer stress causes the slit to produce in the 1T SRAM processing

Technical field

The invention relates to a kind of in the processing of the static read-only access memory of one-transistor (1T SRAM), avoid the method that produces because of the stress induced slit (void) of upper electrode layer, particularly about between the upper electrode layer of electric capacity and its anti-reflecting layer, adding the method that an inner-dielectric-ayer avoids this slit to produce.

Background technology

The basic module configuration of traditional static RAM (SRAM) is made up of six transistors, and normally the metal oxide semiconductor field effect of four N passages (N-channel) answers transistor (MOSFET) to add the MOSFET of two P passages.In order to cut down finished cost, the semiconductor product industry tries to make littler chip, and the density with original chip is identical at least, even bigger.As long as can on a certain size base material, cut out more chip, just the cost of each one chip can reduce.Yet, in the SRAM manufacturing technology, six transistors are positioned on the less semiconductor chip, be some difficult thing.Therefore, the manufacturing technology of SRAM just is absorbed at a transistor, and promptly on the structure cell of 1T SRAM (one-transistor static read-only access memory), it comprises that a metal oxide semiconductor field effect answers a transistor (MOSFET) and a capacitance structure.The one-transistor like this and the feature of capacitance structure but provide and six effects that transistorized SRAM is identical, the road of the littler semiconductor chip of design of also marching toward gradually.

Because process integration is improving always, semiconductor is already made the trend of integrated circuit at present, be and on an one chip, integrate memory array and high speed logic circuit, form an embedded access memory (for example embedded dynamic random access memory, embedded 1T SRAM).Embedded memory array and the logical circuit of having comprised simultaneously can reduce circuit area widely and increase processing speed.For 1T SRAM processing, electric capacity processing must be finished before logic processing beginning, and therebetween in order to dwindle born of the same parents' size, gate will inevitably cover whole capacitor.So less than the processing of 0.13 μ m (micrometre) be have challenging.Because electric capacity processing just need be finished before logic processing beginning, so electric capacity will have a series of high temperature process, for example ion of the growth of gate pole oxidation layer, source/drain implantation.Because these continuous high temperature process, the unequal power distribution between upper electrode layer and the anti-reflecting layer can cause forming slit (void) between upper electrode layer and anti-reflecting layer.Also owing to the generation in these slits, gate can contact with upper electrode layer by the slit when growing up, and causes the short circuit between gate and the upper electrode layer.

Summary of the invention

Because in above-mentioned background technology, the imbalance of the upper electrode layer of electric capacity and its anti-reflecting layer intermediate stress can produce the slit; Simultaneously, this slit also can cause the short circuit between gate and the upper electrode layer.

Therefore, the object of the present invention is to provide the manufacture method of the static read-only access memory capacitor of a kind of one-transistor, can avoid unbalanced stress between upper electrode layer and the anti-reflecting layer.

Another object of the present invention is to provide the manufacture method of the static read-only access memory capacitor of a kind of one-transistor, can avoid in follow-up high temperature process, producing the slit.

A further object of the present invention is to provide the manufacture method of the static read-only access memory capacitor of a kind of one-transistor, can avoid gate to contact with upper electrode layer by the slit when growing up and cause short circuit between gate and the upper electrode layer.

According to the above object, implementation method step of the present invention is as follows: form shallow slot isolation structure on semiconductor substrate, form a pad oxide and one first cover curtain layer thereon in regular turn.On active region and shallow slot isolation structure, form a patterning photoresist layer, expose predetermined electric capacity and make the zone.Etching downwards removes the part shallow slot isolation structure to mold several openings, then, removes photoresist layer, conformally deposits one first conductor layer.Remove first conductor layer on first cover curtain layer in regular turn, remove first cover curtain layer on the pad oxide, the conductor layer of winning can be covered within this shallow slot isolation structure.

Then on this active region and shallow slot isolation structure, form one first dielectric layer, one second conductor layer, one second dielectric layer and an anti-reflecting layer in regular turn.Non-then grade is to etching part anti-reflecting layer, second dielectric layer, second conductor layer and first dielectric layer, and molds a capacitance structure with pad oxide for stopping layer.Then on this pad oxide, form a clearance wall, on active region, form a gate pole oxidation layer then, form gate structure at last and be across on this capacitance structure, this active region and the shallow slot isolation structure.

The invention has the advantages that, by in electric capacity, adding one second dielectric layer, balance the stress between second conductor layer and the anti-reflecting layer, thereby avoided the generation in slit in follow-up high temperature process.In addition, because the balance of stress has been avoided the generation in slit in the follow-up high temperature process, cause short circuit between gate and the upper electrode layer thereby effectively avoid gate when growing up, to contact with upper electrode layer by the slit.

Brief Description Of Drawings

For cooperating the elaboration of preferred embodiment of the present invention, in the literary composition conjunction with figs. is elaborated, wherein: Fig. 1 to Fig. 6 is the generalized section during according to each step of processing of preferred embodiment of the present invention.

Embodiment

For the present invention and above-mentioned purpose, feature and advantage more can be become apparent, only with a better embodiment and after the results are shown in, and the conjunction with figs. label is described in detail:

Please refer to Fig. 1, on semiconductor base material 100, form a shallow slot isolation structure 102 (STI), and form an active region 104 (Active Area).Then, this active region 104 is carried out implanting ions, to form the doped well zone (not shown).

Please refer to Fig. 2, on base material, deposit the pad oxide 18 (Pad Oxide) and first cover curtain layer 20 in regular turn.Wherein, the material of this first cover curtain layer 20 can be a silicon nitride, and it utilizes electricity slurry reinforced-chemical vapour deposition (CVD) (PE-CVD) method or low pressure-chemical vapour deposition (CVD) (LP-CVD) method to form.Then be coated with a photoresist layer (not shown) and cover active region and shallow slot isolation structure top, patterning photoresist layer (not shown) exposes part shallow slot isolation structure 102 and active region 104, with first cover curtain layer 20 on the active region is the cover curtain, form several openings with an etching and processing in shallow slot isolation structure 102, these openings are the structures as capacitor openings.

Please refer to Fig. 3, remove the photoresist layer (not shown).Then on those openings and first cover curtain layer 20, conformally deposit one first conductor layer 22.The material of this first conductor layer can be polysilicon (Poly-silicon) or other conductive metal layer.

Please refer to Fig. 4, utilize cmp or the method for eat-backing to remove first conductive layer 22 partly, and first cover curtain layer 20 is as stopping layer (a stop layer).Then utilize hot phosphoric acid (hot H ₃PO ₄) remove first cover curtain layer 20.

Please refer to Fig. 5, conformally deposit first dielectric layer 24, second conductor layer 26, second dielectric layer 28 and anti-reflecting layer 30 in regular turn.Wherein, the material of first dielectric layer 24 is double-deckers of a silicon nitride and silica.The material of second conductor layer 26 can be polysilicon or other conductive metal layer.Second dielectric layer 28 can be oxide or nitride.The material of anti-reflecting layer 30 can be the silicon oxynitride (SiON) of tool extension power, and it is to utilize the mode of low pressure-chemical vapour deposition (CVD) (LP-CVD) to form.

Please refer to Fig. 6, non-grade is to etching part first dielectric layer 24, second conductor layer 26, second dielectric layer 28 and anti-reflecting layer 30, and with pad oxide 18 for stopping layer so that on STI, mold a capacitance structure 44.Then deposited silicon nitride layer conformally on this electric capacity, silicon oxide layer deposited on this silicon nitride layer more afterwards.Etching removes this silicon nitride layer then, forms silica clearance wall 40 next-door neighbour's silicon nitride layers.Etching removes silicon nitride layer then, and on pad oxide 18, the both sides of electric capacity form silicon nitride gap wall 42, it is the L type substantially.Therefore formed the compound clearance wall of a kind of silicon nitride and silica.Then on active region 104, form gate pole oxidation layer 46, form gate online 56 at last and get final product.

Be noted that wherein in the preferred embodiment of the present invention that first conductor layer 22 is the lower electrode layer of capacitance structure 44, and this lower electrode layer is arranged in sti structure.And second conductor layer 26 is the upper electrode layer of capacitance structure 44.

Be noted that preferred embodiment of the present invention especially, it is characterized in that it adds second dielectric layer 28 in electric capacity, but balance second conductor layer 26, stress between the upper electrode layer just, and anti-reflecting layer 30 is to avoid the generation of slit in the follow-up high temperature process (void).In addition, because the balance of stress has been avoided the generation in slit in the follow-up high temperature process, cause short circuit between gate and the upper electrode layer thereby effectively avoided gate when growing up, to contact with upper electrode layer by the slit.

Just as one of ordinary skill in understanding, the present invention discloses as above by preferred embodiment, but above-mentioned preferred embodiment and non-limiting protection scope of the present invention; Allly do not break away from design modifications or improvements of the present invention, all should be included within the protection range that claim of the present invention limits.

Claims

1. A method for avoiding the generation of gaps in capacitors in the processing of single-transistor static read-only access memory, which at least includes the following steps:

forming a shallow trench isolation structure on a substrate;

performing a forming step to form a plurality of openings in the shallow trench isolation structure;

conformally depositing a first conductor layer;

removing part of the first conductor layer;

depositing a conformal first dielectric layer;

forming a conformal second conductor layer over the first dielectric layer;

forming a second dielectric layer over the second conductor layer;

forming an anti-reflection layer over the second dielectric layer; and

A final step is performed to form the complete capacitor structure.

2. The method according to claim 1, characterized in that the forming step comprises at least the following steps:

forming a pad oxide layer on the substrate;

depositing a first mask layer over the pad oxide layer; and

A lithographic etching step is performed.

3. The method of claim 2, wherein the first mask layer is a silicon nitride layer formed by plasma enhanced chemical vapor deposition or low pressure chemical vapor deposition.

4. The method of claim 1, wherein the material of the first conductive layer comprises polysilicon.

5. The method of claim 1, wherein the first conductive layer is removed by chemical mechanical polishing or etch back.

6. The method of claim 1, wherein the material of the first dielectric layer comprises a double layer structure of silicon nitride and silicon oxide.

7. The method of claim 1, wherein the material of the second conductive layer comprises polysilicon.

8. The method of claim 1, wherein the second dielectric layer comprises oxide or nitride.

9. The method of claim 1, wherein the final step comprises at least the following steps:

performing a forming step to remove part of the anti-reflection layer, the second dielectric layer, the second conductor layer and the first dielectric layer, so as to form a capacitor on the shallow trench isolation structure; and

A spacer is formed on both sidewalls of the capacitor and the pad oxide layer.

10. The method of claim 9, wherein the anti-reflection layer is silicon oxynitride formed by low pressure chemical vapor deposition.

11. The method of claim 9, wherein the spacer is composed of silicon nitride and silicon oxide.

12. A capacitor structure, the structure at least comprising:

One electrode;

a first dielectric layer over the lower electrode;

an upper electrode located on the first dielectric layer;

a second dielectric layer over the top electrode; and

an anti-reflection layer on the second dielectric layer,

Wherein, the second dielectric layer is used to alleviate the stress difference between the upper electrode and the anti-reflection layer to avoid voids between the upper electrode and the anti-reflection layer during subsequent thermal processing.

13. The capacitor structure of claim 12, wherein the bottom electrode material is located in a shallow trench isolation structure.

14. The capacitor structure as claimed in claim 12, wherein the material of the bottom electrode comprises polysilicon.

15. The capacitor structure as claimed in claim 12, wherein the first dielectric layer material comprises a double layer structure of silicon nitride and silicon oxide.

16. The capacitor structure as claimed in claim 12, wherein the material of the upper electrode comprises polysilicon.

17. The capacitor structure as claimed in claim 12, wherein the material of the second dielectric layer comprises oxide or nitride.

18. The capacitor structure as claimed in claim 12, wherein the material of the anti-reflection layer comprises silicon oxynitride.