CN1314131C - Schottky barrier diode and manufacturing method thereof - Google Patents

Abstract

A Schottky barrier diode and its manufacturing method. At present, due to mesa etching or thick polyimide layer, etc., there is no progress in chip miniaturization and the distance between electrodes cannot improve characteristics. Moreover, etching control of the Schottky junction portion is difficult in the manufacturing method. The invention can realize the planar Schottky barrier diode of the compound semiconductor. By providing an InGaP layer and an n ⁺ -type ion implantation region on the surface of the substrate, it is no longer necessary to provide a mesa and a polyimide layer. Since the distance between electrodes can be shortened, chip size can be reduced and high-frequency characteristics can be improved. In addition, GaAs is not etched when forming the Schottky electrode, so a Schottky barrier diode with good reproducibility can be manufactured.

Description

Schottky barrier diode and manufacturing method thereof

technical field

The present invention relates to a Schottky barrier diode of a compound semiconductor used in a high-frequency circuit and a manufacturing method thereof, and more particularly to a Schottky barrier diode of a compound semiconductor and a manufacturing method thereof, in which an operating region and a chip size are miniaturized by adopting a planar structure method.

Background technique

With the expansion of the global mobile phone market and the high demand for digital satellite broadcasting receivers, the demand for high-frequency devices is increasing rapidly. As its components, field-effect transistors using gallium arsenide (GaAs) are considered to be multi-purpose for handling high frequencies, and accordingly, monolithic microwave integrated circuits (MMICs) and local oscillators that integrate the switching circuits themselves are being developed. FET.

In addition, GaAs Schottky barrier diodes are also in high demand for base stations.

FIG. 9 shows a cross-sectional view of an operating region of a conventional Schottky barrier diode.

An n ⁺ -type epitaxial layer 22 (5×10 ¹⁸ cm ^-3 ) of about 6 μm is stacked on an n ⁺ -type GaAs substrate 21 , and an n-type epitaxial layer 23 (1.3×10 ¹⁷ cm ^-3 ) to be an operating layer is deposited, for example, 3500 A or so.

The first metal layer to be the ohmic electrode 28 is AuGe/Ni/Au ohmic-bonded on the n ⁺ -type epitaxial layer 22 . The second metal layer is Ti/Pt/Au, and the pattern of the second metal layer has two kinds of anode side and cathode side. A Schottky junction is formed with the n-type epitaxial layer 23 on the anode side. Hereinafter, the second metal layer on the anode side having this Schottky junction region 31a is referred to as Schottky electrode 31 . The Schottky electrode 31 also becomes the substrate electrode of the third Au plating layer forming the anode pad, and the patterns of both sides completely overlap. The second metal layer on the cathode side is in contact with the ohmic electrode and becomes the base electrode of the third layer of Au plating that forms the cathode pad. Like the anode side, the patterns on both sides completely overlap. Since the Schottky electrode 31 has to be arranged at the pattern end position on the polyimide layer, the pattern is overlapped by 16 μm toward the cathode side around the Schottky junction region 31 a. The substrate other than the Schottky junction is at the cathode potential, and the portion where the anode electrode 34 intersects with the GaAs at the cathode potential is provided with the polyimide layer 30 for insulation. The cross section has an area of about 1300 μm ² , and since the parasitic capacitance is large, it is necessary to make the distance between them a thickness of about 6 to 7 μm to alleviate the parasitic capacitance. Polyimide is used as an interlayer insulating layer because of its low dielectric constant and the property that it can be formed thicker.

The Schottky junction region 31a is provided on the n-type epitaxial layer 23 with a thickness of about 1.3×10 ¹⁷ cm ⁻³ in order to ensure a withstand voltage of about 10 V and good Schottky characteristics. On the other hand, the ohmic electrode 28 is provided on the surface of the n ⁺ -type epitaxial layer 22 exposed by mesa etching to reduce resistance. The lower layer of the n ⁺ -type epitaxial layer 22 is a high-concentration GaAs substrate 21, and an ohmic electrode 28, that is, AuGe/Ni/Au, is provided as a back electrode, and it is also applicable to models that are taken out from the back of the substrate.

FIG. 10 is a plan view showing a Schottky barrier diode of a conventional compound semiconductor.

In the approximate center of the chip, a Schottky junction region 31 a is formed on the n-type epitaxial layer 23 . This region is a circle with a diameter of about 10 μm, and the second metal layer Ti/Pt/Au is sequentially vapor-deposited on the Schottky contact hole 29 exposing the n-type epitaxial layer 23 . A first metal layer ohmic electrode 28 is provided to surround the outer periphery of the circular Schottky junction region 31a. The ohmic electrode 28 is obtained by vapor-depositing AuGe/Ni/Au in sequence, and is arranged on nearly half of the chip area. In addition, in order to take out the electrodes, the second metal layer is in contact with the ohmic electrode 28 to become a substrate electrode.

The substrate electrodes on the anode side and the cathode side are provided for the third layer of Au plating. The anode side is provided in the minimum area necessary for partial bonding to the Schottky junction region 31a, and the cathode side is laid out in a shape surrounding the outer periphery of the circular Schottky junction region 31a. In addition, in order to reduce the induction component of high-frequency characteristic elements, it is necessary to fix many bonding wires, so the area occupying about half of the chip is used as the bonding area.

Furthermore, an Au plating layer is provided to overlap the substrate electrode. Here, the bonding wire is fixed by stitch bonding, and the electrode is taken out. The anode pad portion is 40×60 μm ² , and the cathode pad portion is 240×70 μm ² . The connection by stitch bonding can connect two bonding wires at a time, so even if the bonding area is small, the induction component of high-frequency characteristic parameters can be reduced, which contributes to the improvement of high-frequency characteristics.

11 to 15 show a conventional Schottky barrier diode manufacturing method.

In FIG. 11 , the n ⁺ type epitaxial layer 22 is exposed by mesa transistor etching method, and the first metal layer is attached to form an ohmic electrode 28 .

That is, an n ⁺ type epitaxial layer 22 (5×10 ¹⁸ cm ^-3 ) of about 6 μm is deposited on an n ⁺ GaAs substrate 21, and an n type epitaxial layer 23 (1.3×10 ¹⁷ cm ^-3 ) of about 3500 Ȧ is deposited on it . Then, the entire surface is covered with an oxide film 25, and the resist layer on the predetermined ohmic electrode 28 is subjected to a photolithography process for selectively opening a window. Then use the resist layer as a mask to etch the oxide film 25 of the predetermined ohmic electrode 28 portion, and perform mesa etching of the n-type epitaxial layer 23 to expose the n ⁺ -type epitaxial layer 22 .

Then, the first metal layer, that is, three layers of AuGe/Ni/Au are sequentially vacuum evaporated and laminated. The resist layer is then removed, leaving the metal layer at the intended portion of the ohmic electrode 28 . Next, an ohmic electrode 28 is formed on the n ⁺ -type epitaxial layer 22 by alloying heat treatment.

FIG. 12 forms a Schottky contact hole 29 . A new resist layer is formed on the entire surface, and a photolithography process for selectively opening a window is performed on a predetermined portion of the Schottky junction region 31a. After the exposed oxide film 25 is etched, the resist layer is removed to form a Schottky contact hole 29 exposing the n-type epitaxial layer 23 in a predetermined Schottky junction region 31a.

FIG. 13 forms a polyimide layer 30 for insulation. A thick polyimide layer 30 is provided by plating polyimide several times over the entire surface. A new resist layer is formed on the entire surface, and a window-opening photolithography process is selectively performed to leave a predetermined portion of the polyimide layer 30 . The exposed polyimide is then removed by wet etching. Thereafter, the resist layer is removed and the polyimide layer 30 is cured to have a thickness of 6-7 μm.

14 etches the n-type epitaxial layer 23 exposed in the Schottky contact hole 29 to form the Schottky electrode 31 .

The n-type epitaxial layer 23 is etched using the oxide film 25 around the Schottky contact hole 29 as a mask. As described above, the polyimide layer 30 is formed with the surface of the n-type epitaxial layer 23 exposed after the contact hole 29 is formed. The Schottky junction must be formed on a clean GaAs surface, so the surface of the n-type epitaxial layer 23 must be etched before the Schottky electrode is formed. Moreover, in order to ensure the most suitable thickness of 2500 Ȧ for the action layer, it is necessary to precisely control the temperature and time, and wet etch the thickness from about 3500 Ȧ to 2500 Ȧ.

Thereafter, Ti/Pt/Au were sequentially vacuum deposited to form the Schottky electrode 31 serving as the substrate electrode of the anode electrode and the substrate electrode for the cathode electrode 35 .

FIG. 15 forms Au plating layers to be the anode electrode 34 and the cathode electrode 35 .

Electrolytic gold plating is performed after exposing predetermined substrate electrodes of the anode electrode 34 and cathode electrode 35 and covering the rest with a resist layer. At this time, the resist layer becomes a mask, and only the exposed part of the substrate electrode is adhered with Au plating to form the anode electrode 34 and the cathode electrode 35 . Substrate electrodes are provided on the entire surface, and after removing the resist layer, ion etching is carried out with Ar plasma, and the substrate electrodes at the parts not plated with Au are shaved off to form patterns in the shape of anode and cathode electrodes 34 and 35 . At this time, the Au plated part is also slightly chipped, but since it has a thickness of about 6 μm, there is no problem.

Furthermore, the back side is overlapped, and AuGe/Ni/Au is vapor-deposited sequentially, and an alloying heat treatment is performed to form the ohmic electrode 28 on the back side.

When the compound semiconductor Schottky barrier diode is completed, it is transferred to the post-process of assembly. Wafer-shaped semiconductor chips are divided and separated into semiconductor chips one by one. After the semiconductor chips are fixed on a frame (not shown), the anode and cathode pads of the semiconductor chip are connected to predetermined lead wires (in the figure) by bonding wires. not shown) connection. The bonding wires are gold thin wires and connected by known stitch bonding. Afterwards, transfer molding is performed and resin encapsulation is performed.

The existing Schottky barrier diode substrate has a structure in which the cathode electrode can be taken out from the back, and it can be used in various models. An n ⁺ type epitaxial layer is provided on an n ⁺ type GaAs substrate, and the upper layer is provided with a There is an n-type epitaxial layer of about 1.3×10 ¹⁷ cm ^-3 .

The Schottky electrode exposes the clean surface of the n-type epitaxial layer in order to ensure predetermined characteristics, and vapor-deposits metal to form a Schottky junction. In order to reduce the output resistance of the ohmic electrode, the n ⁺ type epitaxial layer under it forms an ohmic junction.

Here, there are problems as shown below in the existing structure. First, to form the ohmic electrode 28, it is necessary to form a mesa to expose the n ⁺ -type epitaxial layer 22 . The n-type epitaxial layer 23 has a thickness of about 3500 Ȧ, in order to expose the underlying n ⁺ -type epitaxial layer 22, a mesa transistor must be etched. An oxide film 25 is provided on the surface of the substrate to protect the substrate. Mesa etching is carried out by placing a photoresist mask on the surface, but the adhesion between the surface of the oxide film 25 and the resist varies. When wet etching is performed in this state, the etching spreads excessively laterally, and the necessary oxide film 25 may also be etched, and the shape of the GaAs mesa becomes unstable as long as the GaAs mesa is exposed. Therefore, when the ohmic electrode 28 provided at the opening of the mesa is formed, the shape of the photoresist also sags at the periphery, and as a result, the shape of the peeled ohmic electrode 28 deteriorates, and GaAs is etched near the Schottky junction. Problems that adversely affect properties sometimes occur.

Second, almost all of the anode electrode 34 is provided on GaAs at the cathode potential, where the parasitic capacitance becomes large. The area of the intersecting part reaches 1300μm ² , so it is necessary to reduce the parasitic capacitance with a thick interlayer insulating film. In order to bury the mesa and form a thick interlayer insulating film, it is necessary to provide a polyimide layer 30 of 6 to 7 μm. For taking out the electrode of the Schottky junction region 31a, the polyimide layer 30 is provided with openings, by etching the thick polyimide layer 30, and considering the step-by-step cladding of the electrodes on the polyimide layer 30 Purpose, its opening is made into a cone shape. However, due to variations in the film quality of the polyimide layer 30 and variations in the adhesion between the polyimide layer 30 and the resist layer, the angle of the taper varies greatly between 30° and 45°. Therefore, the distance between the Schottky junction region 31 a of the operating region and the ohmic electrode 28 must be about 7 μm in consideration of the tapered shape. However, the distance between the junctions contributes to the series resistance. Therefore, when the distance between the junctions is large, the improvement of the high-frequency characteristics is prevented, which is also the reason why chip miniaturization cannot be advanced.

Third, since there is a tapered shape near the Schottky junction and the ohmic junction, the thickness of the interlayer insulating film of 6 μm cannot be maintained near the operating region of the Schottky barrier diode, which increases the parasitic capacitance and deteriorates the characteristics. .

Also, the conventional manufacturing method has the following problems.

First, the Schottky junction is formed on the uppermost n-type epitaxial layer 23. In order to ensure the optimal thickness of 2500 Ȧ in consideration of the withstand voltage and resistance of the action layer, an n-type epitaxial layer of about 3500 Ȧ is formed. The epitaxial layer 23 is formed by etching to 2500 Ȧ. Since the etching at this time is wet etching, it is not only very difficult to control the time and temperature, as well as the amplitude and vibration velocity of the wafer in the etching solution, but also requires the use of the etching solution within the prescribed fresh-keeping time. Therefore, when this method is used, there is variation for each wafer, and it is very difficult to improve the reproducibility of the operating region characteristics and the high-frequency characteristics.

Second, if the mesa structure is adopted, it is necessary to etch the mesa transistor which requires a lot of steps, and the adhesion between the resist layer and the oxide film may vary, which may cause defects. Furthermore, the steps of forming a polyimide layer as an interlayer insulating film and the step of forming an Au plating layer for providing an output electrode on the polyimide layer are required simultaneously, which complicates the manufacturing process and is time-consuming and inefficient.

Since the substrate price of a compound semiconductor is inherently high, it is necessary to reduce the chip size suppression cost in order to rationalize it. That is, reducing the chip size is inevitable, and it is also desirable to reduce the cost of the material itself. Further improvement in high-frequency characteristics is also required at the same time. Further simplification and efficiency of the manufacturing process are also important issues.

Contents of the invention

The present invention is developed in view of the above problems, and it includes: a compound semiconductor substrate; a flat conductive epitaxial layer on the substrate and a stable compound semiconductor layer protecting the epitaxial layer; a conductive high-concentration ion implantation region, which penetrating through the epitaxial layer of one conductivity type; the first electrode forms an ohmic junction on the surface of the high-concentration ion implantation region; the second electrode forms a Schottky junction with the surface of the epitaxial layer; the metal layer leads out the first and second electrodes. The ohmic electrode is arranged on the surface of the high-concentration ion implantation area arranged on the surface of the substrate, and the mesa, the polyimide layer and the Au plating layer are not required. Realizing a planar Schottky barrier diode of a compound semiconductor in this way can also reduce the area of the action part, so it can contribute to the miniaturization of the chip size and cost reduction, and contributes to improving the performance by reducing parasitic capacitance and resistance. High frequency characteristics.

It is also possible to provide a method for manufacturing a Schottky barrier diode, which includes the following steps: laminating a conductivity-type epitaxial layer and a stable compound semiconductor layer on a non-doped compound semiconductor substrate, and forming a through hole under a predetermined first electrode. The process of implanting a conductive type high-concentration ion region of the first conductive type epitaxial layer; the process of forming an ohmic junction on the surface of the high-concentration ion implantation region to form a first electrode; forming a Schottky contact hole on the compound semiconductor layer to form A step of forming a second electrode forming a Schottky junction with the surface of the epitaxial layer; a step of forming a metal layer respectively in contact with the first and second electrodes. Simplification and efficiency of the manufacturing process can be realized, and high-frequency characteristics can be improved.

Description of drawings

1 is a cross-sectional view illustrating a semiconductor device of the present invention;

FIG. 2 is a top view for explaining the semiconductor device of the present invention;

3 is a top view for explaining the semiconductor device of the present invention;

4 is a top view for explaining the semiconductor device of the present invention;

5 is a cross-sectional view for explaining a method of manufacturing a semiconductor device of the present invention;

6 is a cross-sectional view illustrating a method of manufacturing a semiconductor device of the present invention;

7 is a cross-sectional view for explaining a method of manufacturing a semiconductor device of the present invention;

8 is a cross-sectional view for explaining a method of manufacturing a semiconductor device of the present invention;

9 is a cross-sectional view for explaining a conventional semiconductor device;

FIG. 10 is a top view for explaining a conventional semiconductor device;

11 is a cross-sectional view for explaining a conventional semiconductor device manufacturing method;

12 is a cross-sectional view for explaining a conventional semiconductor device manufacturing method;

13 is a cross-sectional view for explaining a conventional semiconductor device manufacturing method;

14 is a cross-sectional view for explaining a conventional semiconductor device manufacturing method;

FIG. 15 is a cross-sectional view for explaining a conventional method of manufacturing a semiconductor device.

Detailed ways

Embodiments of the present invention will be described in detail with reference to accompanying drawings 1 to 8.

The Schottky barrier diode of the present invention comprises: a compound semiconductor substrate 1, a high-concentration epitaxial layer 2, an epitaxial layer 3, a stable compound semiconductor layer 4, a high-concentration ion implantation region 7, a first electrode 8, a second electrode 11, Metal layers 14,15.

FIG. 1 is a cross-sectional view showing a portion of an operating region.

The compound semiconductor substrate 1 is a non-doped GaAs substrate, on which a 5000 Å n ⁺ type epitaxial layer 2 (5×10 ¹⁸ cm ^-3 ), a 2500 Å n type epitaxial layer 3 (1.3×10 ¹⁷ cm ^-3 ) and a non-doped InGaP layer 4 of 200 Ȧ. None of the layers forms a mesa and has a flat substrate structure. The surface of the n-type epitaxial layer 3 susceptible to external contamination is protected by the uppermost InGaP layer 4 .

The high-concentration ion implantation region 7 extends from the surface of the InGaP layer 4 under the ohmic electrode 8 to the n ⁺ -type epitaxial layer 2, is arranged along the outer periphery of the circular Schottky electrode 11, roughly overlaps with the ohmic electrode 8, and is adjacent to the Schottky electrode 11 A portion is exposed from the ohmic electrode 8 , and the distance between the Schottky electrode 11 and the high-concentration ion implantation region 7 is 1 μm. That is, instead of the currently used mesa structure keeping the planar structure unchanged, the high-concentration ion implantation region 7 is set on the surface, so that the ohmic junction can be realized without setting the mesa.

The first electrode, that is, the ohmic electrode 8 is the first metal layer in contact with the high-concentration ion implantation region 7. AuGe/Ni/Au is evaporated sequentially, and the Schottky junction is engraved into a circular layout. The distance between the Schottky electrodes 11 is 2 μm.

The second electrode, that is, the Schottky electrode 11, is the second layer of metal layer that is sequentially vapor-deposited with Pt/Ti/Pt/Au or Ti/Pt/Au. The n-type epitaxial layer 3 forms a Schottky junction.

The thickness of the n-type epitaxial layer 3 forming the active region is preferably 2500 Ȧ, since predetermined characteristics such as withstand voltage must be obtained. Here, by setting the InGaP layer 4 on the n-type epitaxial layer 3, the n-type epitaxial layer 3 is protected by the InGaP layer 4 until the Schottky electrode 11 is formed, so as to obtain an n-type epitaxial layer 3 of 2500 Ȧ and high-quality and high-precision Schottky. Terki Knot. Since the InGaP layer 4 is undoped, it is possible to suppress generation of capacitance at the sides of the Schottky junction formed by the second metal layer.

The metal layer is a vapor-deposited metal layer composed of Ti/Pt/Au to be the third layer of the anode electrode 14 and the cathode electrode 15 . The anode electrode 14 is in contact with the Schottky electrode 11 and extends to the anode bonding region to become an anode pad 14a. The GaAs of the ohmic electrode 8 or cathode potential is insulated by the nitride film 5 .

The lower surface of the anode pad portion 14a is provided with an insulated region 6 implanted with boron or the like (hereinafter referred to as an insulated region). The cathode potential GaAs and the anode electrode 14 can be insulated by reaching the insulated region 6 of the non-doped GaAs substrate, so the wire bonding part can be directly fixed on the substrate without polyimide and nitride film.

The cathode electrode 15 is arranged opposite to the anode electrode 14 , contacts the ohmic electrode 8 and extends to the cathode junction area to become the cathode pad 15 a. The high-concentration ion-implanted region 7 in contact with the ohmic electrode 8 and the n ⁺ -type epitaxial layer 2 form a cathode potential (electrode). Cathode pad 15 a is fixed directly on the surface of InGaP layer 4 .

2 and 3 show plan views of the compound semiconductor Schottky barrier diode of the present invention. FIG. 2 is a schematic diagram of a chip pattern, and FIG. 3 is an enlarged view of an operating region. This figure is the first embodiment of the present invention, and it is the case of one Schottky junction.

A Schottky electrode 11 forming a Schottky junction on the n-type epitaxial layer 3 is provided substantially in the center of the chip. The electrode is circular with a diameter of about 10 μm, and is obtained by sequentially vapor-depositing the second metal layer Pt/Ti/Pt/Au or Ti/Pt/Au. Only the central circular part is in direct contact with GaAs, and an anode electrode 14 formed by a third vapor-deposited metal layer is provided for taking out the electrode, and an anode pad 14a is extended.

The lower surface of the anode pad 14a is provided with an insulating region 6 implanted with B ⁺ ions. In this way, the anode pad 14a can be directly fixed to the substrate without passing through an insulating film, thereby reducing defects during bonding and eliminating parasitic capacitance at the pad portion.

The portion indicated by the dotted line is the ohmic electrode 8 . The outer circumference of the circular Schottky electrode 11 is in contact with the high-concentration ion implantation region 7 (not shown in the figure). The ohmic electrode 8 is the first metal layer on which AuGe/Ni/Au is evaporated sequentially. It is roughly overlapped with the high-concentration ion implantation region 7, and a cathode electrode 15 composed of a third vapor-deposited metal layer is provided for the extraction electrode, and a cathode pad 15a is extended. In order to reduce the induction component of high-frequency characteristic elements, it is necessary to fix more bonding wires when taking out the cathode electrode, so the area occupying half of the chip is used as the bonding area.

The bonding wires are fixed to the anode and cathode pads 14a, 15a by stitch bonding, and the electrodes are taken out. The area of the anode pad 14a is 60×70 μm, and the area of the cathode pad 15a is 180×70 μm. In the stitch-shaped bonding connection, two bonding wires can be connected at one time, so even if the bonding area is small, the induction component of the high-frequency characteristic parameters can be reduced, which contributes to the improvement of high-frequency characteristics.

As shown in Figure 3, the intersection of the cathode potential GaAs and the anode electrode is only the region indicated by the oblique line, and the area of this part is about 100 μm. Compared with the conventional 1300 μm, it can be reduced to about 1/13, so the thin nitride film 5 can be used instead of the interlayer insulating film polyimide.

The present invention is characterized in that an InGaP layer 4 is provided on the GaAs epitaxial layer, and a high-concentration ion implantation region 7 is provided on the surface of the InGaP layer 4 contacted by the ohmic electrode 8 . In this way, the Schottky electrode 11 and the ohmic electrode 8 are arranged on the surface of GaAs to realize the planar structure of the Schottky barrier diode.

Since there is no need to consider the alignment deviation caused by the deviation of the shape of the mesa, the distance between the Schottky electrode 11 and the ohmic electrode 8 can be greatly shortened. Most of the area under the anode electrode 14 is provided with an insulating region 6, and the area of the intersection of GaAs at the cathode potential and the anode electrode 14 is about 100 μm ² , which is 1/13 of the area compared with the conventional one. Therefore, it is not necessary to suppress parasitic capacitance by increasing the thickness (separation distance), and polyimide can be replaced with a thin nitride film, and there is no need to consider the taper portion of polyimide.

Specifically, the distance between the Schottky junction region and the ohmic electrode can be reduced from 7 μm to 2 μm. And the distance from the high-concentration ion-implantation region 7 is 1 μm. At this time, the high-concentration ion-implantation region 7 is the moving path of carriers, which has approximately the same effect as the ohmic electrode 8, so it can be reduced compared with the existing ratio. to 1/7. The distance between the Schottky electrode 11 and the ohmic electrode 8 contributes to the series resistance, so if the distance between them can be reduced, the resistance can be further reduced, and the high-frequency characteristics can be greatly improved.

This helps miniaturization of the chip, and the existing chip size of 0.27×0.31mm ² can be reduced to 0.25×0.25mm ² . As the size, it is necessary to arrange pads, and the chip size that can be handled during assembly is limited, so 0.25mm square is the current limit, but as the operating area can be greatly reduced to about 1/10, so the operating area is arranged as described later degrees of freedom become very large.

Fig. 4 is a second embodiment of the present invention, showing a case where a plurality of Schottky electrodes are provided.

The structure of the present invention can also have multiple Schottky electrodes 11 . For example, as long as the Schottky electrodes 11 are arranged as shown in the figure, they will be connected in parallel, which contributes to the reduction of resistance.

And as long as the diameter of the Schottky contact hole 19 is reduced and a plurality of them are arranged, the area of the total Schottky contact hole 19 is the same. The distance between the implanted regions 7 can be further reduced, and there is a carrier trap effect in the high-concentration ion implanted region 7 . In this way, the value of the cathode resistance is reduced, and there is an advantage that high-frequency characteristics can be further improved.

5 to 8 show in detail the manufacturing method of the Schottky barrier diode of the present invention.

The Schottky barrier diode is made by the following process: a conductivity type epitaxial layer and a stable compound semiconductor layer are laminated on the non-doped compound semiconductor substrate, and a conductivity type is formed on the surface of the compound semiconductor layer under the predetermined first electrode. The process of implanting high-concentration ions into the region; the process of forming an ohmic junction on the surface of the high-concentration ion implantation region to form the first electrode; forming a Schottky contact hole on the compound semiconductor layer to form a Schottky junction with the surface of the epitaxial layer The process of two electrodes; the process of forming metal layers respectively in contact with the first and second electrodes.

As shown in Figure 5, the first process of the present invention is to laminate a conductivity type epitaxial layer 3 and a stable compound semiconductor layer 4 on the non-doped compound semiconductor substrate 1, and the compound semiconductor layer under the predetermined first electrode 8 4 forms a high-concentration ion implantation region 7 .

This step is a characteristic step of the present invention. The n-type epitaxial layer 3 under the region where the ohmic electrode 8 is to be formed is penetrated to form the high-concentration ion-implanted region 7 reaching the n ⁺ -type epitaxial layer 2 .

That is, an n ⁺ -type epitaxial layer 2 (5×10 ¹⁸ cm ^-3 ) of about 5000 Ȧ is deposited on a non-doped GaAs substrate 1 , and an n-type epitaxial layer 3 (1.3×10 ¹⁷ cm ^{-3 )} of 2500 Ȧ is deposited thereon. ). Furthermore, a non-doped InGaP layer 4 of 200 Å is provided on the upper layer. Afterwards, the whole surface is covered with a nitride film 5, a resist layer is provided, and the resist layer on the predetermined insulating region 6 is selectively subjected to a window-opening photolithography process. Thereafter, B ⁺ impurities are ion-implanted into the resist layer as a mask to form an insulating region 6 reaching the non-doped GaAs substrate 1 to insulate the GaAs at the cathode potential from the anode pad portion 14a.

Next, a photolithography process is performed on the resist layer on the area where the high-concentration ion implantation area 7 is planned to be formed, and windows are selectively opened. Then use the resist layer as a mask to implant high-concentration n-type impurities (Si+, about 1×10 ¹⁸ cm ^-3 ) through the InGaP layer 4 and n-type epitaxial layer 3 under the predetermined ohmic electrode 8 to form n+ The high-concentration ion-implanted region 7 of the epitaxial layer 2 . At this time, the ion implantation is carried out in multiple implants under different conditions, so that the impurity concentration in the high-concentration ion implantation region 7 is as uniform as possible in the depth direction.

After that, the resist layer is removed and the nitride film 5 for annealing is deposited again, and the high-concentration ion-implanted region 7 and the insulating region 6 are activated annealed.

As shown in FIG. 6 , the second step of the present invention is to form the first electrode 8 forming an ohmic junction on the surface of the high-concentration ion implantation region 7 .

A resist layer is formed on the entire surface, and the portion where the ohmic electrode 8 is to be formed is selectively subjected to a window-opening photolithography process. The nitride film 5 exposed from the resist layer was removed, and three layers of AuGe/Ni/Au as the first metal layer were sequentially vacuum-evaporated and laminated. Afterwards, the resist layer is removed by stripping, leaving the first metal layer at the predetermined ohmic electrode 8 portion. Next, an ohmic electrode 8 is formed on the surface of the high-concentration ion implantation region 7 by alloying heat treatment.

As shown in FIG. 7 , the third step of the present invention is to form a Schottky contact hole 19 on the compound semiconductor layer 4 and form a second electrode 11 forming a Schottky junction on the surface of the epitaxial layer 3 .

This step is a characteristic step of the present invention. The Schottky contact hole 9 is formed, and the Schottky junction is formed by vapor-depositing metal.

First, in FIG. 7(A), a resist layer PR is formed on the entire surface, and a photolithography process is performed to selectively open a predetermined portion of the Schottky electrode 11 . After dry etching the exposed nitride film 5, the InGaP layer 4 is etched using the same mask. Here, the etching selectivity ratio between InGaP and GaAs is very large, so only the InGaP layer 4 can be removed by etching under predetermined conditions, and the Schottky contact hole 9 exposing the n-type epitaxial layer 3 can be formed.

Thereafter, as shown in FIG. 7(B), three layers of Ti/Pt/Au as the second metal layer were deposited sequentially by vacuum vapor deposition on the entire surface. Thereafter, the resist layer PR is removed by stripping to form a Schottky junction on the surface of the n-type epitaxial layer 3 as the Schottky electrode 11 . The surface of GaAs is covered with InGaP before the Schottky junction is formed, and the GaAs surface can form the Schottky junction in good condition.

That is, the Schottky electrode 11 forming a good Schottky junction with the surface of the n-type epitaxial layer 3 can be easily formed through the InGaP layer 4 . In the existing manufacturing method, it is very difficult to precisely control the time and temperature, and thus the amplitude and vibration velocity of the wafer in the etching solution, and it is also required to use the etching solution within a specified fresh-keeping time. However, according to the manufacturing method of the present invention, as long as the most suitable 2500 Ȧ epitaxial layer 3 is formed as the action layer, only InGaP is etched by etching with high selectivity, and the thickness of the action layer is easy to control, so the Schottky layer with good reproducibility can be formed. Junction has the advantage of being able to manufacture Schottky barrier diodes with stable characteristics.

As shown in FIG. 8 , the fourth step of the present invention is to form metal layers 14 and 15 that are in contact with the first electrode 8 and the second electrode 11 respectively.

This step is also a characteristic step of the present invention, and a vapor-deposited metal layer is formed as the anode electrode 14 and the cathode electrode 15 in order to take out the Schottky electrode 11 and the ohmic electrode 8 .

First, a nitride film 5 of about 5000 Ȧ is deposited again on the entire surface as an interlayer insulating film. A resist layer is formed, and a photolithography process is performed to selectively open windows on the Schottky electrode 11, the ohmic electrode 8, the anode pad 14a, and the cathode pad 15a as the contact portion, and etch the nitride film 5. After removing the resist film, a new resist layer is set up, and a photolithography process is carried out to selectively open windows for desired patterns of the anode electrode 14 and cathode electrode 15 . Ti/Pt/Au is sequentially vapor-deposited on the entire surface, and the anode electrode 14 and the cathode electrode 15 are formed by peeling off, and the back surface is lapped.

Here, the anode electrode 14 and the cathode electrode 15 are vapor-deposited metals formed by a normal lift-off method. The interlayer insulating film between the anode electrode 14 and the cathode electrode 15 is the nitride film 5, and the pad portion can also be fixed directly on the substrate, so the polyimide layer can be omitted. This can omit the wiring and Au plating process for forming pads that are thickly provided on the conventional polyimide layer to absorb the disadvantages of polyimide.

The existing process of forming a thick polyimide layer uses multiple coatings and curings, which is time-consuming and complicated. The formation process of the Au plating layer is also a factor that increases the number of manufacturing processes. However, according to the production method of the present invention, these steps of forming the polyimide layer and the Au plating layer can be omitted, and the production process can be greatly simplified and improved in efficiency.

When the compound semiconductor Schottky barrier diode is completed, it is transferred to the post-process of assembly. Wafer-like semiconductor chips are divided and separated into semiconductor chips one by one. After fixing the semiconductor chips on a frame (not shown in the figure), the pads 14a, 15a of the semiconductor chip are connected to the prescribed lead wires (Fig. not shown) connection. The bonding wires are gold thin wires and connected by known stitch bonding. Afterwards, transfer molding is performed and resin encapsulation is performed.

According to the structure of the present invention, the following various effects can be obtained.

First, by setting an ohmic electrode on the surface of the high-concentration ion-implanted region from the InGaP layer to the GaAs n ⁺ type epitaxial layer, a Schottky barrier diode with a planar structure is realized. Since there is no mesa, the variation in the shape of the ohmic electrode and the deterioration of the characteristics caused by the variation in the shape of the mesa can be suppressed. Since there is no need to consider the alignment error, the distance between the Schottky electrode 11 and the ohmic electrode 8 can be greatly reduced. Since the distance between the Schottky electrode 11 and the ohmic electrode 8 affects the series resistance, the smaller the distance is, the more the resistance can be reduced.

Second, the area of the intersecting portion of GaAs at the cathode potential and the anode electrode 14 is about 100 μm ² , and the parasitic capacitance is greatly reduced. Most of the region under the anode electrode 14 is provided with the insulating region 6, so that the area of the intersection where parasitic capacitance occurs can be reduced to 1/13 of the conventional Schottky junction. Moreover, the anode pad 14a can also be directly fixed on GaAs, and this part does not generate parasitic capacitance, which can greatly reduce the total parasitic capacitance. At present, polyimide with low permittivity and a thick interlayer insulating film are used to suppress parasitic capacitance, but it can be replaced by a thin nitride film. The nitride film has a higher permittivity than polyimide, but according to the structure of the present invention, even if a nitride film of about 5000 Ȧ is used, the parasitic capacitance can be reduced compared with the conventional one.

Third, since no thick polyimide is used, there is no need to consider variations in the distance of the tapered portion of the opening of the polyimide as the operating region and the angle of the tapered portion.

According to the above, the distance between the Schottky electrode and the ohmic electrode only needs to consider the withstand voltage and the alignment accuracy of the mask. Specifically, the distance between the Schottky junction region and the ohmic electrode can be reduced from 7 μm to 2 μm. The distance from the high-concentration ion implantation region 7 is 1 μm. At this time, the high-concentration ion implantation region 7 is the moving path of the carriers, which has roughly the same effect as the ohmic electrode 8, so the distance can be reduced compared with the existing ones. as small as 1/7. Therefore, the high-frequency characteristics can be greatly improved by greatly reducing the resistance, greatly reducing the parasitic capacitance, and reducing the deviation of the parasitic capacitance.

Fourth, chip miniaturization can be realized, and the existing chip size of 0.27×0.31mm ² can be reduced to 0.25×0.25mm ² . As a size, there is a limit in terms of the necessity of arranging pads and the chip size that can be handled during assembly, so 0.25mm square is the current limit, but the operating area can be greatly reduced to about 1/10, so the operating area is arranged degrees of freedom become very large.

Fifth, the resistance can be further reduced by providing a plurality of Schottky junctions forming the Schottky electrodes. By reducing the contact diameter of the Schottky junction and providing multiple Schottky junctions, the resistance can be further reduced compared with the case where one Schottky electrode is provided with the same total Schottky contact area, and it can be effectively generated in the high-concentration ion implantation region Carrier trap, so there is an advantage of further improving high-frequency characteristics.

Sixth, since the polyimide layer and gold plating are not used, the cost of materials can be reduced and the chip can be reduced to achieve cost reduction.

According to the production method of the present invention, the following effects can be obtained.

First, since a stable Schottky junction can be formed, it is possible to suppress characteristic variation which is a very important issue in high-frequency circuits. The n-type epitaxial layer is covered by InGaP until the Schottky junction is formed. As long as the InGaP is etched and Ti/Pt/Au is evaporated, the Schottky junction can be formed on a completely pollution-free crystal surface. The n-type epitaxial layer is formed at the most suitable 2500 Å as an active layer, and the etching selectivity ratio between InGaP and GaAs is very large, so only InGaP can be etched when etching is carried out under predetermined conditions. The current complex GaAs etch control is therefore not required. That is, it is possible to manufacture Schottky barrier diodes with high qualified product rate, good reproducibility, and stable characteristics.

Second, the manufacturing of the above-mentioned Schottky barrier diode can achieve high efficiency and simplify the manufacturing process. Specifically, the mesa etching process, the n-type epitaxial layer etching process before Schottky junction formation, the polyimide layer forming process, the Au plating process, etc. can be omitted. The polyimide layer is formed by repeated coating and plating several times to a thickness of 6-7 μm. However, coating the polyimide layer several times is time-consuming and complicates the manufacturing process. If polyimide is not required, Au-plated electrodes are not required either. At present, in order to prevent electrode breakage and deformation caused by heat during solder mounting and stress during wire bonding, it is necessary to ensure the strength of the electrodes, and the anode and cathode electrodes are formed by thick Au plating. However, if the polyimide layer is not required, its influence need not be considered. That is, the anode electrode and the cathode electrode can be formed only by vapor-deposited metal of Ti/Pt/Au without the need for gold-plated electrodes, and the reliability is also improved. At present, the above-mentioned factors that caused the low pass rate have disappeared, so the pass rate has also increased.

That is, the advantage is that it can not only provide a Schottky barrier diode that can greatly reduce parasitic capacitance, can further reduce resistance and greatly improve high-frequency characteristics, but also can provide a manufacturing method that seeks to simplify and increase the efficiency of the manufacturing process.

Claims (12)

1. a Schottky barrier diode is characterized in that, comprising: compound semiconductor substrate; Be located at the smooth conductivity type epitaxial loayer on this substrate and protect the stable compound semiconductor layer of this epitaxial loayer; Connect a conductive high concentration ion implanted region territory of a described conductivity type epitaxial loayer; Become first electrode of ohm knot on described high concentration ion injection zone surface; Second electrode with described epi-layer surface formation schottky junction; Draw described first and second metal layer of electrodes.

2. a Schottky barrier diode is characterized in that, comprising: compound semiconductor substrate; Be located at a smooth conductive high concentration epitaxial loayer and the conductivity type epitaxial loayer on this substrate and protect the stable compound semiconductor layer of this epitaxial loayer; Arrive a conductive high concentration ion implanted region territory of described high concentration epitaxial loayer from described compound semiconductor layer surface; Become first electrode of ohm knot on described high concentration ion injection zone surface; Surrounded periphery, form second electrode of schottky junction by described first electrode with the described epi-layer surface of described compound semiconductor layer lower floor; Draw described first and second metal layer of electrodes.

3. Schottky barrier diode as claimed in claim 1 or 2 is characterized in that, described compound semiconductor layer is the InGaP of non-doping.

4. Schottky barrier diode as claimed in claim 1 or 2 is characterized in that, described compound semiconductor substrate is the GaAs substrate of non-doping.

5. Schottky barrier diode as claimed in claim 1 or 2 is characterized in that, described its orlop of second electrode is the evaporation metal of Pt.

6. Schottky barrier diode as claimed in claim 1 or 2 is characterized in that, the spacing distance of described second electrode and described high concentration ion injection zone is below the 5 μ m.

7. Schottky barrier diode as claimed in claim 1 or 2 is characterized in that, the schottky junction Region Segmentation that described second electrode forms is arranged to a plurality of.

8. Schottky barrier diode as claimed in claim 1 or 2 is characterized in that, described high concentration ion injection zone exposes setting from described first electrode.

9. the manufacture method of a Schottky barrier diode, it is characterized in that, comprise: the epitaxial loayer of lamination one conductivity type and stable compound semiconductor layer on non-doped compound semiconductor substrate, the operation of the high concentration ion injection zone of a conductivity type of the described conductivity type epitaxial loayer of formation perforation under the first predetermined electrode; Be formed on the operation that described high concentration ion injection zone surface becomes first electrode of ohm knot; On described compound semiconductor layer, form the Schottky contacts hole, form the operation that forms second electrode of schottky junction with described epi-layer surface; Form the operation of the metal level that contacts with described first and second electrode respectively.

10. the manufacture method of a Schottky barrier diode, it is characterized in that, comprise: lamination one conductive high concentration epitaxial loayer and a conductivity type epitaxial loayer and stable compound semiconductor layer on non-doped compound semiconductor substrate, formation arrive the operation in a conductive high concentration ion implanted region territory of described high concentration epitaxial loayer from the described compound semiconductor layer surface under the first predetermined electrode; Be formed on the operation that described high concentration ion injection zone surface becomes first electrode of ohm knot; On the described compound semiconductor layer of predetermined second electrode part that is surrounded periphery by described first electrode, form the Schottky contacts hole, form the operation that forms second electrode of schottky junction with the described epi-layer surface of exposing; Form the operation of the metal level that contacts with described first and second electrode respectively.

11. the manufacture method as claim 9 or 10 described Schottky barrier diodes is characterized in that, described second electrode multiple layer metal layer of evaporation Ti/Pt/Au in turn forms.

12. the manufacture method as claim 9 or 10 described Schottky barrier diodes is characterized in that the etching selectivity of described compound semiconductor layer and described epitaxial loayer is big.

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