CN1314130C - Longitudina multiface grid metal-oxide-semiconductor field effect transistor and its manufacturing method - Google Patents
Longitudina multiface grid metal-oxide-semiconductor field effect transistor and its manufacturing method Download PDFInfo
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- CN1314130C CN1314130C CNB2004100138056A CN200410013805A CN1314130C CN 1314130 C CN1314130 C CN 1314130C CN B2004100138056 A CNB2004100138056 A CN B2004100138056A CN 200410013805 A CN200410013805 A CN 200410013805A CN 1314130 C CN1314130 C CN 1314130C
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
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- 239000002800 charge carrier Substances 0.000 claims description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- 239000004411 aluminium Substances 0.000 claims description 6
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- 238000007254 oxidation reaction Methods 0.000 claims description 4
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- 238000009826 distribution Methods 0.000 claims description 3
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 claims description 3
- 238000002347 injection Methods 0.000 claims description 3
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Abstract
纵向多面栅金属-氧化物-半导体场效应晶体管及其制造方法是一种利用侧壁栅形式实现载流子纵向迁移和多面栅MOSFET的结构，该晶体管利用侧壁栅的形式实现载流子的纵向迁移，自上而下分别为上源/漏区(1)、多晶硅栅(4)、下漏/源区(3)的MOS三层结构，多晶硅栅的位置位于纵向结构上的P型硅衬底(2)侧面刻蚀出的侧壁表面；即总体结构为在源/漏的外面设有氧化层(11)，在源/漏极和下漏/源区之间为P型硅衬底，在P型硅衬底的侧面为栅氧化层(21)，在栅氧化层外侧为多晶硅栅，P型硅衬底的下部是下漏/源区，在下漏/源区的下部是衬底(5)。它解决了原先实现多面栅MOSFET结构在材料、工艺、可靠性、可重复性和生产成本等诸多方面的问题。
The vertical multi-sided gate metal-oxide-semiconductor field effect transistor and its manufacturing method are a structure that uses the form of side wall gate to realize the longitudinal migration of carriers and the structure of multi-sided gate MOSFET. The transistor uses the form of side wall gate to realize the transfer of carriers. Vertical migration, from top to bottom is the MOS three-layer structure of the upper source/drain region (1), polysilicon gate (4), and lower drain/source region (3). The position of the polysilicon gate is located on the P-type silicon on the vertical structure. The side wall surface etched out of the side of the substrate (2); that is, the overall structure is to have an oxide layer (11) outside the source/drain, and a P-type silicon lining between the source/drain and the lower drain/source region At the bottom, the side of the P-type silicon substrate is a gate oxide layer (21), and the outside of the gate oxide layer is a polysilicon gate. The lower part of the P-type silicon substrate is the lower drain/source region, and the lower part of the lower drain/source region is the substrate Bottom (5). It solves many problems in material, process, reliability, repeatability and production cost of realizing multi-side gate MOSFET structure.
Description
Technical field
The present invention is a kind of structure of utilizing sidewall grid form to realize the metal-oxide semiconductor fieldeffect transistor (MOSFET) of charge carrier vertical migration and multiaspect grid, belongs to the technical field that microelectronic component is made.
Background technology
Develop restriction and restriction that integrated circuit rapidly more and more was subjected to two aspects in the last few years: one, device feature size are very near its physics limit, and significant thereupon and all the more various second-order effects have a strong impact on device and circuit performance; On the other hand, connection resistances is more and more serious to the influence of integrated circuit speed.Therefore vertically integrated is the effective way that three-dimensional integrated technology becomes further raising integrated circuit scale and performance.
Vertically integrated technology must have the device that adapts with it could realize that multiple-gate MOSFET just can well satisfy this demand.At first the structure of multiaspect grid is different from the monoplane structure of conventional MOSFET, and it provides possibility for realizing that three-dimensional integrated three-dimensional multiaspect is drawn; Secondly, multiaspect grid structure devices under the certain condition has been used the body mobility and has been carried out the transmission of charge carrier, add it to the better control action of raceway groove, therefore comprise that every device performance of speed, mutual conductance all is improved, various second-order effects all can improve and restrain.But because the particularity of multiaspect grid structure itself realizes that at present this structure generally needs special materials such as SOI disk, and such as special technologies such as selective epitaxial, Si-Si bondings.Reliability, repeatability that this must influence device significantly increase production cost, are unfavorable for the popularization and large-scale application the in market, also can't satisfy integrated circuit to the device high density simultaneously, the basic demand of high duplication, low failure rate.
Summary of the invention
Technical problem: the purpose of this invention is to provide a kind of sidewall grid form of utilizing and realize vertical multiaspect grid metal-oxide semiconductor fieldeffect transistor and manufacture method thereof, use this structure and can solve and alleviate the problem of original realization multiple-gate MOSFET structure in all many-sides such as material, technology, reliability, repeatability and production costs.
Technical scheme: vertical multiaspect grid metal-oxide semiconductor fieldeffect transistor of the present invention and manufacture method thereof utilize the form of sidewall grid to realize the vertical migration of charge carrier, be respectively the MOS three-decker in source/drain region, polysilicon gate, following leakage/source region from top to bottom, the position of polysilicon gate is positioned at the sidewall surfaces that the P type silicon substrate side on the vertical structure etches, and is sidewall grid structure; Be that general structure is to be provided with oxide layer in the outside in Shang Yuan/drain region, between Shang Yuan/drain region and following leakage/source region is P type silicon substrate, in the side of P type silicon substrate is gate oxide, in the gate oxide outside is polysilicon gate, the bottom of P type silicon substrate is following leakage/source region, is substrate in the bottom in following leakage/source region.
Given here is the NMOS structure, and the PMOS structure is also similar, and difference is that leak in the source is the P+ doped region, and the substrate between two source-drain areas is a N type doped region.This structure is easy to realize different grid number and position by using different etching domains, therefore using this structure just can produce present existing various single grid, double grid, three grid very easily and enclose the device of grid form, no matter how are what and position shape of grid number, all determine and do not have unnecessary sidewall grid structure, really realized grid number and the control of position shape under the unified agent structure by a photoetching and etch step.The concrete grammar of realizing this structure is (is example with NMOS):
1, selects P type silicon substrate;
2, Xia Yuan/drain region makes: the bottom source/light leak that flattens face is carved and doping, and the buried regions in the corresponding bipolar process is made, and adopts the doping impurity of low diffusion coefficient;
3, upper strata semiconductor material growing: carry out the epitaxial growth of N type, thickness 2～2.5 μ m;
4, the device channel region substrate is made: carry out the base boron diffusion, and as the channel region of device, junction depth X
j=1.8～2.2 μ m;
5, Xia Yuan/draw-out area, drain region makes: the dark phosphorous diffusion photoetching and the doping of drawing leakage/source, bottom;
6, Shang Yuan/drain region makes: carry out photoetching of leakage/source, top and injection, select for use phosphorus as impurity, the doping of corresponding emitter region;
7, Impurity Distribution and defect repair: process annealing is handled;
8, sidewall forms processing: carry out the deep trouth photoetching, etching depth is 1.6～1.7 μ m;
9, sidewall surfaces is handled: carry out the polishing of etching surface;
10, grid region processed: grid region photoetching;
11, growth gate oxide: gate oxidation, gate oxide thickness 40～50nm;
12, grid material is made and is handled: carry out twice polysilicon deposit and doping continuously;
13, electrode is drawn processing: make lithography fair lead, deposit aluminium also anti-carves;
14, form ohmic contact and protection: alloying, passivation.
Vertical structure is easy to realize the control of multiaspect gate device and grid number of positions, no matter and what and position shape of grid number how all can determine and not have unnecessary sidewall grid structure by a photoetching and etch step; Vertically the manufacture craft of multiple-gate MOSFET is compatible mutually with the technologies such as CMOS, BiCMOS of main flow; Vertically the channel length of multiple-gate MOSFET does not rely on the lithographic accuracy of processing line, and is determined by the physical dimension and the technical process of device.Distinguish whether to be the standard of this structure as follows:
(a) leakage/source-grid-three layers of MOS structure of vertically arranging in leakage/source, charge carrier is realized vertical migration.
(b) position of grid is located at the sidewall surfaces that etches on the vertical structure described in (a), is sidewall grid structure.
(c) though what and position shape of grid number how, whole sidewall grid structure only need be definite by a photoetching and etch step, and do not have unnecessary sidewall grid structure.
The structure that satisfies above three conditions promptly should be considered as the structure of this vertical multiple-gate MOSFET.
In addition, note also some problems in the whole technical proposal, comprising: the back-diffusion control and the calculating of bottom source/leakage impurity, the accurate customization of this realization for the integral device structure, channel length all is to have crucial meaning; The selection of lithographic method and speed and the degree of depth, this has determined the degree of roughness of etching surface and the overlay length between grid and the bottom source/leakage; The selection of etching surface finishing method, because the particularity of structure, this will do a compromise in surpassing of processing line between property done and the polishing effect; The figure of silicon island photoetching can be one or several limits or circular arc, can also be various figures such as square, rectangle, circle or ellipse; The deposit of polycrystalline and aluminium need be considered the problem of its deep trouth of ascending, and prevents fracture.
The technical process of this vertical multiple-gate MOSFET structure of whole realization, CMOS, the BiCMOS technology with main flow is compatible mutually fully.
Beneficial effect:, the research and development of such device only are confined to scientific research field for a long time because the structure particularity of multiple-gate MOSFET.Multiaspect grid structure applications exists incompatible with main flow technology, repeatable and a series of obstacles such as poor reliability, production cost height in the large-scale production of integrated circuit.Vertical multiple-gate MOSFET structure among the present invention has broken through the thinking restriction of traditional multiaspect grid structure and technology, has searched out the implementation method based on main stream of CMOS, BiCMOS technology, and repeatable reliability all is greatly improved, and production cost significantly reduces.Simultaneously, vertically the multiple-gate MOSFET structure can realize various multiaspect grid more easily than previous methods, comprise single grid, double grid, three grid, rectangle or circle are enclosed grid etc., and realize the number of all types grid and position only need to determine a lithography step, really realized the control easily and effectively of grid number and position under the unified agent structure.
Vertical multiple-gate MOSFET structure among the present invention is different from the pattern that conventional MOS FET charge carrier level transports, and this structure is utilized the vertical migration of the form realization charge carrier of sidewall grid, is respectively the MOS three-decker in source/leakage-grid-leakage/source from top to down.Comparatively speaking, vertically multiple-gate MOSFET has following main feature: one, vertical structure is easier to realize the control of multiaspect gate device and grid number than horizontal structure; Two, the vertical making of multiple-gate MOSFET technologies such as CMOS, the BiCMOS compatibility mutually that need not special material and its technology and main flow; Three, vertically the channel length of multiple-gate MOSFET does not rely on the lithographic accuracy of processing line, and is determined by the physical dimension and the technical process of device.
Characteristics based on above vertical multiple-gate MOSFET structure, the present invention has as can be seen clearly well solved the variety of issue of above mentioning that non-vertical multiple-gate MOSFET ran into, the manufacturing that makes multiaspect grid structure is no longer because the particularity of its structure and difficulty, and be easy to realize high reliability, high duplication, the low production cost of device well satisfy the basic demand of integrated circuit to device.Therefore, vertically the structure of multiple-gate MOSFET has using value and vast market potentiality preferably.
Vertically the structure of multiple-gate MOSFET provides support and assurance for the real commercial application of multiple-gate MOSFET in integrated circuit that realize.
Description of drawings
Fig. 1 is vertical multiple-gate MOSFET structural representation.
Fig. 2 is based on vertical multiple-gate MOSFET structural representation that bipolar process is realized.
Fig. 3 is based on vertical multiple-gate MOSFET output characteristics figure that bipolar process is realized.
Specific embodiments
For vertical multiple-gate MOSFET structure of the present invention, we have designed the complete implementation based on bipolar process, and by the flowing water Success in Experiment produce the vertical structure of using this scheme single grid, double grid, enclose device such as grid and tested out characteristic preferably.Realize the specific as follows of vertical multiple-gate MOSFET organization plan based on bipolar process:
This transistorized structure utilizes the form of sidewall grid to realize the vertical migration of charge carrier, be respectively the MOS three-decker in source/drain region 1, polysilicon gate 4, following leakage/source region 3 from top to bottom, the position of polysilicon gate 4 is positioned at the sidewall surfaces that P type silicon substrate 2 sides on the vertical structure etch, and is sidewall grid structure; Be that general structure is that 1 outside is provided with oxide layer 11 in Shang Yuan/drain region, between Shang Yuan/drain region 1 and following leakage/source region 3 is P type silicon substrate 2, in the side of P type silicon substrate 2 is gate oxide 21, in gate oxide 21 outsides is polysilicon gate 4, the bottom of P type silicon substrate 2 is following leakage/source regions 3, is substrates 5 in the bottom in following leakage/source region 3.Processing step and parameter are as follows:
1, selects P type silicon substrate;
2, Xia Yuan/drain region makes: the bottom source/light leak that flattens face is carved and doping, and the buried regions in the corresponding bipolar process is made, and adopts the doping impurity of low diffusion coefficient; Carry out the photoetching and the doping in leakage/source, bottom on P type silicon substrate, concrete doping figure can be selected leveling face figure or bilateral figure for use, and the impurity of selecting for use need have low back-diffusion coefficient, so that the control of channel length,
3, upper strata semiconductor material growing: carry out the epitaxial growth of N type, thickness 2～2.5 μ m; Carry out the N epitaxial growth on former substrate, concentration and thickness are definite by concrete design,
4, the device channel region substrate is made: carry out the base boron diffusion, and as the channel region of device, junction depth X
j=1.8～2.2 μ m;
5, Xia Yuan/draw-out area, drain region makes: the dark phosphorous diffusion photoetching and the doping of drawing leakage/source, bottom; Whole epitaxial loayer is carried out p type impurity mixes, form channel region,
6, Shang Yuan/drain region makes: carry out photoetching of leakage/source, top and injection, select for use phosphorus as impurity, the doping of corresponding emitter region; Carry out the photoetching and the doping in leakage/source, top on epitaxial loayer, experimental parameters such as the mode of doping, concentration and junction depth are definite by the specific design scheme,
7, Impurity Distribution and defect repair: process annealing is handled;
8, sidewall forms processing: carry out the deep trouth photoetching, etching depth is 1.6～1.7 μ m; Carry out deep etching around leakage/source, top, can select for use RIE (reactive ion etching) or method for distinguishing to carry out etching, the speed of etching, the degree of depth is by the decision of specific design scheme,
9, sidewall surfaces is handled: carry out the polishing of etching surface; Etching surface is polished and surface density of states reduction processing, and present selectable method has:
(1) CMP (chemical-mechanical polishing) technology
(2) sidewall oxidation is removed technology again
(3) in hydrogeneous atmosphere or inert gas, carry out annealing in process
10, grid region processed: grid region photoetching; Carry out the silicon island photoetching, determine the position and the number of grid,
11, growth gate oxide: gate oxidation, gate oxide thickness 40～50nm;
12, grid material is made and is handled: carry out twice polysilicon deposit and doping continuously; Polycrystalline deposition is carved fairlead, and deposit aluminium also anti-carves aluminium,
13, electrode is drawn processing: make lithography fair lead, deposit aluminium also anti-carves;
14, form ohmic contact and protection: alloying, passivation.
Use this processing step, we have produced multiple vertical multiple-gate MOSFET device, and test has obtained characteristic preferably.
Claims (2)
1. vertical multiaspect grid metal-oxide semiconductor fieldeffect transistor, it is characterized in that this transistorized structure utilizes the form of sidewall grid to realize the vertical migration of charge carrier, be respectively the MOS three-decker in source/drain region (1), polysilicon gate (4), following leakage/source region (3) from top to bottom, the position of polysilicon gate (4) is positioned at the whole sidewall surfaces that P type silicon substrate (2) side on the vertical structure etches, and is sidewall grid structure; Be that general structure is that the outside of in Shang Yuan/drain region (1) is provided with oxide layer (11), between Shang Yuan/drain region (1) and following leakage/source region (3) is P type silicon substrate (2), in the side of P type silicon substrate (2) is gate oxide (21), in gate oxide (21) outside is polysilicon gate (4), the bottom of P type silicon substrate (2) is following leakage/source region (3), is substrate (5) in the bottom in following leakage/source region (3).
2. the manufacture method as right 1 described vertical multiaspect grid metal-oxide semiconductor fieldeffect transistor is characterized in that utilizing the implementation method based on bipolar process, adopts following step to make device:
1) selects P type silicon substrate;
2) source/drain region makes down: the bottom source/light leak that flattens face is carved and doping, and the buried regions in the corresponding bipolar process is made, and adopts the doping impurity of low diffusion coefficient;
3) upper strata semiconductor material growing: carry out the epitaxial growth of N type, thickness 2～2.5 μ m;
4) the device channel region substrate is made: carry out the base boron diffusion, and as the channel region of device, junction depth X
j=1.8～2.2 μ m;
5) source/draw-out area, drain region makes down: the dark phosphorous diffusion photoetching and the doping of drawing leakage/source, bottom;
6) going up source/drain region makes: carry out photoetching of leakage/source, top and injection, select for use phosphorus as impurity, the doping of corresponding emitter region;
7) Impurity Distribution and defect repair: process annealing is handled;
8) sidewall forms processing: carry out the deep trouth photoetching, etching depth is 1.6～1.7 μ m;
9) sidewall surfaces is handled: carry out the polishing of etching surface;
10) grid region processed: grid region photoetching;
11) growth gate oxide: gate oxidation, gate oxide thickness 40～50nm;
12) grid material is made and is handled: carry out twice polysilicon deposit and doping continuously;
13) electrode is drawn processing: make lithography fair lead, deposit aluminium also anti-carves;
14) form ohmic contact and protection: alloying, passivation.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5382816A (en) * | 1992-07-03 | 1995-01-17 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having vertical transistor with tubular double-gate |
| CN1230029A (en) * | 1998-02-20 | 1999-09-29 | 日本电气株式会社 | Vertical type metal insulator semiconductor field effect transistor and method of its production |
| CN1234613A (en) * | 1998-04-23 | 1999-11-10 | 国际整流器有限公司 | P-shape channelled metal-oxide semiconductor FET transistor structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5382816A (en) * | 1992-07-03 | 1995-01-17 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having vertical transistor with tubular double-gate |
| CN1230029A (en) * | 1998-02-20 | 1999-09-29 | 日本电气株式会社 | Vertical type metal insulator semiconductor field effect transistor and method of its production |
| CN1234613A (en) * | 1998-04-23 | 1999-11-10 | 国际整流器有限公司 | P-shape channelled metal-oxide semiconductor FET transistor structure |
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