CN1312328C - Methd for preparing monocrystalline silicon nano membrane for nano photon technique - Google Patents
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Abstract
Description
技术领域technical field
本发明涉及纳米材料的制备方法,特别是涉及一种用于纳米光子技术的单晶硅纳米膜的制备方法。The invention relates to a preparation method of nanometer materials, in particular to a preparation method of a single crystal silicon nanofilm used in nanophoton technology.
背景技术Background technique
基于硅材料的纳米光子技术是实现高密度光子集成和高速光互连的重要技术手段。进行硅纳米光子技术研究,硅纳米光子材料的制备是基础。制备硅纳米光子材料的基本思路包括自下而上的方法与自上而下的方法。自下而上的方法主要是采用化学生长的方法,制备包括硅纳米线、硅纳米带和硅纳米管等的硅基纳米光子材料,虽然这是重要的发展方向,但在目前,从纳米光子技术要求的角度上来看,这些硅纳米光子材料无论在光传输特性、结构尺寸,还是器件加工手段上,都远不能够用于实际器件与模块化的研究与开发。自上而下的方法是目前大规模生产的主流技术手段,主要利用已经发展起来的微细加工手段。目前用于硅纳米光子技术研究的材料主要为绝缘体上硅(SOI:Silicon-on-Insulator)材料。虽然基于智敏分离(Smart Cut)技术的绝缘体上硅材料一定程度上可以用于硅纳米光子器件的研究,但是由于绝缘体上硅材料中的氧化隔离层的有限厚度限制了硅纳米线的尺寸,当硅层极薄时,无法保证光隔离作用。为了消除绝缘体上硅材料有限厚度的氧化隔离层对硅纳米光子技术研究的限制,本发明提出了利用绝缘体上硅键合与选择性自停止腐蚀制备单晶硅纳米膜的方法。Nanophotonic technology based on silicon materials is an important technical means to realize high-density photonic integration and high-speed optical interconnection. The preparation of silicon nanophotonic materials is the basis for silicon nanophotonic technology research. The basic idea of preparing silicon nanophotonic materials includes bottom-up method and top-down method. The bottom-up method mainly uses the method of chemical growth to prepare silicon-based nanophotonic materials including silicon nanowires, silicon nanobelts and silicon nanotubes. Although this is an important development direction, at present, from nanophotonics From the perspective of technical requirements, these silicon nanophotonic materials are far from being able to be used in the research and development of actual devices and modularization in terms of optical transmission characteristics, structural dimensions, and device processing methods. The top-down method is the mainstream technical means of mass production at present, mainly using the developed micro-fabrication means. The material currently used in the research of silicon nanophotonic technology is mainly silicon-on-insulator (SOI: Silicon-on-Insulator) material. Although silicon-on-insulator materials based on Smart Cut technology can be used in the research of silicon nanophotonic devices to a certain extent, due to the limited thickness of the oxide isolation layer in silicon-on-insulator materials, the size of silicon nanowires is limited. When the silicon layer is extremely thin, the optical isolation effect cannot be guaranteed. In order to eliminate the limitation of silicon nanophoton technology research by the limited thickness of the oxidation isolation layer of the silicon material on the insulator, the present invention proposes a method for preparing a single crystal silicon nano film by using silicon bonding and selective self-stop etching on the insulator.
发明内容Contents of the invention
本发明的目的在于提供一种用于纳米光子技术的单晶硅纳米膜的制备方法,所制备的单晶硅纳米膜可以用于进行硅纳米光子技术的研究。The object of the present invention is to provide a method for preparing a single-crystal silicon nanofilm for nanophotonic technology, and the prepared single-crystal silicon nanofilm can be used for research on silicon nanophotonic technology.
本发明解决其技术问题所采用的技术方案是采用的步骤如下:The technical solution adopted by the present invention to solve its technical problems is to adopt the steps as follows:
1)将具有50~200nm厚度的绝缘体上硅片和衬底片进行清洗后烘干;1) cleaning and drying the silicon-on-insulator wafer and the substrate wafer having a thickness of 50-200nm;
2)将绝缘体上硅片的顶层硅一侧和衬底片进行键合;2) bonding the top silicon side of the silicon-on-insulator wafer to the substrate wafer;
3)去除键合后的绝缘体上硅片的底层硅。3) Removing the underlying silicon of the bonded silicon-on-insulator wafer.
采用的衬底片为折射率小于硅材料的至少一面抛光的体材料,键合时抛光面与绝缘体上硅片进行键合;或者,采用的衬底片为至少具有一层折射率小于硅材料的薄膜的材料,薄膜的厚度大于光隔离所要求的厚度,键合时薄膜一侧与绝缘体上硅片进行键合。The substrate used is a polished bulk material with at least one side of the material whose refractive index is lower than that of the silicon material, and the polished surface is bonded to the silicon wafer on the insulator during bonding; The thickness of the film is greater than the thickness required for optical isolation. When bonding, one side of the film is bonded to the silicon on the insulator.
采用的衬底片为至少一面抛光的玻璃片,或者为至少一面抛光的石英片,或者为至少一面抛光的铌酸锂片,或者为具有氧化硅层的硅片,或者为具有氮化硅的硅片,或者为具有氮氧化硅的硅片。The substrate used is a glass plate with at least one side polished, or a quartz plate with at least one side polished, or a lithium niobate plate with at least one side polished, or a silicon plate with a silicon oxide layer, or a silicon plate with silicon nitride. sheet, or a silicon sheet with silicon oxynitride.
采用的绝缘体上硅片的顶层硅上有一层折射率小于硅材料折射率的薄膜材料,薄膜的厚度大于光隔离所要求的厚度;采用的衬底片为至少一面抛光的体材料,或者具有二氧化硅层薄膜的材料。The top layer of silicon on the silicon-on-insulator wafer used has a thin film material with a refractive index lower than that of the silicon material, and the thickness of the film is greater than the thickness required for optical isolation; the substrate used is a bulk material with at least one side polished, or has a Silicon film material.
采用的绝缘体上硅片的顶层硅上有一层二氧化硅薄膜,或者氮化硅薄膜,或者氮氧化硅薄膜;采用的衬底片为至少一面抛光的硅片,或者至少一面抛光的玻璃片,或者至少一面抛光的石英片。There is a layer of silicon dioxide film, or silicon nitride film, or silicon oxynitride film on the top silicon of the silicon-on-insulator wafer used; the substrate wafer used is a silicon wafer with at least one side polished, or a glass wafer with at least one side polished, or A quartz plate with at least one side polished.
采用的键合方法是静电键合,键合温度为200-600℃,键合电压为50-1500伏;或者,采用的键合方法是热键合,键合温度为200-1000℃。The bonding method adopted is electrostatic bonding, the bonding temperature is 200-600°C, and the bonding voltage is 50-1500 volts; or, the bonding method adopted is thermal bonding, and the bonding temperature is 200-1000°C.
去除绝缘体上硅片的底层硅的方法为干法刻蚀,或者湿法腐蚀,或者是结合研磨抛光,再干法刻蚀或湿法腐蚀的组合方法;相对于二氧化硅材料,要求刻蚀或腐蚀过程对硅有选择性。The method of removing the underlying silicon of the silicon wafer on the insulator is dry etching, or wet etching, or a combination method combined with grinding and polishing, and then dry etching or wet etching; compared with silicon dioxide materials, etching is required Or the etch process is selective to silicon.
在进行步骤3)之后,采用干法刻蚀,或者湿法腐蚀,或者是结合研磨抛光,再干法刻蚀或湿法腐蚀的组合方法去除绝缘体上硅片的氧化隔离层;相对于硅材料,要求刻蚀或腐蚀过程对二氧化硅有选择性。After performing step 3), dry etching, or wet etching, or a combination of grinding and polishing, dry etching or wet etching is used to remove the oxide isolation layer of the silicon wafer on the insulator; relative to the silicon material , requiring the etch or etch process to be selective to silicon dioxide.
在进行步骤2)的键合之前,采用氧化的方法将绝缘体上硅的顶层硅进行减薄,减薄的厚度值由所需要的纳米膜厚度决定。Before performing the bonding in step 2), the silicon on the top layer of the silicon-on-insulator is thinned by oxidation, and the thinned thickness is determined by the required nanometer film thickness.
在进行步骤2)的键合之前,对绝缘体上硅片和衬底片的键合面一侧进行预处理,制作金属电极,刻蚀结构。Before performing the bonding in step 2), pretreatment is performed on the side of the bonding surface of the silicon-on-insulator wafer and the substrate wafer, metal electrodes are fabricated, and the structure is etched.
本发明具有的有益的效果是:The beneficial effects that the present invention has are:
1、采用本发明制备的硅纳米膜材料的光下限制层有足够的厚度可以实现光隔离,可以进行纳米尺寸硅光子器件研制,这是普通绝缘体上硅片材料的中间氧化层所无法保证的;1. The optical confinement layer of the silicon nanofilm material prepared by the present invention has sufficient thickness to realize optical isolation, and can carry out the development of nanometer-sized silicon photonic devices, which cannot be guaranteed by the intermediate oxide layer of silicon wafer materials on ordinary insulators ;
2、采用本发明制备的硅纳米膜材料的单晶硅层厚度可以从十几纳米到几百纳米,厚度均匀性高;2. The thickness of the monocrystalline silicon layer of the silicon nano-film material prepared by the present invention can be from tens of nanometers to hundreds of nanometers, and the thickness uniformity is high;
3、采用本发明的制备过程,可以根据实际器件制作过程中的需要,在绝缘体上硅片和衬底材料的键合面上进行预处理,设置电极,实现特定图案等,这是直接采用绝缘体上硅片材料所无法进行的。3. By adopting the preparation process of the present invention, according to the needs in the actual device manufacturing process, pretreatment can be carried out on the bonding surface of the silicon chip on the insulator and the substrate material, electrodes are arranged, and specific patterns are realized. This is directly using the insulator What cannot be done on silicon wafer materials.
具体实施方式Detailed ways
实施例1:采用一片具有200nm厚顶层硅的绝缘体上硅片,以有着15μm厚二氧化硅层的硅片为衬底片,进行常规清洗后烘干。将绝缘体上硅片的顶层硅和硅片的二氧化硅层这一面相对叠放,置于键合机上进行热键合,键合温度为800℃间。键合后,将键合的片子放入40%浓度的氢氧化钾溶液中进行湿法腐蚀,腐蚀掉绝缘体上硅片的底层硅。片子进一步放入氢氟酸溶液中进行湿法腐蚀,去除绝缘体上硅片的氧化隔离层。最终可以制备出以硅为衬底的、有着15μm厚二氧化硅层的光隔离层的、具有约200nm硅膜的硅纳米膜材料。Embodiment 1: A silicon-on-insulator wafer with a 200 nm thick top layer of silicon is used, and a silicon wafer with a 15 μm thick silicon dioxide layer is used as a substrate, which is cleaned and dried after conventional cleaning. Stack the top layer silicon of the silicon-on-insulator wafer and the silicon dioxide layer of the silicon wafer facing each other, place them on a bonding machine for thermal bonding, and the bonding temperature is between 800°C. After bonding, put the bonded chips into a 40% potassium hydroxide solution for wet etching to etch the underlying silicon of the silicon chip on the insulator. The chip is further put into a hydrofluoric acid solution for wet etching to remove the oxide isolation layer of the silicon chip on the insulator. Finally, a silicon nano-film material with a silicon substrate, an optical isolation layer with a thickness of 15 μm of silicon dioxide, and a silicon film of about 200 nm can be prepared.
实施例2:采用一片具有100nm顶层硅的绝缘体上硅片,以玻璃片为衬底片,进行常规清洗后烘干。将绝缘体上硅片的顶层硅和玻璃片的抛光面相对叠放,置于静电键合机上进行静电键合,键合温度为300℃间,键合电压900伏。键合后,将键合的片子的绝缘体上硅一面朝上,置于干法刻蚀设备中,用干法刻蚀方法刻蚀掉绝缘体上硅片的底层硅。由此,制备出以玻璃为衬底的、顶层尚有一层二氧化硅层为上限制层的、具有约100nm硅膜的硅纳米膜材料。Embodiment 2: A silicon-on-insulator wafer with 100nm top layer of silicon is used, and a glass wafer is used as the substrate, which is cleaned and dried after conventional cleaning. Stack the top layer of silicon on the silicon-on-insulator wafer and the polished surface of the glass wafer, and place them on an electrostatic bonding machine for electrostatic bonding. The bonding temperature is between 300°C and the bonding voltage is 900 volts. After bonding, the silicon-on-insulator (SOI) side of the bonded wafers is placed upwards, placed in a dry etching device, and the underlying silicon of the silicon-on-insulator wafers is etched away by dry etching. Thus, a silicon nano-membrane material with a silicon film of about 100 nm is prepared, which uses glass as a substrate, and has a silicon dioxide layer as an upper limiting layer on the top layer.
实施例3:采用一片具有50nm顶层硅的绝缘体上硅片,以硅片为衬底片,进行常规清洗后烘干。首先在绝缘体上硅片上生长15μm厚氮化硅层,然后将生长后的绝缘体上硅片和硅片的抛光面相对叠放,置于键合机上进行热键合,键合温度为900℃间。键合后,采用组合方法,首先对键合的片子绝缘体上硅一面进行研磨抛光,当硅层厚度在50-100μm时,放入40%浓度的氢氧化钾溶液中进行湿法腐蚀,腐蚀掉绝缘体上硅片的底层硅。由此,制备出以硅为衬底的、有着15μm厚氮化硅层的光隔离层的、顶层尚有一层二氧化硅层为上限制层的、具有约50nm硅膜的硅纳米膜材料。Embodiment 3: A silicon-on-insulator wafer with a 50nm top layer of silicon is used, and the silicon wafer is used as the substrate, and is dried after conventional cleaning. First grow a silicon nitride layer with a thickness of 15 μm on the silicon-on-insulator wafer, then stack the grown silicon-on-insulator wafer and the polished surface of the silicon wafer opposite each other, and place them on a bonding machine for thermal bonding. The bonding temperature is 900°C between. After bonding, use a combined method to first grind and polish the silicon side of the bonded sheet insulator. When the thickness of the silicon layer is 50-100 μm, put it into a 40% concentration of potassium hydroxide solution for wet etching to etch away The underlying silicon of a silicon-on-insulator wafer. Thus, a silicon nano-membrane material with silicon as the substrate, an optical isolation layer with a thickness of 15 μm silicon nitride layer, a silicon dioxide layer as the upper limiting layer on the top layer, and a silicon film of about 50 nm is prepared.
实施例4:采用一片具有200nm顶层硅的绝缘体上硅片,以玻璃片为衬底片,进行常规清洗后烘干。首先将绝缘体上硅片进行湿氧氧化,在表面氧化出约250nm的二氧化硅,在此二氧化硅层下的顶层硅将为约100nm。然后绝缘体上硅片的顶层硅和玻璃片的抛光面相对叠放,置于静电键合机上进行静电键合,键合温度为500℃间,键合电压1200伏。键合后,对键合的片子绝缘体上硅一面进行研磨抛光,当硅层厚度在50-100μm时,将键合的片子的绝缘体上硅一面朝上,置于干法刻蚀设备中,用干法刻蚀方法刻蚀掉绝缘体上硅片的底层硅。由此,制备出以玻璃为衬底的、顶层尚有一层二氧化硅层为上限制层的、具有约100nm硅膜的硅纳米膜材料。Embodiment 4: A silicon-on-insulator wafer with a top silicon layer of 200 nm is used, and a glass wafer is used as a substrate, which is cleaned and dried after conventional cleaning. First, the silicon-on-insulator wafer is oxidized by wet oxygen, and about 250nm of silicon dioxide is oxidized on the surface, and the top layer of silicon under this silicon dioxide layer will be about 100nm. Then the top layer of silicon on the silicon wafer on the insulator and the polished surface of the glass wafer are superimposed and placed on an electrostatic bonding machine for electrostatic bonding. The bonding temperature is between 500°C and the bonding voltage is 1200 volts. After bonding, grind and polish the silicon-on-insulator side of the bonded sheet. When the thickness of the silicon layer is 50-100 μm, place the silicon-on-insulator side of the bonded sheet facing up and place it in a dry etching device. The underlying silicon of the silicon-on-insulator wafer is etched away by dry etching. Thus, a silicon nano-membrane material with a silicon film of about 100 nm is prepared, which uses glass as a substrate, and has a silicon dioxide layer as an upper limiting layer on the top layer.
实施例5:采用一片具有200nm顶层硅的绝缘体上硅片,以石英片为衬底片,进行常规清洗后烘干。在绝缘体上硅片表面进行光刻和腐蚀,制作出宽度为200nm的硅纳米直线。再将绝缘体上硅片的顶层硅和石英片的抛光面相对叠放,置于键合机上进行热键合,键合温度为700℃间。键合后,将键合的片子放入40%浓度的氢氧化钾溶液中进行湿法腐蚀,腐蚀掉绝缘体上硅片的底层硅。片子进一步放入氢氟酸溶液中进行湿法腐蚀,去除绝缘体上硅片的氧化隔离层。由此,制备出以石英为衬底的、具有约200nm厚和200nm宽的硅纳米膜材料。Embodiment 5: A silicon-on-insulator wafer with a 200 nm top layer of silicon is used, and a quartz wafer is used as a substrate, and is dried after conventional cleaning. Photolithography and etching were carried out on the surface of the silicon wafer on insulator to produce silicon nanometer straight lines with a width of 200 nm. Then stack the top layer silicon of the silicon-on-insulator wafer and the polished surface of the quartz wafer, and place them on a bonding machine for thermal bonding at a bonding temperature of 700°C. After bonding, put the bonded chips into a 40% potassium hydroxide solution for wet etching to etch the underlying silicon of the silicon chip on the insulator. The chip is further put into a hydrofluoric acid solution for wet etching to remove the oxide isolation layer of the silicon chip on the insulator. Thus, a silicon nano-film material with a thickness of about 200nm and a width of 200nm is prepared using quartz as a substrate.
本发明的实施方式有多种,以上列举了5个实施例,用来解释说明本发明,但决非仅限于此5个实施例,而不是对本发明进行限制,在本发明的精神和权利要求的保护范围内,对本发明作出的任何修改和改变,都落入本发明的保护范围。There are multiple implementations of the present invention, above enumerated 5 embodiments, are used for explaining the present invention, but are not limited to these 5 embodiments by no means, rather than limit the present invention, in the spirit of the present invention and claims Within the protection scope of the present invention, any modifications and changes made to the present invention fall within the protection scope of the present invention.
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