CN1306824C - Image boundarg pixel extending system and its realizing method - Google Patents

Abstract

The present invention relates to a system and a method for expanding image boundary pixels in a video decoding chip. The system comprises a reconstructed frame storing circuit, a variable-length decoder, an intraframe predicting circuit and a storage controller, wherein the variable-length decoder transmits a control command signal to the reconstructed frame storing circuit; the intraframe predicting circuit transfers data to the reconstructed frame storing circuit; the storage controller stores and processes output data of the reconstructed frame storing circuit comprising a control command storage, an image data storage and an image boundary pixel expanding module circuit; the control command storage stores the control command signal input by the variable-length decoder; the image data storage stores image data input by an intraframe predictor, and the length of the bit number of the image data is variable; the image boundary pixel expanding module circuit analyzes the an image control signal and repeatedly expands edge pixels and corner point pixels outwards, and expanded pixel data is stored in a dynamic storage. The present invention has the advantages of great coding gain obtainment, motion vector range expansion and efficiency improvement of the digital video decoding chip.

Description

Image boundarg pixel extending system and its implementation

Technical field

The present invention relates to the encoding and decoding technique field of digital video in the digital TV image processing, especially relate to image boundarg pixel extending system and its implementation in a kind of video decoding chip, when the reference macroblock of a certain motion vector indication is positioned at outside the coded image, replace this non-existent macro block (macroblock) with regard to image pixel value, thereby realize this decoding technique of unrestricted motion vector with its edge.

Background technology

In the whole video decode system, motion compensation is a link with critical role.Motion vector is the basis of carrying out motion compensation, and in the prior art, the scope of general motion vector all is limited in the reference frame of having encoded.This restriction, when feasible macro block to the current frame image border carries out estimation, can't obtain optimum effect because reference macroblock may be in outside the reference frame, the compression standard before the standard MPEG-2 of Motion Picture Experts Group and International Telecommunications Union's video encoding and decoding standard all are like this in H.261.H.263, cancelled this restriction among MPEG-4 and the Chinese audio/video encoding/decoding national standard AVS1.0, allow the zone beyond the motion vector points image.But this technology that standard allows fails to realize always

Summary of the invention

In order to solve the deficiencies in the prior art, the object of the present invention is to provide a kind of image boundarg pixel extending system and its implementation, the coding gain when allowing the motion vector points image with exterior domain to improve.

Another object of the present invention is to provide a kind of image boundarg pixel extending system and its implementation, allows to use bigger motion vector, and the scope of extension movement vector is to have improved the efficient that digital video is separated coding.

For finishing above-mentioned purpose, the overall technological scheme that the present invention adopts is: image boundarg pixel extending system, comprise length variable decoder, intraframe prediction circuit, Memory Controller, inverse quantization circuit, inverse transform circuit, dynamic memory and movement compensating circuit, length variable decoder is connected with other device with control bus by command line, between length variable decoder and the intraframe prediction circuit movement compensating circuit is arranged, this system also includes the reconstruction frames memory circuit, length variable decoder is to reconstruction frames memory circuit transmitting control commands signal, intraframe prediction circuit transmits data to the reconstruction frames memory circuit, Memory Controller carries out stores processor to the dateout of rebuilding frame memory circuit, the reconstruction frames memory circuit comprises image control information memory, image data memory and image boundarg pixel expansion module circuit, the control command signal of image control information memory stores length variable decoder input, the image data memory storage is by the view data of intra predictor generator input, image boundarg pixel expansion module circuit analysis diagram is as control signal, edge and corner pixels are outwards repeated to expand, and the pixel data after the expansion deposits dynamic memory in.

Described image control information memory is that bit wide is that 32, the degree of depth are 8 register array.

Described image data memory is that 64 of two width, the degree of depth are 48 random asccess memory, and 64 input data are converted to the output of 128 bit data.

The image control signal of described length variable decoder input comprises clock sync signal, write order and data command, order data and image information data at least.

The form of the image control information of described length variable decoder input comprises initialization information, image sequence level information, frame level information, macro-block level information; Initialization information comprises initializing signal, and the 0-15 position in 32 of described initialization information provides image logical storage width; The width of every two field picture in 2～13 these image sequences of bit flag of the information of image sequence level, the height of every two field picture in this image sequence of 14-29 bit flag of the information of described image sequence level; The plot of the every two field picture of 6-25 bit flag of frame level information; The vertical relative address of 0-6 bit flag macro block in every two field picture of macro-block level information, the horizontal direction relative address of 7-13 bit flag macro block in every two field picture of described macro-block level information.

The output information of described image control information memory comprises at least: feed back to length variable decoder memory command, deposit read data order to image boundarg pixel expansion module circuit.

Described intra predictor generator comprises clock sync signal, write data order, input data at least to the image data information of image data memory input.

Described image data memory comprises at least to the information of image boundarg pixel expansion module circuit output: feed back to intra predictor generator memory command, deposit read data order to primary module.

The extended method of image boundarg pixel extending system, this system comprises length variable decoder, intraframe prediction circuit, Memory Controller, inverse quantization circuit, inverse transform circuit, dynamic memory, movement compensating circuit and reconstruction frames memory circuit, and this method may further comprise the steps at least:

Step 1, length variable decoder send control information to the image control information memory of reconstruction frames memory module;

Step 2, image control information memory send image information data to image boundarg pixel expansion module circuit;

Step 3, whether image boundarg pixel expansion module circuit judges will carry out figure expands to boundary pixel, is then to receive the view data that the intra predictor generator transmission comes to flow in the image data stream memory execution in step 4; Otherwise finish;

Step 4, image boundarg pixel expansion module circuit are set up iconic model in conjunction with the data in two memories, and edge and corner pixels are outwards repeated to expand;

Step 5, the storage after will expanding are in dynamic memory.

The view data that image control information memory in the described step 2 sends to image boundarg pixel expansion module circuit is 128 bit data that converted to by 64 bit data of importing.

Described 64 bit data by input convert 128 bit data to and specifically comprise following switch process:

Step 21, intraframe prediction circuit module I P are unit with 64, write 8 numbers at every turn image data stream is write the image data stream memory, intersect per 8 number writing lines are elected as in 0 and 1 the random asccess memory;

Whether step 22, image data stream memory judgment data have stored, and are then 128 bit data in 0 and 1 two random asccess memory to be done as a whole reading, execution in step 23; Otherwise finish;

Step 23, the data of reading are sent into image boundarg pixel expansion module circuit.

Edge and corner pixels outwards being repeated expand in the described step 4 is meant: in the horizontal direction, each expands 16 pixel p ixel respectively to the right left, in vertical direction, expands 8 pixel p ixel for UV, expands each pixel 16pixel for Y.

Described step 4 further comprises:

Step 41, judge the pattern and the type of decoded bit stream, if decoded bit stream is a frame progressive die formula, then carry out following expansion: for brightness Y, it is that unit directly outwards repeats to expand 16 times that the MB unit at periphery place expands with the edge pixel, the corner pixels that corner expands with the MB of corner is that unit outwards repeats to expand 16 * 16 times, for colourity UV, on left and right directions, respectively the boundary pixel unit of U and V is synthesized one with a U pixel cell and the integral body that the V pixel cell is a unit, expand to the left or to the right respectively 8 times, after on the above-below direction U and V being intersected, expand respectively 8 times, around the corner, the corner point pixel cell of the corner point pixel cell of U and V is integrated, expands 16 * 8 times;

If step 42 decoded bit stream is a progressive die formula, then further judge it is field, top or field, the end, if enter code stream is the field, top, then be as the criterion with first trip calculated address, interlacing is carried out address computation and is stored data with this saltus step address to dynamic memory, and left with the right side, top, to the left side and the right and top margin expansion pixel to the top of image according to the method for step 41;

If it is field, the end that step 43 enters code stream, be as the criterion with first trip calculated address, interlacing is carried out address computation and is stored data with this saltus step address to dynamic memory, and according to the method for step 41 to the left side, the end of image and the right side, the end, to the left side and the right and base expansion pixel.

Storage in the described step 5 specifically may further comprise the steps:

The pattern and the type of step 51, judgement decoded bit stream, if decoded bit stream is a frame progressive die formula, to brightness Y, just write in the dynamic memory if the image subject part has directly been calculated the address, if expansion, calculating under the prerequisite of address, be written in the dynamic memory by the order that expands, for colourity UV, if main part has been calculated the address, depositing dynamic memory in after U and the V intersection, if expansion having calculated under the prerequisite of address, is written in the dynamic memory by expansion in proper order;

Step 52, if decoded bit stream is imported with field progressive die formula, to brightness y, if main part, directly having calculated the address writes in the dynamic memory, if expansion, for the field, top, need to calculate to expand to and push up a left side, top margin, the top is right, the left side, the memory address of the data on the right, store then,, need calculating to expand to a left side, the end for field, the end, the base, the right side, the end, the left side, the memory address of the data on the right, be written to dynamic memory in proper order by expansion then, for colourity UV, if main part has been calculated the address, depositing dynamic memory in after U and the V intersection, if expansion for the field, top, needs to calculate expand to and pushes up a left side, top margin, the top is right, the left side, the memory address of the data on the right, store then, for field, the end, need calculating to expand to a left side, the end, the base, the right side, the end, the left side, the memory address of the data on the right is written in the dynamic memory in proper order by expansion then.

The present invention has tangible advantage and good effect.Image boundarg pixel extending system of the present invention and its implementation have realized the hardware expanding system and the extended method of boundary pixel expansion, allow motion vector points image zone in addition, when the reference macroblock of a certain motion vector indication is positioned at outside the coded image, replace this non-existent macro block with the image pixel value at its edge.The present invention has expanded the scope of motion vector, allows to use bigger motion vector, when having cross-border motion vector, can obtain very big coding gain, realizes the raising of coding gain, and particularly for little image, effect is better.Simultaneously, method of the present invention has also been saved hardware memory space, has improved data-handling efficiency, and the application of two-dimensional storage makes the speed of hardware handles improve.Be specially adapted to the coding chip of separating of digital-video equipments such as digital camera.

Description of drawings

Fig. 1 is a system of the present invention pie graph;

Fig. 2 is the structural representation of reconstruction frames memory of the present invention;

Fig. 3 is an image control command information memory command input and output schematic diagram of the present invention;

Fig. 4 is an image data memory data input and output schematic diagram of the present invention;

Fig. 5 is an image data memory storage operation principle schematic diagram of the present invention;

Fig. 6 is an image boundarg pixel expansion module circuit data input and output framework schematic diagram of the present invention;

Fig. 7 is the integral layout schematic diagram that boundary pixel of the present invention expands to the border;

Fig. 8 is that frame progressive die formula lower boundary pixel of the present invention is to a left side, top, the right expansion process schematic diagram in top;

Fig. 9 is that frame progressive die formula lower boundary pixel of the present invention is to a left side, the end, the end right expansion process schematic diagram;

Figure 10 is that frame progressive die formula lower boundary pixel of the present invention expands the process schematic diagram as top margin, the left side, base, the right;

Figure 11 is a main part storing process schematic diagram under the frame progressive die formula of the present invention;

Figure 12 is that boundary pixel to colourity expands the process schematic diagram under the frame progressive die formula of the present invention;

Figure 13 is that of the present invention progressive die formula lower boundary pixel expands the schematic layout pattern of process;

Figure 14 is the interface schematic diagram of output interface of the present invention and dynamic memory.

Embodiment

The present invention is further detailed explanation below in conjunction with the drawings and specific embodiments.

See also Fig. 1, image boundarg pixel extending system, comprise length variable decoder VLD, intraframe prediction circuit (IP, Intra prediction), Memory Controller (SRAM Controller), inverse quantization circuit, inverse transform circuit, dynamic memory (DRAM) and movement compensating circuit, length variable decoder is connected with other device with control bus by command line, between length variable decoder and the intraframe prediction circuit movement compensating circuit is arranged, reconstruction frames memory circuit (REFERENCE STORE) is connected with intraframe prediction circuit, and be connected with length variable decoder by command line, length variable decoder is to reconstruction frames memory circuit transmitting control commands signal, intraframe prediction circuit transmits data to the reconstruction frames memory circuit, Memory Controller carries out stores processor to the dateout of rebuilding frame memory circuit, the reconstruction frames memory circuit comprises former and later two pushup storages and image boundarg pixel expansion module circuit, the control command signal and the image data stream of former and later two memory stores inputs, image boundarg pixel expansion module circuit analysis diagram is as control signal, edge and corner pixels are outwards repeated to expand, and the pixel data after the expansion deposits dynamic memory in.

See also Fig. 2, the reconstruction frames memory circuit mainly comprises three parts, two pushup storages (FIFO) and primary module image boundarg pixel expansion module circuit (ref_store), two memories are meant the image control information memory CMDFIFO of storage length variable decoder input and the decoded image data memory DATAFIFO of storage intraframe prediction circuit input.

The extended method of image boundarg pixel extending system of the present invention mainly contains following steps:

At first, length variable decoder VLD sends control information to the image control information memory CMDFIFO of reconstruction frames memory module (REFRENCE STORE);

Afterwards, image control information memory CMDFIFO sends image information data to image boundarg pixel expansion module Schaltkreis ef_store;

Next, image boundarg pixel expansion module Schaltkreis ef_store judges whether to carry out figure and expands to boundary pixel, is then to receive the next view data of intra predictor generator IP transmission to flow to DATAFIFO in the image data stream memory; Otherwise finish;

Then, image boundarg pixel expansion module Schaltkreis ef_store sets up iconic model in conjunction with the data in two memory FIFO, and edge and corner pixels are outwards repeated to expand;

At last, with the expansion after storage in dynamic memory DRAM.

See also Fig. 3, image control information memory is that bit wide is that 32bit, the degree of depth are 8 register array, and length variable decoder comprises that to the image control information CMD of image control information memory input clock sync signal, replacement order, write order and data command, order data and view data and memory correctly reply and end signal.Its input and output information is as follows:

Input: I_CLK I_DATA_WR

I_CLK_INV I_DATA

I_RESET I_SRAM_ACK

I_CMD_WR I_SRAM_END

I_CMD_DATA

Output:

O_CMD_FIFO_FULL O_SRAM_SIZE

O_DATA_FIFO_FULL O_SRAM_LINES

O_SRAM_REQ O_SRAM_PITCH

O_SRAM_ADDR O_SRAM_WDATA

Image control information memory output information comprises: feed back to length variable decoder memory command and data flooding information, deposit read data order and main memory module request, address and size thereof, row, location and write data order to image boundarg pixel expansion module circuit.

What VLD sent to image boundarg pixel expansion module circuit REFERENCE STORE is CMD image control signal, and the information that this control signal comprises has:

1,4 orders

0initial (initialization level)

1seq (sequence level)

2frm (frame level)

3mb (macroblock level)

The concrete format assignment of cmd data message is as shown in table 1: LEVEL0 comprises initializing signal, provides DRAM width by the 0-15 position among the 32bit, thereby determines the picture traverse of logical storage.What LEVEL1 comprised is the information of image sequence level, the width (img-width) of every two field picture in its this image sequence of 2-13 bit flag, the height (img-height) of every two field picture in this image sequence of 14-29 bit flag.What LEVEL2 comprised is frame level information, the plot of the every two field picture of its 6-25 bit flag.What LEVEL3 comprised is macro-block level information, the vertical relative address (mb-y) of its 0-6 bit flag macro block in every two field picture, the horizontal direction relative address (mb-x) of its 7-13 bit flag macro block in every two field picture.30～31 of the cmd data as other flag bit of image information level.

Table 1

level＝0(Initialization level)；DRAM width
					31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Level
					15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DRAM width
					level＝1(seq Level)；
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
					Level Img width
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
					Img height
level＝2(Ftame Level)
					31 30 29	28	27	26	25 24 23 22 21 20 19 18 17 16
Level				DRAM Address
					15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
for the pic to be stored top_field_first Frm/Fld
					Annotate: 1.frame/field type 1-frame 0-field 1.top field_first 1-top field first 0-bottom field first
level＝3(mb level)
					31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Level
					15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mb_x Mb_y

1, CMD number: 1/app 1/sequence 1/frm 1/mb

2, parameter:

1)img height and img width

2)DRAM Address

3)mbx and mby

2, the data stream format of CMD

Initial pictures control information data stream is as shown in table 2.

Table 2

Level0

lnitializatio

Level

seq

Level2

pic

Level3

MB

Level3

MB

n

1

Every two field picture control information data stream is as shown in table 3.

Table 3

Level2

pic

Level 3

MB

Level 3

MB

Level 3

MB

5

See also Fig. 4, image data memory is to frame prediction circuit (IP, Intra-Prediction) the decoded view data DATA that finishes that sends stores, provide for image boundarg pixel expansion module Schaltkreis ef_store need image spreading (padding) data in, also provide function served as bridge for the direct output that does not need the image expanding data.

Intraframe prediction circuit comprises clock sync signal, replacement order, write data order, the order of data ready for sending, data entry command to the information of reconstruction frames memory input decoded image data memory.Image data memory comprises to the information of primary module output: feed back to intra predictor generator memory command and data flooding information, deposit read data order to primary module.

See also Fig. 5, image data memory is that two width 64bit, the degree of depth are 48 random asccess memory, and it can be converted to the output of 128bit data to the input data of 64bit.The input data of 64bit are converted to 128bit data output, and this is that change by the mode of storage realizes.Concrete mode is:

1, write data: the image data stream that is write by IP is to be unit with 64bit, write 8 numbers at every turn, 8 numbers that write are first put into the RAM that row is elected 0 64bit as, as the RAM on the left side among Fig. 5,, 8 numbers that write are for the second time put into RAM such as Fig. 5 right side RAM that row is elected 1 64bit as, 8 numbers that write are for the third time put into row and are elected 0 RAM as, 8 numbers that write for the 4th time are put into row and are elected 1 RAM as, and the rest may be inferred, stores the image data stream of all inputs.

2, sense data: two RAM do as a whole reading, and promptly make as a whole beginning writes number from 128bit to DRAM as Y0Y1.

See also Fig. 6, image boundarg pixel expansion module Schaltkreis ef_store is as the primary module of reconstruction frames memory REFERENCE STORE, need resolve to the cmd image control signal of the image control command information memory transmission of reconstruction frames memory variable length encoder, need simultaneously in conjunction with cmd image control signal identification current image date type: frame progressive die formula, a top progressive die formula, field, end progressive die formula, and the corresponding storage first address that sends to dynamic memory that calculates, simultaneously the image data stream data that is sent by intraframe prediction circuit is carried out extension process padding, and need handle the intersection output of pixel among U and the V.

See also Fig. 7, pending image division is nine kinds of situations, and what expansion PADDING was related is the boundary member of image, character string among the figure and Arabic numerals as in the code to the sign of nine kinds of situations of image.The scope of expansion is: in the horizontal direction, each expands 16 pixel p ixel respectively to the right left; In vertical direction,, only need expansion 8pixe1, for brightness Y expansion 16pixel for colourity UV.It repeats to extend out with the edge pixel unit of boundary macroblocks (mb) and forms, and the method for expansion is:

At the expansion on the left and right directions of top/bottom part such as Fig. 8, shown in Figure 9, the order of expansion is: from main part MAIN, launch according to abcdefghijkl.

1.TOP_LEFT； 3.BOT_LEFT；

2.TOP_RIGHT； 4.BOT_RTGHT.

Expand as shown in figure 10 on top, the end, left and right edge direction, the order of expansion is: from main part MAIN, launch according to abcdef.

5.TOP_EDGE； 6.BOT_EDGE；

7.LEFT_EDGE； 8.RIGHT_EDGE

The order of main part MAIN is as shown in figure 11: carry out according to abc.

The general trend of the order that expands is carried out clockwise, has the higher data treatment effeciency like this and saves memory space.For example, take out at first that to need expanded data be (y0y1) of the luminance component of the left MB in top, obtain just to begin to carry out and the relevant expansion of this piece (y0y1) after the data: expansion left forms the luminance component (y0y1) of left side expansion, deposits in the dynamic memory simultaneously; Then expand to the luminance component (y0y1) of upper left corner expansion, store in the dynamic memory simultaneously; Expand to the luminance component (y2y3) of upper left corner expansion then, store in the dynamic memory simultaneously; Expand to the luminance component (y0y1) of top expansion then, store in the dynamic memory simultaneously; Expand to the luminance component (y2y3) of top expansion at last, store in the dynamic memory simultaneously; All do with (y0y1) relevant extension process of the luminance component that pushes up left macro block MB like this and be over, all data have also all been stored simultaneously, next begin (y2y3) of the luminance component of the consideration left macro block in top (MB), after same method is finished, begin to push up the pixel-expansion of (uv) of the chromatic component of left macro block MB.The pixel-expansion of other boundary members is also followed this principle and is carried out the boundary pixel expansion.Such benefit has two: one, the process of processing also are the processes to dynamic memory storage data, so just can save memory space earlier because the storage that pixel-expansion needs gets up to carry out pixel-expansion again; Its two, mainly be only obtain will with data handle, and can not obtain the data of whole macro block and then carry out edge pixel expansion, reduced data redundancy, improved the efficient of deal with data.Storage mode is that a line number signal lines is provided at every turn, only calculate the first address of lines * 16pixel piece, then, the controller of memory is according to first address and line number, only under situation once to the request signal of Memory Controller, just can write the lines line data to dynamic memory successively, thereby realize two-dimensional storage.

See also Figure 11, the method of expansion is: under frame progressive die formula, for brightness Y, it is that unit directly outwards repeats to expand 16 times that the macro block MB unit at periphery place expands with the edge pixel, and the expansion of corner is that unit outwards repeats to expand 16 * 16 times with the corner pixels of the MB of corner.

As shown in figure 12, for colourity UV, the method of expansion is: respectively the boundary pixel unit of U and V is synthesized one with a U pixel cell and the integral body that the V pixel cell is a unit on left and right directions, expand to the left or to the right respectively 8 times, after on the above-below direction U and V being intersected, expand respectively 8 times, around the corner, the corner point pixel cell of the corner point pixel cell of U and V is integrated, expands 16 * 8 times.

As shown in figure 13, if decoded bit stream is a progressive die formula, then further judgement is field, top or field, the end, is the field, top if enter code stream, and need saltus step to the DRAM address stored: be as the criterion with first trip calculated address, address computation is carried out in interlacing again, as 1357....Need push up left TOPLEFT, push up right TOPRIGHT, the expansion of a left side, end BOTLEFT, the end right BOTRIGHT, left side LEFTEDGE, the right RIGHTEDGE, top margin TOPEDGE, base BOTEDGE.

If when entering code stream and being field, the end, need saltus step to dynamic memory DRAM address stored: be as the criterion with first trip calculated address, interlacing is carrying out address computation, as 2468....Need push up left TOPLEFT, push up right TOPRIGHT, the expansion of a left side, end BOTLEFT, the end right BOTRIGHT, left side LEFTEDGE, the right RIGHTEDGE, top margin TOPEDGE, base BOTEDGE.

See also Figure 14, the data after the expansion will deposit in the dynamic memory.When if decoded bit stream is frame progressive die formula, then to brightness Y, if image subject MAIN part, directly calculated the address and just write among the DRAM, if expansion PADDING part is being calculated under the prerequisite of address, be written among the DRAM by the order that expands, for colourity UV, if the MAIN part has been calculated the address, deposit DRAM after the intersection in, if the PADDING part is being calculated under the prerequisite of address, be written among the DRAM in proper order by expansion after intersecting;

Again as shown in figure 13, if decoded bit stream is imported with field progressive die formula, then to brightness Y, if MAIN part, directly having calculated the address writes among the DRAM, if PADDING part, for the field, top, need to calculate to expand to and push up left TOPLEFT, push up right TOPRIGHT, a left side, end BOTLEFT, the right BOTRIGHT in the end, left side LEFTEDGE, the right RIGHTEDGE, top margin TOPEDGE, the memory address of the data of base BOTEDGE, store then, for field, the end, need to calculate to expand to and push up left TOPLEFT, push up right TOPRIGHT, a left side, end BOTLEFT, the right BOTRIGHT in the end, left side LEFTEDGE, the right RIGHTEDGE, top margin TOPEDGE, the memory address of the data of base BOTEDGE, be written to DRAM in proper order by expansion then, for colourity UV, if MAIN part, calculated and deposited DRAM in after the address intersects, if PADDING part, for the field, top, need to calculate to expand to and push up left TOPLEFT, push up right TOPRIGHT, a left side, end BOTLEFT, the right BOTRIGHT in the end, left side LEFTEDGE, the right RIGHTEDGE, top margin TOPEDGE, the memory address of the data of base BOTEDGE, store then, for field, the end, need to calculate to expand to and push up left TOPLEFT, push up right TOPRIGHT, a left side, end BOTLEFT, the right BOTRIGHT in the end, left side LEFTEDGE, the right RIGHTEDGE, top margin TOPEDGE, the memory address of the data of base BOTEDGE is written to DRAM in proper order by expansion then.

It should be noted last that: above embodiment is the unrestricted technical scheme of the present invention in order to explanation only, although the present invention is had been described in detail with reference to the foregoing description, those of ordinary skill in the art is to be understood that: still can make amendment or be equal to replacement the present invention, and not breaking away from any modification or partial replacement of the spirit and scope of the present invention, it all should be encompassed in the middle of the claim scope of the present invention.

Claims (14)

1, image boundarg pixel extending system, comprise length variable decoder, intraframe prediction circuit, Memory Controller, inverse quantization circuit, inverse transform circuit, dynamic memory and movement compensating circuit, length variable decoder is connected with other device with control bus by command line, between length variable decoder and the intraframe prediction circuit movement compensating circuit is arranged, it is characterized in that, this system also includes the reconstruction frames memory circuit, length variable decoder is to reconstruction frames memory circuit transmitting control commands signal, intraframe prediction circuit transmits data to the reconstruction frames memory circuit, Memory Controller carries out stores processor to the dateout of rebuilding frame memory circuit, the reconstruction frames memory circuit comprises image control information memory, image data memory and image boundarg pixel expansion module circuit, the control command signal of image control information memory stores length variable decoder input, the image data memory storage is by the view data of intra predictor generator input, image boundarg pixel expansion module circuit analysis diagram is as control signal, edge and corner pixels are outwards repeated to expand, and the pixel data after the expansion deposits dynamic memory in.

2, image boundarg pixel extending system according to claim 1 is characterized in that, described image control information memory is that bit wide is that 32, the degree of depth are 8 register array.

3, image boundarg pixel extending system according to claim 1 is characterized in that, described image data memory is that 64 of two width, the degree of depth are 48 random asccess memory, and 64 input data are converted to the output of 128 bit data.

4, image boundarg pixel extending system according to claim 1 is characterized in that, the image control signal of described length variable decoder input comprises clock sync signal, write order and data command, order data and view data at least.

5, image boundarg pixel extending system according to claim 2 is characterized in that, the form of the image control information of described length variable decoder input comprises initialization information, image sequence level information, frame level information, macro-block level information; Initialization information comprises initializing signal, and 0～15 provides image logical storage width in 32 of described initialization information; The width of every two field picture in 2～13 these image sequences of bit flag of the information of image sequence level, the height of every two field picture in 14～29 these image sequences of bit flag of the information of described image sequence level; The plot of the every two field picture of 6～25 bit flags of frame level information; The vertical relative address of 0～6 bit flag macro block in every two field picture of macro-block level information, the horizontal direction relative address of 7～13 bit flag macro blocks in every two field picture of described macro-block level information.

6, image boundarg pixel extending system according to claim 1, it is characterized in that the output information of described image control information memory comprises at least: feed back to length variable decoder memory command, deposit read data order to image boundarg pixel expansion module circuit.

7, image boundarg pixel extending system according to claim 1 is characterized in that, described intra predictor generator comprises clock sync signal, write data order, input data at least to the image data information of image data memory input.

8, image boundarg pixel extending system according to claim 2, it is characterized in that described image data memory comprises at least to the information of image boundarg pixel expansion module circuit output: feed back to intra predictor generator memory command, deposit read data order to primary module.

9, the extended method of image boundarg pixel extending system, this system comprises length variable decoder, intraframe prediction circuit, Memory Controller, inverse quantization circuit, inverse transform circuit, dynamic memory, movement compensating circuit and reconstruction frames memory circuit, it is characterized in that this method may further comprise the steps at least:

Step 1, length variable decoder send control information to the image control information memory of reconstruction frames memory module;

Step 2, image control information memory send image information data to image boundarg pixel expansion module circuit;

Whether step 3, image boundarg pixel expansion module circuit judges will carry out the image boundarg pixel expansion, are then to receive the next view data of intra predictor generator transmission to flow in the image data stream memory execution in step 4; Otherwise finish;

Step 4, image boundarg pixel expansion module circuit are set up iconic model in conjunction with the data in two memories, and edge and corner pixels are outwards repeated to expand;

Step 5, the storage after will expanding are in dynamic memory.

10, the extended method of image boundarg pixel extending system according to claim 9, it is characterized in that the view data that the image control information memory in the described step 2 sends to image boundarg pixel expansion module circuit is 128 bit data that converted to by 64 bit data of importing.

11, the extended method of image boundarg pixel extending system according to claim 10 is characterized in that, described 64 bit data by input convert 128 bit data to and specifically comprise following switch process:

Step 21, intraframe prediction circuit module I P are unit with 64, write 8 numbers at every turn image data stream is write the image data stream memory, intersect per 8 number writing lines are elected as in 0 and 1 the random asccess memory;

Whether step 22, image data stream memory judgment data have stored, and are then 128 bit data in 0 and 1 two random asccess memory to be done as a whole reading, execution in step 23; Otherwise finish;

Step 23, the data of reading are sent into image boundarg pixel expansion module circuit.

12, the extended method of image boundarg pixel extending system according to claim 9, it is characterized in that, edge and corner pixels outwards being repeated expand in the described step 4 is meant: in the horizontal direction, each expands 16 pixels respectively to the right left, in vertical direction, expand 8 pixels for chromatic component UV, expand 16 pixels for luminance component Y.

13, the extended method of image boundarg pixel extending system according to claim 9 is characterized in that, described step 4 further comprises:

Step 41, judge the pattern and the type of decoded bit stream, if decoded bit stream is a frame progressive die formula, then carry out following expansion: for brightness Y, it is that unit directly outwards repeats to expand 16 times that the MB unit at periphery place expands with the edge pixel, the corner pixels that corner expands with the MB of corner is that unit outwards repeats to expand 16 * 16 times, for colourity UV, on left and right directions, respectively the boundary pixel unit of U and V is synthesized one with a U pixel cell and the integral body that the V pixel cell is a unit, expand to the left or to the right respectively 8 times, after on the above-below direction U and V being intersected, expand respectively 8 times, around the corner, the corner point pixel cell of the corner point pixel cell of U and V is integrated, expands 16 * 8 times;

If step 42 decoded bit stream is a progressive die formula, then further judge it is field, top or field, the end, if enter code stream is the field, top, then be as the criterion with first trip calculated address, address computation is carried out in interlacing, store data with this saltus step address to dynamic memory, and left with the right side, top, to the left side and the right and top margin expansion pixel according to the method for step 41 to the top of image;

If it is field, the end that step 43 enters code stream, be as the criterion with first trip calculated address, address computation is carried out in interlacing, stores data with this saltus step address to dynamic memory, and according to the method for step 41 to the left side, the end of image and the right side, the end, to the left side and the right and base expansion pixel.

14, the extended method of image boundarg pixel extending system according to claim 9 is characterized in that, the storage in the described step 5 specifically may further comprise the steps:

The pattern and the type of step 51, judgement decoded bit stream, if decoded bit stream is a frame progressive die formula, to brightness Y, just write in the dynamic memory if the image subject part has directly been calculated the address, if expansion, calculating under the prerequisite of address, be written in the dynamic memory by the order that expands, for colourity UV, if main part has been calculated the address, depositing dynamic memory in after U and the V intersection, if expansion having calculated under the prerequisite of address, is written in the dynamic memory by expansion in proper order;

Step 52, if decoded bit stream is imported with field progressive die formula, to brightness Y, if main part, directly having calculated the address writes in the dynamic memory, if expansion, for the field, top, need to calculate to expand to and push up a left side, top margin, the top is right, the left side, the memory address of the data on the right, store then,, need calculating to expand to a left side, the end for field, the end, the base, the right side, the end, the left side, the memory address of the data on the right, be written to dynamic memory in proper order by expansion then, for colourity UV, if main part has been calculated the address, depositing dynamic memory in after U and the V intersection, if expansion for the field, top, needs to calculate expand to and pushes up a left side, top margin, the top is right, the left side, the memory address of the data on the right, store then, for field, the end, need calculating to expand to a left side, the end, the base, the right side, the end, the left side, the memory address of the data on the right is written in the dynamic memory in proper order by expansion then.

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