CN1300753C

CN1300753C - Dynamic matrix type display device

Info

Publication number: CN1300753C
Application number: CNB031023665A
Authority: CN
Inventors: 宫岛康志; 横山良一
Original assignee: Sanyo Electric Co Ltd
Current assignee: Sanyo Electric Co Ltd
Priority date: 2003-02-10
Filing date: 2003-02-10
Publication date: 2007-02-14
Anticipated expiration: 2023-02-10
Also published as: CN1521711A

Abstract

The present invention provides a dynamic matrix type display device which is provided with auxiliary capacitor electrodes in pixel regions of pixel electrodes and an auxiliary capacitor, wherein the auxiliary capacitor is composed of a first auxiliary capacitor line and a second auxiliary capacitor line, and is arranged corresponding to a plurality of pixel electrodes. By exchanging that an element applies each frame period for the pixel electrodes, any voltage mode of first video voltage of which the polarity can generate reverse rotation and second video voltage of which the polarity is opposite to the first video voltage is used for displaying. In this way, the dot inversion drive caused by the auxiliary capacitance lines can be implemented, and display capability with low power consumption and high display quality can be implemented.

Description

Active matrix display device

Technical Field

The present invention relates to an active matrix display device.

Technical Field

In a dynamic matrix display device in which image signals are supplied to individual pixel electrodes through switching elements such as Thin Film Transistors (TFTs), an AC driving method of applying an AC potential to a counter electrode and an auxiliary capacitor can reduce the potential difference between the positive and negative polarities of a video signal input to a drain driver while preventing deterioration of liquid crystal, and reduce the current and voltage of the drain driver, thereby achieving low power consumption.

However, in the horizontal inversion counter AC driving method in which the polarity of the video signal supplied to each drain line is inverted every 1 horizontal period, since the polarities of the voltages of the counter electrode and all the auxiliary capacitance lines are inverted every 1 horizontal period, the capacitive load of the counter electrode and all the auxiliary capacitance lines and the power consumption caused thereby are still large.

Therefore, in order to achieve lower power consumption, japanese patent application laid-open No. 12-81606 discloses a driving method (hereinafter, referred to as "SC driving") in which a voltage of a counter electrode is set to a constant value by inverting a voltage polarity of an auxiliary capacitor, thereby reducing power consumption, reducing a potential difference between positive and negative polarities of a video signal, and reducing a current and a voltage of a drain driver. The following description will be made of an active matrix type liquid crystal display device using SC driving.

Fig. 11 is an equivalent circuit diagram of a display panel of an active matrix type liquid crystal display device using SC driving. The circuit is provided with a plurality of drain lines 105 in the vertical direction, a plurality of gate lines 107 in the horizontal direction, and switching elements TFT109 at the intersections thereof. The TFT109 has its gate connected to the gate line 107 and its drain connected to the drain line 105. The source of the TFT109 is connected to one of the electrodes of the liquid crystal capacitor 112. The other electrode of the liquid crystal capacitor 112 is a counter electrode 111 which integrates a substrate provided with the TFT109 and an opposite substrate sandwiching the liquid crystal.

The source of the TFT109 is connected to a capacitor electrode on one side of the auxiliary capacitor 110. The other electrode of the auxiliary capacitor 110 is connected to the auxiliary capacitor line 108. The auxiliary capacitance line 108 is parallel to the gate line 107 and communicates with a plurality of auxiliary capacitances 110 in the row direction.

FIG. 12 is a signal waveform diagram of a display panel driven by focusing on a single pixel, in which a gate voltage V is shown_GPixel voltage V_PSource voltage V_SVideo signal voltage V_DAuxiliary capacitor voltage V_SCAnd an opposed electrode voltage V_COM. Gate voltage V_GThere is one ON period within each frame period.

When the gate is turned on, a gate voltage V is applied to the gate line 107_GBecomes a High level (hereinafter referred to as "High"). During this period, the TFT109 is on, the drain and the source are on, and the source voltage V is set to_SIs in accordance with the video signal voltage V applied to the drain line 105_DTo become the video signal voltage V_DThe same level. Thus, the source voltage V_SIs applied to the liquid crystal capacitor 112 and the capacitor electrode on one side of the auxiliary capacitor 110. When the grid is cut OFF (OFF), the grid voltage V_GIt becomes Low (hereinafter referred to as "Low") level, the TFT109 is in off state, and the source voltage V is determined_SAt the same time, the gate voltage V is accompanied_GIs lowered, levelDecrease only by Δ V_STo be V_PL。

Counter electrode voltage V_COMAt a constant voltage, the voltage is set to be the source voltage V only in advance_SDecrease of Δ V_SLeft-right ratio video signal voltage V_DCentral level V of_CAnd also on the low level.

When a gate voltage V is applied to the corresponding gate line 107_GAfter the drop, the auxiliary capacitance voltage V is applied to each auxiliary capacitance line 108_SCThe level is inverted. Auxiliary capacitor voltage V_SCWill be represented by V_SCHAnd V_SCLThe two high and low levels are inverted. For example, when the source voltage V is_SAt a voltage higher than the counter electrode voltage V_COMDuring the positive polarity period, when the gate voltage V is applied_GAfter dropping, the source voltage V_SWill change from low level V_SCLRises to a high level V_SCH. Therefore, when the gate voltage V is applied_GFalling energy-determining source voltage V_SThe resulting pixel voltage V_PWill receive an auxiliary capacitor voltage V through the auxiliary capacitor 110_SCInfluence of the rise, but only by Δ V_P. Pixel voltage V at this time_PIs held during the gate OFF period, i.e., 1 frame.

Thus, the voltage V is passed through the auxiliary capacitor_SCCharge redistribution occurs between the liquid crystal capacitor 112 and the auxiliary capacitor 110, and the pixel voltage V_POnly rise by Δ V_P＝V_PH-V_PL. In contrast, at the source voltage V_SLower than the counter electrode voltage V_COMDue to the auxiliary capacitor voltage V during the negative polarity period_SCWill drop from a positive value to a negative value, so the pixel voltage V_POnly decrease Δ V_P. The result is a pixel voltage V_PBecomes large and the voltage applied to the liquid crystal capacitance 112 can be increased.

I.e. by making the auxiliary capacitance voltage V_SCInverted between two levels, i.e. counter-electrode voltage V_COMFor DC voltages, the video signal voltage V can also be reduced_DOf a vibration amplitude ofA sufficient voltage is applied to the liquid crystal capacitor 112.

In general, the storage capacitor 110 is much larger than the liquid crystal capacitor 112, so that the voltage variation V (V) of the storage capacitor of 1 row can be passed_SCH-V_SCL) To control the variation degree DeltaV of the pixel voltage_P. Therefore, by changing the auxiliary capacitance voltage of the auxiliary capacitance line 108, a large voltage can be applied to the liquid crystal capacitance 112. That is, by changing the auxiliary capacitance voltage, the video signal voltage V can be reduced_DThe amplitude of (d).

However, at present, the driving method is generally used in which several drain lines 105 are turned on simultaneously with the increase of pixels, and the video signal voltage V is applied to several liquid crystal capacitors 112 and auxiliary capacitors 110 simultaneously_DThe driving method of (1). By this method, it is sufficiently ensured that the drain line 105 applies the video signal voltage V to the liquid crystal capacitor 112 and the auxiliary capacitor 110_DTime of (d).

Particularly, when a large or high-definition display panel is driven by the dot sequential method, tens of drain lines 105 are simultaneously turned on, and a video signal voltage V is simultaneously applied to tens of liquid crystal capacitors 112 and auxiliary capacitors 110_D. Thus, when several tens of drain lines 105 are simultaneously turned on, a large amount of capacitive coupling occurs at the overlapping portion of the drain lines 105 and the auxiliary capacitance lines 108 in the on state. That is, the voltage of the auxiliary capacitance line 108 or the gate line 107 is finally influenced by the voltage of the drain line 105 and fluctuates. By this voltage change, image unevenness occurs in the unit of the drain lines 105 which are simultaneously in the on state.

Disclosure of Invention

In the present invention, voltages having different polarities may be applied to each of the adjacent single or several pixel electrodes, that is, so-called dot inversion may be performed.

The present invention has a plurality of 1 st and 2 nd auxiliary capacitance lines corresponding to respective rows of pixel electrodes and extending in a row direction, and auxiliary capacitances are alternately arranged in respective columns of the pixel electrodes corresponding to the 1 st and 2 nd auxiliary capacitance lines. This makes it possible to supply signals having different polarities to the auxiliary capacitance lines. Therefore, voltages having different polarities are applied to adjacent pixels by the 1 st and 2 nd auxiliary capacitance lines, so-called dot inversion driving can be realized.

It is preferable that the 1 st and 2 nd auxiliary capacitance lines be supplied with 1 st and 2 nd auxiliary capacitance voltages which change in opposite phases to each other while the switching element is in the off state. In this way, it is possible to reduce the amplitude of the video signal voltage and apply a sufficient voltage to the pixel electrode while realizing the dot inversion driving by the auxiliary capacitance line.

Drawings

Fig. 1 is a plan view of a display panel of an active matrix type display device.

Fig. 2 is a plan view of a display panel according to embodiment 1 of the present invention.

Fig. 3 is an equivalent circuit diagram of the display panel according to embodiment 1 of the present invention.

Fig. 4 is a timing chart showing the relationship between signals in the display panel according to embodiment 1 of the present invention.

Fig. 5(a) and 5(b) are signal waveform diagrams illustrating a driving method of a display device according to embodiment 1 of the present invention.

Fig. 6 is a plan view of a display panel according to embodiment 2 of the present invention.

Fig. 7 is an equivalent circuit diagram of a display panel according to embodiment 2 of the present invention.

Fig. 8 is a plan view of a display panel according to embodiment 3 of the present invention.

Fig. 9 is an equivalent circuit diagram of the display panel according to embodiment 3 of the present invention.

Fig. 10(a) and 10(b) are schematic diagrams showing vertical inversion driving and dot inversion driving.

Fig. 11 is an equivalent circuit diagram of a conventional display panel.

Fig. 12 is a signal waveform diagram of a driving method of a conventional display device.

Detailed Description

Embodiment 1 will be described below. Fig. 1 is a plan view of a display panel of an active matrix display device, fig. 2 is a plan view of a display panel of embodiment 1, and fig. 3 is an equivalent circuit diagram of the display panel.

First, in fig. 1, a drain driver (drain driver)2 is disposed as a row driver (row driver) in the row direction and a gate driver (gate driver)3 is disposed as a column driver (row driver) in the column direction on a display panel 1. A display region 4 for displaying an image is disposed in a region surrounded by the drain driver 2 and the gate driver 3.

In the display area 4, as shown in fig. 2 and 3, a plurality of drain lines 5 are provided as data lines along the column direction, and a plurality of long rectangular pixel electrodes 6 are provided, and a gate line 7 as a selection line, and a 1 st auxiliary capacitance line 8a and a 2 nd auxiliary capacitance line 8b are provided along the row direction. In a region where each pixel electrode 6 is disposed (hereinafter referred to as "pixel region"), the TFT9 and one of the 1 st auxiliary capacitance line 10a and the 2 nd auxiliary capacitance line 10b are disposed.

The TFT9 includes: a gate electrode 9g extended from the gate line 7, a channel region of the semiconductor layer thereunder, a drain region 9d of the semiconductor layer electrically connected through the drain line 5 and the contact, and a source region 9s of the semiconductor layer electrically connected through the pixel electrode 6 and the contact. In this embodiment, the TFT9 is a double-gate type having two gate electrodes 9 g.

The 1 st auxiliary capacitance 10a is composed of an auxiliary capacitance electrode 10x composed of a semiconductor layer connected to the TFT9, and an auxiliary capacitance electrode 10y formed by extending the 1 st auxiliary capacitance line 8 a. The 2 nd auxiliary capacitance 10b is constituted by the auxiliary capacitance electrode 10x and the auxiliary capacitance electrode 10z formed by extending the 2 nd auxiliary capacitance line 8 b.

Further, the counter electrode 11 is provided on the substrate on which the TFT9 is provided and on the opposite side of the substrate with the liquid crystal interposed therebetween, and constitutes an opposite capacitor electrode corresponding to the pixel electrode 6 of the liquid crystal capacitor 12.

In this embodiment, since the TFT9 is formed of an N-channel TFT, the data line is referred to as a drain line, and the driver is referred to as a drain driver. However, the TFT9 may be a P-channel TFT.

As shown in fig. 1, the 1 st video signal voltage Vda and the 2 nd video signal voltage VDb having opposite polarities to each other are input to the drain driver 2, and any one of the 1 st video signal voltage Vda and the 2 nd video signal voltage VDb is applied to each drain line 5 selected in sequence.

Sequentially selecting the gate lines 7 applies the gate signal GV to the gate driver 3. The display region 4 is a region in which a plurality of pixel electrodes 6 are arranged in a matrix form, and a voltage is applied between the pixel electrodes 6 and the counter electrode 11 to display an image.

The drain line 5 is a connection line for transmitting the video signal voltage VDa or VDb to the drain of the TFT9 through a contact point after applying either the 1 st video signal voltage VDa or the 2 nd video signal voltage VDb having opposite polarities to each other.

The pixel electrode 6 is an electrode which constitutes a pixel region as a display unit and drives liquid crystal together with the counter electrode 11 by a video signal voltage VD transmitted from the drain line 5 through the TFT 9.

The gate line 7 is selected by the gate driver 3, and the gate signal GV is applied, whereby the connected TFT9 is turned ON (ON).

The 1 st auxiliary capacitance line 8a is formed in the same layer as the gate line 7 and is parallel to the gate line 7. On the 1 st auxiliary capacitance line 8a, a plurality of auxiliary capacitance electrodes 10y are arranged in a row direction integrally therewith. Therefore, the auxiliary capacitance electrodes 10y of the 1 st auxiliary capacitance 10a of each row are connected to each other.

The 2 nd auxiliary capacitance line 8b is formed in the same layer as the gate line 7, and is also parallel to the gate line 7. On the 2 nd auxiliary capacitance line 8b, a plurality of auxiliary capacitance electrodes 10z integrally formed therewith are arranged in the row direction. Therefore, the auxiliary capacitance electrodes 10z of the 2 nd auxiliary capacitance 10b of each row are connected to each other.

In addition, the 1 st auxiliary capacitance line 8a is supplied with the 1 st auxiliary capacitance voltage, and the 2 nd auxiliary capacitance line 8b is supplied with the 2 nd auxiliary capacitance voltage having a polarity opposite to that of the 1 st auxiliary capacitance voltage.

The TFT9 is a switching element (switching element) in which, only when a voltage is applied to the gate electrode 9g, a current flows in either a direction from the source region 9s to the drain region 9d or a direction from the drain region 9d to the source region 9s in a semiconductor layer channel region immediately below the gate electrode 9 g. The 1 st auxiliary capacitor 10a and the 2 nd auxiliary capacitor 10b hold the electric charges generated by the video signal voltage VD output from the drain line 5 through the TFT9 for 1 frame period to compensate for the electric charge loss of the liquid crystal capacitor 12.

Since a constant voltage is applied to the counter electrode 11, a drive voltage corresponding to the video signal voltage VD applied to the pixel electrode 6 is applied to the liquid crystal between the pixel electrode 6 and the counter electrode 11, thereby driving the liquid crystal capacitance 12 of the pixel.

Held in the liquid crystal capacitance 12 is electric charge generated by the video signal voltage VD output from the drain line 5 held by the liquid crystal through the TFT 9. However, since the electric charges held in the liquid crystal capacitor 12 are much smaller than the electric charges held in the 1 st storage capacitor 10a or the 2 nd storage capacitor 10b, these electric charges are likely to flow out due to leakage current when the TFT9 is turned OFF (OFF) or leakage current from impurities in the liquid crystal. Therefore, it is necessary to supplement the electric charge held in the liquid crystal capacitor 12 with the electric charges held in the 1 st auxiliary capacitor 10a and the 2 nd auxiliary capacitor 10 b.

Next, a driving method will be described. Fig. 4 is a timing chart showing the relationship between signals in the display panel. It shows the timing of voltage changes in the vertical start signal STV and the gate signals GV1, GV2, GV3, the horizontal start signal STH and the horizontal pulse signal CKH, and the potential SCa of the 1 st auxiliary capacitance line 8a and the potential SCb of the 2 nd auxiliary capacitance line 8 b.

First, in response to the falling of the pulse of the vertical start signal STV, the pulse of the gate signal GV1 rises, and the gate signal GV1 is transmitted to the gate line 7 in the 1 st row to turn on the TFT9 connected to the gate line 7. Then, the pulse of the horizontal start signal STH rises, and when the pulse falls, the pulse of the first horizontal pulse signal CKH in the selected period at the same time rises for the gate line 7 of the 1 st row.

While the gate signal GV1 is being supplied to the gate line 7 in the 1 st row, the pulses of the horizontal pulse signal CKH sequentially rise, and the drain line 5 is sequentially selected at the same time as the rise of the pulses, and the video signal voltage VD is sequentially applied to the pixel electrode 6, the 1 st auxiliary capacitor 10a, and the 2 nd auxiliary capacitor 10b via the TFT 9. Then, the 1 st video signal voltage VDa is applied to the pixel electrode 6 and the 1 st auxiliary capacitor 10a, and the 2 nd video signal voltage VDb is applied to the pixel electrode 6 and the 2 nd auxiliary capacitor 10 b.

If the video signal voltage VD is applied to all the drain lines 5, the gate signal GV1 cannot be transmitted to the gate line 7 of the 1 st row, so that the TFT9 connected to the gate line 7 is in a cut-off state. Therefore, the pulses of the gate signal GV2 and the gate signal GV3 sequentially rise, and the above operation is repeated so that the gate signal GV2 is applied to the gate line 7 in the 2 nd row and the gate signal GV3 is applied to the gate line 7 in the 3 rd row, respectively.

When the TFT9 connected to the gate line 7 is off, that is, when the gate signal GV is not supplied to the gate line 7, the polarities of the potential SCa of the 1 st auxiliary capacitance line 8a and the potential SCb of the 2 nd auxiliary capacitance line 8b in the row are inverted. The polarities of the storage capacitor voltages VCa and VCb of the 1 st and 2 nd

storage capacitor lines

8a and 8b are opposite to each other at the beginning, and the video signal voltage applied to the pixel at that time is set to be the same polarity by the inversion of the levels, and then the state is maintained. Since the inversion of the level is performed immediately after the moment when the TFT9 is turned off, the 1 st or 2 nd video signal voltage is applied to either the

storage capacitor

10a or 10b, and the TFT9 is turned off, so that the potential difference between the counter electrode 11 and the source voltage Vs becomes small once, but the potential difference between the counter electrode 11 and the 1 st or 2 nd storage capacitor voltage increases thereafter.

In this way, if the gate signal GV is supplied to all the gate lines 7, the pulse of the vertical start signal STV rises again, and the gate signal GV is applied to the gate line 7 of the 1 st row in synchronization with the pulse, and the same operation is repeated.

Fig. 5 is a signal waveform diagram showing a driving method of a display device according to embodiment 1 of the present invention, and shows signal waveforms between 1 frame in pixel regions adjacent in the gate line direction. Fig. 5(a) shows a signal waveform of the 1 st auxiliary capacitor 10a, and fig. 5(b) shows a signal waveform of the 2 nd auxiliary capacitor 10 b. The signal waveform shown in fig. 5(a) is substantially the same as that shown in fig. 12, but the signal waveform shown in fig. 5(b) is just opposite in polarity to that shown in fig. 12.

As shown in fig. 1, the 1 st auxiliary capacitor 10a and the 2 nd auxiliary capacitor 10b are disposed in the pixels adjacent in the horizontal direction. Therefore, the video signal voltages VDa and VDb having opposite polarities are applied to the adjacent pixels, and the auxiliary capacitance voltage VCa having the same polarity as the video signal voltage VDa is applied to the 1 st auxiliary capacitance 10a of the pixel to which the video signal voltage VDa is applied. On the other hand, in the pixel to which the video signal voltage VDb has been applied, the auxiliary capacitor voltage VCb having the same polarity as the video signal voltage VDb is applied to the 2 nd auxiliary capacitor 10b, and the polarity of the auxiliary capacitor voltages VCa and VCb is inverted while the TFT9 is turned off. Therefore, by turning off the TFT9, the source voltage Vs of the TFT9 will only decrease by Δ Vs. However, the voltage change Δ V of the pixel electrode due to the inversion of the auxiliary capacitance voltage VC_PThe voltage between the electrodes of the liquid crystal capacitor 12 is increased, and thus the liquid crystal can be driven with a sufficient voltage.

As described above, the active matrix display device of the present embodiment includes: any one of the auxiliary capacitance 10a and the auxiliary capacitance 10b is arranged in each pixel region where the pixel electrode 6 is formed. Then, one side of each of the

storage capacitors

10a and 10b arranged in parallel in the row direction is connected to the source of the TFT9 of the pixel. On the other hand, the other electrode of the auxiliary capacitance 10a disposed every other in the row direction is connected to the 1 st auxiliary capacitance line 8 a. The other electrode of the auxiliary capacitance 10b arranged every other in the row direction is connected to the 2 nd auxiliary capacitance line 8 b.

Then, the video signal voltage whose polarity is inverted is supplied to the drain line 5 for each frame period. The video signal voltages have a 1 st video signal voltage and a 2 nd video signal voltage of opposite polarities to each other, and the 1 st video signal voltage and the 2 nd video signal voltage are applied to the adjacent drain lines 5, respectively.

Then, when the TFT9 is turned on by the 1 st video signal voltage to charge the 1 st auxiliary capacitor 10a, the polarity of the 1 st auxiliary capacitor voltage VCa applied to the 1 st auxiliary capacitor line 8a of the pixel is inverted so as to be the same as the 1 st video signal voltage. Further, when the TFT9 is turned on by the 2 nd video signal voltage to charge the 2 nd storage capacitor 10b, the polarity of the 2 nd storage capacitor voltage VCb applied to the 2 nd storage capacitor line 8b of the pixel can be inverted to be the same as the polarity of the 2 nd video signal voltage.

Thus, the so-called dot inversion driving can be realized by using the

auxiliary capacitance lines

8a and 8 b.

Then, in the present dynamic matrix type display device, when the TFT9 is turned on, the 1 st video signal voltage is supplied to the 1 st auxiliary capacitance 10a connected to the 1 st auxiliary capacitance line 8a, and the 2 nd video signal voltage is supplied to the 2 nd auxiliary capacitance having the 2 nd auxiliary capacitance line. When the TFT9 is turned off, the source voltage Vs of the TFT9 decreases, and the voltages of the

storage capacitors

10a and 10b connected to the TFT decrease.

However, if the TFT9 is turned off according to this embodiment, the 1 st auxiliary capacitance voltage VCa is supplied to the 1 st auxiliary capacitance line 8a and the level is changed to the voltage polarity held by the 1 st auxiliary capacitance (the source voltage Vs or the pixel electrode voltage V of the pixel at this time)_PThe polarity of (b) and a 2 nd auxiliary capacitance voltage VCb having a polarity opposite to that of the 1 st auxiliary capacitance voltage VCa is supplied to the 2 nd auxiliary capacitance line 8b to change the level to the voltage polarity held by the 1 st auxiliary capacitance (at this time, the source voltage Vs or the pixel electrode voltage V of the pixel is set to be the same as the source voltage Vs or the pixel electrode voltage V of the pixel)_PPolarity of (d). Therefore, the voltage held by the 1 st and 2 nd storage capacitors, which have fluctuated, can be filled by the switching-off operation of the TFT9, and the voltage held by the 1 st and 2 nd storage capacitors can be increased.

In this embodiment, by performing dot inversion driving, it is possible to eliminate the influence of adjacent video signal voltages and prevent image unevenness due to capacitive coupling. While the switching element (TFT9) is in the OFF state, the 1 st and 2 nd auxiliary capacitance lines are inverted, and the 1 st or 2 nd auxiliary capacitance voltages of opposite polarities are applied. Thus, even if the amplitude of the video signal voltage is narrowed, a sufficient voltage can be applied to the liquid crystal, and power consumption can be reduced.

In this embodiment, in order to reduce image unevenness and flicker as much as possible, the 1 st and 2 nd

auxiliary capacitance lines

8a and 8b are configured to have auxiliary capacitance electrodes alternately in the row direction for each pixel. However, the present invention is not limited to this, and the 1 st and 2 nd

auxiliary capacitors

10a and 10b may be alternately arranged in units of several columns of continuous pixels in the row direction.

For example, it is also preferable that: the three pixels of RGB primary color display are used as a unit, and the units are arranged as

auxiliary capacitors

10a and 10b connected to either the 1 st or 2 nd

auxiliary capacitor lines

8a and 8 b.

Next, embodiment 2 will be explained.

In embodiment 1, as shown in fig. 2, the 1 st auxiliary capacitance line 8a and the 2 nd auxiliary capacitance line 8b are configured to overlap all of the auxiliary capacitance electrodes 10 x. In this way, only in the pixel region where the auxiliary capacitance electrode 10z in which the 2 nd auxiliary capacitance line 8b and the 2 nd auxiliary capacitance 10b are formed, the overlapping portion 13 overlapping the semiconductor layer connected to the 1 st auxiliary capacitance line 8a and the auxiliary capacitance electrode 10z exists. Therefore, a derived capacitance C will be generated at this overlapping portion 13_PAR。

The problem to be solved by the 2 nd embodiment is derived capacitance C_PARThe problem caused by the formation of the second auxiliary capacitor 10b is solved. Fig. 6 is a plan view of a display panel according to embodiment 2 of the present invention, and fig. 7 is an equivalent circuit diagram thereof. The same components as those of embodiment 1 are denoted by the same reference numerals and their description is omitted.

This embodiment differs from embodiment 1 in that: in the pixel region having the storage capacitor electrode 10y, a dummy (dummy) line 14 extending from the storage capacitor electrode 10y and overlapping the 2 nd storage capacitor electrode 8b is provided. The dummy wiring 14 forms a derived capacitance C of a portion 13 overlapping the auxiliary capacitance electrode 10z and the 1 st auxiliary capacitance line 8a by forming a portion 13' overlapping the 2 nd auxiliary capacitance line 8b where no auxiliary capacitance is formed_PAREqual derivative capacitance C_PAR’。

In embodiment 1, the derived capacitance C is generated only in the portion 13 where the auxiliary capacitance electrode 10z and the 1 st auxiliary capacitance line 8a overlap each other_PARTherefore, only the potential of the 2 nd auxiliary capacitance 10b having the auxiliary capacitance electrode 10z is lowered. Therefore, between the pixel region having the storage capacitor electrode 10y and the pixel region having the storage capacitor electrode 10z, a difference occurs in the magnitude of the counter electrode voltage that matches best with the pixel electrode 6 in each pixel region, and thus contrast (contrast) shift or flicker phenomenon is liable to occur.

However, in the present embodiment, by forming the dummy wiring 14 at the 1 st auxiliary capacity electrode 10x, the overlapping portion 13' where the 1 st auxiliary capacity voltage 10x overlaps with the 2 nd auxiliary capacity line 8b where the auxiliary capacity is not formed and the dummy wiring 14 is formed, thereby generating the derived capacity C_PAR’。

As a result, by balancing the polarities of the 1 st auxiliary capacitor 10a and the 2 nd auxiliary capacitor 10b, the difference in the magnitude of the counter electrode voltage that matches the pixel electrode 6 in each pixel region can be eliminated, and contrast shift and flicker caused by the difference can be eliminated.

Next, embodiment 3 will be described. Fig. 8 is a plan view of a display panel according to embodiment 3 of the present invention, and fig. 9 is an equivalent circuit diagram thereof. The same components as those of embodiment 1 are denoted by the same reference numerals and their description is omitted. In this embodiment, the arrangement of the drain lines 5 and the pixel electrodes 6 is the same as that of embodiment 1 or 2.

The present embodiment differs from embodiments 1 and 2 in that: the gate line 7 is disposed in the central portion of the pixel electrode and is sandwiched between the 1 st auxiliary capacitance line 8a and the 2 nd auxiliary capacitance line 8 b. In each pixel region, a region where the storage capacitor electrode 10x is provided is formed in the gate line 7 as a boundary between the gate electrodes of the TFT9 integrally formed with the gate line 7.

In embodiment 2, dummy wirings are disposed in addition to the auxiliary capacitor electrodes that are originally required, and therefore, the pattern (pattern) becomes complicated and the aperture ratio decreases.

However, in the present embodiment, by disposing the gate line 7 between the 1 st auxiliary capacitance line 8a and the 2 nd auxiliary capacitance line 8b, since all the auxiliary capacitance electrodes 10x overlap only one of the 1 st auxiliary capacitance line 8a and the 2 nd auxiliary capacitance line 8b constituting the auxiliary capacitance, the overlapping portion 13 and the overlapping portion 13' are not necessary, and the derived capacitance C generated in the overlapping portion can be eliminated_PAR。

In addition, in this embodiment, the distance between the 2 nd auxiliary capacitance line 8b and the TFT9 can be shortened, and the wiring resistance can be reduced. In this way, the area of the semiconductor layer necessary for forming the storage capacitor electrode 10z according to embodiment 1 or the dummy wiring 14 according to embodiment 2 can be reduced, and therefore the aperture ratio can be increased.

In each embodiment, a double-gate TFT is used as an example, but the present invention is not limited to this, and 1 gate or 3 or more gates may be used. In addition, although the auxiliary capacitance lines of the respective embodiments are formed in the same layer as the gate lines, the auxiliary capacitance lines may be formed in a different layer from the gate lines.

In the embodiments, the present invention is not limited to the active matrix type liquid crystal display device, but the present invention is also applicable to an active matrix Electroluminescence (EL) display device.

As described above, in the present embodiment, there are provided a plurality of 1 st and 2 nd auxiliary capacitance lines extending in the row direction corresponding to each row of the pixel electrodes, and auxiliary capacitances corresponding to the 1 st and 2 nd auxiliary capacitance lines are alternately arranged in each column of the pixel electrodes. Thus, signals having different polarities can be supplied to the auxiliary capacitance lines. Therefore, by applying voltages of different polarities to the adjacent pixels through the 1 st and 2 nd auxiliary capacitance lines, so-called dot inversion driving can be realized.

It is preferable that the display is performed by applying either a 1 st video signal voltage whose polarity is inverted every frame period or a 2 nd video signal voltage whose polarity is opposite to that of the 1 st video signal voltage to the pixel electrode, and that the 1 st and 2 nd auxiliary capacitance voltages which change in opposite phases to each other during the switching element OFF (OFF) period are supplied to the 1 st and 2 nd auxiliary capacitance lines. In particular, the 1 st video signal voltage and the 1 st storage capacitor voltage have the same polarity, and the 2 nd video signal voltage and the 2 nd storage capacitor voltage have the same polarity. Thus, dot inversion driving by the auxiliary capacitance line can be realized, and the amplitude of the video signal voltage can be reduced.

In addition, the 1 st and 2 nd auxiliary capacitance lines are preferably in units of several columns of continuous pixel electrodes, and have auxiliary capacitance electrodes alternately. For example, in 1 group (group) of pixel electrodes for three primary colors RGB among display colors, voltages having opposite polarities may be applied to each adjacent group. In this way, inversion driving in units of groups can be realized.

It is preferable that the 1 st and 2 nd auxiliary capacitance lines overlap all the auxiliary capacitance electrodes arranged corresponding to the respective rows forming the pixel electrode. Thus, the polarity of the derived capacitance generated in the overlapping region of the auxiliary capacitance line where the auxiliary capacitance is not formed and the auxiliary capacitance electrode can be balanced, and thus, the image unevenness can be prevented.

The storage capacitor electrode preferably has a dummy wiring overlapping the storage capacitor line on which the storage capacitor is not formed, of the 1 st or 2 nd storage capacitor lines. Since the 1 st and 2 nd auxiliary capacitance lines are formed so as to overlap all the auxiliary capacitance electrodes in the same manner, the polarity between the derived capacitances generated in the overlapping region of the auxiliary capacitance line where no auxiliary capacitance is formed and the auxiliary capacitance electrode can be balanced, and further, the image unevenness can be prevented.

In addition, in the pixel region where the pixel electrode is formed, the gate line is preferably disposed between the 1 st and 2 nd auxiliary capacitance lines. Thus, the overlapping area of the auxiliary capacitance line where the auxiliary capacitance is not formed and the auxiliary capacitance electrode and the derived capacitance generated in the area can be eliminated, and the image unevenness can be prevented.

In the pixel region, it is preferable that a gate electrode composed of a switching element is formed in a region where the auxiliary capacitance electrode is provided, with respect to the gate line, as a boundary. Thus, the overlapping area of the auxiliary capacitance line where the auxiliary capacitance is not formed and the auxiliary capacitance electrode and the derived capacitance generated in the area can be eliminated, and the image unevenness can be prevented.

In the present dynamic matrix display device, a common electrode (counter electrode 11) is disposed on the 2 nd substrate, and a constant voltage is applied to the common electrode. Thus, the voltage of the common electrode having a large area can be prevented from varying, and the active matrix display device can be driven at a low voltage and power consumption.

Further, by inverting the levels of the 1 st and 2 nd storage capacitor voltages immediately after the switching element (TFT9) is turned off during the switching element (TFT9) off period, the charge of the storage capacitor that has fluctuated is replenished when the voltage held by the 1 st and 2 nd storage capacitors has fluctuated less, and therefore, a larger amount of charge can be used to increase the voltage holding the 1 st and 2 nd storage capacitors, without being easily affected by the switching element's off operation.

Therefore, according to this embodiment, an active matrix display device with high display quality can be provided.

Here, voltages of the same polarity may be applied to pixel electrodes adjacent to each other in the drain line direction. At this time, vertical inversion driving as shown in fig. 10(a) will be formed.

However, in consideration of the characteristics, it is preferable to apply dot inversion driving of opposite polarities to all pixels adjacent to each other in the vertical and horizontal directions as shown in fig. 10 (b). In either driving method, a voltage of opposite polarity to the previous frame is applied to each frame as shown.

By performing dot inversion driving, not only deterioration of liquid crystal can be prevented, but also capacitance coupling can be effectively prevented.

Claims

1. An active matrix display device, comprising: it is disposed several pixels in matrix form, and controls the display of each pixel; the device is provided with a plurality of devices,

several gate lines extending along the row direction for transmitting gate voltage;

several data lines extending along the column direction for transmitting video signal voltage;

switching elements disposed corresponding to intersections of the gate lines and the data lines;

a pixel electrode connected to the data line through the switching element; and the number of the first and second groups,

a plurality of 1 st and 2 nd auxiliary capacitance lines extending in a row direction corresponding to the respective rows of the pixel electrodes;

an auxiliary capacitance electrode superposed on any one of the 1 st or 2 nd auxiliary capacitance lines is further arranged on each pixel; the 1 st and 2 nd auxiliary capacitance lines are supplied with 1 st and 2 nd auxiliary capacitance voltages which change in opposite phases to each other during the period in which the switching element is turned off.

2. The active matrix type display device as claimed in claim 1, wherein: applying a constant voltage to an opposing electrode formed on an opposing substrate facing the substrate on which the pixel electrode is formed,

the 1 st and 2 nd auxiliary capacitance voltages which change in opposite phases to each other during the switching-off period are supplied to the 1 st and 2 nd auxiliary capacitance lines, respectively.

3. The active matrix type display device as claimed in claim 1, wherein: the auxiliary capacitance electrode of each pixel alternately overlaps with either the 1 st or 2 nd auxiliary capacitance line for every 1 column of pixels.

4. The active matrix type display device as claimed in claim 1, wherein: the auxiliary capacitance electrode of each pixel is alternately overlapped with any one of the 1 st or 2 nd auxiliary capacitance lines in units of a plurality of continuous columns of the pixels.

5. The active matrix type display device as claimed in claim 1, wherein: the 1 st and 2 nd auxiliary capacitance lines overlap all the auxiliary capacitance electrodes arranged corresponding to the respective rows of pixels forming the auxiliary capacitance lines.

6. The active matrix type display device according to claim 5, wherein: the auxiliary capacitance electrode has a dummy wiring in which one part of the 1 st or 2 nd auxiliary capacitance line forms an auxiliary capacitance and the other part overlaps an auxiliary capacitance line in which no auxiliary capacitance is formed.

7. The active matrix type display device as claimed in claim 1, wherein: in a pixel region where the pixel electrode is formed, the gate line is disposed between the 1 st and 2 nd auxiliary capacitance lines.

8. The active matrix type display device according to claim 7, wherein: in the pixel region, a gate electrode having the switching element structure is formed in a region where the storage capacitor electrode is provided, on the gate line, with the gate line as a boundary.

9. An active matrix display device, comprising: it is configured with several pixels in matrix form, and controls the display of each pixel; it is provided with a water-soluble polymer,

a plurality of pixel electrodes arranged in rows and columns on the 1 st substrate;

switching elements respectively connected to the pixel electrodes;

auxiliary capacitance electrodes respectively arranged in the pixel regions where the pixel electrodes are arranged;

1 st and 2 nd auxiliary capacitance lines arranged corresponding to the pixel electrodes in each row; and the number of the first and second groups,

1 st and 2 nd auxiliary capacitors formed in a direction facing either one of the 1 st or 2 nd auxiliary capacitor lines and the auxiliary capacitor electrodes; wherein,

by applying any one of the following voltages, that is, the 1 st video signal voltage, to the pixel electrode and the auxiliary capacitance electrode, the polarity of which is inverted every frame period; or 2 nd video signal voltage, which is opposite in polarity to the 1 st video signal voltage described above, while performing display,

the 1 st and 2 nd auxiliary capacitance voltages whose levels change while the switching element is in the off state are supplied to the 1 st and 2 nd auxiliary capacitance lines, respectively.

10. The active matrix type display device according to claim 9, wherein: while the switching element is in the on state, the 1 st video signal voltage is supplied to the 1 st auxiliary capacitance electrode, the 2 nd video signal voltage is supplied to the 2 nd auxiliary capacitance electrode,

while the switching element is in the OFF state, the level of the 1 st auxiliary capacitance voltage supplied to the 1 st auxiliary capacitance line is changed to a level of the same polarity as the 1 st video signal voltage,

the level of the 2 nd auxiliary capacitance voltage supplied to the 2 nd auxiliary capacitance line is changed to a level having the same polarity as the 2 nd video signal voltage.

11. The active matrix type display device according to claim 9, wherein: while the switching element is in the on state, supplying the 1 st video signal voltage to the 1 st auxiliary capacitance electrode, supplying a 1 st auxiliary capacitance voltage having a polarity opposite to that of the 1 st video signal voltage to the 1 st auxiliary capacitance line, supplying the 2 nd video signal voltage to the 2 nd auxiliary capacitance electrode, and supplying a 2 nd auxiliary capacitance voltage having a polarity opposite to that of the 2 nd video signal voltage to the 2 nd auxiliary capacitance line;

while the switching element is in the off state, the level of the 1 st storage capacitor voltage is changed to the level having the same polarity as the 1 st video signal voltage, and the level of the 2 nd storage capacitor voltage is changed to the level having the same polarity as the 2 nd video signal voltage.

12. The active matrix type display device according to claim 9, wherein: a common electrode is disposed on the No. 2 substrate, and a constant voltage is applied to the common electrode.

13. The active matrix type display device according to claim 9, wherein: while the switching element is in the off state, the levels of the 1 st and 2 nd storage capacitor voltages change immediately after the switching element is turned off.