CN1297252A - Multi-chip module device and manufacturing method thereof - Google Patents

Abstract

A multi-chip module device and a method for manufacturing the same. The multi-chip module device includes a substrate having a through hole with a predetermined circuit trace on one surface thereof, a first chip unit having a bonding pad mounting surface and a bonding pad mounted on one surface of the substrate such that a chip unit receiving space is formed between the first chip unit and a hole wall of the through hole of the substrate and the bonding pad is electrically connected to a corresponding circuit trace of the substrate, and at least a second chip unit disposed in the chip unit receiving space and having a bonding pad electrically connected to a corresponding bonding pad of the first chip unit.

Description

Multi-chip module device and manufacturing method thereof

The present invention relates to a multi-chip module device and a manufacturing method thereof, more particularly, relates to a multi-chip module device that combines chips with different functions and can improve the production yield of the multi-chip module device packaging method.

In today's increasingly progressive society, all portable electronic devices are striving towards the goal of being thin, light and small, and this trend is gradually infecting non-portable electronic devices in order to reduce the space they occupy. This phenomenon can be seen from the current popular desktop liquid crystal display computer. In order to reduce the overall volume of a computer, it is first necessary to reduce the volume of the motherboard. However, in terms of the functions required by the current computer, reducing the volume of the motherboard will inevitably cause the problem that the area of the motherboard is not enough to install the required components. Therefore, At present, the research units of the world's leading technology manufacturers are working hard towards how to provide a multi-chip module device that combines chips with different functions. However, the biggest problem that has plagued the multi-chip module device all the time is the low production yield, because as long as one of the chips has a problem, it will affect the entire multi-chip module device. In addition, since it is impossible to know which chip has the problem, all the chips must be recycled and tested one by one, which wastes manpower and material resources and greatly increases the cost.

One of the objectives of the present invention is to provide a multi-chip module device combining chips with different functions.

The second object of the present invention is to provide a packaging method for a multi-chip module device that can improve the production yield.

According to a feature of the present invention, a multi-chip module device includes: a substrate, the substrate has a first surface and a second surface opposite to the first surface, and at least one through hole is formed on the substrate Predetermined circuit traces are laid on one of the first and second surfaces; a first chip unit having a bonding pad mounting surface and a plurality of bonding pads mounted on the bonding pad mounting surface a first adhesive layer, the first adhesive layer has a first adhesive surface and a second adhesive surface, and is formed with a through hole corresponding to the perforation of the substrate and at least one for exposing the first For the window hole of the bonding pad of the chip unit, the first bonding surface of the first adhesive layer is bonded to the mounting surface of the bonding pad of the first chip unit, so that the hole wall forming each window hole and the first bonding pad A conductor accommodating space for accommodating a conductor electrically connected to the bonding pad is formed between a chip unit, and the second bonding surface of the first adhesive layer is connected to the substrate on which predetermined circuit traces are laid. The surface bonding makes it possible to fix the first chip unit on the substrate such that the electrical conductors are electrically connected to corresponding circuit traces on the first surface of the substrate, the perforated hole forming walls of the substrate being in contact with the first A chip unit capacity space is formed between the chip units; at least one second chip unit is accommodated in the chip unit accommodating space and has an adhesive pad mounting surface and a plurality of adhesive pads arranged on the adhesive pad an adhesive pad on the pad mounting surface; and at least one second adhesive layer formed with at least one window for exposing the adhesive pad of the second chip unit and having a first adhesive surface and a second adhesive surface, the first adhesive surface of these second adhesive layers is bonded to the adhesive pad mounting surface of the first chip unit so that the hole wall of the window hole of the second adhesive layer A conductor accommodating space for accommodating conductors electrically connected to the corresponding bonding pads of the first chip unit is formed between the first chip unit, and the second bonding surface of the second adhesive layer Adhesion to the bonding pad mounting surface of the second chip unit makes it possible to fix the second chip units on the first chip unit such that the conductors are electrically connected to the corresponding bonding pads of the second chip unit.

According to the characteristics of the present invention, a packaging method for a multi-chip module device is proposed, including the following steps: providing a first substrate, the first substrate has a first surface and a second surface opposite to the first surface , the first substrate is formed with a plurality of plated through-holes and predetermined circuit traces are arranged on the second surface of the first substrate, and a layer is electroplated on the wall of each plated through-hole electrically connected to the corresponding circuit traces. Conductive material, on the second surface of the first substrate is also provided with a plurality of test bumps, these test bumps are electrically connected with the corresponding circuit traces; a second substrate smaller in size than the first substrate is provided, the first substrate A second substrate is placed on the first substrate without covering the test bumps of the first substrate, the second substrate has a first surface bonded to the second surface of the first substrate and a first surface bonded to the second surface of the first substrate. On the second surface opposite to one surface, predetermined circuit traces are arranged on the second surface of the second substrate and a plurality of test bumps are arranged. The second substrate is also formed with a plurality of bumps corresponding to the first substrate. The plated through hole and a through hole are aligned so that a first chip unit accommodating space is formed between the hole forming wall of the second substrate and the first substrate, and each plating plated on the second substrate A layer of conductive material electrically connected to the corresponding circuit track of the second substrate and the conductive material of the corresponding plated through hole of the first substrate is electroplated on the hole wall of the through hole; The chip unit is placed in the accommodating space of the first chip unit, the first chip unit has a bonding pad mounting surface provided with a plurality of bonding pads, and the first adhesive layer has a connection with the first substrate. A first bonding surface bonded to the second surface and a second bonding surface bonded to the bonding pad mounting surface of the first chip unit, the first adhesive layer corresponding to the bonding of the first chip unit The pad is formed with a plurality of windows exposing the corresponding bonding pads of the first chip unit, and a hole for accommodating a Conductor accommodating space for conductors that realize the electrical connection between the bonding pad of the first chip unit and the corresponding circuit track of the first substrate; test the first chip unit through the test bump on the first substrate ; providing a third substrate smaller in size than the second substrate, the third substrate is placed on the second substrate without covering the test bumps of the second substrate, the third substrate has a The second surface of the second substrate is bonded to the first surface and a second surface opposite to the first surface, and a predetermined circuit track is arranged on the second surface of the third substrate and a plurality of test bumps are arranged, The third substrate is also formed with a plurality of plated through holes aligned with corresponding plated through holes of the second substrate and a through hole concentric with the through hole of the second substrate and larger than the through hole of the second substrate, So that a second chip unit accommodating space is formed between the through-hole forming wall of the third substrate and the second substrate, and a layer is electroplated on the hole wall of each plated through hole of the third substrate with the second substrate. The corresponding circuit traces of the three substrates and the conductive material of the corresponding plated through hole of the second substrate are electrically connected to the conductive material; a second chip unit is placed in the second chip unit by using a second adhesive layer space, the second chip unit has a bonding pad mounting surface provided with a plurality of bonding pads, the second adhesive layer has a first bonding surface bonded to the second surface of the second substrate and a A second adhesive surface bonded to the adhesive pad mounting surface of the second chip unit, the second adhesive layer corresponding to the adhesive pad of the second chip unit is formed with a plurality of corresponding exposed second chip units The window holes of the bonding pads, a hole forming wall for each window hole of the second adhesive layer and the second chip unit and the second substrate is formed for accommodating the second chip unit. The conductor accommodating space of the electrical conductor of the electrical connection between the bonding pad and the corresponding circuit track of the second substrate; the second chip unit is tested through the test bump on the second substrate; and all the substrates Edges trimmed to size.

In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is specifically cited below and described in detail with accompanying drawings. In the attached picture:

Fig. 1-7 depicts the schematic side view of the first preferred embodiment of the packaging method of the multi-chip module device of the present invention;

Figure 8 depicts a schematic plan view of the first substrate used in the first preferred embodiment of the present invention;

Figure 9 depicts a schematic perspective view of the adhesive layer used in the first preferred embodiment of the present invention;

Figure 10 depicts a schematic perspective view of another adhesive layer used in the first preferred embodiment of the present invention;

Fig. 11 depicts a schematic side view of another multi-chip module device fabricated using the first preferred embodiment of the present invention;

Fig. 12 depicts a schematic side view of yet another multi-chip module device fabricated using the first preferred embodiment of the present invention;

Fig. 13 depicts a schematic side view of yet another multi-chip module device fabricated using the first preferred embodiment of the present invention;

14-20 depict schematic side views of a second preferred embodiment of the packaging method of the multi-chip module device of the present invention;

Fig. 21 is a schematic side view of a third preferred embodiment of the multi-chip module device of the present invention;

22 is a schematic perspective view of a part of the substrate of the third preferred embodiment of the present invention;

Fig. 23 is a schematic perspective view of the first adhesive layer of the third preferred embodiment of the present invention;

Fig. 24 shows a partially enlarged schematic side view of the relationship between the electrical connection between the substrate and the chip unit in the third preferred embodiment of the present invention;

Fig. 25 shows another partially enlarged schematic side view of the relationship between the electrical connection between the substrate and the chip unit in the third preferred embodiment of the present invention;

Figure 26 shows a schematic perspective view of another form of the adhesive layer of Figure 23;

Fig. 27 is a schematic perspective view of the second adhesive layer of the third preferred embodiment of the present invention;

Figure 28 shows a schematic perspective view of another form of the adhesive layer of Figure 27;

Fig. 29 is a schematic side view of the fourth preferred embodiment of the multi-chip module device of the present invention;

Fig. 30 is a schematic side view of the fifth preferred embodiment of the multi-chip module device of the present invention;

Fig. 31 is a schematic side view of the sixth preferred embodiment of the multi-chip module device of the present invention;

Fig. 32 is a schematic side view of the seventh preferred embodiment of the multi-chip module device of the present invention;

Fig. 33 is a schematic side view of the eighth preferred embodiment of the multi-chip module device of the present invention;

Fig. 34 is a schematic side view of the ninth preferred embodiment of the multi-chip module device of the present invention;

Fig. 35 is a schematic side view of the tenth preferred embodiment of the multi-chip module device of the present invention;

Fig. 36 is a schematic side view of an eleventh preferred embodiment of the multi-chip module device of the present invention;

Fig. 37 is a schematic side view of a twelfth preferred embodiment of the multi-chip module device of the present invention;

Fig. 38 is a schematic side view of a thirteenth preferred embodiment of the multi-chip module device of the present invention;

Fig. 39 is a schematic side view of the fourteenth preferred embodiment of the multi-chip module device of the present invention;

Figure 40 is a schematic side view of a fifteenth preferred embodiment of the multi-chip module device of the present invention; and

Fig. 41 is a schematic side view of the sixteenth preferred embodiment of the multi-chip module device of the present invention.

As shown in FIG. 1 , the first preferred embodiment of the packaging method of the multi-chip module device of the present invention firstly provides a first substrate 101 a. The substrate 101a may be a circuit board or a metal plate coated with an insulating material. The first substrate 101a has a first surface 110a and a second surface 111a. A plurality of solder balls 112 are disposed on the first surface 110a of the first substrate 101a. The first substrate 101 a is also formed with a plurality of plated through holes 113 a corresponding to the solder balls 112 . A layer of conductive material electrically connected to the corresponding solder ball 112 is plated on the hole wall of each plated through hole 113 a. Please refer to FIG. 8 , predetermined circuit traces 114 are arranged on the second surface 111 a of the first substrate 101 a, and these circuit traces 114 are electrically connected to the conductive material of the corresponding plated through holes 113 a. A plurality of test bumps 115a are also disposed on the second surface 111a of the first substrate 101a. These test bumps 115 a are electrically connected to corresponding circuit traces 114 . The function of these test bumps 115a will be described in more detail later.

Referring to FIG. 2, a second substrate 101b having a smaller size than the first substrate 101a is placed on the first substrate 101a under the test bumps 115a that do not cover the first substrate 101a. Likewise, the second substrate 101b may be a circuit board or a metal plate coated with an insulating material. The second substrate 101b has a first surface 110b bonded to the second surface 111a of the first substrate 101a and a second surface 111b. On the second surface 111b of the second substrate 101b, predetermined circuit traces as shown in FIG. 8 are laid out and a plurality of test bumps 115b are arranged. The second substrate 101b is also formed with a plurality of plated through holes 113b aligned with the corresponding plated through holes 113a of the first substrate 101a and a through hole 116b such that the hole forming wall in the through hole 116b is aligned with the first substrate 101a. A first chip accommodating space is formed therebetween. On the hole wall of each plated through hole 113b of the second substrate 101b, a layer of conductive material electrically connected to the corresponding circuit track of the second substrate 101b and the conductive material of the corresponding plated through hole 113a of the first substrate 101a is electroplated. Material.

A first chip unit 102 is placed in the first chip unit accommodating space. The first chip unit 102 has a pad mounting surface 120 provided with a plurality of bonding pads 121 and a bottom surface 122 opposite to the pad mounting surface 120 . A metal heat sink 123 is installed on the bottom surface 122 of the first chip unit 102 .

A first adhesive layer 106a is disposed between the first chip unit 102 and the first substrate 101a. Please refer to FIG. 9, the first adhesive layer 106a has a first bonding surface 160a bonded to the second surface 111a of the first substrate 101a and a bonding pad mounted on the first chip unit 102- The second bonding surface 161a to which the surface 120 is bonded. The first adhesive layer 106 a is formed with a plurality of windows 162 a corresponding to the bonding pads 121 of the first chip unit 102 exposing the corresponding bonding pads 121 of the first chip unit 102 . Between the hole forming wall of each window hole 162a and the first chip unit 102 and the first substrate 101a, a bonding pad 121 for accommodating the first chip unit 102 and the first substrate 101a is formed. Corresponding circuit traces 114 are electrically connected to the conductor accommodating space of the conductor 104 . The conductor 104 can be formed by conductive silver paste (silver paste) and solder balls, solder paste and solder balls, conductive silver paste and conductive metal balls, or solder paste and conductive metal balls. It should be noted that the window holes 162a arranged in a row in the same longitudinal direction can also be replaced by a long hole.

At this time, the first chip unit 102 can be tested through the test bumps 115a on the first substrate 101a. If a problem is found, the first chip unit 102 can be repaired or replaced immediately.

Referring to FIG. 3 , a third substrate 101c having a smaller size than the second substrate 101b is placed on the second substrate 101b without covering the test bumps 115b of the second substrate 101b. Likewise, the third substrate 101c may be a circuit board or a metal plate coated with an insulating material. The third substrate 101c has a first surface 110c bonded to the second surface 111b of the second substrate 101b and a second surface 111c. On the second surface 111c of the third substrate 101c, predetermined circuit traces similar to those shown in FIG. 8 are laid out and a plurality of test bumps 115c are arranged. The third substrate 101c is also formed with a plurality of plated through holes 113c aligned with the corresponding plated through holes 113b of the second substrate 101b and a through hole 116b concentric with the second substrate 101b and lower than the second substrate 101b. The through hole 116b of 101b is larger than the through hole 116c, so that a second chip unit accommodating space is formed between the hole forming wall of the through hole 116c and the second substrate 101b. On the wall of each plated through hole 113c of the third substrate 101c, a layer of conductive material electrically connected to the corresponding circuit track of the third substrate 101c and the conductive material of the corresponding plated through hole 113b of the second substrate 101b is electroplated. Material.

A second chip unit 103 is placed in the second chip unit accommodating space. The second chip unit 103 has a pad mounting surface 130 provided with a plurality of bonding pads 131 and a bottom surface 132 opposite to the pad mounting surface 130 . A metal heat sink 133 is installed on the bottom surface 132 of the second chip unit 103 .

A second adhesive layer 106b is disposed between the second chip unit 103 and the second substrate 101b. Please refer to FIG. 10 , the second adhesive layer 106b has a first bonding surface 160b bonded to the second surface 111b of the second substrate 101b and a bonding pad mounting surface of the second chip unit 103 130 is bonded to the second bonding surface 161b. The second adhesive layer 106b is formed with a plurality of windows 162b corresponding to the bonding pads 131 of the second chip unit 103 to expose the corresponding bonding pads 131 of the second chip unit 103 and corresponding to the second substrate 101b. The through hole 116b forms a through hole 163b, so that the bonding pad mounting surface 130 of the second chip unit 103 without the bonding pad 131 is attached to the metal heat sink 123 of the first chip unit 102. Between the hole forming wall of each window hole 162b and the second chip unit 103 and the second substrate 101b, a bonding pad 131 for accommodating the second chip unit 103 and the second substrate 101b is formed. The corresponding circuit traces are electrically connected to the conductor accommodation space of the conductor 104 . Same as the first adhesive layer 106a, the windows 162b arranged in a row in the same longitudinal direction of the second adhesive layer 106b can also be replaced by a long hole.

At this time, the second chip unit 103 can be tested through the test bumps 115b on the second substrate 101b. If a problem is found, the second chip unit 103 can be repaired or replaced immediately.

Referring to FIG. 4, a fourth substrate 101d having a smaller size than the third substrate 101c is placed on the third substrate 101c without covering the test bumps 115c of the third substrate 101c. Likewise, the fourth substrate 101d may be a circuit board or a metal plate coated with an insulating material. The fourth substrate 101d has a first surface 110d bonded to the second surface 111c of the third substrate 101c and a second surface 111d. On the second surface 111d of the fourth substrate 101d, predetermined circuit traces of the type shown in FIG. 8 are laid out and a plurality of test bumps 115d are arranged. The fourth substrate 101d is also formed with a plurality of plated through holes 113d aligned with the corresponding plated through holes 113c of the third substrate 101c and a through hole 116c concentric with the third substrate 101c and lower than the third substrate 101c. The through hole 116c of 101c is larger than the through hole 116d, so that a third chip unit accommodating space is formed between the hole forming wall of the through hole 116d and the third substrate 101c. On the wall of each plated through hole 113d of the fourth substrate 101d, a layer of conductive material electrically connected to the corresponding circuit track of the fourth substrate 101d and the conductive material of the corresponding plated through hole 113c of the third substrate 101c is electroplated. Material.

A third chip unit 105 is placed in the third chip unit accommodating space. The third chip unit 105 has a bonding pad mounting surface 150 provided with a plurality of bonding pads 151 and a bottom surface 152 opposite to the bonding pad mounting surface 150 . A metal backing plate 153 is installed on the bottom surface 152 of the third chip unit 105 .

A third adhesive layer 106c is disposed between the third chip unit 105 and the third substrate 101c. The third adhesive layer 106c has a first bonding surface 160c bonded to the second surface 111c of the third substrate 101c and a second bonding surface 160c bonded to the bonding pad mounting surface 150 of the third chip unit 105. Adhesive surface 161c. The third adhesive layer 106c is formed with a plurality of window holes 162c corresponding to the bonding pads 151 of the third chip unit 105 that expose the corresponding bonding pads 151 of the third chip unit 105 and corresponding to the third substrate 101c. The through hole 106c forms a through hole 163c, so that the bonding pad mounting surface 150 of the third chip unit 105 without the bonding pad 151 is bonded to the metal heat sink 133 of the second chip unit 103 . Between the hole forming wall of each window hole 162c and the third chip unit 105 and the third substrate 101c, a bonding pad 151 for accommodating the third chip unit 105 and the third substrate 101c is formed. The corresponding circuit traces are electrically connected to the conductor accommodation space of the conductor 104 .

At this time, the third chip unit 105 can be tested through the test bumps 115c on the third substrate 101c. If a problem is found, the third chip unit 105 can be repaired or replaced immediately.

Referring to FIG. 5, a fifth substrate 101e having a size smaller than that of the fourth substrate 101d is placed on the fourth substrate 101d without covering the test bumps 115d of the fourth substrate 101d. Likewise, the fifth substrate 101e may be a circuit board or a metal plate coated with an insulating material. The fifth substrate 101e has a first surface 110e bonded to the second surface 111d of the fourth substrate 101d and a second surface 111e. On the second surface 111e of the fifth substrate 101e, predetermined circuit traces as shown in FIG. 8 are laid out and a plurality of test bumps 115e are arranged. The fifth substrate 101e is also formed with a plurality of plated through holes 113e aligned with the corresponding plated through holes 113d of the fourth substrate 101d and a through hole 116d concentric with the fourth substrate 101d and lower than the fourth substrate 101d. The through hole 116d of 101d is larger than the through hole 116e, so that a fourth chip unit accommodating space is formed between the hole forming wall of the through hole 116e and the fourth substrate 101d. On the hole wall of each plated through hole 113e of the fifth substrate 101e, a layer of conductive material electrically connected to the corresponding circuit track of the fifth substrate 101e and the conductive material of the corresponding plated through hole 113d of the fourth substrate 101d is electroplated. Material.

A fourth chip unit 107 is placed in the fourth chip unit accommodating space. The fourth chip unit 107 has a bonding pad mounting surface 170 provided with a plurality of bonding pads 171 and a bottom surface 172 opposite to the bonding pad mounting surface 170 . A metal heat sink 173 is installed on the bottom surface 172 of the fourth chip unit 107 .

A fourth adhesive layer 106d is placed between the fourth chip unit 107 and the fourth substrate 101d. The fourth adhesive layer 106d has a first bonding surface 160d bonded to the second surface 111d of the fourth substrate 101d and a second bonding surface 160d bonded to the bonding pad mounting surface 170 of the fourth chip unit 107. Adhesive surface 161d. The fourth adhesive layer 106d is formed with a plurality of window holes 162d corresponding to the bonding pads 171 of the fourth chip unit 107 corresponding to the bonding pads 171 of the fourth chip unit 107 and corresponding to the fourth substrate 101d. The through hole 116d forms a through hole 163d, so that the bonding pad mounting surface 170 of the fourth chip unit 107 without the bonding pad 171 is bonded to the metal heat sink 153 of the third chip unit 105 . Between the hole forming wall of each window hole 162d and the fourth chip unit 107 and the fourth substrate 101d, a bonding pad 171 for accommodating the fourth chip unit 107 and the fourth substrate 101d is formed. The corresponding circuit traces are electrically connected to the conductor accommodation space of the conductor 104 .

At this time, the fourth chip unit 107 can be tested through the test bumps 115d on the fourth substrate 101d. If a problem is found, the fourth chip unit 107 can be repaired or replaced immediately.

Referring to FIG. 6, a fifth chip unit 108 is mounted on the fifth substrate 101e through a fifth adhesive layer 106e. The fifth chip unit 108 has a pad mounting surface 180 provided with a plurality of bonding pads 181 and a bottom surface 182 opposite to the pad mounting surface 180 . A metal heat sink 183 is installed on the bottom surface 182 of the fifth chip unit 108 .

The fifth adhesive layer 106e is disposed between the fifth chip unit 108 and the fifth substrate 101e. The fifth adhesive layer 106e has a first bonding surface 160e bonded to the second surface 111e of the fifth substrate 101e and a second bonding surface 160e bonded to the bonding pad mounting surface 180 of the fifth chip unit 108. Adhesive surface 161e. The fifth adhesive layer 106e is formed corresponding to the bonding pad 181 of the fifth chip unit 108 with a plurality of windows 162e exposing the corresponding bonding pad 181 of the fifth chip unit 108 and corresponding to the fifth substrate 101e. The through hole 116e forms a through hole 163e, so that the bonding pad mounting surface 180 of the fifth chip unit 108 without the bonding pad 181 is bonded to the metal heat sink 173 of the fourth chip unit 107 . Between the hole forming wall of each window hole 162e and the fifth chip unit 108 and the fifth substrate 101e, a bonding pad 181 for accommodating the fifth chip unit 108 and the fifth substrate 101e is formed. The corresponding circuit traces are electrically connected to the conductor accommodation space of the conductor 104 .

At this time, the fifth chip unit 108 can be tested through the test bumps 115e on the fifth substrate 101e. If a problem is found, the fifth chip unit 108 can be repaired or replaced immediately.

Then, an encapsulation layer 109 is formed between the fifth chip unit 108 and the second surface 111e of the fifth substrate 101e, so as to prevent the fifth chip unit 108 from being directly impacted by external force and isolate moisture. In this embodiment, the encapsulation layer 109 is made of metal material. Of course, the encapsulation layer 109 can also be formed of materials such as epoxy resin.

Please refer to FIG. 7 , finally, the edges of the first to fifth substrates 101a to 101e are trimmed to a proper size to complete the packaging of the multi-chip module device.

It can be seen from the above description that the packaging method of the present invention combines testing procedures, so that the yield of the multi-chip module device after packaging can reach 100%. Therefore, it is possible to eliminate the need to test the recovered chips one by one for any problems in the past, saving manpower and material resources, and reducing costs.

Please refer to FIG. 11 , which shows another multi-chip module device manufactured by using the first preferred embodiment of the present invention. In this embodiment, after the first to fifth substrates 101a to 101e and the first to fourth chip units 102, 103, 105, 107 are assembled, a sixth substrate 101f that is smaller in size than the fifth substrate 101e does not cover the fifth substrate The test bumps of 101e are placed on the fifth substrate 101e. Likewise, the sixth substrate 101f may be a circuit board or a metal plate coated with an insulating material. The sixth substrate 101f has a first surface 110f bonded to the second surface 111e of the fifth substrate 101e and a second surface 111f. Predetermined circuit traces as shown in FIG. 8 are arranged on the second surface 111f of the sixth substrate 101f. The sixth substrate 101f is also formed with a plurality of plated through holes 113f aligned with the corresponding plated through holes 113e of the fifth substrate 101e and a through hole 116e concentric with the fifth substrate 101e and lower than the fifth substrate. The through hole 116e of 101e is larger than the through hole 116f, so that a fifth chip unit accommodating space is formed between the hole forming wall of the through hole 116f and the fifth substrate 101e. On the hole wall of each plated through hole 113f of the sixth substrate 101f, a layer of conductive material electrically connected to the corresponding circuit track of the sixth substrate 101f and the conductive material of the corresponding plated through hole 113e of the fifth substrate 101e is electroplated. Material.

The fifth chip unit 108 is placed in the fifth chip unit accommodating space. Since how the fifth chip unit 108 is installed on the fifth substrate 101e is the same as that described above, it will not be repeated here.

In this embodiment, between each chip unit 102, 103, 105, 107, 108 and the through-holes 116b, 116c, 116d, 116e, 116f of the corresponding substrate 101b, 101c, 101d, 101e, 101f is formed a hole formed by a material such as epoxy resin. encapsulation layer 109 .

Please refer to FIG. 12 , which shows yet another multi-chip module device manufactured by using the first preferred embodiment of the present invention. Different from the multi-chip module device shown in FIG. 7 , the solder balls 112 are disposed on the second surface 111e of the fifth substrate 101e.

Please refer to FIG. 13 , which shows yet another multi-chip module device manufactured by using the second preferred embodiment of the present invention. Different from the multi-chip module device shown in FIG. 11 , the solder balls 112 are disposed on the second surface 111f of the sixth substrate 101f.

Please refer to FIG. 14 , the second preferred embodiment of the packaging method of the multi-chip module device of the present invention firstly provides a substrate unit 101 . In this embodiment, the substrate unit 101 is composed of first to fifth substrates 101a to 101e. Since the materials and structures of these substrates 101a to 101e are the same as those of the first preferred embodiment of the present invention, details will not be repeated here.

After that, please refer to FIG. 15 , a first chip unit 102 is placed in the first chip unit accommodating space. The first chip unit 102 has a pad mounting surface 120 provided with a plurality of bonding pads 121 and a bottom surface 122 opposite to the pad mounting surface 120 . A metal heat sink 123 is installed on the bottom surface 122 of the first chip unit 102 .

A first adhesive layer 106a is disposed between the first chip unit 102 and the first substrate 101a. The first adhesive layer 106a has a first bonding surface 160a bonded to the second surface 111a of the first substrate 101a and a second bonding surface 160a bonded to the bonding pad mounting surface 120 of the first chip unit 102. Adhesive surface 161a. The first adhesive layer 106 a is formed with a plurality of windows 162 a corresponding to the bonding pads 121 of the first chip unit 102 exposing the corresponding bonding pads 121 of the first chip unit 102 . Between the hole forming wall of each window hole 162a and the first chip unit 102 and the second substrate 101a, a bonding pad 121 for accommodating the first chip unit 102 and the first substrate 101a is formed. Corresponding circuit traces 114 are electrically connected to the conductor accommodating space of the conductor 104 . The conductor 104 can be formed by conductive silver paste and solder balls, solder paste and solder balls, conductive silver paste and conductive metal balls, or solder paste and conductive metal balls.

At this time, the first chip unit 102 can be tested through the test bumps 115a on the first substrate 101a. If a problem is found, the first chip unit 102 can be repaired or replaced immediately.

Referring to FIG. 16 , a second chip unit 103 is placed in the second chip unit accommodating space. The second chip unit 103 has a pad mounting surface 130 provided with a plurality of bonding pads 131 and a bottom surface 132 opposite to the pad mounting surface 130 . A metal heat sink 133 is installed on the bottom surface 132 of the second chip unit 103 .

A second adhesive layer 106b is disposed between the second chip unit 103 and the second substrate 101b. The second adhesive layer 106b has a first bonding surface 160b bonded to the second surface 111b of the second substrate 101b and a second bonding surface 160b bonded to the bonding pad mounting surface 130 of the second chip unit 103. Adhesive surface 161b. The second adhesive layer 106b is formed with a plurality of windows 162b corresponding to the bonding pads 131 of the second chip unit 103 to expose the corresponding bonding pads 131 of the second chip unit 103 and corresponding to the second substrate 101b. The through hole 116b forms a through hole 163b, so that the bonding pad mounting surface 130 of the second chip unit 103 without the bonding pad 131 is attached to the metal heat sink 123 of the first chip unit 102. Between the hole forming wall of each window hole 162b and the second chip unit 103 and the second substrate 101b, a bonding pad 131 for accommodating the second chip unit 103 and the second substrate 101b is formed. The corresponding circuit traces are electrically connected to the conductor accommodation space of the conductor 104 .

At this time, the second chip unit 103 can be tested through the test bumps 115b on the second substrate 101b. If a problem is found, the second chip unit 103 can be repaired or replaced immediately.

Referring to FIG. 17 , a third chip unit 105 is placed in the third chip unit accommodating space. The third chip unit 105 has a bonding pad mounting surface 150 provided with a plurality of bonding pads 151 and a bottom surface 152 opposite to the bonding pad mounting surface 150 . A metal heat sink 153 is installed on the bottom surface 152 of the third chip unit 105 .

A third adhesive layer 106c is disposed between the third chip unit 105 and the third substrate 101c. The third adhesive layer 106c has a first bonding surface 160c bonded to the second surface 111c of the third substrate 101c and a second bonding surface 160c bonded to the bonding pad mounting surface 150 of the third chip unit 105. Adhesive surface 161c. The third adhesive layer 106c is formed with a plurality of window holes 162c corresponding to the bonding pads 151 of the third chip unit 105 that expose the corresponding bonding pads 151 of the third chip unit 105 and corresponding to the third substrate 101c. The through hole 116c forms a through hole 163c, so that the bonding pad mounting surface 150 of the third chip unit 105 without the bonding pad 151 is bonded to the metal heat sink 133 of the second chip unit 103 . Between the hole forming wall of each window hole 162c and the third chip unit 105 and the third substrate 101c, a bonding pad 151 for accommodating the third chip unit 105 and the third substrate 101c is formed. The corresponding circuit traces are electrically connected to the conductor accommodation space of the conductor 104 .

At this time, the third chip unit 105 can be tested through the test bumps 115c on the third substrate 101c. If a problem is found, the third chip unit 105 can be repaired or replaced immediately.

Referring to FIG. 18 , a fourth chip unit 107 is placed in the fourth chip unit accommodating space. The fourth chip unit 107 has a bonding pad mounting surface 170 provided with a plurality of bonding pads 171 and a bottom surface 172 opposite to the bonding pad mounting surface 170 . A metal heat sink 173 is installed on the bottom surface 172 of the fourth chip unit 107 .

A fourth adhesive layer 106d is placed between the fourth chip unit 107 and the fourth substrate 101d. The fourth adhesive layer 106d has a first bonding surface 160d bonded to the second surface 111d of the fourth substrate 101d and a second bonding surface 160d bonded to the bonding pad mounting surface 170 of the fourth chip unit 107. Adhesive surface 161d. The fourth adhesive layer 106d is formed with a plurality of window holes 162d corresponding to the bonding pads 171 of the fourth chip unit 107 corresponding to the bonding pads 171 of the fourth chip unit 107 and corresponding to the fourth substrate 101d. The through hole 116d forms a through hole 163d, so that the bonding pad mounting surface 170 of the fourth chip unit 107 without the bonding pad 171 is bonded to the metal heat sink 153 of the third chip unit 105 . Between the hole forming wall of each window hole 162d and the fourth chip unit 107 and the fourth substrate 101d, a bonding pad 171 for accommodating the fourth chip unit 107 and the fourth substrate 101d is formed. The corresponding circuit traces are electrically connected to the conductor accommodation space of the conductor 104 .

At this time, the fourth chip unit 107 can be tested through the test bumps 115d on the fourth substrate 101d. If a problem is found, the fourth chip unit 107 can be repaired or replaced immediately.

Referring to FIG. 19, a fifth chip unit 108 is mounted on the fifth substrate 101e through a fifth adhesive layer 106e. The fifth chip unit 108 has a pad mounting surface 180 provided with a plurality of bonding pads 181 and a bottom surface 182 opposite to the pad mounting surface 180 . A metal heat sink 183 is installed on the bottom surface 182 of the fifth chip unit 108 .

The fifth adhesive layer 106e is disposed between the fifth chip unit 108 and the fifth substrate 101e. The fifth adhesive layer 106e has a first bonding surface 160e bonded to the second surface 111e of the fifth substrate 101e and a second bonding surface 160e bonded to the bonding pad mounting surface 180 of the fifth chip unit 108. Adhesive surface 161e. The fifth adhesive layer 106e is formed corresponding to the bonding pad 181 of the fifth chip unit 108 with a plurality of windows 162e exposing the corresponding bonding pad 181 of the fifth chip unit 108 and corresponding to the fifth substrate 101e. The through hole 116e forms a through hole 163e, so that the bonding pad mounting surface 180 of the fifth chip unit 108 without the bonding pad 181 is bonded to the metal heat sink 173 of the fourth chip unit 107 . Between the hole forming wall of each window hole 162e and the fifth chip unit 108 and the fifth substrate 101e, a bonding pad 181 for accommodating the fifth chip unit 108 and the fifth substrate 101e is formed. The corresponding circuit traces are electrically connected to the conductor accommodation space of the conductor 104 .

At this time, the fifth chip unit 108 can be tested through the test bumps 115e on the fifth substrate 101e. If a problem is found, the fifth chip unit 108 can be repaired or replaced immediately.

Then, referring to FIG. 20, an encapsulation layer 109 is formed between the fifth chip unit 108 and the second surface 111e of the fifth substrate 101e, thereby preventing the fifth chip unit 108 from being directly hit by external force and Insulate from moisture. In this embodiment, the encapsulation layer 109 is made of metal material. Of course, the encapsulation layer 109 can also be formed of materials such as epoxy resin. Finally, the edges of the first to fifth substrates 101a to 101e are trimmed to a proper size to complete the packaging of the multi-chip module device.

It should be noted that the multi-chip module arrangement shown in FIGS. 11-13 can also be made by the second preferred embodiment of the present invention.

Referring to FIG. 21 , the third preferred embodiment of the multi-chip module device of the present invention is shown to include a substrate 201 , a first chip unit 202 and two second chip units 203 .

The substrate 201 may be a circuit board or a metal plate coated with insulating material. The substrate 201 has a first surface 210 and a predetermined circuit trace 212 (see FIG. 22 ) and a plurality of electrical circuits for connecting the corresponding circuit trace 212 to an external circuit (not shown) are arranged on the first surface 210. Connected solder balls 213 . In this embodiment, the substrate 201 is formed with two through holes 211 .

The first chip unit 202 has a bonding pad mounting surface 220 and a plurality of bonding pads 221 are disposed on the bonding pad mounting surface 220 . Please refer to FIG. 23, a first adhesive layer 204 has a first adhesive surface 240 and a second adhesive surface 241, and is formed with two through holes 242 corresponding to the through holes 211 of the substrate 201 and a plurality of Corresponds to the window hole 243 of the bonding pad 221 of the first chip unit 202 . The first bonding surface 240 of the first adhesive layer 204 is bonded to the bonding pad mounting surface 220 of the first chip unit 202 . A conductor accommodating space for accommodating the conductor 205 electrically connected to the bonding pad 221 is formed between the hole wall forming each window hole 243 and the first chip unit 202 . The conductor 205 may be formed by conductive solder balls and conductive silver paste, conductive solder balls and solder paste, conductive silver paste and metal balls placed through a wire bonding machine, or solder paste and metal balls. Referring to FIG. 4 , conductive solder balls or metal balls 250 can be placed on the bonding pads 221 of the first chip unit 202 , and conductive silver glue or solder paste 251 can be placed on the corresponding first surface 210 of the substrate 201 . Location. Alternatively, as shown in FIG. 25 , conductive silver paste or solder paste 251 can be placed on the bonding pad 221 of the first chip unit 202, and conductive solder balls or metal balls 250 can be placed on the first surface 210 of the substrate 201. corresponding position on the . The second adhesive surface 241 of the first adhesive layer 204 is bonded to the first surface 210 of the substrate 201, the first chip unit 202 can be fixed on the substrate 201 and the conductor 205 is connected to the substrate 201 Corresponding circuit traces 212 on the first surface 210 are electrically connected. A chip unit accommodating space is formed between the hole forming wall of each through hole 211 and the first chip unit 202 .

In order to dissipate heat and protect the first chip unit 202 , a metal heat dissipation plate 223 is disposed on the bottom surface 222 of the first chip unit 202 opposite to the bonding pad mounting surface 220 .

An encapsulation layer 224 is further disposed between the first chip unit 202 and the first surface 210 of the substrate 201 to further protect the first chip unit 202 . The encapsulation layer 224 may be formed of materials such as epoxy resin.

It should be noted that the windows 243 of the first adhesive layer 204 arranged in a row in the longitudinal direction can also be replaced by a long hole, as shown in FIG. 26 .

Each of the second chip units 203 is accommodated in a corresponding chip unit accommodating space and has an adhesive pad mounting surface 230 . A plurality of adhesive pads 231 are provided on the adhesive pad mounting surface 230 . Please refer to FIG. 27 , each second chip unit 203 is disposed on the first chip unit 202 by a second adhesive layer 206 . The second adhesive layer 206 is formed with a plurality of windows 262 for exposing the bonding pads 221 of the second chip unit 202 and the first bonding surface 260 of the second adhesive layer 206 is connected to the first chip unit. The bonding pad mounting surface 220 of the window hole 202 is bonded so that a conductor accommodating space for accommodating the conductor 205 is formed between the hole wall forming each window hole 262 and the first chip unit 202 . The second bonding surface 261 of the second adhesive layer 206 is bonded to the bonding pad mounting surface 230 of the second chip unit 203 , so that the second chip unit 203 can be fixed on the first chip unit 202 . The electrical connection between the first chip unit 202 and the second chip units 203 is realized by the conductors 205 .

A metal heat sink 233 is disposed on the bottom surface 232 of each second chip unit 203 opposite to the bonding pad mounting surface 230 .

An encapsulation layer 234 is also provided between the periphery of each second chip unit 203 and the through hole 211 of the substrate 201 , so as to further protect the second chip unit 203 . The encapsulation layer 234 may be formed of materials such as epoxy resin.

It should be noted that the first chip unit 202 and the second chip units 203 are functionally different, for example, the first chip unit 202 may be a CPU, and the second chip units 203 may be memory.

As shown in FIG. 28 , the windows 262 of the second adhesive layer 206 arranged in a row in the longitudinal direction can also be replaced by a long hole.

It should be noted that the second surface 214 of the substrate 201 opposite to the first surface 210 may also be provided with circuit traces as shown in FIG. Hole 215. The hole wall of each plated through hole 215 is plated with a conductive material that is electrically connected to the circuit track and the solder ball 213 on the second surface 214 of the substrate 201, so that other circuit components (not shown) can be surface-attached to the surface of the substrate 201. on the second surface 214 .

Please refer to Fig. 29, which shows a schematic side view of the fourth preferred embodiment of the present invention. In this embodiment, a third chip unit 207 is further included, and the third chip unit 207 has a bonding pad mounting surface 270 provided with a plurality of bonding pads 271 . A first adhesive surface 280 of the third adhesive layer 208 having the same structure as the first adhesive layer 204 of FIG. A conductor for accommodating the conductor 205 electrically connected to the corresponding bonding pad 271 of the third chip unit 207 is formed between the hole wall of each window hole 282 of the three adhesive layers 208 and the third chip unit 207 Accommodate space. The second bonding surface 281 of the third adhesive layer 208 is bonded to the second surface 214 of the substrate 201 , so that the third chip unit 207 can be disposed on the second surface 214 of the substrate 201 . The bonding pad 271 of the third chip unit 207 is electrically connected to the corresponding circuit trace on the second surface 214 of the substrate 201 through the conductor 205 .

A metal heat sink 273 is mounted on the bottom surface 272 of the third chip unit 207 opposite to the bonding pad mounting surface 270 . It should be noted that, the area of the bonding pad mounting surface 270 of the third chip unit 207 where the bonding pad 271 is not provided is attached to the metal heat sink 233 of the second chip units 203 .

An encapsulation layer 274 is further disposed between the periphery of the third chip unit 207 and the second surface 214 of the substrate 102 to further protect the third chip unit 207 .

In this embodiment, the encapsulation layer 274 is formed of a material such as epoxy resin, however, the encapsulation layer 274 may also be formed of a metal material. If the encapsulation layer 274 is formed of a metal material, the encapsulation layer between the periphery of each second chip unit 203 and the hole wall of the through hole 211 of the substrate 201 can be dispensed with.

Please refer to FIG. 30, the fifth preferred embodiment of the present invention is shown to include a first substrate 201a, a second substrate 201b, a first chip unit 202a, a third substrate 201c, a second chip unit 203a and three third substrates. Three-chip unit 207a.

The first substrate 201a may be a circuit board or a metal plate coated with an insulating material. The first substrate 201a has a first surface 210a with a plurality of solder balls 213a and a second surface 214a with predetermined circuit traces as shown in FIG. The through hole 215a. The wall of each plated through hole 215a is plated with a conductive material electrically connected to the corresponding solder ball 213a and the corresponding circuit trace on the second surface 214a.

The second substrate 201b may be a circuit board or a metal plate coated with an insulating material. The second substrate 201b has a first surface 210b bonded to the second surface 214a of the first substrate 201a and a second surface 214b on which predetermined circuit traces are arranged as shown in FIG. The corresponding plated through hole 215a of the first substrate 201a is aligned with the plated through hole 215b. The hole wall of each plated through hole 215b is plated with a conductive material electrically connected to the corresponding circuit track on the second surface 214a of the first substrate 201a and to the corresponding circuit track on the second surface 214b of the second substrate 201b . The second substrate 201b is further formed with a through hole 211b, so that a chip unit accommodating space is formed between the wall of the through hole 211b and the first substrate 201a.

The first chip unit 202a is placed in the chip unit accommodating space and has a bonding pad mounting surface 220a provided with a plurality of bonding pads 221a. A first adhesive layer 206a has a first adhesive surface 260a and a second adhesive surface 261a, and is formed with a plurality of windows 262a corresponding to the adhesive pads 221a of the first chip unit 202a. The bonding pad mounting surface 220a of the first chip unit 202a is bonded to the first bonding surface 260a of the first adhesive layer 206a so that between the hole forming walls of each window hole 262a and the first chip unit 202a A conductor accommodating space for accommodating the first conductor 205a is formed. The first conductor 205a is electrically connected to the corresponding bonding pad 221a of the first chip unit 202a. The second adhesive surface 261a of the first adhesive layer 206a is bonded to the second surface 214a of the first substrate 201a, so that the first chip unit 202a can be disposed on the second surface 214a of the first substrate 201a . The first conductor 205a is also electrically connected to the corresponding circuit trace on the second surface 214a of the first substrate 201a. A metal heat sink 223a is mounted on the bottom surface 222a of the first chip unit 202a opposite to the bonding pad mounting surface 220a. An encapsulation layer 224a is formed between the periphery of the first chip unit 202a and the wall of the through hole 211b of the first substrate 201b.

The third substrate 201c may be a circuit board or a metal plate coated with an insulating material. The third substrate 201c has a first surface 210c bonded to the second surface 214b of the second substrate 201b and a second surface 214c on which predetermined circuit traces are arranged as shown in FIG. The corresponding plated through hole 215b of the second substrate 201b is aligned with the plated through hole 215c. The hole wall of each plated through hole 215c is plated with a conductive material electrically connected to the corresponding circuit track on the second surface 214b of the second substrate 201b and to the corresponding circuit track on the second surface 214c of the third substrate 201c . The third substrate 201c is further formed with a through hole 211c, so that a chip unit accommodating space is formed between the wall of the through hole 211c and the second substrate 201b.

The second chip unit 203a is placed in the chip unit accommodating space formed between the second substrate 201b and the wall of the through hole 211c of the third substrate 201c and has a plurality of bonding pads 231a. Adhesive pad mounting surface 230a. A second adhesive layer 206b has a first adhesive surface 260b and a second adhesive surface 261b, and is formed with a plurality of windows 262b corresponding to the adhesive pads 231a of the second chip unit 203a. The bonding pad mounting surface 230a of the second chip unit 203a is bonded to the first bonding surface 260b of the second adhesive layer 206b so that between the hole forming wall of each window hole 262b and the second chip unit 203a A conductor accommodating space for accommodating the second conductor 205b is formed. The second conductor 205b is electrically connected to the corresponding bonding pad 231a of the second chip unit 203a. The second bonding surface 261b of the second adhesive layer 206b is bonded to the second surface 214b of the second substrate 201b, so that the second chip unit 203a can be disposed on the second surface 214b of the second substrate 201b . The second conductor 205b is also electrically connected to the corresponding circuit trace on the second surface 214b of the second substrate 201b. A metal heat sink 233a is mounted on the bottom surface 232a of the second chip unit 203a opposite to the bonding pad mounting surface 230a. An encapsulation layer 234a is formed between the periphery of the second chip unit 203a and the wall of the through hole 211c of the third substrate 201c.

Each of the third chip units 207a has a bonding pad mounting surface 270a provided with a plurality of bonding pads 271a. Each third chip unit 207a is mounted on the second surface 214c of the third substrate 201c through a third adhesive layer 206c. The third adhesive layer 206c has a first adhesive surface 260c and a second adhesive surface 261c, and a plurality of windows 262c are formed corresponding to the third chip unit 207a. The first bonding surface 260c of the third adhesive layer 206c is bonded to the bonding pad mounting surface 270a of the third chip unit 207a so that between the hole forming wall of each window hole 262c and the third chip unit 207a A conductor accommodating space for accommodating the third conductor 205c is formed. One of the third adhesive layers 206c also forms a through hole 262c corresponding to the through hole 211c of the second adhesive layer 201c. The third conductor 205c is electrically connected to the corresponding bonding pad 271a of the third chip unit 207a. The second bonding surface 261c of the third adhesive layer 206c is bonded to the second surface 214c of the third substrate 201c, so that the third chip unit 207a can be disposed on the second surface 214c of the third substrate 201c . The third conductor 205c is also electrically connected to the corresponding circuit trace on the second surface 214c of the third substrate 201c.

A metal heat sink 273a is disposed on the bottom surface 272a of each third chip unit 207a opposite to the bonding pad mounting surface 270a. It should be noted that the portion of the region where the bonding pad 271a is not provided on the bonding pad mounting surface 270a of the third chip unit 207a bonded to the adhesive layer 206a formed with the through hole 262c is the same as that of the second chip unit 203a. The metal cooling plates 233a are bonded together. In addition, an encapsulation layer 274a is formed between the periphery of each third chip unit 207a and the second surface 214c of the third substrate 201c.

31, the sixth preferred embodiment of the present invention is shown to include a first substrate 201a, a second substrate 210b, a first chip unit 202a, a third substrate 201c, a second chip unit 203a, a fourth The substrate 201d, a third chip unit 207a and a fourth chip unit 209.

The first substrate 201a may be a circuit board or a metal plate coated with an insulating material. The first substrate 210a has a first surface 210a with a plurality of solder balls 213a and a second surface 214a with predetermined circuit traces as shown in FIG. The through hole 215a. The hole forming wall of each plated through hole 215a is plated with a conductive material electrically connected to the corresponding solder ball 213a and the corresponding circuit trace on the second surface 214a.

The second substrate 210b may be a circuit board or a metal plate coated with an insulating material. The second substrate 210b has a first surface 210b bonded to the second surface 214a of the first substrate 210a and a second surface 214b on which predetermined circuit traces are arranged as shown in FIG. The corresponding plated through hole 215a of the first substrate 201a is aligned with the plated through hole 215b. The hole forming wall of each plated through hole 215a is electroplated with the corresponding circuit trace on the second surface 214a of the first substrate 201a and electrically connected with the corresponding circuit trace on the second surface 214b of the second substrate 201b. conductive material. The second substrate 201b is further formed with a through hole 211b, so that a chip unit accommodating space is formed between the wall of the through hole 211b and the first substrate 201a.

The first chip unit 202a is placed in the chip unit accommodating space, and has a bonding pad mounting surface 220a provided with a plurality of bonding pads 221a. A first adhesive layer 206a has a first adhesive surface 260a and a second adhesive surface 261a, and is formed with a plurality of windows 262a corresponding to the adhesive pads 221a of the first chip unit 202a. The bonding pad mounting surface 220a of the first chip unit 202a is bonded to the first bonding surface 260a of the first adhesive layer 206a so that between the hole forming walls of each window hole 262a and the first chip unit 202a A conductor accommodating space for accommodating the first conductor 205a is formed. The first conductor 205a is electrically connected to the corresponding bonding pad 221a of the first chip unit 202a. The second adhesive surface 261a of the first adhesive layer 206a is bonded to the second surface 214a of the first substrate 201a, so that the first chip unit 202a can be disposed on the second surface 214a of the first substrate 201a . The first conductor 205a is also electrically connected to the corresponding circuit trace on the second surface 214a of the first substrate 201a.

A metal heat sink 223a is mounted on the bottom surface 222a of the first chip unit 202a opposite to the bonding pad mounting surface 220a. An encapsulation layer 224a is formed between the periphery of the first chip unit 202a and the wall of the through hole 211b of the second substrate 201b.

The third substrate 201c may be a circuit board or a metal plate coated with an insulating material. The third substrate 201c has a first surface 210c bonded to the second surface 214b of the second substrate 201b and a second surface 214c on which predetermined circuit traces are arranged as shown in FIG. The corresponding plated through hole 215b of the second substrate 201b is aligned with the plated through hole 215c. The hole wall of each plated through hole 215c is plated with a conductive material electrically connected to the corresponding circuit track on the second surface 214b of the second substrate 201b and to the corresponding circuit track on the second surface 214c of the third substrate 201c . The third substrate 201c is further formed with a through hole 211c, so that a chip unit accommodating space is formed between the wall of the through hole 211c and the second substrate 201b. In this embodiment, the through hole 211c of the third substrate 201c is coaxial with the through hole 211b of the second substrate 201b and is larger than the through hole 211b of the second substrate 201b.

The second chip unit 203a is placed in the chip unit accommodating space formed between the second substrate 210b and the hole wall of the through hole 211c of the third substrate 210c, and has a plurality of bonding pads 231a. The adhesive pad mounting surface 230a. A second adhesive layer 206b has a first bonding surface 260b and a second bonding surface 261b, and forms a through hole 263b corresponding to the through hole 211b of the second substrate 201b and a plurality of holes 263b corresponding to the second chip unit The window 262b corresponds to the adhesive pad 231a of 203a. The bonding pad mounting surface 230a of the second chip unit 203a is bonded to the first bonding surface 260b of the second adhesive layer 206b, so that the hole forming wall of each window hole 262b is formed between the second chip unit 203a. A conductor accommodating space for accommodating the second conductor 205b is formed between them. The second conductor 205b is electrically connected to the corresponding bonding pad 231a of the second chip unit 203a. The second bonding surface 261b of the second adhesive layer 206b is bonded to the second surface 214b of the second substrate 201b, so that the second chip unit 203a can be disposed on the second surface 214b of the second substrate 201b . The second conductor 205b is also electrically connected to the corresponding circuit trace on the second surface 214b of the second substrate 201b.

A metal heat dissipation plate 233a is disposed on the bottom surface 232a of the second chip unit 203a opposite to the bonding pad mounting surface 230a. It should be noted that the bonding pad mounting surface 230a of the second chip unit 203a is bonded to the metal heat sink 223a of the first chip unit 202a in the area where the bonding pad 231a is not provided. An encapsulation layer 234a is formed between the periphery of the second chip unit 203a and the third substrate 201c.

The fourth substrate 201d may be a circuit board or a metal plate coated with an insulating material. The fourth substrate 201d has a first surface 210d bonded to the second surface 214c of the third substrate 201c and a second surface 214d on which predetermined circuit traces are arranged as shown in FIG. The corresponding plated through hole 215c of the third substrate 201c is aligned with the plated through hole 215d. The hole wall of each plated through hole 215d is plated with a conductive material electrically connected to the corresponding circuit track on the second surface 214c of the third substrate 201c and to the corresponding circuit track on the second surface 214d of the fourth substrate 201d . The fourth substrate 201d is further formed with a through hole 211d, so that a chip unit accommodating space is formed between the wall of the through hole 211d and the third substrate 201c. In this embodiment, the through hole 211d of the fourth substrate 201d is coaxial with the through hole 211c of the third substrate 201c and is larger than the through hole 211c of the third substrate 201c.

The third chip unit 207a is placed in the chip unit accommodating space formed between the third substrate 201c and the hole wall of the through hole 211d of the fourth substrate 201d and has a plurality of bonding pads 271a disposed thereon. Adhesive pad mounting surface 270a. The third chip unit 207a is mounted on the second surface 214c of the third substrate 201c through a third adhesive layer 206c. The third adhesive layer 206c has a first bonding surface 260c and a second bonding surface 261c, and is formed with a through hole 263c corresponding to the through hole 211c of the third substrate 201c and a plurality of holes 263c corresponding to the third chip unit. The window 262c corresponds to the adhesive pad 271a of 207a. The first bonding surface 260c of the third adhesive layer 206c is bonded to the bonding pad mounting surface 270a of the third chip unit 207a so that between the hole forming wall of each window hole 262c and the third chip unit 207a A conductor accommodating space for accommodating the third conductor 205c is formed. The third conductor 205c is electrically connected to the corresponding bonding pad 271a of the third chip unit 207a. The second bonding surface 261c of the third adhesive layer 206c is bonded to the second surface 214c of the third substrate 201c, so that the third chip unit 207a can be disposed on the second surface 214c of the third substrate 201c . The third conductor 205c is also electrically connected to the corresponding circuit trace on the second surface 214c of the third substrate 201c.

A metal heat sink 273a is disposed on the bottom surface 272a of the third chip unit 207a opposite to the bonding pad mounting surface 270a. It should be noted that the bonding pad mounting surface 270a of the third chip unit 207a is bonded to the metal heat sink 233a of the second chip unit 203a in the area where the bonding pad 271a is not provided. An encapsulation layer 274a is formed between the periphery of the third chip unit 207a and the fourth substrate 201d.

The fourth chip unit 209 has a bonding pad mounting surface 290 provided with a plurality of bonding pads 291 . The fourth chip unit 209 is mounted on the second surface 214d of the fourth substrate 201d through a fourth adhesive layer 206d. The fourth adhesive layer 206d has a first bonding surface 260d and a second bonding surface 261d, and is formed with a through hole 263d corresponding to the through hole 211d of the fourth substrate 201d and a plurality of holes 263d corresponding to the fourth chip unit. The adhesive pad 291 of 209 corresponds to the window 262d. The first bonding surface 260d of the fourth adhesive layer 206d is bonded to the bonding pad mounting surface 290 of the fourth chip unit 209, so that the hole forming wall of each window hole 262d and the fourth chip unit 209 are bonded. A conductor accommodating space for accommodating the fourth conductor 205d is formed between them. The fourth conductor 205d is electrically connected to the corresponding bonding pad 291 of the fourth chip unit 209 . The second adhesive surface 261d of the fourth adhesive layer 206d is bonded to the second surface 214d of the fourth substrate 201d, so that the fourth chip unit 209 can be disposed on the second surface 214d of the fourth substrate 201d . The fourth conductor 205d is also electrically connected to the corresponding circuit trace on the second surface 214d of the fourth substrate 201d.

A metal heat sink 293 is disposed on the bottom surface 292 of the fourth chip unit 209 opposite to the bonding pad mounting surface 290 . It should be noted that, the area of the bonding pad mounting surface 290 of the fourth chip unit 209 where no bonding pad 291 is provided is attached to the metal heat dissipation plate 273a of the third chip unit 207a.

In addition, an encapsulation layer 294 is formed between the periphery of the fourth chip unit 209 and the second surface 214d of the fourth substrate 201d. The encapsulation layer 294 may be formed of epoxy resin.

It should be noted that, in this embodiment, a plurality of second surfaces 214a, 214b, 214c that are compatible with the substrates 201a, 201b, 201c are also provided on the first, second and third substrates 201a, 201b, 201c The corresponding circuit traces on the circuit board are electrically connected, and are suitable for testing contact points TP that are electrically connected with test probes (not shown in the figure). In this way, the chip units 202a, 203a, 207a, 209 mounted on the respective substrates 201a, 201b, 201c, 201d can be tested via the corresponding test contact points TP.

Please refer to Fig. 32, which shows the seventh preferred embodiment of the present invention. Different from the sixth preferred embodiment, this embodiment further includes a fifth substrate 201e, a sixth substrate 201f and a fifth chip unit D5.

The fifth substrate 201e may be a circuit board or a metal plate coated with an insulating material. The fifth substrate 201e has a first surface 210e bonded to the second surface 214e of the fourth substrate 201e and a second surface 214e on which predetermined circuit traces are arranged as shown in FIG. The corresponding plated through hole 215d of the fourth substrate 201d is aligned with the plated through hole 215e. The hole wall of each plated through hole 215e is plated with a conductive material electrically connected to the corresponding circuit track on the second surface 214d of the fourth substrate 201d and to the corresponding circuit track on the second surface 214e of the fifth substrate 201e . The fifth substrate 201e is further formed with a through hole 211e, so that a chip unit accommodating space for accommodating the fourth chip unit 209 is formed between the hole wall of the through hole 211e and the fourth substrate 201d. In this embodiment, the through hole 211e of the fifth substrate 201e is coaxial with the through hole 211d of the fourth substrate 201d and is larger than the through hole 211d of the fourth substrate 201d.

The sixth substrate 201f may be a circuit board or a metal plate coated with an insulating material. The sixth substrate 201f has a first surface 210f bonded to the second surface 214e of the fifth substrate 201e and a second surface 214f on which predetermined circuit traces are laid out as shown in FIG. The corresponding plated through hole 215e of the fifth substrate 201e is aligned with the plated through hole 215f. The hole wall of each plated through hole 215f is plated with a conductive material electrically connected to the corresponding circuit track on the second surface 214e of the fifth substrate 201e and to the corresponding circuit track on the second surface 214f of the sixth substrate 201f . The sixth substrate 201f is formed with a through hole 211f, so that a chip unit accommodating space is formed between the hole wall of the through hole 211f and the fifth substrate 201e. In this embodiment, the through hole 211f of the sixth substrate 201f is coaxial with the through hole 211e of the fifth substrate 201e and is larger than the through hole 211e of the fifth substrate 201e.

The fifth chip unit D5 is placed in the chip unit accommodating space formed between the fifth substrate 201e and the hole wall of the through hole 211f of the sixth substrate 201f and has a plurality of bonding pads D51 disposed thereon. Adhesive pad mounting surface D50. The fifth chip unit D5 is mounted on the second surface 214e of the fifth substrate 201e through a fifth adhesive layer 206e. The fifth adhesive layer 206e has a first bonding surface 260e and a second bonding surface 261e, and forms a through hole 263e corresponding to the through hole 211e of the fifth substrate 201e and a plurality of holes 263e corresponding to the fifth chip unit. The window hole 262e corresponds to the adhesive pad D51 of D5. The first bonding surface 260e of the fifth adhesive layer 206e is bonded to the bonding pad mounting surface D50 of the fifth chip unit D5 so that between the hole forming walls of each window hole 262e and the fifth chip unit D5 A conductor accommodating space for accommodating the fifth conductor 205e is formed. The fifth conductor 205e is electrically connected to the corresponding bonding pad D51 of the fifth chip unit D5. The second adhesive surface 261e of the fifth adhesive layer 206e is bonded to the second surface 214e of the fifth substrate 201e, so that the fifth chip unit D5 can be disposed on the second surface 214e of the fifth substrate 201e . The fifth electrical conductor 205e is also electrically connected to the corresponding circuit trace on the second surface 214e of the fifth substrate 201e.

A metal heat sink D53 is disposed on the bottom surface D52 of the fifth chip unit D5 opposite to the bonding pad mounting surface D50 . It should be noted that, the area of the bonding pad mounting surface D50 of the fifth chip unit D5 where the bonding pad D51 is not provided is attached to the metal heat dissipation plate 293 of the fourth chip unit 209 .

In addition, an encapsulation layer 224a, 234a, 274a, 294, D54 is formed between each chip unit 202a, 203a, 207a, 209, D5 and the hole wall of the corresponding through hole 211b to 211f of the substrate 201b to 201f.

It should be noted that, in this embodiment, the first chip unit 202a can be a memory, the second chip unit 203a can be an input/output control chip unit, and the third chip unit 207a can be a graphics control chip unit, the fourth chip unit 209 may be a chipset chip unit, and the fifth chip unit D5 may be a central processing unit.

33, the eighth preferred embodiment of the present invention is shown to include a first substrate 201a, a second substrate 201b, a first chip unit 202a, a third substrate 201c, a second chip unit 203a, a fourth The substrate 201d , a third chip unit 207a , a fifth substrate 201e and a fourth chip unit 209 .

The first substrate 201a may be a circuit board or a metal plate whose surface is coated with insulating material. The first substrate 201a has a first surface 210a with a plurality of solder balls 213a and a second surface 214a with predetermined circuit traces as shown in FIG. The through hole 215a. The hole formation of each plated through-hole 215a is plated with conductive material on the wall for electrical connection with the corresponding solder ball 213a and the corresponding circuit trace on the second surface 214a.

The second substrate 201b may be a circuit board or a metal plate coated with an insulating material. The second substrate 201b has a first surface 210b bonded to the second surface 214a of the first substrate 201a and a second surface 214b on which predetermined circuit traces are arranged as shown in FIG. The corresponding plated through hole 215a of the first substrate 201a is aligned with the plated through hole 215b. The hole forming wall of each plated through hole 215b is electroplated with the corresponding circuit trace on the second surface 214a of the first substrate 201a and electrically connected with the corresponding circuit trace on the second surface 214b of the second substrate 201b. conductive material. The second substrate 201b is further formed with a through hole 211b, so that a chip unit accommodating space is formed between the wall of the through hole 211b and the first substrate 201a.

The first chip unit 202a is placed in the chip unit accommodating space and has a bonding pad mounting surface 220a provided with a plurality of bonding pads 221a and a bottom surface 222a opposite to the bonding pad mounting surface 220a. A first adhesive layer t1 has a first adhesive surface t1a and a second adhesive surface t1b. The bonding pad mounting surface 220a of the first chip unit 202a is bonded to the first bonding surface t1a of the first adhesive layer t1. The second adhesive surface t1b of the first adhesive layer t1 is bonded to the second surface 214a of the first substrate 1a, so that the first chip unit 202a can be disposed on the second surface 214a of the first substrate 201a . The electrical connection between the bonding pads 221a of the first chip unit 202a and the corresponding circuit traces on the second surface 214b of the second substrate 201b is realized by the first wire w1.

The third substrate 201c may be a circuit board or a metal plate coated with an insulating material. The third substrate 201c has a first surface 210c bonded to the second surface 214b of the second substrate 201b and a second surface 214c on which predetermined circuit traces are arranged as shown in FIG. The corresponding plated through hole 215b of the second substrate 201b is aligned with the plated through hole 215c. The hole wall of each plated through hole 215c is plated with a conductive material electrically connected to the corresponding circuit track on the second surface 214b of the second substrate 201b and to the corresponding circuit track on the second surface 214c of the third substrate 201c . The third substrate 201c is further formed with a through hole 211c such that a chip unit accommodating space is formed between the wall of the through hole 211c and the second substrate 201b. In this embodiment, the through hole 211c of the third substrate 201c is coaxial with the through hole 211b of the second substrate 201b and is larger than the through hole 211b of the second substrate 210b.

The second chip unit 203a is placed in the chip unit accommodating space formed between the second substrate 201b and the wall of the through hole 211c of the third substrate 201c, and has a plurality of bonding pads 231a An adhesive pad mounting surface 230a and a bottom surface 232a opposite to the adhesive pad mounting surface 230a. A second adhesive layer t2 has a first adhesive surface t2a and a second adhesive surface t2b. The bottom surface 232a of the second chip unit 203a is bonded to the first bonding surface t2a of the second adhesive layer t2. The second bonding surface t2b of the second adhesive layer t2 is bonded to the bonding pad mounting surface 220a of the first chip unit 202a under the bonding pad 221a not covering the first chip unit 202a, so that The second chip unit 203a is disposed on the bonding pad mounting surface 220a of the first chip unit 202a. The electrical connection between the bonding pads 231a of the second chip unit 203a and the corresponding circuit traces on the second surface 214c of the third substrate 201c is realized by the second wire w2.

The fourth substrate 201d may be a circuit board, which has a first surface 210d bonded to the second surface 214c of the third substrate 201c and a second surface 214d with predetermined circuit traces as shown in FIG. 22 , Furthermore, a plurality of plated through holes 215d aligned with the corresponding plated through holes 215c of the third substrate 201c are formed. The hole wall of each plated through hole 215d is plated with a conductive material electrically connected to the corresponding circuit track on the second surface 214c of the third substrate 201c and to the corresponding circuit track on the second surface 214d of the fourth substrate 201d . The fourth substrate 201d is further formed with a through hole 211d such that a chip unit accommodating space is formed between the wall of the through hole 211d and the third substrate 201c. In this embodiment, the through hole 211d of the fourth substrate 201d is coaxial with the through hole 211c of the third substrate 201c and is larger than the through hole 211c of the third substrate 201c.

The third chip unit 207a is placed in the chip unit accommodating space formed between the third substrate 210c and the wall of the through hole 211d of the fourth substrate 201d, and has a plurality of bonding pads 271a. An adhesive pad mounting surface 270a and a bottom surface 272a opposite to the adhesive pad mounting surface 270a. The third chip unit 207a is mounted on the bonding pad mounting surface 230a of the second chip unit 203a through a third adhesive layer t3. The third adhesive layer t3 has a first adhesive surface t3a and a second adhesive surface t3b. The first bonding surface t3a of the third adhesive layer t3 is bonded to the bottom surface 272a of the third chip unit 207a, and the second bonding surface t3b of the third adhesive layer t3 does not cover the second chip unit. 203a under the bonding pad 231a is bonded to the bonding pad mounting surface 230a of the second chip unit 203a, so that the third chip unit 207a can be placed on the bonding pad mounting surface 230a of the second chip unit 203a . The electrical connection between the bonding pad 271a of the third chip unit 207a and the corresponding circuit trace on the second surface 214d of the fourth substrate 201d is realized by the third wire w3.

The fourth chip unit 209 has a bonding pad mounting surface 290 provided with a plurality of bonding pads 291 . The fourth chip unit 209 is mounted on the second surface 214d of the fourth substrate 201d through a fourth adhesive layer 206d. The fourth adhesive layer 206d has a first bonding surface 260d and a second bonding surface 261d, and is formed with a through hole 263d corresponding to the through hole 211d of the fourth substrate 201d and a plurality of holes 263d corresponding to the fourth chip unit. The adhesive pad 291 of 209 corresponds to the window 262d. The first bonding surface 260d of the fourth adhesive layer 206d is bonded to the bonding pad mounting surface 290 of the fourth chip unit 209, so that the hole forming wall of each window hole 262d and the fourth chip unit 209 are bonded. A conductor accommodating space for accommodating the conductor 205 is formed between them. The conductor 205 is electrically connected to the corresponding bonding pad 291 of the fourth chip unit 209 . The second bonding surface 261d of the fourth bonding pad 206d is bonded to the second surface 214d of the fourth substrate 201d, so that the fourth chip unit 209 can be disposed on the second surface 214d of the fourth substrate 201d. . The conductor 205 is also electrically connected to the corresponding circuit trace on the second surface 214d of the fourth substrate 201d.

A metal heat sink 293 is disposed on the bottom surface 292 of the fourth chip unit 209 opposite to the bonding pad mounting surface 290 . In addition, an encapsulation layer 294 is formed between the periphery of the fourth chip unit 209 and the second surface 214d of the fourth substrate 201d. In this embodiment, the encapsulation layer 294 is made of metal material.

34, the ninth preferred embodiment of the present invention is shown to include a first substrate 201a, a second substrate 201b, two first chip units 202a, a third substrate 201c, two second chip units 203a, a fourth The substrate 201d and a third chip unit 207a.

The first substrate 201a may be a circuit board or a metal plate whose surface is coated with insulating material. The first substrate 201a has a first surface 210a with a plurality of solder balls 213a and a second surface 214a with predetermined circuit traces as shown in FIG. The through hole 215a. The hole forming wall of each plated through hole 215 a is plated with conductive material electrically connected to the corresponding solder ball 213 a and the corresponding circuit trace on the second surface 214 .

The second substrate 201b may be a circuit board or a metal plate coated with an insulating material. The second substrate 201b has a first surface 210b bonded to the second surface 214a of the first substrate 201a and a second surface 214b on which predetermined circuit traces are arranged as shown in FIG. The corresponding plated through hole 215a of the first substrate 201a is aligned with the plated through hole 215b. The hole forming wall of each plated through hole 215b is electroplated with the corresponding circuit trace on the second surface 214a of the first substrate 201a and electrically connected with the corresponding circuit trace on the second surface 214b of the second substrate 201b. conductive material. The second substrate 201b is further formed with two through holes 211b, so that a chip unit accommodating space is formed between the walls of each through hole 211b and the first substrate 201a.

Each of the first chip units 202a is placed in the corresponding chip unit accommodating space, and has a bonding pad mounting surface 220a provided with a plurality of bonding pads 221a. Each first chip unit 202a is disposed on the first substrate 201a through a first adhesive layer 206a. The first adhesive layer 206a has a first adhesive surface 260a and a second adhesive surface 261a, and is formed with a plurality of windows 262a corresponding to the adhesive pads 221a of the first chip unit 202a. The bonding pad mounting surface 220a of the first chip unit 202a is bonded to the first bonding surface 260a of the first adhesive layer 206a, so that the hole forming wall of each window hole 262a is formed between the first chip unit 202a. A conductor accommodating space for accommodating the first conductor 205a is formed between them. The first conductor 205a is electrically connected to the corresponding bonding pad 221a of the first chip unit 202a. The second adhesive surface 261a of the first adhesive layer 206a is bonded to the second surface 214a of the first substrate 201a, so that the first chip unit 202a can be disposed on the second surface 214a of the first substrate 201a . The first conductor 205a is also electrically connected to the corresponding circuit trace on the second surface 214a of the first substrate 201a.

A metal heat dissipation plate 223a is disposed on the bottom surface 222a of each first chip unit 202a opposite to the bonding pad mounting surface 220a. In addition, an encapsulation layer 224a is formed between the periphery of each first chip unit 202a and the hole wall of the corresponding through hole 211b of the second substrate 201b.

The third substrate 201c may be a circuit board or a metal plate coated with an insulating material. The third substrate 201c has a first surface 210c bonded to the second surface 214b of the second substrate 201b and a second surface 214c on which predetermined circuit traces are arranged as shown in FIG. The corresponding plated through hole 215b of the second substrate 201b is aligned with the plated through hole 215c. The hole wall of each plated through hole 215c is plated with a conductive material electrically connected to the corresponding circuit track on the second surface 214b of the second substrate 201b and to the corresponding circuit track on the second surface 214c of the third substrate 201c . The third substrate 201c is further formed with a through hole 211c, so that a chip unit accommodating space is formed between the wall of the through hole 211c and the second substrate 201b.

The second chip units 203a are placed in the chip unit accommodating space formed between the second substrate 201b and the hole wall of the through hole 211c of the third substrate 201c and each has a plurality of bonding pads 231a. The adhesive pad mounting surface 230a. Each second chip unit 203a is disposed on the second substrate 201b through a second adhesive layer 206b. The second adhesive layer 206b has a first bonding surface 260b and a second bonding surface 261b, and forms a through hole 263b corresponding to the through hole 211b of the second substrate 201b and a plurality of holes 263b corresponding to the second chip unit. The window 262b corresponds to the adhesive pad 231a of 203a. The bonding pad mounting surface 230a of the second chip unit 203a is bonded to the first bonding surface 260b of the second adhesive layer 206b so that between the hole forming wall of each window hole 262b and the second chip unit 203a A conductor accommodating space for accommodating the second conductor 205b is formed. The second conductor 205b is electrically connected to the corresponding bonding pad 231a of the second chip unit 203a. The second bonding surface 261b of the second adhesive layer 206b is bonded to the second surface 214b of the second substrate 201b, so that the second chip unit 203a can be disposed on the second surface 214b of the second substrate 201b . The second conductor 205b is also electrically connected to the corresponding circuit trace on the second surface 214b of the second substrate 201b.

A metal heat dissipation plate 233a is disposed on the bottom surface 232a of each second chip unit 203a opposite to the bonding pad mounting surface 230a. It should be noted that the area of the bonding pad mounting surface 230a where the bonding pad 231a is not provided in each second chip unit 203a is bonded to the metal heat dissipation plate 223a of the corresponding first chip unit 202a. In addition, an encapsulation layer 234a is formed between the periphery of each second chip unit 203a and the second surface 214b of the second substrate 201b.

The fourth substrate 201d may be a circuit board or a metal plate coated with an insulating material. The fourth substrate 201d has a first surface 210d bonded to the second surface 2214c of the third substrate 201c and a second surface 214d on which predetermined circuit traces such as those shown in FIG. 22 are arranged, and a plurality of The plated through holes 215d are aligned with the corresponding plated through holes 215c of the third substrate 201c. The hole wall of each plated through hole 215d is plated with a conductive material electrically connected to the corresponding circuit track on the second surface 214c of the third substrate 201c and to the corresponding circuit track on the second surface 214d of the fourth substrate 201d . The fourth substrate 201d is further formed with a through hole 211d, so that a chip unit accommodating space is formed between the wall of the through hole 211d and the third substrate 201c. In this embodiment, the through hole 211d of the fourth substrate 201d is coaxial with the through hole 211c of the third substrate 201c and is larger than the through hole 211c of the third substrate 201c.

The third chip unit 207a is placed in the chip unit accommodating space formed between the third substrate 201c and the hole wall of the through hole 211d of the fourth substrate 201d and has a plurality of bonding pads 271a disposed thereon. Adhesive pad mounting surface 270a. The third chip unit 270a is mounted on the second surface 214c of the third substrate 201c through a third adhesive layer 206c. The third adhesive layer 206c has a first bonding surface 260c and a second bonding surface 261c, and is formed with a through hole 263c corresponding to the through hole 211c of the third substrate 201c and a plurality of holes 263c corresponding to the third chip unit. The window 262c corresponds to the adhesive pad 271a of 207a. The first bonding surface 260c of the third adhesive layer 206c is bonded to the bonding pad mounting surface 270a of the third chip unit 207a so that between the hole forming wall of each window hole 262c and the third chip unit 207a A conductor accommodating space for accommodating the third conductor 205c is formed. The third conductor 205c is electrically connected to the corresponding bonding pad 271a of the third chip unit 207a. The second bonding surface 261c of the third bonding pad 206c is bonded to the second surface 214c of the third substrate 201c, so that the third chip unit 207a can be disposed on the second surface 214c of the third substrate 201c . The third conductor 205c is also electrically connected to the corresponding circuit trace on the second surface 214c of the third substrate 201c.

A metal heat sink 273a is disposed on the bottom surface 272a of the third chip unit 207a opposite to the bonding pad mounting surface 270a. The area of the bonding pad mounting surface 270a where the bonding pad 271a is not provided in the fourth chip unit 207a is attached to the metal heat sink 233a of the second chip units 203a. In addition, an encapsulation layer 274a is formed between the periphery of the third chip unit 207a and the wall of the through hole 211d of the fourth substrate 201d.

Please refer to FIG. 35 , which is the tenth preferred embodiment of the present invention. Different from the third preferred embodiment, the solder balls 213 are mounted on the second surface 214 of the substrate 201 .

Please refer to Fig. 36, which shows an eleventh preferred embodiment of the present invention. Different from the fourth preferred embodiment, the solder balls 213 are installed on the second surface 214 of the substrate 201 and are electrically connected to the conductive material of the hole walls of the corresponding through holes 215 .

Please refer to Fig. 37, which shows the twelfth preferred embodiment of the present invention. Different from the fifth preferred embodiment, the solder balls 213a are disposed on the second surface 214c of the third substrate 201c, and are electrically connected to the conductive material of the hole walls of the corresponding through holes 215c.

Please refer to Fig. 38, which shows the thirteenth preferred embodiment of the present invention. Different from the sixth preferred embodiment, the solder balls 213a are disposed on the second surface 214d of the fourth substrate 201d and are electrically connected to the conductive material of the hole walls of the corresponding through holes 215d.

Please refer to Fig. 39, which shows the fourteenth preferred embodiment of the present invention. Different from the seventh preferred embodiment, the solder balls 213a are disposed on the second surface 214f of the sixth substrate 201f and are electrically connected to the conductive material of the hole walls of the corresponding through holes 215f.

Please refer to Fig. 40, which shows the fifteenth preferred embodiment of the present invention. Different from the eighth preferred embodiment, the solder balls 213a are disposed on the second surface 214d of the fourth substrate 201d, and are electrically connected to the conductive material of the hole walls of the corresponding through holes 215d.

Please refer to Fig. 41, which shows the sixteenth preferred embodiment of the present invention. Different from the ninth preferred embodiment, the solder balls 213a are disposed on the second surface 214d of the fourth substrate 201d and are electrically connected to the conductive material of the hole walls of the corresponding through holes 215d.

Although the present invention has been disclosed above in conjunction with a preferred embodiment, it is not intended to limit the present invention. Those skilled in the art can make changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention It should be defined by the appended claims.

Claims (66)

1. A packaging method for a multi-chip module device, comprising the steps of: A first substrate is provided, the first substrate has a first surface and a second surface opposite to the first surface, the first substrate is formed with a plurality of plated through holes on the second surface of the first substrate Predetermined circuit traces are arranged, and a layer of conductive material electrically connected to the corresponding circuit traces is electroplated on the wall of each plated through hole, and a plurality of test bumps are also arranged on the second surface of the first substrate, these The test bumps are electrically connected to the corresponding circuit traces; A second substrate having a smaller size than the first substrate is provided, the second substrate is placed on the first substrate without the test bumps covering the first substrate, the second substrate has a The second surface of the substrate is bonded to the first surface and a second surface opposite to the first surface, on the second surface of the second substrate, predetermined circuit traces are arranged and a plurality of test bumps are arranged, the The second substrate is also formed with a plurality of plated through holes aligned with corresponding plated through holes of the first substrate and a through hole such that a hole forming wall of the through hole of the second substrate is formed between the first substrate and the first substrate. A first chip unit accommodation space, a layer of conductive material corresponding to the circuit traces of the second substrate and the corresponding plating through holes of the first substrate is electroplated on the hole wall of each plated through hole of the second substrate Conductive material for electrical connections; A first chip unit is placed in the first chip unit accommodating space by using a first adhesive layer, the first chip unit has a bonding pad mounting surface provided with a plurality of bonding pads, the first chip unit The adhesive layer has a first adhesive surface adhered to the second surface of the first substrate and a second adhesive surface adhered to the adhesive pad mounting surface of the first chip unit, the first adhesive A layer corresponding to the bonding pad of the first chip unit is formed with a plurality of window holes exposing the corresponding bonding pads of the first chip unit, and the hole forming walls of each window hole are connected with the first chip unit and the first chip unit. A conductor accommodating space is formed between the substrates for accommodating conductors for realizing the electrical connection between the bonding pad of the first chip unit and the corresponding circuit trace of the first substrate; testing the first chip unit through the test bumps on the first substrate; providing a third substrate smaller in size than the second substrate, the third substrate is placed on the second substrate without covering the test bumps of the second substrate, the third substrate has a The second surface of the substrate is bonded to the first surface and a second surface opposite to the first surface, predetermined circuit traces are arranged on the second surface of the third substrate and a plurality of test bumps are arranged, the The third substrate is also formed with a plurality of plated through holes aligned with corresponding plated through holes of the second substrate and a through hole concentric with and larger than the through hole of the second substrate, such that A second chip unit accommodating space is formed between the hole forming wall of the through hole of the third substrate and the second substrate, and a layer and the third chip are electroplated on the hole wall of each plated through hole of the third substrate. the conductive material electrically connecting the corresponding circuit trace of the substrate and the conductive material of the corresponding plated through hole of the second substrate; Use a second adhesive layer to place a second chip unit in the second chip unit accommodating space, the second chip unit has an adhesive pad mounting surface provided with a plurality of adhesive pads, the second adhesive The glue layer has a first bonding surface bonded to the second surface of the second substrate and a second bonding surface bonded to the bonding pad mounting surface of the second chip unit, the second glue layer A plurality of window holes exposing the corresponding bonding pads of the second chip unit are formed corresponding to the bonding pads of the second chip unit, and the hole forming walls of each window hole of the second adhesive layer are in contact with the second A conductor accommodating space for accommodating conductors for realizing the electrical connection between the bonding pad of the second chip unit and the corresponding circuit track of the second substrate is formed between the chip unit and the second substrate; testing the second chip unit through test bumps on the second substrate; and Trim the edges of all substrates to size. 2. The packaging method of a multi-chip module device according to claim 1, further comprising disposing a plurality of tins corresponding to the plated through holes on one of the first surface of the first substrate and the second surface of the third substrate Ball step, these solder balls are electrically connected with the conductive material of the corresponding plated through holes. 3. The method for packaging a multi-chip module device according to claim 1, before the step of aligning the edges of all substrates, further comprising the following steps: providing a fourth substrate smaller in size than the third substrate, the fourth substrate is placed on the third substrate without covering the test bumps of the third substrate, the fourth substrate has a The second surface of the substrate is bonded to the first surface and a second surface opposite to the first surface, predetermined circuit traces are arranged on the second surface of the fourth substrate and a plurality of test bumps are arranged, the The fourth substrate is also formed with a plurality of plated through holes aligned with corresponding plated through holes of the third substrate and a through hole concentric with and larger than the through hole of the third substrate, so that A third chip unit accommodating space is formed between the hole forming wall of the through hole of the fourth substrate and the third substrate. The conductive material electrically connected to the corresponding circuit trace of the substrate and the conductive material of the corresponding plated through hole of the third substrate; A third chip unit is placed in the third chip unit accommodating space by using a third adhesive layer, the third chip unit has an adhesive mounting surface provided with a plurality of adhesive pads, the third adhesive The glue layer has a first bonding surface bonded to the second surface of the third substrate and a second bonding surface bonded to the bonding pad mounting surface of the third chip unit, the third bonding glue A layer corresponding to the bonding pad of the third chip unit is formed with a plurality of window holes exposing the corresponding bonding pads of the third chip unit, and the hole forming walls of each window hole of the third adhesive layer are in contact with the first bonding pad. A conductor accommodating space for accommodating a conductor for realizing the electrical connection between the bonding pad of the third chip unit and the corresponding circuit trace of the third substrate is formed between the three-chip unit and the third substrate ; testing the third chip unit through the test bump on the third substrate; providing a fifth substrate smaller in size than the fourth substrate, the fifth substrate is placed on the fourth substrate without covering the test bumps of the fourth substrate, the fifth substrate has a The second surface of the substrate is bonded to a first surface and a second surface opposite to the first surface, predetermined circuit traces are arranged on the second surface of the fifth substrate, and a plurality of test bumps are arranged, The fifth substrate is also formed with a plurality of plated through holes aligned with corresponding plated through holes of the fourth substrate and a through hole concentric with the through hole of the fourth substrate and larger than the through hole of the fourth substrate, So that a fourth chip unit accommodating space is formed between the hole forming wall of the through hole and the fourth substrate, and a layer corresponding to the fifth substrate is electroplated on the hole wall of each plated through hole of the fifth substrate. The conductive material electrically connected to the conductive material of the circuit trace and the corresponding plated through hole of the fourth substrate; A fourth chip unit is placed in the fourth chip unit accommodating space by using a fourth adhesive layer, the fourth chip unit has a bonding pad mounting surface provided with a plurality of bonding pads, the fourth The adhesive layer has a second adhesive surface bonded to the second surface of the fourth substrate and a second adhesive surface bonded to the bonding pad mounting surface of the fourth chip unit, the fourth adhesive A layer corresponding to the bonding pad of the fourth chip unit is formed with a plurality of window holes exposing the corresponding bonding pads of the fourth chip unit, and the hole forming walls of each window hole of the fourth adhesive layer are in contact with the first bonding pad. A conductor accommodating space is formed between the four-chip unit and the fourth substrate for accommodating conductors for electrically connecting the bonding pads of the fourth chip unit with the corresponding circuit traces of the fourth substrate ; testing the fourth chip unit through the test bumps on the fourth substrate; A fifth chip unit is mounted on the fifth substrate by using a fifth adhesive layer, the fifth chip unit has an adhesive pad mounting surface provided with a plurality of adhesive pads, the fifth adhesive layer has a A first bonding surface bonded to the second surface of the fifth substrate and a second bonding surface bonded to the bonding pad mounting surface of the fifth chip unit, the fifth bonding adhesive layer corresponds to the The bonding pads of the fifth chip unit are formed with a plurality of windows exposing the corresponding bonding pads of the fifth chip unit, and the hole forming walls of each window hole of the fifth adhesive layer are in contact with the fifth chip unit and the fifth chip unit. A conductor accommodating space for accommodating conductors for realizing the electrical connection between the bonding pad of the fifth chip unit and the corresponding circuit trace of the fifth substrate is formed between the fifth substrates; and The fifth chip unit is tested through the test bumps on the fifth substrate. 4. The method for packaging a multi-chip module device according to claim 3, wherein in the step of aligning the edges of all substrates, further comprising forming a A step of encapsulation layer. 5. The packaging method of a multi-chip module device as claimed in claim 4, wherein the encapsulation layer is formed of a metal material. 6. The method for packaging a multi-chip module device as claimed in claim 4, wherein the encapsulation layer is formed of epoxy resin. 7. The packaging method of a multi-chip module device according to claim 3, further comprising disposing a plurality of tins corresponding to the plated through holes on one of the first surface of the first substrate and the second surface of the fifth substrate Ball step, these solder balls are electrically connected with the conductive material of the corresponding plated through holes. 8. The packaging method of a multi-chip module device according to claim 1, wherein, in the step of placing the first chip unit and the first chip unit accommodating space, further comprising installing a metal heat dissipation plate on the on the bottom surface of the first chip unit opposite to the bonding pad mounting surface, and wherein, in the step of placing the second chip unit in the second chip unit accommodating space, the second adhesive A through hole is formed in the layer corresponding to the through hole of the second substrate, so that the bonding pad mounting surface of the second chip unit not provided with the bonding pad is attached to the metal heat dissipation plate of the first chip unit. 9. The packaging method of a multi-chip module device according to claim 3, wherein, in the step of placing the first chip unit in the first chip unit accommodating space, further comprising installing a metal heat sink on the on the bottom surface of the first chip unit opposite to the adhesive pad mounting surface, and wherein, in the step of placing the second chip unit in the second chip unit accommodating space, the second adhesive The adhesive layer forms a through hole corresponding to the through hole of the second substrate, so that the bonding pad mounting surface of the second chip unit without the bonding pad is attached to the metal heat dissipation plate of the first chip unit. 10. The packaging method of a multi-chip module device according to claim 3, wherein, in the step of placing the second chip unit in the second chip unit accommodating space, further comprising installing a metal heat sink on the on the bottom surface of the second chip unit opposite to the adhesive pad mounting surface, and wherein, in the step of placing the third chip unit in the third chip unit accommodating space, the third adhesive The adhesive layer forms a through hole corresponding to the through hole of the third substrate, so that the bonding pad mounting surface of the third chip unit without the bonding pad is attached to the metal heat dissipation plate of the second chip unit. 11. The packaging method of a multi-chip module device according to claim 3, wherein, in the step of placing the third chip unit in the third chip unit accommodating space, further comprising installing a metal heat sink on the on the bottom surface of the third chip unit opposite to the adhesive pad mounting surface, and wherein, in the step of placing the fourth chip unit in the fourth chip unit accommodating space, the fourth adhesive The adhesive layer forms a through hole corresponding to the through hole of the fourth substrate, so that the bonding pad mounting surface of the fourth chip unit without the bonding pad is attached to the metal heat dissipation plate of the third chip unit. 12. The packaging method of a multi-chip module device according to claim 3, wherein, in the step of placing the fourth chip unit in the fourth chip unit accommodating space, further comprising installing a metal heat sink on the on the bottom surface of the fourth chip unit opposite to the bonding pad mounting surface, and wherein, in the step of mounting the fifth chip unit on the second surface of the fifth substrate, the fifth adhesive A through hole is formed in a layer corresponding to the through hole of the fifth substrate, so that the bonding pad mounting surface of the fifth chip unit not provided with the bonding pad is attached to the metal heat dissipation plate of the fourth chip unit. 13. The packaging method of a multi-chip module device according to claim 3, wherein, in the step of mounting the fifth chip unit on the second surface of the fifth substrate, further comprising mounting a metal heat dissipation plate on the A step on the bottom surface of the fifth chip unit opposite to the bonding pad mounting surface. 14. The packaging method of a multi-chip module device according to claim 3, wherein, before the step of mounting the fifth chip unit on the second surface of the fifth substrate, the following steps are further included: providing a sixth substrate smaller in size than the fifth substrate, the sixth substrate is placed on the fifth substrate without the test bumps covering the fifth substrate, the sixth substrate has a A first surface bonded to the second surface of the second surface and a second surface opposite to the first surface, predetermined circuit traces are laid on the second surface of the sixth substrate, and a plurality of The corresponding plated through hole of the fifth substrate is aligned with the plated through hole and a through hole concentric with the fifth substrate and the through hole and larger than the through hole of the fifth substrate, so that the hole forming wall of the through hole is in contact with the through hole. A fifth chip unit accommodating space for accommodating the fifth chip unit is formed between the fifth substrates, and a layer corresponding to the sixth substrate is electroplated on the wall of each plated through hole of the sixth substrate. The conductive material electrically connects the circuit trace of the fifth substrate with the conductive material of the corresponding plated through hole. 15. The packaging method of a multi-chip module device according to claim 14, wherein, in the step of aligning the edges of all substrates, further comprising forming an encapsulation layer between each chip unit and the corresponding through-hole of the substrate step. 16. The method for packaging a multi-chip module device as claimed in claim 15, wherein the encapsulation layers are formed of epoxy resin. 17. A packaging method for a multi-chip module device, comprising the steps of: A substrate unit is provided, the substrate unit includes first to third substrates, the first substrate has a first surface and a second surface opposite to the first surface, the first substrate is formed with a plurality of plated through holes and Predetermined circuit traces are arranged on the second surface of the first substrate, and a layer of conductive material electrically connected to the corresponding circuit traces is electroplated on the hole wall of each plated through hole, and on the second surface of the first substrate A plurality of test bumps are also provided, and these test bumps are electrically connected to corresponding circuit traces, the size of the second substrate is smaller than that of the first substrate, and the second substrate is under the test bumps that do not cover the first substrate placed on the first substrate, the second substrate has a first surface bonded to the second surface of the first substrate and a second surface opposite to the first surface, on the second substrate Predetermined circuit traces and a plurality of test bumps are arranged on the second surface, and a plurality of plated through holes and a through hole aligned with corresponding plated through holes of the first substrate are formed on the second substrate so that A first chip unit accommodating space is formed between the hole forming wall of the second substrate and the first substrate, and a layer is plated on the hole wall of each plated through hole of the second substrate with the second substrate. The conductive material electrically connected to the corresponding circuit trace and the conductive material of the corresponding plated through hole of the first substrate, the size of the third substrate is smaller than that of the second substrate, and the third substrate does not cover the second substrate The test bumps are placed on the second substrate, the third substrate has a first surface bonded to the second surface of the second substrate and a second surface opposite to the first surface, on the The second surface of the third substrate is provided with predetermined circuit traces and provided with a plurality of test bumps, and the third substrate is also formed with a plurality of electroplating through holes corresponding to the pair of electroplating through holes of the second substrate and a The through hole is coaxial with the through hole of the second substrate and is larger than the through hole of the second substrate, so that a second chip unit is formed between the hole forming wall of the third substrate and the second substrate. Space, on the hole wall of each plated through hole of the third substrate, a layer of conductive material electrically connected to the corresponding circuit trace of the third substrate and the conductive material of the second substrate and the corresponding plated through hole is electroplated; A first chip unit is placed in the first chip unit accommodating space by using a first adhesive layer, the first chip unit has a bonding pad mounting surface provided with a plurality of bonding pads, the first chip unit The adhesive layer has a first adhesive surface adhered to the second surface of the first substrate and a second adhesive surface adhered to the adhesive pad mounting surface of the first chip unit, the first adhesive A layer corresponding to the adhesive pad of the first chip unit is formed with a plurality of window holes exposing the corresponding adhesive pads of the first chip unit, and the hole forming walls of the window holes of the first adhesive layer are in contact with the first adhesive layer. A conductor accommodating space is formed between a chip unit and the first substrate for accommodating conductors for electrically connecting the bonding pads of the first chip unit with the corresponding circuit traces of the first substrate ; testing the first chip unit through the test bumps on the first substrate; A second chip unit is placed in the second chip unit accommodating space by using a second adhesive layer, the second chip unit has an adhesive pad mounting surface provided with a plurality of adhesive pads, the second The adhesive layer has a first bonding surface bonded to the second surface of the second substrate and a second bonding surface bonded to the bonding pad mounting surface of the second chip unit, the second adhesive A layer corresponding to the bonding pad of the second chip unit is formed with a plurality of window holes exposing the corresponding bonding pads of the second chip unit, and the hole forming walls of each window hole of the second adhesive layer are in contact with the first bonding pad. A conductor accommodating space for accommodating conductors for realizing the electrical connection between the bonding pad of the second chip unit and the corresponding circuit trace of the second substrate is formed between the second chip unit and the second substrate ; testing the second chip unit through test bumps on the second substrate; and Trim the edges of all substrates to size. 18. The packaging method of a multi-chip module device according to claim 17, further comprising disposing a plurality of tins corresponding to the plated through holes on one of the first surface of the first substrate and the second surface of the third substrate Ball step, these solder balls are electrically connected with the conductive material of the corresponding plated through holes. 19. The packaging method of a multi-chip module device according to claim 17, wherein, in the step of providing the substrate unit, the substrate unit further includes a fourth substrate and a fifth substrate, and the size of the fourth substrate is smaller than the The third substrate is small, the fourth substrate is placed on the third substrate without covering the test bumps of the third substrate, the fourth substrate has a first substrate bonded to the second surface of the third substrate A surface and a second surface opposite to the first surface, predetermined circuit traces are arranged on the second surface of the fourth substrate and a plurality of test bumps are arranged, and a plurality of test bumps are also formed on the fourth substrate. The plated through hole aligned with the corresponding plated through hole of the third substrate and a through hole concentric with the through hole of the third substrate and larger than the through hole of the third substrate, so that in the through hole of the fourth substrate A third chip unit accommodating space is formed between the hole forming wall and the third substrate, and a layer of circuit traces corresponding to the fourth substrate and the first circuit traces corresponding to the fourth substrate are electroplated on the hole walls of the plated through holes of the fourth substrate. The conductive material of the corresponding plated through holes of the three substrates is electrically connected to the conductive material, the size of the fifth substrate is larger than that of the fourth substrate, and the fifth substrate is placed on the test bump without covering the fourth substrate. On the fourth substrate, the fifth substrate has a first surface bonded to the second surface of the fourth substrate and a second surface opposite to the first surface, and the fifth substrate is arranged on the second surface of the fifth substrate. There are predetermined circuit traces and a plurality of test bumps are provided, and the fifth substrate is also formed with a plurality of plated through holes aligned with the corresponding plated through holes of the fourth substrate and a plated through hole aligned with the through hole of the fourth substrate. A perforation with a center axis and larger than the perforation of the fourth substrate, so that a fourth chip unit accommodating space is formed between the hole forming wall of the perforation and the fourth substrate, and each plated through hole of the fifth substrate A layer of conductive material that is electrically connected to the corresponding circuit track of the fifth substrate and the conductive material of the corresponding plated through hole of the fourth substrate is electroplated on the wall of the hole, and the packaging method cuts the edges of all substrates evenly Before the steps, the following steps are also included: A third chip unit is placed in the third chip unit accommodating space by using a third adhesive layer, the third chip unit has an adhesive pad mounting surface provided with a plurality of adhesive pads, the third The adhesive layer has a first adhesive surface adhered to the second surface of the third substrate and a second adhesive surface adhered to the adhesive pad mounting surface of the third chip unit, the third adhesive A layer corresponding to the bonding pad of the third chip unit is formed with a plurality of window holes exposing the corresponding bonding pads of the third chip unit, and the hole forming walls of each window hole of the third adhesive layer are in contact with the first bonding pad. A conductor accommodating space for accommodating a conductor for realizing the electrical connection between the bonding pad of the third chip unit and the corresponding circuit trace of the third substrate is formed between the three-chip unit and the third substrate ; testing the third chip unit through the test bump on the third substrate; A fourth chip unit is placed in the fourth chip unit accommodating space by using a fourth adhesive layer, the fourth chip unit has a bonding pad mounting surface provided with a plurality of bonding pads, the fourth The adhesive layer has a first adhesive surface adhered to the second surface of the fourth substrate and a second adhesive surface adhered to the bonding pad mounting surface of the fourth chip unit, the fourth adhesive A layer corresponding to the bonding pad of the fourth chip unit is formed with a plurality of window holes exposing the corresponding bonding pads of the fourth chip unit, and the hole forming walls of each window hole of the fourth adhesive layer are in contact with the first bonding pad. A conductor accommodating space is formed between the four-chip unit and the fourth substrate for accommodating conductors for electrically connecting the bonding pads of the fourth chip unit with the corresponding circuit traces of the fourth substrate ; testing the fourth chip unit through the test bumps on the fourth substrate; A fifth chip unit is mounted on the fifth substrate by using a fifth adhesive layer, the fifth chip unit has an adhesive pad mounting surface provided with a plurality of adhesive pads, the fifth adhesive layer has a A first bonding surface bonded to the second surface of the fifth substrate and a second bonding surface bonded to the bonding pad mounting surface of the fifth chip unit, the fifth adhesive layer corresponds to the fifth adhesive layer The bonding pads of the five-chip unit are formed with a plurality of windows exposing the corresponding bonding pads of the fifth chip unit, and the holes of each window hole in the fifth adhesive layer form a wall with the fifth chip unit and the fifth chip unit. A conductor accommodating space for accommodating conductors for realizing the electrical connection between the bonding pads of the fifth chip unit and the corresponding circuit traces of the fifth substrate is formed between the fifth substrates; and The fifth chip unit is tested through the test bumps on the fifth substrate. 20. The packaging method of a multi-chip module device according to claim 19, wherein in the step of aligning the edges of all substrates, further comprising forming a A step of encapsulation layer. twenty one. The packaging method of a multi-chip module device as claimed in claim 20, wherein the encapsulation layer is formed of metal material. twenty two. The method for packaging a multi-chip module device as claimed in claim 20, wherein the encapsulation layer is formed of epoxy resin. twenty three. The packaging method of a multi-chip module device according to claim 19, further comprising disposing a plurality of tins corresponding to the plated through holes on one of the first surface of the first substrate and the second surface of the fifth substrate Ball step, these solder balls are electrically connected with the conductive material of the corresponding plated through holes. twenty four. The packaging method of a multi-chip module device according to claim 17, wherein, in the step of placing the first chip unit in the accommodating space of the first chip unit, further comprising installing a metal heat sink on the on the bottom surface of the first chip unit opposite to the adhesive pad mounting surface, and wherein, in the step of placing the second chip unit in the second chip unit accommodating space, the second adhesive The adhesive layer forms a through hole corresponding to the through hole of the second substrate, so that the bonding pad mounting surface of the second chip unit without the bonding pad is attached to the metal heat dissipation plate of the first chip unit. 25． The packaging method of a multi-chip module device according to claim 19, wherein, in the step of placing the first chip unit in the first chip unit accommodating space, further comprising installing a metal heat sink on the on the bottom surface of the first chip unit opposite to the adhesive pad mounting surface, and wherein, in the step of placing the second chip unit in the second chip unit accommodating space, the second adhesive The adhesive layer forms a through hole corresponding to the through hole of the second substrate, so that the bonding pad mounting surface of the second chip unit without the bonding pad is attached to the metal heat dissipation plate of the first chip unit. 26． The packaging method of a multi-chip module device according to claim 19, wherein, in the step of placing the second chip unit in the second chip unit accommodating space, further comprising installing a metal heat sink on the on the bottom surface of the second chip unit opposite to the adhesive pad mounting surface, and wherein, in the step of placing the third chip unit in the third chip unit accommodating space, the third adhesive The adhesive layer forms a through hole corresponding to the through hole of the third substrate, so that the bonding pad mounting surface of the third chip unit without the bonding pad is attached to the metal heat dissipation plate of the second chip unit. 27． The packaging method of a multi-chip module device according to claim 19, wherein, in the step of placing the third chip unit in the third chip unit accommodating space, further comprising installing a metal heat sink on the on the bottom surface of the third chip unit opposite to the adhesive pad mounting surface, and wherein, in the step of placing the fourth chip unit in the fourth chip unit accommodating space, the fourth adhesive The adhesive layer forms a through hole corresponding to the through hole of the fourth substrate, so that the bonding pad mounting surface of the fourth chip unit without the bonding pad is attached to the metal heat dissipation plate of the third chip unit. 28． The packaging method of a multi-chip module device according to claim 19, wherein, in the step of placing the fourth chip unit in the fourth chip unit accommodating space, further comprising installing a metal heat sink on the on the bottom surface of the fourth chip unit opposite to the bonding pad mounting surface, and wherein, in the step of mounting the fifth chip unit on the second surface of the fifth substrate, the fifth adhesive A through hole is formed in a layer corresponding to the through hole of the fifth substrate, so that the bonding pad mounting surface of the fifth chip unit not provided with the bonding pad is attached to the metal heat dissipation plate of the fourth chip unit. 29． The packaging method of a multi-chip module device according to claim 19, wherein, in the step of mounting the fifth chip unit on the second surface of the fifth substrate, further comprising mounting a metal heat sink on the A step on the bottom surface of the fifth chip unit opposite to the bonding pad mounting surface. 30． The packaging method of a multi-chip module device according to claim 19, wherein, before the step of mounting the fifth chip unit on the second surface of the fifth substrate, the following steps are further included: providing a sixth substrate smaller in size than the fifth substrate, the sixth substrate is placed on the fifth substrate without the test bumps covering the fifth substrate, the sixth substrate has a A first surface bonded to the second surface of the second surface and a second surface opposite to the first surface, predetermined circuit traces are laid on the second surface of the sixth substrate, and a plurality of The corresponding plated through hole of the fifth substrate is aligned with the plated through hole and a through hole concentric with the through hole of the fifth substrate and larger than the through hole of the fifth substrate so that a wall is formed in the hole of the through hole. A fifth chip unit accommodating space for accommodating the fifth chip unit is formed between the fifth substrate, and a layer is electroplated on the hole wall of each plated through hole of the sixth substrate with the sixth substrate. The corresponding circuit trace and the conductive material of the corresponding plated through hole of the fifth substrate are electrically connected to the conductive material. 31． The packaging method of a multi-chip module device according to claim 30, wherein, in the step of aligning the edges of all substrates, it further includes forming an encapsulation layer between each chip unit and the corresponding through-hole of the substrate step. 32． The method for packaging a multi-chip module device as claimed in claim 31, wherein the encapsulation layers are formed of epoxy resin. 33． A multi-chip module device, comprising: A substrate, the substrate has a first surface and a second surface opposite to the first surface, and at least one through hole is formed, and a predetermined circuit is laid on one of the first and second surfaces of the substrate track; A first chip unit, the first chip unit has a bonding pad mounting surface and a plurality of bonding pads mounted on the bonding pad mounting surface; A first adhesive layer, the first adhesive layer has a first adhesive surface and a second adhesive surface, and is formed with through holes corresponding to the through holes of the substrate and at least one for exposing the first chip The window hole of the adhesive pad of the unit, the first adhesive surface of the first adhesive layer is bonded to the adhesive pad mounting surface of the first chip unit, so that the hole wall forming each window hole and the first A conductor accommodating space for accommodating conductors electrically connected to the bonding pads is formed between the chip units, and the second bonding surface of the first adhesive layer is connected to the substrate on which predetermined circuit traces are laid. Surface bonding, so that the first chip unit can be fixed on the substrate, so that the conductor is electrically connected to the corresponding circuit trace on the first surface of the substrate, and the hole forming wall of the substrate is connected to the first surface of the substrate. A chip unit accommodating space is formed between the chip units; at least one second chip unit, the second chip unit is accommodated in the chip unit accommodating space, and has an adhesive pad mounting surface and a plurality of adhesive pads disposed on the adhesive pad mounting surface; and At least one second adhesive layer, the second adhesive layer is formed with at least one window hole for exposing the bonding pad of the second chip unit and has a first bonding surface and a second bonding surface, these The first bonding surface of the second adhesive layer is bonded to the bonding pad mounting surface of the first chip unit so that a gap is formed between the hole wall of the window hole of the second adhesive layer and the first chip unit. a conductor accommodating space for accommodating a conductor electrically connected to the corresponding bonding pad of the first chip unit, the second bonding surface of the second adhesive layer is connected to the bonding pad of the second chip unit The mounting surface is bonded so that the second chip units can be fixed on the first chip unit, so that the conductors are electrically connected to the corresponding bonding pads of the second chip unit. 34． The multi-chip module device according to claim 33, wherein the substrate further comprises a plurality of solder balls disposed on one of the first and second surfaces, and the substrate is formed with a plurality of solder balls corresponding to the solder balls. The plated through holes, the walls of each plated through hole are plated with a conductive material electrically connected to the corresponding circuit trace and the corresponding solder ball on the one of the first and second surfaces of the substrate. 35． The multi-chip module device as claimed in claim 33, wherein the first chip unit further has a bottom surface opposite to the bonding pad mounting surface, and a metal heat dissipation plate is disposed on the bottom surface of the first chip unit. 36． The multi-chip module device as claimed in claim 33, wherein an encapsulation layer is formed between the periphery of the first chip unit and the surface of the substrate on which the circuit traces are laid out. 37． The multi-chip module device as claimed in claim 36, wherein the encapsulation layer is formed of epoxy resin. 38． The multi-chip module device as claimed in claim 36, wherein the encapsulation layer is formed of metal material. 39． The multi-chip module device as claimed in claim 33, wherein the second chip unit further has a bottom surface opposite to the bonding pad mounting surface, and a metal heat dissipation plate is disposed on the bottom surface of the second chip unit. 40． The multi-chip module device as claimed in claim 33, wherein an encapsulation layer is formed between the periphery of the second chip unit and the wall of the through hole of the substrate. 41． The multi-chip module device according to claim 34, wherein the other surface of the first and second surfaces of the substrate is provided with a predetermined circuit electrically connected to the conductive material on the hole wall of the corresponding plated through hole track, the multi-chip module device also includes: a third chip unit having a bonding pad mounting surface provided with a plurality of bonding pads; and A third adhesive layer, the third adhesive layer has a first adhesive surface and a second adhesive surface, and is formed with through holes corresponding to the through holes of the substrate and at least one for exposing the third chip The window hole of the adhesive pad of the unit, the first adhesive surface of the third adhesive layer is bonded to the adhesive pad mounting surface of the third chip unit, so that the hole wall forming each window hole and the third A conductor accommodating space for accommodating conductors electrically connected to the bonding pads is formed between the chip units, the second bonding surface of the third adhesive layer and the first and second surfaces of the substrate The other surface is bonded so that the third chip unit can be fixed on the substrate, so that the conductor is electrically connected to the conductive material on the wall of the corresponding plated through hole of the substrate. 42． The multi-chip module device as claimed in claim 41, wherein the third chip unit further has a bottom surface opposite to the bonding pad mounting surface, and a metal heat dissipation plate is disposed on the bottom surface of the third chip unit. 43． The multi-chip module device as claimed in claim 41, wherein an encapsulation layer is formed between the periphery of the third chip unit and the other one of the first and second surfaces of the substrate. 44． A multi-chip module device, comprising: A first substrate, the first substrate has a first surface and a second surface opposite to the first surface and on which predetermined circuit traces are arranged, and a plurality of electroplating through holes are formed, and the hole wall of each electroplating through hole electroplated with a conductive material electrically connected to corresponding circuit traces on the second surface of the first substrate; A second substrate, the second substrate has a first surface bonded to the second surface of the first substrate and a second surface on which predetermined circuit traces are laid, and a plurality of connections with the first substrate are formed The corresponding plated through hole is aligned with the plated through hole, and the hole wall of each plated through hole of the second substrate is electroplated with the conductive material of the hole wall of the corresponding plated through hole of the first substrate and the hole wall of the second substrate. The corresponding circuit traces on the second surface are electrically connected to the conductive material, and the second substrate is further formed with a through hole, so that a chip unit accommodating space is formed between the hole wall of the through hole and the first substrate; a first chip unit, the first chip unit is placed in the chip unit accommodating space and has an adhesive pad mounting surface provided with a plurality of adhesive pads; A first adhesive layer, the first adhesive layer has a first adhesive surface and a second adhesive surface, and is formed with at least one window for exposing the adhesive pad of the first chip unit, the The bonding pad mounting surface of the first chip unit is bonded to the first bonding surface of the first adhesive layer so that a hole for accommodating the first chip unit is formed between the hole forming wall of the window hole and the first chip unit. Conductor accommodating space for conductors, the first conductor is electrically connected to the corresponding bonding pad of the first chip unit, the second bonding surface of the first adhesive layer is connected to the second surface of the first substrate bonding, so that the first chip unit can be disposed on the second surface of the first substrate, and the first conductor is also electrically connected to a corresponding circuit trace on the second surface of the first substrate; A third substrate, the third substrate has a first surface bonded to the second surface of the second substrate and a second surface on which predetermined circuit traces are laid, and a plurality of connections with the second substrate are formed The plated through holes aligned with the corresponding plated through holes, the hole walls of the plated through holes of the third substrate are electroplated with the conductive material of the hole walls of the corresponding plated through holes of the second substrate and the wall of the third substrate. The corresponding circuit track on the second surface is electrically connected to the conductive material, and the third substrate is also formed with a through hole, so that a chip unit accommodating space is formed between the hole wall of the through hole and the second substrate; A second chip unit, the second chip unit is placed in the chip unit accommodating space formed between the second substrate and the wall of the through hole of the third substrate, and has a plurality of bonding Adhesive pad mounting surface for pads; A second adhesive layer has a first adhesive surface and a second adhesive surface, and is formed with at least one window for exposing the adhesive pad of the second chip unit, the adhesive pad of the second chip unit The pad mounting surface is bonded to the first adhesive surface of the second adhesive layer so that a conductor for accommodating the second conductor is formed between the hole forming wall of the window hole and the second chip unit. The accommodating space, the second conductor is electrically connected to the corresponding bonding pad of the second chip unit, and the second bonding surface of the second adhesive layer is bonded to the second surface of the second substrate, so that disposing the second chip unit on the second surface of the second substrate, and the second conductor is also electrically connected to the corresponding circuit trace on the second surface of the second substrate; at least one third chip unit having an adhesive pad mounting surface provided with a plurality of adhesive pads; and at least one third adhesive layer, the third adhesive layer has a first adhesive surface and a second adhesive surface, and is formed with at least one window for exposing the adhesive pad of the third chip unit, The first adhesive surface of the third adhesive layer is bonded to the adhesive pad mounting surface of the third chip unit, so that a hole for accommodating the third chip unit is formed between the hole forming wall of the window hole and the third chip unit. Conductor accommodating space of three conductors, the third conductor is electrically connected to the corresponding bonding pad of the third chip unit, the second bonding surface of the third bonding pad is connected to the first bonding surface of the third substrate The two surfaces are bonded, so that the third chip unit can be disposed on the second surface of the third substrate, and the third conductor is also electrically connected to the corresponding circuit track on the second surface of the third substrate. 45． The multi-chip module device as claimed in claim 44, further comprising a plurality of solder balls disposed on one of the first surface of the first substrate and the second surface of the third substrate, and the solder balls are connected to the second surface of the third substrate. A substrate is electrically connected to the conductive material of the hole wall of the corresponding plated through hole of one of the third substrates. 46． The multi-chip module device as claimed in claim 44, wherein the first chip unit further has a bottom surface opposite to the bonding pad mounting surface, and a metal heat dissipation plate is disposed on the bottom surface of the first chip unit. 47． The multi-chip module device as claimed in claim 44, wherein an encapsulation layer is formed between the periphery of the first chip unit and the wall of the through hole of the second substrate. 48． The multi-chip module device as claimed in claim 44, wherein the second chip unit further has a bottom surface opposite to the bonding pad mounting surface, and a metal heat dissipation plate is disposed on the bottom surface of the second chip unit. 49． The multi-chip module device as claimed in claim 48, wherein the area of the mounting surface of the bonding pad where no bonding pad is provided on the third chip unit is bonded to the metal heat sink of the second chip unit. 50． The multi-chip module device as claimed in claim 44, wherein an encapsulation layer is formed between the periphery of the second chip unit and the wall of the through hole of the substrate. 51． A multi-chip module device, comprising: A first substrate, the first substrate has a first surface and a second surface opposite to the first surface and on which predetermined circuit traces are arranged, and a plurality of electroplating through holes are formed, and the holes of each electroplating through hole are formed the walls are plated with a conductive material electrically connected to corresponding circuit traces on the second surface of the first substrate; A second substrate, the second substrate has a first surface bonded to the second surface of the first substrate and a second surface on which predetermined circuit traces are laid, and a plurality of connections with the first substrate are formed The corresponding plated through hole is aligned with the plated through hole, and the hole formation wall of each plated through hole of the second substrate is electroplated with the conductive material of the hole wall of the corresponding plated through hole of the first substrate and the second substrate. a conductive material electrically connected to the corresponding circuit traces on the second surface of the substrate, and the second substrate is also formed with a through hole, so that a chip unit accommodating space is formed between the hole wall of the through hole and the first substrate; a first chip unit, the first chip unit is placed in the chip unit accommodating space, and has a bonding pad mounting surface provided with a plurality of bonding pads; A first adhesive layer, the first adhesive layer has a first adhesive surface and a second adhesive surface, and is formed with at least one window for exposing the adhesive pad of the first chip unit, the The bonding pad mounting surface of the first chip unit is bonded to the first bonding surface of the first adhesive layer, so that a hole for accommodating the first chip unit is formed between the hole forming wall of the window hole and the first chip unit. a conductor accommodating space for a conductor, the first conductor is electrically connected to the corresponding bonding pad of the first chip unit, the second bonding surface of the first adhesive layer is connected to the second bonding pad of the first substrate Surface bonding, so that the first chip unit can be arranged on the second surface of the first substrate, and the first conductor is also electrically connected to the corresponding circuit trace on the second surface of the first substrate; A third substrate, the third substrate has a first surface bonded to the second surface of the second substrate and a second surface on which predetermined circuit traces are laid, and a plurality of connections with the second substrate are formed The plated through holes aligned with the corresponding plated through holes, the hole walls of the plated through holes of the third substrate are electroplated with the conductive material of the hole walls of the corresponding plated through holes of the second substrate and the wall of the third substrate. The corresponding circuit track on the second surface is electrically connected to the conductive material, and the third substrate is also formed with a through hole, so that a chip unit accommodating space is formed between the hole wall of the through hole and the second substrate, and the third substrate The through hole of the substrate is concentric with the through hole of the second substrate and is larger than the through hole of the second substrate; A second chip unit, the second chip unit is placed in the chip unit accommodating space formed between the second substrate and the wall of the through hole of the third substrate, and has a plurality of bonding Adhesive pad mounting surface for pads; A second adhesive layer, the second adhesive layer has a first adhesive surface and a second adhesive surface, and is formed with a through hole corresponding to the through hole of the second substrate and at least one for exposing the first The window hole of the bonding pad of the second chip unit, the bonding pad mounting surface of the second chip unit is bonded to the first bonding surface of the second adhesive layer, so that the hole forming wall of the window hole is in contact with the first bonding surface of the second adhesive layer. A conductor accommodating space for accommodating a second conductor is formed between the two chip units, the second conductor is electrically connected to the corresponding bonding pad of the second chip unit, and the second adhesive layer of the second adhesive layer Two bonding surfaces are bonded to the second surface of the second substrate, so that the second chip unit can be arranged on the second surface of the second substrate, and the second conductor is also bonded to the second surface of the second substrate. Corresponding circuit traces on the surface are electrically connected; A fourth substrate, the fourth substrate has a first surface bonded to the second surface of the third substrate and a second surface on which predetermined circuit traces are laid, and a plurality of connections with the third substrate are formed The plated through holes aligned with the corresponding plated through holes, the hole wall of each plated through hole of the fourth substrate is electroplated with the conductive material of the hole wall of the corresponding plated through hole of the third substrate and the wall of the fourth substrate The corresponding circuit track on the second surface is electrically connected to the conductive material, and the fourth substrate is also formed with a through hole, so that a chip unit accommodating space is formed between the hole wall of the through hole and the third substrate, the fourth substrate The through hole of the substrate is concentric with the through hole of the third substrate and is larger than the through hole of the third substrate; A third chip unit, the third chip unit is placed in the chip unit accommodating space formed between the wall of the through hole of the third substrate and the fourth substrate, and has a plurality of bonding Adhesive pad mounting surface for pads; A third adhesive layer, the third adhesive layer has a first adhesive surface and a second adhesive surface, and is formed with a through hole corresponding to the through hole of the third substrate and at least one for exposing the first adhesive layer. The window hole of the bonding pad of the three-chip unit, the first bonding surface of the third adhesive layer is bonded to the mounting surface of the bonding pad of the third chip unit, so that the hole forming wall of the window hole is in contact with the first bonding surface of the third chip unit. A conductor accommodating space for accommodating a third conductor is formed between the three chip units, the third conductor is electrically connected to the corresponding bonding pad of the third chip unit, and the first part of the third adhesive layer Two bonding surfaces are bonded to the second surface of the third substrate, so that the third chip unit can be arranged on the second surface of the third substrate, and the third conductor is also bonded to the second surface of the third substrate. Corresponding circuit traces on the surface are electrically connected; a fourth chip unit having a bonding pad mounting surface provided with a plurality of bonding pads; and A fourth adhesive layer, the fourth adhesive layer has a first adhesive surface and a second adhesive surface, and is formed with a through hole corresponding to the through hole of the fourth substrate and at least one for exposing the first The window hole of the bonding pad of the four-chip unit, the first bonding surface of the fourth adhesive layer is bonded to the bonding pad mounting surface of the fourth chip unit, so that the hole forming wall of the window hole is connected to the first bonding surface of the fourth chip unit. A conductor accommodating space for accommodating a fourth conductor is formed between the four chip units, the fourth conductor is electrically connected to the corresponding bonding pad of the fourth chip unit, and the fourth adhesive layer of the fourth adhesive layer Two bonding surfaces are bonded to the second surface of the fourth substrate, so that the fourth chip unit can be arranged on the second surface of the fourth substrate, and the fourth conductor is also bonded to the second surface of the fourth substrate. Corresponding circuit traces on the surface are electrically connected. 52． The multi-chip module device according to claim 51, wherein a plurality of corresponding circuit traces on the first, second, third and fourth substrates are further electrically connected to the second surface, and are adapted to Test contacts for electrical connection to external test probes. 53． The multi-chip module device as claimed in claim 51, further comprising a plurality of solder balls disposed on one of the first surface of the first substrate and the second surface of the fourth substrate, and the solder balls are connected to the second surface of the fourth substrate. The conductive material and the electrical material of the hole wall of the plated through hole corresponding to one of the substrate and the third substrate. 54． The multi-chip module device as claimed in claim 51, wherein each of the first, second, third and fourth chip units further has a bottom surface opposite to the bonding pad mounting surface, and each of the first, second 2. A metal heat dissipation plate is arranged on the bottom surface of the third and fourth chip units. 55． The multi-chip module device as claimed in claim 51, wherein the periphery of each of the first, second and third chip units is formed between the hole walls of the corresponding second, third and fourth substrates. There is an encapsulation layer. 56． The multi-chip module device as claimed in claim 51, wherein an encapsulation layer is formed between the periphery of the second chip unit and the second surface of the fourth substrate. 57． The multi-chip module device as claimed in claim 54, wherein the second, third and fourth chip units have regions of the bonding pad mounting surfaces where bonding pads are not provided and are respectively connected to the first, second and fourth chip units. The metal heat dissipation plates of the third chip unit are bonded together. 58． The multi-chip module device as claimed in claim 51, further comprising: A fifth substrate, the fifth substrate has a first surface bonded to the second surface of the fourth substrate and a second surface on which predetermined circuit traces are laid, and a plurality of connections with the fourth substrate are formed The corresponding plated through hole is aligned with the plated through hole, the hole wall of each plated through hole of the fifth substrate is plated with the conductive material of the hole wall of the corresponding plated through hole of the fourth substrate and the conductive material of the fifth substrate. The corresponding circuit track on the second surface is electrically connected to the conductive material, and the fifth substrate is also formed with a through hole, so that a hole for accommodating the fourth chip unit is formed between the hole wall of the through hole and the fourth substrate. The chip unit accommodating space, the through hole of the fifth substrate is coaxial with the through hole of the fourth substrate, and is larger than the through hole of the fourth substrate; A sixth substrate, the sixth substrate has a first surface bonded to the second surface of the fifth substrate and a second surface on which predetermined circuit traces are laid, and a plurality of connections with the fifth substrate are formed The plated through holes aligned with the corresponding plated through holes, the hole wall of each plated through hole of the sixth substrate is electroplated with the conductive material of the hole wall of the corresponding plated through hole of the fifth substrate and the conductive material of the sixth substrate. The corresponding circuit traces on the second surface are electrically connected to the conductive material, and the sixth substrate is also formed with a through hole, so that a chip unit accommodation space is formed between the hole wall of the through hole and the fifth substrate, the sixth substrate The through hole of the sixth substrate is concentric with the through hole of the fifth substrate and is larger than the through hole of the fifth substrate; a fifth chip unit, the fifth chip unit is placed in the chip unit accommodating space formed between the hole wall of the fifth substrate and the through hole of the sixth substrate, and has a plurality of bonding pads adhesive pad mounting surface; and A fifth adhesive layer, the fifth adhesive layer has a first adhesive surface and a second adhesive surface, and is formed with a through hole corresponding to the through hole of the fifth substrate and at least one for exposing the first In the window hole of the bonding pad of the five-chip unit, the first bonding surface of the fifth adhesive layer is bonded to the bonding pad mounting surface of the fifth chip unit, so that the hole forming wall of the window hole is in contact with the first bonding surface of the fifth chip unit. A conductor accommodating space for accommodating a fifth conductor is formed between the five chip units. The fifth conductor is electrically connected to the corresponding bonding pad of the fifth chip unit. The fifth adhesive layer of the fifth adhesive layer Two bonding surfaces are bonded to the second surface of the fifth substrate, so that the fifth chip unit can be disposed on the second surface of the fifth substrate, and the fifth conductor is also bonded to the second surface of the fifth substrate. Corresponding circuit traces on the surface are electrically connected. 59． The multi-chip module device as claimed in claim 58, further comprising a plurality of solder balls disposed on one of the first surface of the first substrate and the second surface of the sixth substrate, and the solder balls are connected to the first surface of the sixth substrate. A substrate is electrically connected to the conductive material of the hole wall of the plated through hole corresponding to one of the sixth substrates. 60． The multi-chip module device as claimed in claim 58, wherein each of the first, second, third, fourth and fifth chip units further has a bottom surface opposite to the bonding pad mounting surface, and each of the first One, the second, the third, the fourth and the fifth chip unit are provided with a metal heat dissipation plate on the bottom surface. 61． The multi-chip module device as claimed in claim 58, wherein the surroundings of each of the first, second, third, fourth and fifth chip units are associated with the corresponding second, third, fourth and fourth An encapsulation layer is formed between the walls of the through holes of the fifth and sixth substrates. 62． The multi-chip module device according to claim 60, wherein the area portions of the bonding pad mounting surfaces of the second, third, fourth and fifth chip units not provided with bonding pads are respectively connected to the first, The metal heat dissipation plates of the second, third and fourth chip units are bonded together. 63． A multi-chip module device, comprising: A first substrate, the first substrate has a first surface and a second surface opposite to the first surface, and is formed with a plurality of plated through holes, and conductive material is plated on the hole wall of each plated through hole; A second substrate, the second substrate has a first surface bonded to the second surface of the first substrate and a second surface on which predetermined circuit traces are laid, and a plurality of connections with the first substrate are formed The corresponding plated through hole is aligned with the plated through hole, the hole wall of each plated through hole of the second substrate is plated with the conductive material of the hole wall of the corresponding plated through hole of the first substrate and the second substrate The conductive material electrically connected to the corresponding circuit track on the second surface of the second substrate, and a perforation is formed on the second substrate, so that a chip unit accommodating space is formed between the hole wall of the perforation and the first substrate; A first chip unit, the first chip unit is placed in the chip unit accommodating space, and has a bonding pad mounting surface provided with a plurality of bonding pads and a bottom surface opposite to the bonding pad mounting surface ; A first adhesive layer, the first adhesive layer has a first adhesive surface and a second adhesive surface, the adhesive pad mounting surface of the first chip unit and the first adhesive layer of the first adhesive layer bonding surface, the second bonding surface of the first adhesive layer is bonding to the second surface of the first substrate, so that the first chip unit can be arranged on the second surface of the first substrate, the The electrical connection between the bonding pads of the first chip unit and the corresponding circuit traces on the second surface of the second substrate is realized by means of first wires; A third substrate, the third substrate has a first surface bonded to the second surface of the second substrate and a second surface on which predetermined circuit traces are laid, and a plurality of connections with the second substrate are formed The plated through holes aligned with the corresponding plated through holes, the hole walls of the plated through holes of the third substrate are electroplated with the conductive material of the hole walls of the corresponding plated through holes of the second substrate and the wall of the third substrate. The corresponding circuit track on the second surface is electrically connected to the conductive material, and the third substrate is also formed with a through hole, so that a chip unit accommodating space is formed between the hole wall of the through hole and the second substrate, and the third substrate The through hole of the substrate is concentric with the through hole of the second substrate and is larger than the through hole of the second substrate; a second chip unit, the second chip unit is placed in the chip unit accommodating space formed between the second substrate and the wall of the through hole of the third substrate and has a plurality of bonding pads an adhesive pad mounting surface and a bottom surface opposite the adhesive pad mounting surface; A second adhesive layer, the second adhesive layer has a first adhesive surface and a second adhesive surface, the bottom surface of the second chip unit is bonded to the first adhesive surface of the second adhesive layer , the second bonding surface of the second adhesive layer is bonded to the bonding pad mounting surface of the first chip unit without covering the bonding pad of the first chip unit, so that the second chip unit can It is arranged on the bonding pad mounting surface of the first chip unit, and the electrical connection between the bonding pad of the second chip unit and the corresponding circuit track on the second surface of the third substrate is achieved by means of a second wire. accomplish; A fourth substrate, the fourth substrate has a first surface bonded to the second surface of the third substrate and a second surface on which predetermined circuit traces are laid, and a plurality of connections with the third substrate are formed The plated through holes aligned with the corresponding plated through holes, the hole wall of each plated through hole of the fourth substrate is electroplated with the conductive material of the hole wall of the corresponding plated through hole of the third substrate and the wall of the fourth substrate The corresponding circuit track on the second surface is electrically connected to the conductive material, and the fourth substrate is also formed with a through hole, so that a chip unit accommodating space is formed between the hole wall of the through hole and the third substrate, the fourth substrate The through hole of the substrate is concentric with the through hole of the third substrate and is larger than the through hole of the third substrate; A third chip unit, the third chip unit is placed in the chip unit accommodating space formed between the wall of the through hole of the third substrate and the fourth substrate, and has a plurality of bonding an adhesive pad mounting surface of the pad and a bottom surface opposite the adhesive pad mounting surface; A third adhesive layer, the third adhesive layer has a first adhesive surface and a second adhesive surface, the first adhesive surface of the third adhesive layer is bonded to the bottom surface of the third chip unit , and the second bonding surface of the third adhesive layer is bonded to the bonding pad mounting surface of the second chip unit without covering the bonding pad of the second chip unit, so that the third chip can be The unit is arranged on the bonding pad mounting surface of the second chip unit, and the electrical connection between the bonding pad of the third chip unit and the corresponding circuit trace on the second surface of the fourth substrate is by means of a third wire to fulfill; a fourth chip unit having a bonding pad mounting surface provided with a plurality of bonding pads; and A fourth adhesive layer, the fourth adhesive layer has a first adhesive surface and a second adhesive surface, and is formed with a through hole corresponding to the through hole of the fifth substrate and at least one for exposing the first The window hole of the bonding pad of the four-chip unit, the first bonding surface of the fourth adhesive layer is bonded to the bonding pad mounting surface of the fourth chip unit, so that the hole forming wall of the window hole is connected to the first bonding surface of the fourth chip unit. A conductor accommodating space for accommodating a conductor is formed between the four chip units, the conductor is electrically connected to the corresponding bonding pad of the fourth chip unit, and the second bonding surface of the fourth adhesive layer Bonded to the second surface of the fourth substrate, so that the fourth chip unit can be arranged on the second surface of the fourth substrate, and the conductor is also connected to the corresponding circuit on the second surface of the fifth substrate trace electrical connections. 64． The multi-chip module device as claimed in claim 63, further comprising a plurality of solder balls disposed on one of the first surface of the first substrate and the second surface of the fourth substrate, and the solder balls are connected to the second surface of the fourth substrate. A substrate is electrically connected to the conductive material of the hole wall of the plated through hole corresponding to one of the fourth substrates. 65． The multi-chip module device as claimed in claim 63, wherein the fourth chip unit further has a bottom surface opposite to the bonding pad mounting surface, and a metal heat dissipation plate is disposed on the bottom surface of the fourth chip unit. 66． The multi-chip module device as claimed in claim 63, wherein an encapsulation layer is formed between the periphery of the fourth chip unit and the second surface of the fourth substrate.

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