CN1277719A - Phase comparator and digital phase-locked circuit - Google Patents
Phase comparator and digital phase-locked circuit Download PDFInfo
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/10009—Improvement or modification of read or write signals
- G11B20/10222—Improvement or modification of read or write signals clock-related aspects, e.g. phase or frequency adjustment or bit synchronisation
- G11B20/1024—Improvement or modification of read or write signals clock-related aspects, e.g. phase or frequency adjustment or bit synchronisation wherein a phase-locked loop [PLL] is used
- G11B20/1025—Improvement or modification of read or write signals clock-related aspects, e.g. phase or frequency adjustment or bit synchronisation wherein a phase-locked loop [PLL] is used the PLL being discrete time or digital PLL
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/10009—Improvement or modification of read or write signals
- G11B20/10037—A/D conversion, D/A conversion, sampling, slicing and digital quantisation or adjusting parameters thereof
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- G11B20/10—Digital recording or reproducing
- G11B20/14—Digital recording or reproducing using self-clocking codes
- G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
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- G—PHYSICS
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- G11B20/10—Digital recording or reproducing
- G11B20/12—Formatting, e.g. arrangement of data block or words on the record carriers
- G11B2020/1264—Formatting, e.g. arrangement of data block or words on the record carriers wherein the formatting concerns a specific kind of data
- G11B2020/1265—Control data, system data or management information, i.e. data used to access or process user data
- G11B2020/1287—Synchronisation pattern, e.g. VCO fields
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- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B2220/00—Record carriers by type
- G11B2220/20—Disc-shaped record carriers
- G11B2220/25—Disc-shaped record carriers characterised in that the disc is based on a specific recording technology
- G11B2220/2537—Optical discs
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Abstract
本发明涉及一种相位比较器及一数字相位同步电路。设输入RF信号的重放同步时钟信号的重复周期为T时,延迟元件(11)可将RF信号延时nT,由减法器(12)从延迟元件(11)所输出的RF信号D(t－nT)减去现在时刻的RF信号D(t)。判定电路(13)由RF信号D(t)及现在时刻t前后时刻的数字RF信号D(t±mT),判定现在时刻的RF信号D(t)是在上升沿点或下降沿点中何种状态。信号处理电路(14),由前述判定电路(13)的判断结果及所述减法器(12)的相减结果,检测重放同步时钟信号相对于输入RF信号,是处于超前相位或滞后相位中哪一种状态,并将检测结果输出作为相位误差信号。由此,可消除RF信号中DC偏移的影响,且提高数字相位同步电路的导入特性。
The invention relates to a phase comparator and a digital phase synchronization circuit. When the repetition period of the playback synchronous clock signal of the input RF signal is T, the delay element (11) can delay the RF signal by nT, and the RF signal D(t) output by the subtractor (12) from the delay element (11) -nT) minus the RF signal D(t) at the present moment. The judging circuit (13) judges whether the RF signal D(t) at the current moment is on the rising edge point or the falling edge point from the RF signal D(t) and the digital RF signal D(t±mT) at the time before and after the current time t. state. The signal processing circuit (14) detects whether the playback synchronous clock signal is in a leading phase or a lagging phase relative to the input RF signal based on the judgment result of the aforementioned judgment circuit (13) and the subtraction result of the subtractor (12). Which state, and output the detection result as a phase error signal. Thus, the influence of DC offset in the RF signal can be eliminated, and the lead-in characteristics of the digital phase synchronization circuit can be improved.
Description
Technical field
The present invention relates to a kind of in recording the recording medium of numerical data, again to reset with the digital phase synchronizing circuit of replay signal clock signal synchronous and to be used for the phase comparator of this digital phase synchronizing circuit.
Background technology
Optical disc recording apparatus (CD-ROM, DVD-ROM, DVD-RAM) and magnetic recording replay apparatus (disk) etc., in order to reset one when being recorded in the signal of recording medium, then must have one can with this replay signal clock signal synchronous.Phase locking circuit means, can be in order to the clock signal of playback synchronization, and this synchronizing circuit can be read RF (high frequency) signal that contains data by recording medium, is generated the clock signal that is used for data playback by this RF signal.This phase locking circuit, available digital formula phase locking circuit replaces analog phase locking circuit (PLL:Phase Locked Loop circuit in the past; Phase-locked loop).
In Fig. 6, show digital phase synchronizing circuit one example in the past.At first, read the RF signal that contains data, and input to waveform equalization circuit 61, carry out wave shape equalization, make it to become desired characteristic from the recording medium that records data.And the output signal of this waveform equalization circuit 61 is imported automatic gain adjust circuit (AGC) 62, the adjustment that gains makes it to become pre-sizing.Then, the signal content input low-pass filter (LPF) 63 with having been gained and adjusted by AGC62 makes the frequency band ceiling restriction of input rf signal become below 1/2 of playback synchronization clock signal frequency.Then, use the playback synchronization clock signal, carry out the RF signal sampling by analog/digital conversion circuit (ADC) 64, and be transformed into digital RF signal.At this, employed playback synchronization clock signal clk is generated by aftermentioned Voltage-Controlled oscillation circuit (VCO) 68 in ADC64.
By the digital conversion signal input digit phase comparator 65 of ADC64 sampling, with the phase error of the digital calculating of aftermentioned method with respect to reference phase.Then, phase error signal digital loop filters 66 filtering of being calculated by digital phase comparator 65.Then, be transformed into simulating signal, produce the VCO control signal by digital-to-analog translation circuit (DAC) 67.VC068 is according to the simulation VCO control signal of DAC67 output, and vibration produces synchronizing clock signals CLK.This playback synchronization clock signal clk is as the sampled signal among the aforementioned ADC64.At this, specify the action of the digital phase comparator 65 that can calculate phase error signal.Digital phase comparator 65 on the sample point of RF signal, behind the zero crossing during the detected phase locking, detects rising edge or the negative edge of this zero crossing corresponding to the RF signal.Then,, and utilize the value of RF cycle signal zero-cross point, generate the phase error signal Perr of corresponding rising point or drop point according to this testing result.When rising edge point, use the zero passage point value as phase error signal Perr.When negative edge point, then, be used as phase error signal Perr with go up (1) on duty of zero crossing again.
At this, as the method that detects zero crossing, can lift following determination methods is example: ask the absolute value of the difference signal of two sample points of clamping zero level and zero level, the sample point that this absolute value is few is judged as zero crossing.Again, in the method as rising edge point that detects the RF signal and negative edge point, one method of judging by RF signal sampling point symbol is arranged, symbol by-(negative sign) under+situation that (positive sign) changes, can be judged as the rising edge point, opposite, by+(positive sign) under-situation that (negative sign) changes, then can be judged as the negative edge point.
For example, with respect to the playback synchronization clock signal clk with repetition period T as shown in Figure 2, and input has the situation of the RF signal in about 8T cycle.Fig. 7 (a)～(c) shows among the ADC64 oscillogram of the RF signal sampling point of playback synchronization clock signal clk.The zero crossing of A point expression RF signal rising edge among the figure, the zero crossing of B point expression RF signal negative edge.At this, respectively set the RF signal value that A point, B are ordered for DT (tA), DT (tB).
(1) shown in Fig. 7 a, do not having under the state of phase error, because of the zero crossing A point of RF signal rising edge is positioned on the zero level, so DT (tA) ≈ 0, the phase error signal that A is ordered then is Perr (tA) ≈ 0.Again, same, the zero crossing B point of RF signal negative edge is DT (tB) ≈ 0, so the phase error signal that B is ordered also is Perr (tB) ≈ 0.
(2) shown in Fig. 7 b, the playback synchronization clock signal clk is with respect to the RF signal, and during its phase lag, the zero crossing A of RF signal rising edge gets negative value DT (tA), and the zero crossing B of RF signal negative edge then gets on the occasion of DT (tB).At this moment, RF signal rising edge point is that the error signal at A point place is: Perr (tA)=DT (tA), RF signal negative edge point be B point place error signal then for Perr (tB)=-DT (tB), the value of the phase error signal that A point and B are ordered is all got negative value with respect to lagging phase.
(3) shown in Fig. 7 c, the playback synchronization clock signal clk is with respect to the RF signal, and when its phase place was leading, RF signal zero crossing A when rising edge got on the occasion of DT (tA), and the RF signal is then got negative value DT (tB) at the zero crossing B of negative edge.At this moment, the RF signal is that the error signal at A point place is Perr (tA)=DT (tA) at the rising edge point, the negative edge point of RF signal be B point place error signal then for Perr (tB)=-DT (tB), the value of A point and B point phase error signal is with respect to leading phase, all get on the occasion of.
By above-mentioned action, digital phase comparator 65 produces phase error signal, according to this signal, makes the digital phase synchronization circuit action, can realize the playback synchronization clock signal clk.
But, as shown in Figure 8, having DC at the input signal of digital phase comparator 65 with respect to zero level and shift into timesharing, when detecting digital phase comparator 65 zero crossings, judgement can make a mistake.When this false judgment takes place, on other stable point, as shown in Figure 9, phase-locking, and phase error can not be fed back.So, the problem that can not correctly implement phase control is arranged.
Invention discloses
The present invention is in order to solve aforementioned problems, the digital phase synchronization circuit that its purpose is to realize a kind of phase comparator and uses this phase comparator, this phase comparator can be eliminated the influence of DC skew in the RF signal, and improves the importing characteristic of digital phase synchronization circuit.
For solving aforementioned problems, a kind of phase comparator of the present invention's the 1st example, the medium that numerical data is arranged at sweep record, when producing the playback synchronization clock signal of reproduction digital data by the resulting RF signal of described recording medium, described RF signal transformation is become digital RF signal, and detect the reference point of described digital RF signal and the phase error of described playback synchronization clock signal; This phase comparator comprises: delay element, and the maximum frequency of establishing aforementioned RF signal is f, and repetition period of described playback synchronization clock signal when being T (T≤1/ (2f)), this delay element makes described digital RF signal time-delay nT (n is an integer); Subtracter, the digital RF signal D (t-nT) that exports from described delay element deducts the digital RF signal D (t) of present moment; Decision circuitry, (t ± mT) (m is an integer) judges the digital RF signal D (t) of present moment is in which kind of state in rising edge point or the negative edge point by constantly digital RF signal D before and after the digital RF signal D (t) of present moment and the present moment t; Signal processing circuit, D (the t-nT)-D (t) as a result that subtracts each other by the judged result of described decision circuit and described subtracter, detect described playback synchronization clock signal with respect to input rf signal, be any state that is in leading phase or the lagging phase, this testing result is exported as phase error signal.
A kind of digital phase synchronization circuit of the present invention's the 2nd example is used for the recording medium of sweep record numerical data, produces the playback synchronization clock signal that is used for reproduction digital data by the resulting RF signal of described recording medium; Its formation includes: waveform equalization circuit is used to reduce the waveform distortion by the resulting RF signal of described recording medium; Low-pass filter is with stagnant below 1/2 of repetition frequency that is limited to described playback synchronization clock signal of the frequency of described waveform equalization circuit output signal; The DC control circuit is removed DC skew composition contained in the RF signal by described low-pass filter output; Analog/digital conversion circuit is sampled the RF signal that described DC control circuit is exported by described playback synchronization clock signal, be transformed into digital RF signal; Delay element, the maximum frequency of establishing described RF signal is f, and repetition period of described playback synchronization clock signal when being T (T≤1/ (2f)), this delay element makes described digital RF signal time-delay nT (n is an integer); Subtracter, the digital RF signal D (t-nT) that exports from described delay element deducts the digital RF signal D (t) of present moment; Decision circuit, (t ± mT) (m is an integer) judges the digital RF signal D (t) of present moment is in which kind of state in rising edge point or the negative edge point by constantly digital RF signal D before and after the digital signal D (t) of present moment and the present moment t; Signal processing circuit, D (the t-nT)-D (t) as a result that subtracts each other by the judged result of described decision circuit and described subtracter, detect described playback synchronization clock signal with respect to input rf signal, be any state that is in leading phase or the lagging phase, and this testing result is exported as phase error signal; The digital-to-analog translation circuit, the phase error signal that described signal processing circuit is exported is transformed into simulating signal; Voltage-Controlled oscillation circuit, vibration produces described playback synchronization clock signal, and provides to described analog/digital conversion circuit, and this playback synchronization clock signal frequency is corresponding to the analogue phase error signal of described digital-to-analog translation circuit institute conversion.
Summary of drawings
Fig. 1 is the pie graph of the phase comparator of the invention process form 1; Fig. 2 is the oscillogram that expression RF signal and playback synchronization clock signal concern an example; Fig. 3 is in the phase comparator of the invention process form, and expression is in order to the RF signal of the point of generation phase error signal; Fig. 4 is the pie graph of the digital phase synchronization circuit of the invention process form 2; Fig. 5 be have synchronous importing pattern (VFO pattern) intermittence replay data key diagram; Fig. 6 comprises the pie graph of the digital phase synchronization circuit of phase comparator in the past; Fig. 7 is in phase comparator in the past, and expression generates the oscillogram of the point of phase error signal; Fig. 8 is the oscillogram that has the RF signal of DC skew with respect to zero level; Fig. 9 is in phase comparator in the past, and expression has the oscillogram of the RF signal stabilization point of DC skew.
Implement optimal morphology of the present invention
Hereinafter, embodiments of the invention are described.At first, with reference to Fig. 1, the phase comparator of the present invention's the 1st example is described.Fig. 1 is the pie graph of the phase comparator of this example.This phase comparator 10 is imported by the digitized digital RF signal D of analog/digital conversion circuit (t), and digitally calculates phase error signal Perr.The formation of phase comparator 10 includes: delay element 11, subtracter 12, decision circuit 13, signal processing circuit 14.
In the prior art method, generate phase error signal with the RF cycle signal zero-cross point, but the feature of the phase comparator 10 of this example is then: the intermediate point with the RF signal waveform generates phase error signal.At this, suppose input one digital RF signal D (t), this digital RF signal D (t) is with respect to the playback synchronization clock signal clk with 1T repetition period shown in Figure 2, and 4T has only a maximum value or minimum value in the time at least, and sets the maximum frequency composition for f.The passband of setting LPF63 among Fig. 6 again is to satisfy this condition.At this, be 2T the time delay of establishing delay element 11.The constructive method of delay element 11 is can be by the d type flip flop of playback synchronization clock signal clk action with 2.At difference signal with the intermediate point of this digital RF signal, when promptly using D (t-2T)-D (t) to generate phase error signal, be multiplied by the value of (one 1) by the difference signal of getting RF waveform the latter half, can generation and phase retardation and the corresponding phase error signal of leading phase.The method that generates this phase error signal is described with Fig. 3.
Fig. 3 (a)～(c) expression is according to the oscillogram of RF signal sampling point in the analog/digital conversion circuit (ADC64 that is equivalent to Fig. 6) of RF signal and playback synchronization clock signal clk.The intermediate point of the A1 point expression RF signal the first half rising edge among the figure, the intermediate point of A2 point expression RF signal the first half negative edge, the B1 point is then represented the intermediate point of RF signal the latter half negative edge, the intermediate point of B2 point expression RF signal the latter half rising edge.The content of these sample points can be judged by decision circuit 13.At this, the value that the RF signal is ordered at A1, A2, B1, B2 respectively is assumed to be DT (tA1), DT (tA2), DT (tB1), DT (tB2).
(1) shown in Fig. 3 a, in the absence of phase error, when the A1 point of RF signal the first half deducted the A2 point, this difference signal then was DT (tA1)-DT (tA2) ≈ 0 by subtracter 12.At this moment, signal processing circuit 14 output is as the phase error signal of RF signal the first half:
Perr＝DT(tA1)-DT(tA2)≈0
Again, in the time of will deducting the B2 point from the B1 point of RF signal the latter half by subtracter 12, this difference signal also is DT (tB1)-DT (tB2) ≈ 0.At this moment, signal processing circuit 14 output is as the phase error signal of RF signal the latter half:
Perr＝{DT(tB1)-DT(tB2)}≈0
(2) shown in Fig. 3 b, the playback synchronization clock signal clk is with respect to the RF signal, and during its phase lag, when the A1 point of RF signal the first half deducted the A2 point, this difference signal then was DT (tA1)-DT (tA2)＜0 by subtracter 12.At this moment, signal processing circuit 14 output is as the phase error signal of RF signal the first half:
Perr＝DT(tA1)-DT(tA2)＜0
Again, when the B1 point of RF signal the latter half deducted the B2 point, this difference signal then became DT (tB1)-DT (tB2)＞0 by subtracter 12.At this moment, signal processing circuit 14 output is as the phase error signal of RF signal the latter half:
Perr＝-{DT(tB1)-DT(tB2)}＜0
Thereby, can generate the phase error signal that is negative value with respect to lagging phase.
(3) shown in Fig. 3 (c), the playback synchronization clock signal clk is with respect to the RF signal, and when its phase place was leading, when the A1 point of RF signal the first half deducted the A2 point, this difference signal then was DT (tA1)-DT (tA2)＞0 by subtracter 12.At this moment, signal processing circuit 14 output is as the phase error signal of RF signal the first half:
Perr＝DT(tA1)-DT(tA2)＞0
Again, when the B1 point of RF signal the latter half deducted the B2 point, this difference signal then was DT (tB1)-DT (tB2)＜0 by subtracter 12.At this moment, signal processing circuit 14 output is as the phase error signal of RF signal the latter half:
Perr＝-{DT(tB1)-DT(tB2)}＞0
Thereby, can generate with respect to leading phase be on the occasion of phase error signal.
As described above, when making phase comparator 10 actions, can generate phase error signal, the DC skew that becomes problem in the previous methods can be eliminated thus, and generate the phase error signal of eliminating the DC bias effect by the difference signal of RF signal.
The 2nd form of the present invention is that to be used for optical disc recording apparatus be that example is illustrated to the phase comparator with the 1st form.Fig. 4 is the pie graph of the digital phase synchronizing circuit of the invention process form 2, and this circuit can be used for optical disc recording apparatus.As shown in the figure, the formation of optical disc recording apparatus includes: as the CD 401 of recording medium, from the light picker 402 of CD 401 replay data, by the RF signal of reading through light picker 402 with playback synchronization signal extracted digit formula phase locking circuit 400.
Digital phase synchronizing circuit 400 is with shown in Figure 6 same, be provided with: ripple has equalizing circuit 403, automatic gain to adjust circuit (AGC) 404, low-pass filter (LPF) 405, analog/digital conversion circuit (ADC) 407, digital phase comparator 408, digital loop filters 409, digital-to-analog translation circuit (DAC) 410, Voltage-Controlled oscillation circuit (VCO) 411, these unit and prior art example are same, so in this detailed.Except that said units, also set up in the digital phase synchronizing circuit 400 of this example: the DC deviation in order to the DC skew of removing the LPF405 output signal removes circuit 406, detects the DC deviation detection circuit 412 of the DC skew composition that is comprised in the ADC407 output signal, the output signal of DC deviation detection circuit 412 is converted to simulating signal and removes the DAC413 that circuit 406 provides to the DC deviation.At this, the DC deviation is removed circuit 406, DC deviation detection circuit 412 and DAC413 and be can be used as one in order to DC contained in the RF signal is offset the DC control circuit that composition is removed.
The replay data at intermittence that from the RF signal that CD 401 is read, in the unit of sector, contains the synchronous introducing pattern (VFO pattern) that has as shown in Figure 5.The optical disc recording apparatus that is shown in Fig. 4 also must carry out data playback during as DVD-RAM when high-velocity scanning.Playback speed is different according to CD 401 sector units, therefore can write down synchronous lead-in signal in the VFO pattern.
At this, with the RF signal that is write down in the CD 401, read with light picker 402, make this signal input to waveform equalization circuit 403, and carry out wave shape equalization, make it to form desired characteristic.Subsequently, the output signal of waveform equalization circuit 403 is inputed to AGC404, the adjustment that gains, make formation fixed amplitude.Secondly, make to apply the signal content that gain adjusts through AGC404 and import to LPF405, the frequency band upper limit with restriction RF signal makes it to be below 1/2 of playback synchronizing clock signals repetition frequency.Remove by the DC deviation that the DC skew makes it to be minimum in the circuit 406 control RF signals.With the output signal that this DC deviation is removed circuit 406, use the playback synchronization clock signal, sample by ADC407, and convert digital signal to.At this, employed playback synchronization signal CLK generates with aftermentioned VC0411.
Digital conversion signal by the ADC407 sampling is imported digital phase comparator 408 of the present invention.As previously mentioned, can digital calculating with respect to the phase error of reference phase.With phase error signal Perr digital loop filters 409 filtering of being calculated, and convert the interior VCO control signal of scope that can make the VC0411 action to.This numeral VCO control signal can be transformed into simulation VCO control signal by DAC410, imports VC0411 again.VC0411 produces the playback synchronization clock signal clk with frequency corresponding with the value of VCO control signal.This playback synchronization clock signal clk can be used as the sampled signal of aforementioned ADC407 and uses.
On the other hand, DC deviation detection circuit 412 can detect the DC deviation composition as the DC skew by the digital conversion data of ADC407 sampling.The detection of this DC deviation composition is undertaken by each value of the above sample point of average 8T.Then, generate remove the suitable digital signal of the DC control voltage of circuit 406 with the DC deviation after, be transformed into simulating signal by DAC413.The DC deviation is removed circuit 406, and the DC composition according to the value control RF signal of the analog D C control signal of DAC413 output carries out the DC level translation of RF signal, and the DC deviation is diminished.
In the digital phase synchronization circuit of this example, with phase comparator in the past the time, if input has the RF signal of DC skew, then virtual lockout is applied on other stable point.Therefore, in the DC control circuit, as shown in Figure 5, after the DC skew of getting, make digital phase comparator 408 actions except that the VFO pattern.In this occasion, must control and two actions of phase-locking and carry out DC in order to the VFO pattern of finite length, therefore, can not obtain fully and carry out the phase locked time.Especially in the digital phase synchronization circuit, this digital phase synchronization circuit is compared with the analogue phase synchronizing circuit, and the time delay in the phase-locking loop is long, and makes the frequency acquisition scope that phase place can be synchronous that the tendency that narrows down be arranged.
In addition,, the influence of DC skew be can eliminate, the DC control and two actions of phase-locking of VFO pattern therefore can be carried out simultaneously according to phase comparator 10 of the present invention or 408.Thereby, the VFO pattern of finite length all can be used for phase-locking.Therefore, comparable phase comparator in the past more can fully be guaranteed to provide the importing characteristic of digital phase synchronization circuit in order to carry out the phase locked time.Utilizability on the industry
As mentioned above, the phase comparator of the 1st example according to the present invention can be eliminated the influence of DC skew in the RF signal, and certain output phase error signal.
The digital phase synchronization circuit of the 2nd example according to the present invention can use intermittent recording not to be subjected to import synchronously the influence of the DC composition in the pattern at the synchronous importing pattern of recording medium, and generate a playback synchronization clock signal at a high speed again.
If in optical disc recording apparatus, use this digital phase synchronization circuit, can when retrieving the CD session at a high speed, also can make synchronous importing become easy.Thus, at the variable-ratio playback time, can make data access more certain.
Claims (2)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10258041A JP2985957B1 (en) | 1998-09-11 | 1998-09-11 | Phase comparator and digital phase locked loop |
| JP258041/1998 | 1998-09-11 |
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| Publication Number | Publication Date |
|---|---|
| CN1277719A true CN1277719A (en) | 2000-12-20 |
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| CN99801514A Pending CN1277719A (en) | 1998-09-11 | 1999-09-08 | Phase comparator and digital phase-locked circuit |
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| Country | Link |
|---|---|
| JP (1) | JP2985957B1 (en) |
| KR (1) | KR20010031740A (en) |
| CN (1) | CN1277719A (en) |
| ID (1) | ID24226A (en) |
| TW (1) | TW439360B (en) |
| WO (1) | WO2000016330A1 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101005481B (en) * | 2006-01-20 | 2012-05-02 | 富士通半导体股份有限公司 | Demodulation circuit and demodulation method |
| CN108352829A (en) * | 2015-11-10 | 2018-07-31 | 特利丹E2V半导体简化股份公司 | Method by being sent to the signal synchrodata converter of next converter from a converter |
| CN115037430A (en) * | 2022-02-15 | 2022-09-09 | 北京时代民芯科技有限公司 | I, Q-path DAC synchronous design method |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7889818B2 (en) * | 2006-11-14 | 2011-02-15 | Samsung Electronics Co., Ltd. | Method and apparatus for controlling sampling of signals produced in relation to stored data |
| CN106555132B (en) * | 2016-12-02 | 2017-11-24 | 机械科学研究总院青岛分院 | A kind of high-carbon-chromium bearing steel Technology for Heating Processing |
| JP7474566B2 (en) * | 2019-03-29 | 2024-04-25 | ローム株式会社 | Oscillator circuit, semiconductor device, oscillator IC |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03266263A (en) * | 1990-03-15 | 1991-11-27 | Ricoh Co Ltd | Recording/reproducing timing generating device |
| US5311178A (en) * | 1992-08-14 | 1994-05-10 | Silicon Systems, Inc. | Method for processing sample values in an RLL channel |
| JPH06124545A (en) * | 1992-08-25 | 1994-05-06 | Sony Corp | Automatic phase adjusting circuit for clock signals |
-
1998
- 1998-09-11 JP JP10258041A patent/JP2985957B1/en not_active Expired - Fee Related
-
1999
- 1999-09-08 KR KR1020007004805A patent/KR20010031740A/en not_active Application Discontinuation
- 1999-09-08 CN CN99801514A patent/CN1277719A/en active Pending
- 1999-09-08 ID IDW20000886A patent/ID24226A/en unknown
- 1999-09-08 WO PCT/JP1999/004857 patent/WO2000016330A1/en not_active Application Discontinuation
- 1999-09-10 TW TW088115665A patent/TW439360B/en active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101005481B (en) * | 2006-01-20 | 2012-05-02 | 富士通半导体股份有限公司 | Demodulation circuit and demodulation method |
| CN108352829A (en) * | 2015-11-10 | 2018-07-31 | 特利丹E2V半导体简化股份公司 | Method by being sent to the signal synchrodata converter of next converter from a converter |
| CN108352829B (en) * | 2015-11-10 | 2022-02-25 | 特利丹E2V半导体简化股份公司 | Method for synchronizing analog-to-digital data converters and/or digital-to-analog data converters |
| CN115037430A (en) * | 2022-02-15 | 2022-09-09 | 北京时代民芯科技有限公司 | I, Q-path DAC synchronous design method |
| CN115037430B (en) * | 2022-02-15 | 2024-04-05 | 北京时代民芯科技有限公司 | A Synchronous Design Method for I and Q DACs |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2985957B1 (en) | 1999-12-06 |
| ID24226A (en) | 2000-07-13 |
| KR20010031740A (en) | 2001-04-16 |
| TW439360B (en) | 2001-06-07 |
| JP2000091910A (en) | 2000-03-31 |
| WO2000016330A1 (en) | 2000-03-23 |
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