CN1277355C - Emitter-coupled logic circuit with data reload function - Google Patents
Emitter-coupled logic circuit with data reload function Download PDFInfo
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- CN1277355C CN1277355C CN02142231.1A CN02142231A CN1277355C CN 1277355 C CN1277355 C CN 1277355C CN 02142231 A CN02142231 A CN 02142231A CN 1277355 C CN1277355 C CN 1277355C
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Abstract
具有数据重载功能的发射极耦合逻辑电路，包含第一与第二串接晶体管，分别由双极型晶体管(BJT)与场效应晶体管(FET)所构成。双极型晶体管接收重载控制信号，而场效应晶体管接收重载数据，以利用双极型晶体管与场效应晶体管的串联控制，来将数字重载数据重载于该ECL电路。由于是利用场效应晶体管直接接收设定重载数据，数字重载数据不必经过前置ECL电压电平转换处理。重载数据可在重载控制信号动作前，先设定传送至场效应晶体管，所以场效应晶体管可先设定导通或关闭。只要重载控制信号一动作，即可根据重载数据控制输出端的状态，提升ECL电路的数据重载动作速度。
An emitter coupled logic circuit with a data reload function includes a first and a second series transistor, which are respectively composed of a bipolar transistor (BJT) and a field effect transistor (FET). The bipolar transistor receives a reload control signal, and the field effect transistor receives the reload data, so as to utilize the series control of the bipolar transistor and the field effect transistor to reload the digital reload data on the ECL circuit. Since the field effect transistor is used to directly receive the set reload data, the digital reload data does not need to be processed by the pre-ECL voltage level conversion. The reload data can be set and transmitted to the field effect transistor before the reload control signal is activated, so the field effect transistor can be set to be turned on or off first. As long as the reload control signal is activated, the state of the output terminal can be controlled according to the reload data, thereby improving the data reload action speed of the ECL circuit.
Description
Technical field
(Emitter Couple Logic, ECL) circuit is particularly about utilizing the transistorized emitter-coupled logic (ECL) with data heavy duty function of bond oxide-semiconductor field effect (MOSFET) to the present invention relates to emitter coupled logic.
Background technology
Because the service speed of emitter coupled logic (hereinafter to be referred as ECL) circuit is fast, so the ECL circuit has been widely used in logic gates (logic gate circuit), for example D flip-flop (Flip-Flop).Figure 1 shows that the ECL circuit " ECL circuit for forcibly setting ahigh level output " of the 4th, 546, No. 272 patents of the U.S..This ECL circuit comprises emitter-coupled bipolar transistor TR1, the TR2 of a pair of reception differential wave and the resistance R that load resistance R1, R2, are connected in the emitter of bipolar transistor TR1, TR2
s, one be connected in resistance R
sCurrent source and a pair of bipolar transistor TR3, the TR4 that is used for receive being provided with (set) or (reset) signal that resets.
This traditional ECL circuit utilizes resistance R
sVoltage difference is provided, make the base stage and base stage and the emitter voltage poor (VBE1, VBE2) of emitter voltage poor (VBE3, VBE4) greater than the emitter-coupled bipolar transistor TR1, the TR2 that receive differential wave, the output signal of forcing setting to be output as setting or to reset of bipolar transistor TR3, TR4 that (set) or (reset) signal that resets receive to be set.
Though providing, this traditional ECL circuit is provided with and the function that resets, not the function of heavy duty (Reload).Because the ECL circuit is not that complementary metal oxide is partly led (CMOS) transistorized logic digital circuits, can't directly receive digital overloading data as signalization and reset signal.Therefore, during for needs numeral overloading data, must judge earlier that the overloading data of required loading is logic high (Logichigh) H, or logic low (Logic low) L.If H then is set at high-voltage level with signalization, and reset signal is set at low voltage level.If anti-L then is set at low voltage level with signalization, and reset signal is set at high-voltage level.So, with the complexity that causes in the design, and when carrying out overloading data conversion ECL voltage level, can cause the delay on the data heavy duty speed, and influence the data over-loading operation speed of this ECL circuit.
Summary of the invention
Because the problems referred to above the objective of the invention is to propose a kind of ECL circuit with data heavy duty function.
The objective of the invention is to propose the ECL circuit that a kind of digital overloading data can direct-coupledly have data heavy duty function.
For reaching above-mentioned purpose, the present invention has the ECL circuit of data heavy duty function, and comprise: a differential and double bipolar transistor is right, comprises first bipolar transistor and second bipolar transistor, the emitter of these two bipolar transistors is connected to each other, and base stage receives a differential wave; One load resistance is right, comprises first load resistance and second load resistance, is serially connected with the right collector electrode of differential and double bipolar transistor respectively; One resistance has first end and second end, and this first end is connected in the right emitter of differential and double bipolar transistor; One fixed current source is connected in second end of resistance; The first serial connection transistor, comprise the 3rd bipolar transistor and first field-effect transistor, the collector electrode of the 3rd bipolar transistor is connected in the collector electrode of first bipolar transistor, base stage receives an override signal, and emitter is connected in the drain electrode of this first field-effect transistor, and the source electrode of this first field-effect transistor is connected in second end of resistance, and grid receives an overloading data; One inverter is oppositely exported overloading data; And second the serial connection transistor, comprise the 4th bipolar transistor and second field-effect transistor, the collector electrode of the 4th bipolar transistor is connected in the collector electrode of second bipolar transistor, base stage receives override signal, and emitter is connected in the drain electrode of this second field-effect transistor, and the source electrode of this second field-effect transistor is connected in second end of resistance, and grid receives the dateout of inverter, wherein, the current collection of described the 4th bipolar transistor is first output very, and the current collection of described the 3rd bipolar transistor second output very.
Because the present invention utilizes field-effect transistor directly to receive the setting overloading data, therefore digital overloading data needn't be passed through preposition ECL voltage level conversion treatment.And overloading data can be set earlier and be sent to field-effect transistor, so field-effect transistor can be set conducting earlier or close before heavily loaded control signal action.Therefore, as long as one action of heavily loaded control signal can promote the data heavy duty responsiveness of ECL circuit according to the state of overloading data control output end.
Description of drawings
Fig. 1 is a traditional E CL circuit.
Fig. 2 has the ECL circuit of data heavy duty function for the present invention.
Embodiment
The ECL circuit that has the data heavy duty below with reference to graphic detailed description the present invention.
Fig. 2 has the ECL circuit of data heavy duty function for the present invention.As shown in the drawing, ECL circuit of the present invention comprises a differential emitter coupling bipolar transistor B1, B2, a load resistance is connected in bipolar transistor is connected in the current source Is of resistance R e, a pair of reception overloading data to the resistance R e, of the emitter of B1, B2 field effect transistor M 1, M2 and an inverter INV to R1, R2, a pair of heavy duty control bipolar transistor B3, B4.
The emitter-coupled bipolar transistor is connected in high working voltage VCC to the collector electrode (collector) of B1, B2 via resistance R 1, R2, and base stage (base) then receives differential wave DA, DB respectively.This emitter-coupled bipolar transistor is connected to low-work voltage VEE to the emitter (emitter) of B1, B2 via resistance R e and current source Is.The current collection of bipolar transistor B2 is the output OUTA of this ECL circuit very, and the current collection of the bipolar transistor B1 inverse output terminal OUTB of this ECL circuit very.
The collector electrode of heavy duty control bipolar transistor B3 is connected in the collector electrode of bipolar transistor B1, and base stage receives a heavily loaded control signal RL.And the drain electrode of field effect transistor M 1 (drain) is connected in the emitter of heavy duty control bipolar transistor B3, and grid (gate) receives an overloading data DATA, and source electrode (source) is connected in current source Is.The collector electrode of heavy duty control bipolar transistor B4 is connected in the collector electrode of bipolar transistor B2, and base stage receives heavily loaded control signal RL.And the drain electrode of field effect transistor M 2 is connected in the emitter of heavy duty control bipolar transistor B4, and grid receives via the reverse reverse overloading data of inverter, and source electrode is connected in current source Is.
Because the conducting resistance of field effect transistor M 1 and M2 is much smaller than resistance R e, therefore heavy duty control bipolar transistor B3 is identical with the bipolar transistor TR3 function of traditional E CL circuit (with reference to figure 1) with the combination of field effect transistor M 1, and the bipolar transistor TR4 function of the heavily loaded combination of controlling bipolar transistor B4 and field effect transistor M 2 and traditional E CL circuit (with reference to figure 1) is identical.So, when the equal conducting of heavy duty control bipolar transistor B3 and field effect transistor M 1, output OUTA can be set at H.And when the equal conducting of heavy duty control bipolar transistor B4 and field effect transistor M 2, output OUTA can be set at L.
But because the present invention utilizes field effect transistor M 1 and M2 directly to receive to set overloading data, therefore digital overloading data needn't be passed through preposition ECL voltage level conversion treatment.And overloading data can be set earlier and be sent to field effect transistor M 1 and M2, so field effect transistor M 1 can be set conducting earlier with M2 or close before heavily loaded control signal RL action.So, as long as heavily loaded control signal RL one action can promote data heavy duty responsiveness according to overloading data DATA control output end OUTA and OUTB state.
The below operation of explanation ECL circuit of the present invention.At first, when heavily loaded control signal RL is L, bipolar transistor B3, all not conductings of B4.Therefore, the output of this ECL circuit is controlled by differential wave DA, DB.The action of this part identical with conventional art (with reference to figure 1), no longer repeat specification.
When heavily loaded control signal RL is H, because the equal conducting of bipolar transistor B3, B4.At this moment, if overloading data DATA is H, then field effect transistor M 1 conducting, field effect transistor M 2 not conductings are L so the output OUTA of this ECL circuit is H, OUTB.And if overloading data DATA is L, then field effect transistor M 1 not conducting, field effect transistor M 2 conductings are H so the output OUTA of this ECL circuit is L, OUTB.The operation principle of this part identical with conventional art (with reference to figure 1), no longer repeat specification.
Though more than with embodiment the present invention is described, therefore do not limit scope of the present invention, only otherwise break away from main idea of the present invention, those skilled in the art can carry out various distortion or change.For example, the differential and double bipolar transistor among Fig. 2 to replaceable be different emitter coupled logic frameworks, as " with " (and collection (AND)), latch (breech lock (latch)) etc., be applicable to that still this has the function of data heavy duty.
Claims (4)
1. emitter-coupled logic (ECL) with data heavy duties function comprises:
One differential and double bipolar transistor is right, comprises first bipolar transistor and second bipolar transistor, and the emitter of these two bipolar transistors is connected to each other, and base stage receives a differential wave;
One load resistance is right, comprises first load resistance and second load resistance, and an end is serially connected with the right collector electrode of aforementioned differential and double bipolar transistor respectively, and the other end then is connected in a high working voltage;
One resistance has first end and second end, and this first end is connected in the right emitter of aforementioned differential and double bipolar transistor;
One fixed current source, an end are connected in second end of aforementioned resistance, and the other end is connected in low-work voltage;
The first serial connection transistor, comprise the 3rd bipolar transistor and first field-effect transistor, the collector electrode of the 3rd bipolar transistor is connected in the collector electrode of aforementioned first bipolar transistor, base stage receives an override signal, and emitter is connected in the drain electrode of this first field-effect transistor, and the source electrode of this first field-effect transistor is connected in second end of aforementioned resistance, and grid receives an overloading data;
One inverter is oppositely exported aforementioned overloading data; And
The second serial connection transistor, comprise the 4th bipolar transistor and second field-effect transistor, the collector electrode of the 4th bipolar transistor is connected in the collector electrode of aforementioned second bipolar transistor, base stage receives aforementioned override signal, and emitter is connected in the drain electrode of this second field-effect transistor, and the source electrode of this second field-effect transistor is connected in second end of aforementioned resistance, and grid receives the dateout of aforementioned inverter
Wherein, the current collection of described the 4th bipolar transistor is first output very, and the current collection of described the 3rd bipolar transistor second output very.
2. the emitter-coupled logic (ECL) with data heavy duties function as claimed in claim 1, wherein aforementioned differential and double bipolar transistor to replaceable be different emitter coupled logic frameworks.
3. the emitter-coupled logic (ECL) with data heavy duties function as claimed in claim 2, wherein aforementioned differential and double bipolar transistor to replaceablely be " with " structure.
4. the emitter-coupled logic (ECL) with data heavy duties function as claimed in claim 2, wherein aforementioned differential and double bipolar transistor to replaceable for latching structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN02142231.1A CN1277355C (en) | 2002-08-26 | 2002-08-26 | Emitter-coupled logic circuit with data reload function |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN02142231.1A CN1277355C (en) | 2002-08-26 | 2002-08-26 | Emitter-coupled logic circuit with data reload function |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1479449A CN1479449A (en) | 2004-03-03 |
| CN1277355C true CN1277355C (en) | 2006-09-27 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN02142231.1A Expired - Lifetime CN1277355C (en) | 2002-08-26 | 2002-08-26 | Emitter-coupled logic circuit with data reload function |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101342240B (en) * | 2008-07-17 | 2011-07-20 | 岳泉 | Externally used medical ointment for treating dermatosis, uses, preparation method and apparatus thereof |
| CN103647547A (en) * | 2013-11-27 | 2014-03-19 | 苏州贝克微电子有限公司 | Series-connection gating emitter coupled logic circuit |
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2002
- 2002-08-26 CN CN02142231.1A patent/CN1277355C/en not_active Expired - Lifetime
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| CN1479449A (en) | 2004-03-03 |
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Granted publication date: 20060927 |