CN1269538A - Low-CTE power source and stratum - Google Patents

Abstract

Conductive materials having low coefficients of thermal expansion (CTEs) for power sources and formations are disclosed herein. Fiber materials with low CTE (eg, carbon, graphite, glass, quartz, polyethylene, and liquid crystal polymer fibers) are metallized to provide conductive materials with low CTE. These fibers are metallized in their respective states and then formed into fabrics, or these materials can be formed into fabrics and then metallized, or a combination of both metallizations are used. In addition, graphite or carbon sheets can be metallized on one or both sides to provide materials with low CTE and high conductivity.

Description

Low CTE Power and Formation

This application involves a co-examination patent application filed by Japp et al. on April 26, 1999, serial number 09/300762, entitled "POROUS POWER AND GROUND PLANES FORREDUCED PCB DELAMINATION AND BETTER RELIABLITY", which is hereby incorporated by reference.

This invention relates generally to the field of computer manufacturing, and more particularly to reducing the coefficient of thermal expansion of circuit boards used in computers.

Computers and similar electronic devices are ubiquitous in people's daily lives. Many businesses, banks, and government agencies rely on computers for their daily activities. Most of society as a whole requires computers to be able to perform their economic, social and communication activities reliably and stably. Computers are required to run longer with less downtime today than computers have ever been.

Because computers are so needed, computer designers place greater emphasis on their reliability. Many systems today do not allow for extensive downtime to replace failed components that make up the computer system. If every component is designed to last longer and be more reliable, then every computer built from only those components will live longer and be more reliable.

Reproducibility of component reliability also applies to printed circuit boards (PCBs). Most components in a computer system are designed by placing semiconductor packages containing semiconductor chips on PCBs or by directly placing chips on laminated chip carriers (LCCs) and connecting the LCCs to the PCB. PCBs are called "printed" because the circuit traces or copper wires are laid on the board using a technique originally similar to the newsprint printing process. These circuit lines connect the individual semiconductor packages or the individual chips together. PCBs can be formed simply as insulators with traces printed on one or both sides and one or more packages affixed to one or both sides. However, PCBs are usually becoming more and more complex, generally consisting of conductive metal power and ground planes and several signal layers containing circuit lines sandwiched between several insulating layers, with metal lines and solder on the upper and lower surfaces of the interlayers. plate. The upper and lower conductors are connected to each other and to the internal circuit layers through plated through holes (PTHs).

PCBs manufactured in this way have become standard electronics. Advances in manufacturing methods have made PCBs relatively inexpensive. And their simplicity makes them more reliable. However, there are still problems associated with PCBs. One of the causes of some of these issues is the coefficient of thermal expansion (CTE) of the entire PCB and layers.

Many PCBs, especially LCCs, are generally composed of organic matter and need to have a low CTE that better matches that of silicon chips. When trying to reduce the CTE of a PCB, various low CTE dielectric materials can be used. However, the effectiveness of using these low CTE dielectrics is limited because the power and ground planes that make up the bulk of the PCB are still composed of copper. Copper has a high CTE compared to some low CTE dielectric materials. Due to the higher CTE of copper, the higher amount of copper used, and the high tensile modulus of copper, the circuit board or LCC maintains a high composite CTE.

High CTE power and ground planes cause the overall CTE of the PCB to be similar to the CTE of these metal layers. Due to the relatively high total CTE, the PCB or LCC itself will become longer and larger in size as the temperature rises. The increase in size means that chips, packages, wires and other devices on the surface of PCB or LCC need to expand in the same proportion, or be able to tolerate the stress caused by the mismatch of size. Sometimes these devices or the electrical connections between them cannot withstand these stresses, especially after repeated temperature cycling.

These stresses especially degrade LCCs. The chip is connected to the LCC by small solder bumps called controlled-collapse chip connections (C4). LCCs are generally connected to PCBs through ball grid arrays (BGAs). Sealing and/or undercoating are performed under and around the chip to protect the chip.

Previous chip carriers were almost all composed of ceramics with low CTEs. Low CTE chip carriers do not place as much stress on the chip because the ceramic layers do not expand as much. However, laminated materials are currently used as chip carriers. Laminate materials have higher CTEs as described above, which creates greater stress on the chip connected to the LCC. Unfortunately, since the chip is originally constructed from crack-prone crystalline silicon, this stress will either crack the C4 connection, or the CTE mismatch of the chip/LCC will cause the assembled package to warp, putting tension on the chip, possibly making the Chip cracks.

In addition, metal layers commonly used in PCB manufacturing have higher CTEs that are much higher than some low CTE dielectrics. Due to the difference in CTEs, an increase in temperature causes the metal to elongate at a higher rate than the medium. This difference in expansion creates high stresses on the media, which can cause cracks in the media material. Since the circuit wire will be pulled off, the crack in the medium will cause an open circuit. Another effect caused by the difference in CTE is shear-induced debonding, whereby the dielectric is peeled off from the power/ground plane. Since the stripped dielectric is essentially "suspended" and disconnected from the metallization power/ground plane, the shear-induced stripping exacerbates the CTE-induced cracking mechanism. However, the periphery of the lift-off region is connected to the metallization layer, and tends to move together with the metallization layer when the metallization layer becomes longer with increasing temperature. As the peripheral region moves away from the stripping medium, cracks develop around the peripheral region.

Although low-CTE metals such as iron-nickel alloys, stainless steel, and molybdenum have been used to form the low-CTE power planes of PCBs and LCCs, the use of these alternative metals complicates fabrication. These complexities include galvanic action and erosion, multi-step corrosion, and complex waste handling.

Therefore, there is no way to limit failures and cracks caused by CTE differences between dielectric and power/ground planes, and the higher overall CTE of PCBs and LCCs will continue to cause a large number of failures and reliability problems.

Accordingly, embodiments of the present invention provide conductive materials having low coefficients of thermal expansion (CTEs) useful for power sources and formations. Fiber materials (such as carbon, graphite, glass, and liquid crystal polymers, etc.) are metallized to provide the resulting conductive material with a low CTE. The fibers can be metallized in their individual state and then formed into a fabric, or the materials can be formed into a fabric and then metalized, or a combination of both metallization methods can be used. In addition, graphite layers can be metallized on one or both sides to provide a material with low CTE and high electrical conductivity. These metallized low CTE power and ground planes can then be laminated into composites for printed circuit boards (PCBs) or for PCBs as stacked chip carriers. The present invention can provide conductors for PCBs and LCCs without the problems associated with particular low CTE metals.

The above and other advantages and features of the invention will become apparent from the following more particular description of the preferred embodiments of the invention, as illustrated in the accompanying drawings.

Preferred exemplary embodiments of the present invention will be described below in conjunction with the accompanying drawings, in which like numerals represent like elements:

Fig. 1 is a sectional view of a power supply or a formation according to several preferred embodiments of the present invention;

Fig. 2 is a cross-sectional view of a six-layer printed circuit board according to a preferred embodiment of the present invention and each layer that constitutes a six-layer printed circuit board;

Fig. 3 is a process flow diagram of a method for manufacturing and using a power source or formation according to a preferred embodiment of the present invention;

Fig. 4 is a cross-sectional view of a six-layer printed circuit board and layers constituting the six-layer printed circuit board.

Preferred embodiments of the present invention overcome the limitations of the prior art by providing materials with low coefficients of thermal expansion (CTEs) for power sources and formations. Power and ground planes may form the core, if desired, and are preferably used for printed circuit boards (PCBs), or for PCBs as laminated chip carriers (LCCs). The present invention generally relates to the manufacture of PCBs. A short introduction to general fabrication techniques for PCBs is given below, followed by preferred embodiments.

For the manufacture of printed circuit boards, the starting material is typically a thin sheet of fiberglass and epoxy resin. Since the fibers are impregnated with resin during initial processing, this is commonly referred to as "prepreg". The resin is primarily used as a binder, binding the fibers to the board. Instead of fiberglass cloth, compressed paper or other suitable material may be used. Thus, a substrate is a flat rigid or slightly flexible dielectric material that will be made into the final printed circuit. This starting material can be laminated on both sides of the board with a thin layer of copper or other metal using a suitable adhesive. This combination is commonly referred to as a copper clad laminate (CCL). These CCLs can be made simple double-sided (with copper lines on both sides) or can be circuitized and laminated with additional dielectric to form multilayer composites.

In many cases, small holes are formed through the plates, typically by drilling, to accommodate electrical connections for the various electronic components to be mounted. The small holes are generally drilled by a high-speed drilling machine, and the positions of the small holes are shown in the drawings or depend on the design of the board.

In order to make an electrical connection from one side of the copper stack through the hole to the other side, the plastic walls of the hole must be made conductive. This can be accomplished by chemical processes known in the industry such as metallization, which consists of a relatively complex series of chemical bath treatment, rinsing and activation steps to deposit a thin layer of copper on the hole walls.

Since the copper layer formed by the metallization process is generally too thin to form a suitable bridge between the two layers of the board, copper electroplating is used to deposit a thick layer of copper in the small hole to form a suitable copper cross-section to carry the current. Copper plating can be followed by tin-lead or tin plating to improve solderability.

After metallization, circuit treatments are applied to those surfaces requiring circuit patterns. A circuit pattern is a circuit design where specifications or design needs are applied to the metal surface of a drilled board. Images can be formed by applying an organic photoresist coating as a dry film. Ultraviolet (UV) light is projected onto the photoresist through a mask. The mask contains patterns that block UV light. For negative tone photoresists, the areas of the photoresist that were not exposed to UV light will be removed in a subsequent development step. The exposed surface metal is then removed by chemical etching. Then, the remaining photoresist is stripped, leaving only the metal pattern.

Referring now to FIG. 4, this figure shows an example of a six-layer PCB and the layers that make up the six-layer PCB. In Fig. 4, parts of a PCB are shown at different stages of manufacture. In this example, the six-layer PCB 120 is partially used as a laminated chip carrier (LCC) connecting the chip 160 and the PCB/LCC 120 to the PCB (not shown). The six-layer PCB 120 includes a "compound" formed by pressing together (called "lamination") two signal core layers 101 and 130, a power core layer 111, and dielectric layers 150 and 152. Each core layer is individually patterned and then pressed together to form a composite PCB. During this lamination, the media will flow back into any gaps that exist between the core and media layers. After lamination, the composite is drilled, the epoxy over the exposed drilled copper layer is stripped, the through-holes are plated, and processed. For the sake of simplicity, Figure 4 shows the medium recirculation zone when the replacement medium contains air. Additionally, plated through holes (PTHs) are shown as solid metal, although generally cylindrical metal holes. Finally, the tooling holes that will be used to align the workpiece with the stack and layers are not shown.

The signal core layer 100 includes a dielectric layer 104 sandwiched between two copper layers 102 and 105 . The signal core layer 100 is an unprocessed CCL. Copper layers 102 and 105 are signal carrying layers on which copper lines will be formed. The copper layer 102 may also have pads to which the individual chips or surface mount packages containing the chips are to be soldered. The signal core layer 101 represents the signal core layer 100 after the signal core layer 100 is patterned. Signal core layer 101 includes copper layers 102 and 105 which have been patterned with circuitry, gaps for PTHs and other gaps/machined holes and dielectric layer 104 . Copper layer 102 has two wires (not counted) and two pads 107 and 103, while copper layer 105 has five wires. In addition, the copper layer 105 has a gap region 170 through which the PTH passes after the signal core layer 101 is laminated as a composite, drilled and plated.

The power core layer 110 in FIG. 4 includes a dielectric layer 114 sandwiched between two copper layers 112 and 115 . Copper layers 112 and 115 may be thicker than copper layers 102 and 104 to provide additional current carrying capability. The power core layer 110 is unprocessed CCL. Copper layer 112 will become the power plane of the PCB, and copper layer 115 will become the ground plane of the PCB (and vice versa). The power core layer 111 represents the power core layer 110 after the power core layer 110 has been patterned. The power core layer 111 includes patterned copper layers 112 and 115 and a dielectric layer 114 . Copper layer 112 is patterned with two gap regions 182 and 179 and copper layer 115 is patterned with two gap regions 184 and 180 . These clearance areas will prevent the power and ground planes from coming into contact with the PTHs that are drilled at these locations after the power core layer 111 is laminated into a composite, drilled and plated.

The completed PCB section is shown as a six-layer PCB section 120 . Because it has six conductive layers, this PCB is generally called a "six-layer" board. The PCB portion 120 is being used as an LCC to connect the chip 160 to the underlying metal layer 135 of the PCB (not shown). Attachment (not shown) between layer 135 and PCB 120 is typically accomplished by a grid array (BGA) or similar connection. The six-layer PCB portion 120 is shown after the signal core layers 101 and 130 , the power core layer 111 and the dielectric layers 150 and 152 have been laminated to form a composite. The composite has been drilled and the applied epoxy removed from the holes. The small holes have been plated. In addition, various components are mounted on the completed LCC. For example, the chip 160 has been soldered to the pad 103 of the copper layer 102 of the signal core layer 101 through a controlled collapse chip connection (C4) ball 107 . A seal or underfill 162 protects chip 160 . The signal core layer 130 is a signal core layer patterned similarly to the signal core layer 101 . The signal core layer 130 includes copper layers 132 and 135 and a dielectric layer 134 . Copper layers 132 and 135 have been patterned to form lines. A dielectric layer 150 has been applied between the power layer (copper layer) 112 of the power core layer 111 and the copper layer 105 of the signal core layer 101, and has been applied between the ground layer (copper layer) 115 of the power core layer 111 and the signal core layer 130. A dielectric layer 152 is applied between the copper layers 132. Each dielectric layer 150, 152 may consist of more than one dielectric layer.

Several PTHs are shown in PCB 120. The PTH 109 connects the power layer 112 with the C4 ball 107, the lines on the patterned copper layer 105 and the lines on the patterned copper layer 135. The gap region 180 prevents the PTH 109 from shorting to ground. Note that after lamination, the interstitial region 180 will be filled with reflow medium, but for simplicity, it is not shown in FIG. 4 . PTH 108 connects lines on copper layers 102, 105, 132 and 135, signal lines on copper layer 102 also connect to C4 ball 107. Clearance regions 184 and 182 may prevent PTH 108 from contacting ground plane 115 or power plane 112, respectively. PTH 106 connects ground layer 115 to lines or pads on copper layers 135 , 132 and 102 .

Even with low CTE dielectrics used in layers 104, 150, 114, 152, and 134, the overall coefficient of thermal expansion (CTE) of PCB 120 remains high. A high percentage of copper is maintained which increases the overall CTE. This higher overall CTE can cause problems for both PCBs and PCBs used as LCCs. For the former, PCBs will experience peeling or cracking of the dielectric material due to shear force as the temperature increases, and the high CTE causes the PCB to expand. Since the semiconductor chip disposed on the PCB is located in the package, the package and the connecting pins or leads absorb the stress caused by the increase in size of the PCB. Therefore, the semiconductor chip itself is generally not affected by the increase in PCB size. However, for PCBs used as LCCs, semiconductor chips are directly provided on the PCB without packages and pins or leads. The chip itself bears the stress generated by the increase of the PCB area as the temperature rises.

This can be seen from FIG. 4, where chip 160 is directly connected to metal layer 102 of PCB 120. If the PCB expands with increasing temperature, the expansion caused by the higher CTE moves the C4 ball 107 with the PCB. The C4 balls 107 are directly connected to the chip, and the chip necessarily absorbs the tension caused by the increased spacing between the balls 107 . Unfortunately, semiconductor chips are primarily crystalline silicon. The chip itself is vulnerable to cracking as its structure and balls also move away from the chip.

The present invention overcomes the limitations of the prior art by providing conductive materials with low CTEs for power and ground planes in printed circuits (PCBs) and PCBs as stacked chip carriers (LCCs). By providing low CTE materials for the power and ground planes of PCBs, the overall CTE of the PCB is reduced, which in turn reduces the chances of chip failure, dielectric cracking, and shear-induced delamination. In addition, problems associated with the use of special low-CTE metals (such as battery action and erosion, multi-step corrosion, and complex waste disposal) can be completely eliminated or significantly reduced.

Before discussing the preferred embodiments, it is helpful to briefly discuss terminology. As mentioned in the overview section, the term "prepreg" generally includes fiberglass and epoxy. Because of the impregnation of the fibers with resin during processing, they are often referred to as "prepregs". A resin-containing fibrous material sheet is generally referred to as a "fiber-resin composite", and a fibrous material sheet may be referred to as a "fibrous composite". Unfortunately, when one or more signal layers are stacked with one or more power/ground layers, or when power/ground layers are stacked between prepregs, it is called a "composite". To avoid confusing such composite structures with fiber composites or fiber-resin composites, the fiber composites and fiber-resin composites will be referred to as "fiber laminates". The term 'fiber laminate' is intended to include all types of prepregs, fiber composites, fiber resin composites, dielectrics, insulators and other materials used in PCB manufacturing. Additionally, embodiments of the present invention may use conductive fiber laminates (eg, prepreg impregnated with copper). It should also be noted that although the term "fiber laminate" is used here, the term is intended to refer to all types of thermosetting resins and thermoplastic polymers currently used to construct PCBs, including but not limited to epoxy, bismaleyl Iminotriazine epoxies, cyanide esters, polyimides, polytrifluoroethylene (PTEE) and other fluoropolymers, etc., whether or not they contain any fibers or fillers.

Preferred embodiments of the present invention include a variety of conductive low CTE materials that can be used in power sources and formations. For example, a core layer of solid low CTE material (preferably a carbon-based material such as graphite) metallized on one or both sides may form the basis of the power supply/ground formation. In addition, metallized low CTE fibers such as glass, carbon, and liquid crystal polymer fibers can form fabrics that can serve as the basis for power/ground formations, preferably conductive materials with CTEs typically between -5 and 5 PPM/°C. Materials with CTEs less than 5 PPM/°C are preferred. A power/ground core formed from these preferred materials should have a composite CTE of 8-12 PPM/°C, depending on the fiber layup used. Using these core layers in PCB/LCC can result in a PCB/LCC with a composite CTE of 8-12PPM/°C. The CTE is significantly reduced compared to PCBs constructed from common layers (ie, copper clad laminate (CCL)). Even with low CTE fiber laminates, due to the high CTE of copper and the relatively high percentage (volume or weight) of copper in PCBs, the CTE of ordinary PCBs is generally close to or higher than 17PPM/°C. Therefore, even though PCBs are manufactured with low CTE fiber laminates limited to those fiber laminates with a CTE close to 17PPM/°C, the CTE of the PCB is generally higher than 17PPM/°C. Although embodiments of the present invention can use conductive materials with a CTE higher than 5 PPM/°C, the composite CTE of the resulting PCB is still too high for some applications. The conductive material of the present invention is most beneficial when the semiconductor chip is mounted directly on the LCC. The small difference between the CTE of the chip and the composite CTE of PCBs/LCCs fabricated according to the present invention inhibits chip cracking due to CTE mismatch. Utilizing conductive materials with high CTEs will lead to higher composite CTE of PCB/LCC, which will increase the probability of chip defects and cracks. Specific preferred materials will be discussed after describing preferred methods of making and using low CTE power sources/formations.

Some preferred materials for forming the low CTE power/ground layers of the present invention are relatively brittle during drilling or shipping in PCB or LCC manufacturing. For example, fibrous materials may be more susceptible to damage during drilling than metal foils. Also, since it is not possible to pattern some of these low CTE power and ground planes with photolithography and etch techniques, it is preferable to make some changes to the normal PCB or LCC fabrication steps. Before describing the preferred materials that can be used in low CTE power sources and formations, a discussion of the general steps involved in utilizing and fabricating low CTE power sources/formations from low CTE materials is discussed.

Referring now to Figure 1, this figure shows three preferred configurations for low CTE power sources and formations. Each structure has slightly different processing steps to fabricate and utilize low CTE power or ground planes in a PCB/LCC. The most preferred structure for the low CTE power and ground formation is denoted power/ground core layer 300 . The power/ground core layer 300 includes a low CTE layer 304 sandwiched between two fiber laminates 302,305. Two clearance holes 310 are shown, which have been drilled in the power/ground core 300 to provide the power/ground core 300 to be laminated with another power/ground core and one or several signal cores for Clearance of PTHs. Lamination forms a composite body that is then drilled and metallized to form a PCB or LCC. By laminating the low CTE layer 304 between the two fiber laminates 302 and 305, the fiber laminate provides protection for the low CTE layer during drilling and transport. The fiber stacks 302, 305 may be electrically non-conductive or electrically conductive. In the case of the latter embodiment, the power/ground core layer 300 would be a conductive composite. The power/ground core layer 300 is then stacked between two non-conductive fiber stacks to form a larger "core layer", or the power/ground core layer 300 is combined with other signal layers, power/ground core layers, and non-conductive The fiber stacks are stacked to form a PCB composite. It should be noted that layer 304 may actually have one or more metal layers on both sides adjoining fiber stacks 302,305. These layers are not shown in FIG. 1 .

Figure 1 also shows second and third less preferred configurations for low CTE sources and formations that are more susceptible to drilling and transport damage. The power/ground core layer 320 includes a fiber stack 324 sandwiched between two low CTE layers 322,325. Additionally, the fiber stack 324 may be conductive or non-conductive. The power/ground core layer 320 has been drilled with clearance holes 330 . The power/ground core layer 350 includes a low CTE layer 352 . Similarly, the power/ground core layer 350 has been drilled with clearance holes 360 . These are less preferred power/earth core layer embodiments due to the low CTE layer's susceptibility to drilling and shipping damage. However, there can be minimal or no damage to the low CTE material from which the power supply/formation is made if care is taken during transportation and drilling. Sealing low CTE materials in fiber laminates that are susceptible to shipping or drilling damage reduces the likelihood of damage, so it is preferable to do so.

Each of these core layers can be processed in a slightly different manner. Typically, the power/ground core layer 300 will be laminated after an optional adhesion enhancement process (using chemicals such as silane) has been performed on the low CTE layer 304 . Clearance holes 310 are then typically drilled in the power/earth core layer. Instead of patterning and etching with photoresist at this stage, drilling is used, since fiber stacks and most low CTE fiber materials in general cannot be etched. In addition, in this step, the gap hole 310 may be filled with an insulator/medium. The drilled power/ground core 300 can then be laminated into a composite with another power/ground core and one or several signal cores. Holes are then drilled into the composite and metallized (as PTHs) to form a PCB or LCC. Optionally, the power/ground core layer 350 may be drilled, treated with an adhesion enhancing process, and then laminated with two fiber laminates to form the power/ground core layer 300 . While the power/ground core layer 350 may be mechanically drilled to form clearance holes and machining holes, laser or other less damaging drilling methods are preferred for power/ground layer materials that are susceptible to drilling damage.

In general, the power/ground core layer 320 may be formed by treating the low CTE layers 322, 325 with an adhesion enhancing process (optional). A fiber laminate (conductive or non-conductive) is then laminated between two low CTE layers. Drilling is then typically performed to form clearance (or machined) holes 330 . For power/formation materials susceptible to drilling damage, laser or other less damaging drilling techniques are preferred. An additional advantage of laser drilling in this embodiment is that the two conductive low CTE layers can be patterned with different clearance hole patterns. The gaps are then filled with insulating/dielectric material or holes machined. Then, the power/ground core layer 320 is laminated into a composite with another power/ground core layer and one or several signal layers.

In general, holes can be drilled in the power/ground core layer 350, treated with an optional adhesion enhancing material such as a silane or copper oxide treatment, and then laminated with a two-fiber stack (conductive or non-conductive) to form the core layer 300. Optionally, holes can be drilled in the power/ground core layer 350 and treated with an adhesion layer strengthening step, then laminated with another power/ground core layer, several fiber stacks, and one or several signal core layers Complex. For example, to form a six-layer composite, the layers from the "top" layer to the "bottom" layer of the composite are as follows: signal core (such as signal core 101 of FIG. 4), one or several fiber stacks, power supply /ground core layer 352, one or several fiber stacks, power/ground core layer 352, one or several fiber stack layers, and a second signal core layer (eg, signal core layer 130 in FIG. 4). The composite is then drilled and metallized to form the PCB/LCC.

As mentioned above, it is preferred that the conductive material is used for low CTE power or ground formations that are susceptible to drilling or transportation damage to be formed into the power/earth core layer, wherein the low CTE conductive material is sandwiched or sealed between two fiber stacks . The power or ground core layer formed in this way will support and protect the low CTE layer conductive material during the drilling step. This protection reduces the amount of fibrous material that can be ruptured by the drilling process. Power core layers like power core layer 320 (similar to power core layer 110 of FIG. 4 ) or power core layer 350 could also be fabricated, but drilling and/or shipping would cause some cracking and cracking of the low CTE material . Additionally, loose fibers or carbon materials can contaminate certain processing steps. By sealing the fiber or carbon material and filling the drilled holes with an insulator/media, the fiber material is less likely to contaminate subsequent processing steps.

See Figure 2, which shows several cross-sections of the power and ground core layers and the six-layer PCB/LCC made up of these core layers. Figure 2 is an example showing a power core 1000, a drilled power core 1001, a ground core 1010, a drilled ground core 1011, and a six-layer PCB/LCC 1020 used as an LCC. The power core layer 1000 is formed by subjecting the low CTE power layer 1087 to an adhesion enhancing process and then laminating this layer between two fiber stacks 1002 and 1005 . In this case, the low-CTE power supply layer 1087 is a graphite layer 1004 having metal layers 1097 and 1098 formed on its surface. Then, the power core layer 1000 is drilled to form clearance holes 1082 and 1079 . After applying the photoresist mask, a "standard" CCL power core layer is etched to form an imaged power core layer (ie, power core layer 111 of FIG. 4). Since corrosion is not possible with some low CTE conductive materials or fiber stacks used in power/ground formations, it is preferred to use drilling to form the interstitial holes. The power core layers 1000 and 1001 in this example are mainly low CTE conductive layers sandwiched between two non-conductive fiber laminations.

The core layer 1010 is formed by subjecting the low CTE formations 1012, 1015 (in this case, metallized fiber materials) to an adhesion enhancing process, and then laminating these layers on both sides of a conductive fiber stack. The core layer 1010 is then drilled to form interstitial holes 1084 and 1080 . The core layer 1010 in this example is essentially one conductive layer with three conductive layers (a stack of conductive fibers sandwiched between two layers of low CTE conductive material). Although not shown in FIG. 2 , a dielectric or other insulator may be added to the power core 1001 and the ground core 1011 to fill the interstitial holes in these cores.

Regarding the conductive fiber layer 1014, a better way to form this layer is to add 40% by volume of copper powder to the fiber or fiber/resin layer. During lamination, the copper should be evenly distributed in the fiber layers. Other conductive fillers and other types of layer materials can also be used, but have the advantage of being less expensive and commonly used materials in PCB manufacturing.

After drilling the cores (and adding insulators if desired), the power core 1001 and ground core 1011 are pressed together with the patterned signal cores 101, 130 and fiber stacks 1096, 1095 and 1099 to form a composite. The composite is drilled and metallized to form PTHs. After mounting the components on the PCB/LCC, the illustrated six-layer PCB/LCC part 1020 is obtained. Fiber laminates 1095, 1096 and 1099 are non-conductive dielectric layers used to isolate signal, power and ground core layers. Additionally, these layers adhere the power, ground, and signal core layers together. The power core 1001 has a fiber laminate 1005 that will be used to adhere the power core 1001 and the ground core 1011 . Similarly, the fiber stack 1002 of the power core 1001 may be adhered to the signal core 101 . Typically, however, the fiber layup 1005 (and 1002) will be sufficiently cured, meaning that another fiber layup has to be used to bond the power, ground and signal cores together. Certain fibers, once cured, will not reflow enough to adequately bond with another layer. The layers can be partially cured, allowing some of them to reflow as the core layers are stacked. Additionally, some fiber laminates will reflow multiple times and provide adequate adhesion between the two core layers. In these cases, fibrous layers 1095 and 1096 are not necessary for adhesion. Although these fiber layups are not required for adhesion purposes in these cases, there may be other reasons for utilizing additional fiber layups (such as layer 1095). For example, if better electrical insulation is desired, additional fiber layups can provide such insulation. Note that fiber layup 1099 is generally necessary to provide electrical insulation (in addition to adhesion) and to provide resin filling for interstitial holes 1082 and 1079 between patterned signal layer 132 and metallized fiber layer 1015 .

PTH 1008 is similar to PTH 108 in FIG. 4 , it connects the wires of signal layers 102 and 105 of signal core layer 101 and the wires of signal layers 132 and 135 of signal core layer 130 . Clearance regions 1082 and 1084 prevent the ground and power planes from contacting the TPH. Although the interstitial zones 1082 and 1084 are filled with "air", in practice these zones are typically filled with a dielectric: either after the power supply or the core layer is drilled, or with fiber during layup. A stacked dielectric/insulator fills these regions.

PTH 1009 is similar to PTH 109 of FIG. 4 in that it connects pad 103 (and C4 ball 107) on layer 135 of signal core layer 130 and line to power layer 1001. In this example, the power supply layer 1001 includes a conductive layer 1087 that actually has three conductive layers (graphite layer 1004, two metal layers 1097 and 1098). In this example, all three layers of conductive layer 1087 are in contact with PTH 1099. The gap region 1080 prevents the PTH 1009 from connecting to the core layer 1011. Similarly, the PTH 1006 is similar to the PTH 106 of FIG. 4 , it connects the wires on the layer 102 of the signal core layer 101 and the wires on the layers 135 and 132 of the signal core layer 130 with the ground core layer 1011. The core layer 1011 includes three conductive layers (two low CTE layers 1012 and 1015, and a conductive fiber stack 1014), all of which are connected to the PTH 1006. Gap region 1079 prevents PTH 1006 from connecting to power plane 1087.

In the example of Figure 2, the majority of the fiber layups on each core layer are shown to be thin. For example, fiber stacks 1002 and 1005 are very thin. This is just to show that more layers, thinner or thicker fiber layups can be added if desired, as known to those skilled in the art. The main difference between the six-layer PCB/LCC 1020 of FIG. 2 and the six-layer PCB/LCC 120 of FIG. 4 is that the PCB/LCC 1020 has separate power and ground layers, and these power/ground layers are formed differently Ordinary CCL core layer. The PCB/LCC 1020 also has low CTE power and ground planes including most of the LCC. The signal layers 102, 105, 132, and 135, although with some metal, consist primarily of fiber stacks. Thus, the overall CTE of signal core layers 101 and 130 is close to the CTE of fiber stacks 104 and 134 . If a low CTE media is used in these fiber stacks, the CTE will be very low. In this case, the CTE of the high PCB is essentially generated by the metal layer of the power/ground core layer of the CCL. In this case, the copper in the CCL determines the CTE of the power/ground plane due to the amount of copper in the power and ground planes. This high CTE power/ground core layer will increase the total CTE of the PCB, resulting in possible peeling due to shear force, cracking of the medium or chip, tension on the chip fixed on the PCB (used as LCC), and other adverse effects.

However, formation 1011 in FIG. 2 includes metallized low CTE fiber material. In addition, the power layer 1087 includes a metallized graphite sheet. These layers all contain high amounts of low CTE materials that reduce the overall CTE of the core layer. Therefore, both cores have lower overall CTEs compared to an equivalent CCL core, and these lower overall CTEs reduce the overall CTE of the PCB/LCC. Furthermore, such low CTE core layers can be obtained without alternative metals such as iron-nickel alloys, stainless steel, and molybdenum, which would cause manufacturing complications including battery action and erosion, multi-step corrosion, and complex waste disposal.

FIG. 3 illustrates a preferred method of forming a power or ground core (eg, power core 1000 ) comprising a low CTE conductive material in accordance with the present invention. The method 400 in FIG. 3 is preferably used to form power and ground cores to combine power and ground cores into a composite PCB or LCC. This approach can also be used in the preferred embodiment where a low CTE conductive material is sandwiched between two fiber stacks as the power layer 1000 . This embodiment can better protect the inner low CTE conductive material. In addition, the fiber layup can help "seal" the metal covered fiber material and other loose material, which helps to keep the inner fiber material to the laminate. This is particularly beneficial in the case of carbon materials that may contaminate parts of the PCB/LCC and manufacturing process. Method 400 begins by forming an optional thin metal coating on the low CTE material used (step 410). The metallized fiber material of the present invention is generally sufficient metal to carry the required current; more metal can be formed on the fiber at step 410 if additional current carrying capacity is required.

Additionally, if the preferred low CTE materials of the present invention are not metallized, these materials may also be metallized at this step. For example, if non-metallized carbon fiber tow is used as the low CTE material, the tow can be metallized at step 410 and formed into a woven fabric. Additional metal can then be attached to the fabric at step 410 if desired. In the particular example of power core layer 1000 , both sides of graphite layer 1004 are metallized at step 410 to form power layer 1087 . Briefly, step 410 may be used to metallize unmetallized material and add additional metal to already metallized material. Following the method 400, preferred material types for the power source and formation will be discussed in more detail.

The low CTE material is then optionally treated with an adhesion enhancing chemical process or copper oxide treatment (step 420). A sandwich conductor is then laminated between the two fiber laminates to form a sealed low CTE power or ground core (step 430). In general, low CTE ground/power materials are laminated using standard lamination processes. Alternatively, the fibrous low CTE material may be impregnated with resin using standard infusion processes (step 433). This standard impregnation process essentially seals the fibrous material. The resin-impregnated cloth is then laminated against a release sheet or roughened copper foil. If rough copper foil is used, it can be etched away (step 437) or stripped by drilling (step 440). The release sheet is typically removed prior to drilling (step 435).

These openings are formed in the power/ground core layer (step 440) since fiber stacks generally cannot etch to form the necessary electrical clearance holes (and other openings). Generally, these openings can be formed by drilling clearance hole patterns or machining holes in and through the stack and low CTE layers. Drilling may be performed using mechanical drilling or using a laser or other similar hole forming device. If the rough copper foil was overlaid on the low CTE material (step 435), and was not removed (at step 437), it can now be removed by etching (step 445). At this point, the opening may be refilled with neat resin containing a non-conductive filler or other suitable insulator/medium (step 450). The power/ground core is introduced into the composite, preferably by re-lamination or pressing onto a composite panel structure (step 460). If the holes are not filled at step 450, during the lamination cycle, additional resin flows from the fiber layup and fills the drilled power plane holes. The holes for the PTHs may then be re-drilled and metallized (step 470). After step 470, a PCB/LCC similar to PCB/LCC 1020 will be formed.

Although method 400 is a preferred method for fabricating a PCB/LCC with a low CTE power/ground layer, the steps of method 400 may vary slightly depending on the configuration of the power/ground layer used. For example, two layers of low CTE conductive material may be laminated on top of a fiber stack such as previously shown in power and ground core layer 320 of FIG. 1 . In this example, the processing steps are very similar to those shown for method 400 . For example, steps 410 and 420 of method 400 may be performed, respectively, to add additional metal to the conductive material and enhance adhesion. A fiber laminate (conductive or non-conductive) is then laminated between two low CTE layers. Additionally, a liquid resin impregnation step (step 433 ) may be performed prior to laminating the fiber stack between two low CTE conductive materials. Drilling is then generally performed to form clearance holes or machined holes (step 440). For power/formation materials that are susceptible to drilling damage, laser or other non-damaging drilling methods may preferably be used. An additional advantage of laser drilling in this example is that the two conductive low CTE layers can be patterned with different interstitial hole patterns. At this stage (step 450 ) gaps can be filled with insulating material or holes machined. The power/ground core layer 320 is then laminated into a composite with another power/ground core layer, one or several signal layers, and a non-conductive fiber stack (step 460). The composite is then drilled and metallized to form a PCB/LCC (step 470).

In addition, a power/ground core layer similar to the power/ground core layer 350 of FIG. 1 may also be used to form a power or ground plane. In this example, the processing steps used to form the power source and formation are somewhat different from method 400 . For example, drilling (step 440) may be performed before or after step 410 (if performed). The low CTE conductive layer can then be treated with an optional adhesion enhancing material (step 420 ) and laminated with a two-fiber stack (conductive or non-conductive) to form the core layer 300 of FIG. 1 . In this example, step 450 is generally unnecessary since the lamination process can fill the holes with a fiber lamination. Alternatively, a low CTE conductive layer similar to the power/ground core 350 can be drilled and treated with an adhesion enhancement step (step 420) and then laminated with another power/ground core, several fiber laminations, and One or several signal cores are laminated into a composite (step 460). The composite is then drilled and metallized to form a PCB/LCC (step 470).

Finally, the method 400 is applicable to PCBs of other structures than the six-layer PCB shown in FIG. 2 . By applying the processes of method 400 to a particular number of layers, a greater or fewer number of layers may be formed. For example, (again see FIG. 2 ), if a four-layer PCB is desired, the power core layer 1000 can be stacked on the outer surface of the layer 1002 with the copper stackup. Then drill holes to form the power core layer 1001 . Similarly, a core layer 1010 may be laminated on the outer surface of a layer 1015 with a fiber stack and copper layer. The core layer 1011 is then drilled. The openings formed in the power and ground core layers may be filled with insulators. The two copper stacks can then be patterned, the two power and ground core layers to form a composite. Drill holes and plate PTHs to form a PCB. Alternatively, the drilled power core 1001 and the drilled ground core 1011 may form a composite of layers in the following order: copper layer, optional non-conductive fiber stack, power core 1001, ground core 1011, Non-conductive fiber laminate, and copper layer. The two coppers can then be patterned into the signal layer, and the vias drilled and metallized to form a four-layer PCB.

The manner in which low CTE conductive power sources and formations are fabricated from low CTE materials has now been discussed in a general sense. These approaches and materials can be used with any of the specific low CTE conductive materials discussed below. If there are any additional processing steps that are better employed so that the material can be formed into a power or ground core layer, those steps will be discussed in connection with the power/ground material.

The most preferred embodiment of a power source/formation containing a low CTE material is a graphite or carbon sheet with copper on one or both sides. Graphite is a naturally occurring conductive material composed of carbon. The term "graphite" refers to a characteristic special structure of carbon atoms. Graphite can be naturally occurring or man-made. Although graphite has a somewhat crystalline structure, the electrical conductivity of graphite is mainly anisotropic. Very pure crystalline graphite has excellent electrical and thermal conductivity and negative CTE. Bulk graphite generally has very low electrical and thermal conductivity and has a low positive to negative CTE.

Those skilled in the art will recognize that graphite or carbon sheets suitable as a base material for a power source/formation can be fabricated in a variety of ways. For example, bulk graphite can be sintered or compressed into thin graphite sheets. Graphite flakes can be produced by chemical vapor deposition, which can form extremely ordered pyrolytic graphite. However, the latter tablets are fragile and very expensive. Alternatively, graphite sheets can be formed by winding carbon fibers onto a stem to form a carbon fiber bobbin, removing the stem, flattening the bobbin, and graphitizing the bobbin under high heat. In some cases, this produces a sheet in which the carbon fibers lose all their orientation and shape, which is essentially well crystallized into a purer graphite. These methods of forming graphite/carbon sheets are well known in the art.

The metal is deposited on graphite or carbon flakes, and this composite material has a low CTE. Metals can be deposited on graphite using a variety of methods known to those skilled in the art. For example, metals can be deposited on graphite by sputtering, evaporation or chemical vapor deposition. These metal cladding methods will be described in more detail below. The metallization may be on one or both sides of the graphite sheet, although metallization on both sides of the sheet is preferred because it provides more metal and increases current carrying capability.

The metallized graphite or carbon material can be utilized to form PCBs and PCBs used as LCCs in the manner shown and described above. For example, a power/ground core layer similar to power/ground core layers 300, 320 or 350 can be fabricated using the conductive sheet. The total CTE of the obtained PCBs/LCCs is reduced, which can reduce the peeling caused by shear force and the connection cracks between the chip and C4.

Additional preferred materials for forming low CTE conductive power sources and formations may be referred to as fibrous conductive materials. These preferred additional materials include metalized fabrics (eg liquid crystal polymers), metalized carbon fiber fabrics, metalized fiberglass. Fabrics can also be divided into woven fabrics (fabrics with some regular structure) and irregular paper fabrics. Random paper webs are generally composed of randomly oriented fibers. Random paper fabrics do not have the same fiber structure.

For example, a preferred material for forming a low CTE power source/formation is metallized low CTE organic fibers such as liquid crystal polymers (LCPs). Several companies manufacture LCPs, and some of these fibers have familiar trademarks. Aramid is an LCP made by DuPont, sometimes called KEVLAR. VECTRAN is an LCP manufactured by Heochst-Celanse. These fibers have CTEs of about -5 to 5 parts per million per degree Celsius (PPM°C). In addition, these fibers are thermally stable. Other types of organic fibers suitable for use in the present invention having CTEs similar to those of LCPs include SPECTRA (which is a polyethylene manufactured by AlliedSignal). Woven and random paper fabrics of these materials are commercially available. In addition, metallized products of certain LCPs are already commercially available. For example, ARACON is DuPont's trademark for metallized aramid fibers.

Although some organic fiber materials are commercially available as coated fabrics, metallized organic fiber materials suitable for use as power sources or formations can also be produced by the following procedure. First, an organic fiber material is placed in a processing chamber and held in a slightly stretched and/or flat position. Having the material stretched or flattened ensures that the metal covers the exposed surface evenly. The metal is then deposited on the organic fibrous material. This deposition can be done in several ways including plating, sputtering, evaporation or chemical vapor deposition. If the process requires or is necessary, the organic fiber material can be turned over and more metal deposited. For example, if sputtering is used, metal is typically deposited on only one surface of the fabric. When fabrics can be used in this way, generally more metal is applied to the other side of the fabric to increase the current carrying capacity of the fabric. Alternatively, the rolling method can be used to spray the fabric on both sides at the same time. After sputtering or chemical vapor deposition, more metal can be applied using conventional plating. This additional metal will enhance the current carrying capability of the metal fiber fabric power supply/formation. These processes can also be used to metal coat the carbon or graphite flakes discussed above. In addition, these processes can also be used to coat the other preferred low CTE materials discussed above with metals. Additionally, these techniques can also be used to coat the carbon or graphite flakes discussed above with metals.

Once metallized fiber sheets are formed, these low CTE conductive sheets can be used to make power/ground cores similar to power/ground cores 300 , 320 or 350 . Furthermore, any of the methods described above for manufacturing these core layers and integrating them into a PCB/LCC can be performed.

Another most preferred metallized fiber material suitable for use as a power source or formation for PCBs or LCCs is metallized carbon or graphite fibers. Since carbon or graphite fibers are available as textile yarns and single-ply yarns or tows, it is possible to metallize the fibers in both states. For example, metals can be deposited on carbon or graphite fiber fabrics. Alternatively, deposition may be on carbon or graphite fibers and on carbon or graphite fibers woven into cloth or fabric. Metallized products of carbon and graphite fibers and products already formed into tows or yarns are commercially available. The tow or yarn can be used to weave flat weave fabrics. In addition, irregular sheets of carbon fiber are available. Any carbon fiber with a low CTE (preferably less than 2PPM/°C) can be used in embodiments of the present invention.

As an example, 1K (1000 6 micron fibers per yarn or tow) graphite/carbon fibers can be plated with 50-60 wt% copper. The plated tow can be used to weave flat woven fabrics of 30 x 30 threads per inch. As described in connection with Figure 3, one method of making a power/ground core layer is to treat the fabric with an adhesion enhancing step such as a silane coupling agent or a copper oxide conversion process. The treated fabric is impregnated with resin according to standard impregnation procedures. The resin-impregnated cloth is then laminated to a release sheet or roughened copper foil. If rough copper foil is used, it is generally etched away at this point. Remove the release sheet and drill the section with the clearance hole pattern. In this example, the patterned power layer is then laminated to a composite body and adhered thereto with a fiber laminate. The composite is then drilled and plated in the usual manner. Where the carbon/graphite fabric is drilled, a PTH connection is formed. The fabric is a dense woven fabric and provides a substantially continuous layer to form connections at the location of any drilled holes.

After this process, a power supply layer in which metal-clad carbon fibers account for 60% of the volume can be obtained, and the CTE is about 9PPM/°C. This CTE is already much lower than that of the solid copper layer, which has a CTE of about 17PPM/°C. Using carbon fibers with a CTE of approximately 2PPM/°C, 9PPM/°C can be produced. Even lower CTEs can be obtained using lower CTE graphite fibers. Carbon and graphite fibers have CTEs of about -1.4 PPM/°C to about 2.0 PPM/°C. Such a power/ground plane should have the current carrying capability of about 1 oz of pure copper, but the structure is about 3-4 mils thick, displacing the 1.4 mil thickness of 1 oz of pure copper.

Additionally, carbon fiber and graphite are less reactive than most standard PCB chemistries. So corrosion and other processes are less likely to affect carbon fiber and graphite.

Once metallized fiber sheets are formed, these low CTE conductive sheets can be used to make power/ground cores similar to power/ground cores 300 , 320 or 350 . Furthermore, any of the methods described above for manufacturing these core layers and integrating them into a PCB/LCC can be performed.

Yet another preferred example of a fiber material with a low CTE is metallized glass or quartz fibers. Similar to carbon fibers, yarns or woven sheets of glass and quartz fibers or random paper fibers are already available. Strands of yarn can be metallized and formed into fabrics, or fibers that have been formed into sheets can be metallized. Additional metals can be added to each fabric for additional current carrying capabilities. Metallized products for these fibers are currently not commercially available. To form metallized fibers or fabrics, metallized fibers, or metallized fabrics, can be formed using previous methods. In addition, fiberglass sheets are commercially available in the form of random paper. The flakes can be metallized using the metal deposition methods discussed previously.

Glass comes in many different forms, many of which are formed by adding certain "impurities" to silica. For example, S-glass is a silicon-aluminum-magnesium compound that can or cannot be wound into fibers, and E-glass is a calcium-aluminum-borosilicate (Ca-Al ₂ O ₃ -SiO ₂ ) compound, D-glass is a glass with a low dielectric constant. The CTEs of ordinary glass fibers are about 1-3PPM/°C. For example, E-glass has a CTE of about 2.8PPM/°C, while S-glass has a CTE of about 1.6-2.2PPM/°C.

The CTE of a power/ground core layer formed using copper-clad glass and laminated with resin (eg, method 400) is approximately 12 PPM/°C when the metal-clad glass fiber occupies 60% by volume. This CTE has been significantly reduced from the CTE of the solid copper layer (or PCB made of solid copper layer) of about 17PPM/°C.

Once metallized fiber sheets are formed, these low CTE conductive sheets made of metallized glass fibers can be used to make power/ground cores similar to power/ground cores 300 , 320 or 350 . Furthermore, any of the methods described above for manufacturing these core layers and integrating them into a PCB/LCC can be performed.

It should be noted that the fibrous material used as the power source and formation of the present invention is permeable to water and other solvents. Permeability to water or other solvents reduces debonding of the fiber stack and cathode/anode filamentous growth in PCBs. Such low CTE power/ground planes are discussed in co-pending EN9-98-002 "POROUS POWER AND GROUND PLANES FOR REDUCED PCBDELAMINATION AND BETTER RELIABLITY".

Accordingly, embodiments of the present invention provide low CTE materials that can be used to form power/ground core layers that form the basis of PCBs or PCBs used as LCCs. When forming power/ground planes, these low CTE materials reduce the stress on the PCB/LCC layers and the chips and chip connections mounted thereon. The stress reduction is particularly beneficial for PCBs used as LCCs, since chips are mounted directly on the LCC, which does not tolerate high tension before cracking. Embodiments of the fibrous material of the present invention have the added advantage of being permeable to water or other solvents.

Although copper is primarily discussed as the metallization metal, those skilled in the art will recognize that the techniques used to deposit copper can also be used to deposit silver, gold, aluminum, tin, and the like. Furthermore, even when copper is used as the base metal for metallization, additional amounts of other metals may be added during certain processing steps. For example, some manufacturers will add a small amount of gold during processing to enhance the conductivity of the base connection.

Claims (34)

1. power supply/ground sandwich layer that is used for printed circuit board (PCB), this power supply/ground sandwich layer comprises:

At least one deck superimposed fiber; And

At least layer of conductive material, the thermal expansivity of said conductive material (CTE) is lower than the CTE of copper layer.

2. according to the power supply/ground sandwich layer of claim 1, wherein layer of conductive material is a two layers of conductive material at least, and one deck superimposed fiber is clipped between this two layers of conductive material at least.

3. according to the power supply/ground sandwich layer of claim 1, wherein one deck superimposed fiber is two-layer superimposed fiber at least, and layer of conductive material is clipped between this two-layer superimposed fiber at least.

4. according to the power supply/ground sandwich layer of claim 1, wherein one deck superimposed fiber is nonconducting at least.

5. according to the power supply/ground sandwich layer of claim 1, wherein one deck superimposed fiber conducts electricity at least.

6. according to the power supply/ground sandwich layer of claim 1, wherein the CTE of conductive material is less than 5PPM/ ℃.

7. according to the power supply/ground sandwich layer of claim 1, wherein conductive material comprises metallization carbon or graphite flake.

8. according to the power supply/ground sandwich layer of claim 1, wherein conductive material comprises the metallization fibrous material that is woven into fabric or forms irregular paper cloth.

9. power supply according to Claim 8/ground sandwich layer, wherein fibrous material is selected from mainly in the group that is made of carbon fiber, graphite fiber, liquid crystal polymer fibre, polyethylene fibre, quartz fibre and glass fibre.

10. according to the power supply/ground sandwich layer of claim 1, wherein one deck superimposed fiber is selected from mainly in the group by epoxy, Bismaleimide Triazine epoxy, cyaniding ester, polyimide, poly-trifluoro-ethylene (PTEE) and fluoropolymer formation at least.

11. a printed circuit board (PCB) (PCB), this PCB comprises:

At least one signal sandwich layer, each signal sandwich layer comprise at least one signals layer and at least one superimposed fiber; And

At least one power supply/ground sandwich layer, this sandwich layer comprises:

At least one deck superimposed fiber; And

At least layer of conductive material, the thermal expansivity of said conductive material (CTE) is lower than the CTE of copper layer.

12. according to the PCB of claim 11, wherein layer of conductive material is a two layers of conductive material at least, wherein the superimposed fiber of one deck at least of at least one power supply/ground sandwich layer is clipped between this two layers of conductive material.

13. according to the PCB of claim 11, wherein the superimposed fiber of one deck at least of at least one power supply/ground sandwich layer is two-layer superimposed fiber, layer of conductive material is clipped between this two-layer superimposed fiber at least.

14. according to the PCB of claim 11, wherein the superimposed fiber of one deck at least of at least one power supply/ground sandwich layer is nonconducting.

15. according to the PCB of claim 11, wherein the superimposed fiber of one deck at least of at least one power supply/ground sandwich layer conducts electricity.

16. according to the PCB of claim 11, wherein the CTE of conductive material is less than 5PPM/ ℃.

17. according to the PCB of claim 11, wherein conductive material comprises metallization carbon or graphite flake.

18. according to the PCB of claim 11, wherein conductive material comprises the metallization fibrous material that is woven into fabric or forms irregular paper cloth.

19. according to the PCB of claim 18, wherein fibrous material is selected from mainly in the group that is made of carbon fiber, graphite fiber, liquid crystal polymer fibre, polyethylene fibre, quartz fibre and glass fibre.

20. according to the PCB of claim 11, wherein one deck superimposed fiber is selected from mainly in the group by epoxy, Bismaleimide Triazine epoxy, cyaniding ester, polyimide, poly-trifluoro-ethylene (PTEE) and fluoropolymer formation at least.

21. a method of making printed circuit board (PCB) (PCB), this method may further comprise the steps:

A) provide one to comprise the power/ground layer of layer of conductive material at least at least, the CTE of said conductive material is lower than the CTE of copper layer;

B) at least one power/ground layer, form a plurality of openings;

C) form complex with at least one power/ground layer and at least one signals layer;

D) in complex, form a plurality of openings; And

E) in complex, form a plurality of plating coating ventilating holes.

22., wherein provide the step of at least one power/ground layer also to comprise to be formed up to a rare superimposed fiber and the step of the power supply/ground sandwich layer of the low CTE conductive material of one deck at least according to the method for claim 21.

23. according to the method for claim 22, wherein at least one superimposed fiber of power supply/ground sandwich layer is selected from mainly in the group by epoxy, two 3 maleimide triazine epoxies, cyaniding ester, polyimide, poly-trifluoro-ethylene (PTEE) and fluoropolymer formation.

24. according to the method for claim 22, wherein layer of conductive material is a two layers of conductive material at least, the step that wherein forms power supply/ground sandwich layer is included in and sandwiches at least one superimposed fiber between two layers of conductive material.

25. according to the method for claim 24, the step that wherein sandwiches at least one superimposed fiber between two layers of conductive material comprises utilizes impregnation technology to seal layer of conductive material at least, and the step of stacked sealing conductive material and releasing piece or coarse Copper Foil.

26. according to the method for claim 22, wherein one deck superimposed fiber is two-layer superimposed fiber at least, the step that wherein forms source/ground sandwich layer is included in and sandwiches layer of conductive material at least between two superimposed fibers.

27. according to the method for claim 22, wherein one deck superimposed fiber is nonconducting at least.

28. according to the method for claim 22, wherein one deck superimposed fiber conducts electricity at least.

29., also comprise step with additional metal coating electrically conductive material according to the method for claim 21.

30., also comprise the step of low CTE conductive material being carried out the adhesiveness enhanced process according to the method for claim 21.

31. according to the method for claim 30, wherein adhering to strengthening process is that cupric oxide is handled or silane treatment.

32. according to the method for claim 21, wherein low CTE conductive material comprises metallized carbon or graphite flake.

33. according to the method for claim 21, wherein conductive material comprises the metallization fibrous material that is woven into fabric or forms irregular paper cloth.

34. according to the method for claim 33, wherein fibrous material is selected from mainly in the group that is made of carbon fiber, graphite fiber, liquid crystal polymer, polyethylene fibre, quartz fibre and glass fibre.

Images