CN1260799C - Semiconductor multi-die testing system and method with expandable channel - Google Patents

Abstract

The invention relates to a semiconductor multi-tube core test system and method capable of expanding channels, which is used for testing a plurality of pins to be tested of at least one tube core to be tested or testing a plurality of tube cores to be tested, and the system comprises: a test handler, a test device and a multiplexer; the test processor has a plurality of test channels with the total number less than the pins to be tested, and reads the test results of the pins to be tested through the test channels, the test module tests the die to be tested to generate the test results of the pins to be tested, and the multiplexer switches and receives the test results in sequence to output the test results to the test channels in turn; the invention can improve the testing speed.

Description

Semiconductor multi-die testing system and method with expandable channel

The present invention relates to a semiconductor multi-die testing system and method, in particular to a semiconductor multi-die testing system and method with expandable channels, using the limited test channel (channel) in the test processor for pinning (pin) Testing of multiple dies whose total exceeds the number of channels.

FIG. 1 shows a block diagram of a conventional semiconductor multi-die test system. The system includes a test handler 1 (Handler/Prober), a test device 2 and an interface device 3 .

The test handler 1 includes a receiving device 13 , and a wafer (not shown) is placed in the receiving device 13 to test a die 11 to be tested on the wafer. The die 11 to be tested has eight pins P1-P8 to be tested. The display 14 respectively acquires and displays the test results of each pin P1-P8 from the eight test channels 15a-15h.

The testing device 2 includes a testing module 21 and a testing machine 22 opposite to the die 11 to be tested. When performing a digital test (such as embedded memory (embedded memory) test), the tester 22 controls the test module 21 to send a group of test signals to the pins P1-P8 of the die 11 to be tested via the signal line L1, and the test results It is also sent back through the signal line L1 and then transferred to the testing machine 22 through the testing module 21 . While performing the analog test, the testing machine 22 skips the testing module 21 and directly tests the die 11 to be tested.

The test machine 22 sends the test results to the interface device 3 via the signal line L2, and then sends the test results back to the test channels 15a-15h of the test processor 1 via the signal line L3 after the signal connector is converted by the interface device 3.

Utilize above-mentioned traditional semiconductor multi-die test system to carry out the test procedure of die as follows:

As shown in FIG. 2 , firstly, in step 21 , an analog test is performed on the first die to be tested selected on the wafer, that is, to test the analog properties of the pins to be tested, such as voltage value, current value, and the like.

Then, in step 22, perform a digital test on the die to be tested, that is, to test the logic operation function of the pin to be tested, such as outputting a digital signal representing a specific value, here it can be to test the embedded memory (embedded memory) .

Furthermore, in step 23, if there is still a second die to be tested on the wafer, then continue to repeat the above steps 21 and 22 for the second die to be tested; otherwise, end the test.

From the description of the traditional semiconductor multi-die testing system and method above, it can be known that when a group of test channels is used to test a plurality of dies, if the total number of dies is greater than the test capacity of the group of test channels, or all When the total number of core pins to be tested is greater than the total number of test pins that can be provided by the group of test channels, all the cores must use the channels in turn to test one by one due to insufficient test channels, and the test time spent will vary with The increase of the number of dies to be tested increases, which is very time-consuming.

In addition, since the time spent on digital testing accounts for more than 95% of the total testing time during die testing, if the time required for digital testing can be shortened, the total testing time will be effectively reduced.

Therefore, in order to overcome the deficiencies of the above-mentioned prior art, the present invention provides a semiconductor multi-die testing system and method with expandable channels. When performing digital testing, multiple testing modules can be tested simultaneously and the test results The test channels are input sequentially, so that a quick test can be performed when the total number of pins to be tested is greater than the number of test channels.

An object of the present invention is to provide a semiconductor multi-die test system with expandable channels, which is used for testing a plurality of test pins of at least one test die.

The technical solution is: the system includes: a test processor, a test device and a multiplexer. Wherein, the test processor has a plurality of test channels whose total number is less than the pins to be tested, and reads the test results of the pins to be tested through the test channels. The test module tests the die to be tested to generate test results of the pins to be tested. The multiplexer switches and receives the test results sequentially, so that the test results are output to the test channel in turn.

Another object of the present invention is to provide a semiconductor multi-die test system with expandable channels for testing multiple dies to be tested.

The technical solution is: the system includes: a test processor, a test device and a multiplexer. Wherein, the test processor has a group of test channels, through which a group of test results of each die to be tested is read one by one. The testing device tests each die under test to generate a set of test results for each die under test. The multiplexer receives each set of test results sequentially and outputs each set of test results to the test channel in turn.

Yet another object of the present invention is to provide a semiconductor multi-die testing method, which uses a test processor with a set of test channels and a plurality of test modules to test a plurality of dies to be tested.

The technical solution is: wherein each test module tests each die to be tested and generates a set of test results respectively, and the test processor reads a set of test results of each die to be tested through a test channel. The method includes the following steps: firstly, make the test modules test the dies to be tested at the same time, so that each group of test results can be generated at the same time. Then, make the test handler use the group of test channels in turn to read each group of test results one by one.

From the above description of the purpose and technical solutions of the present invention, it can be seen that the semiconductor multi-die testing system and method with expandable channels of the present invention can be used to test a plurality of pins under test of at least one die under test, and can test multiple pins at the same time. cores to be tested. The above-mentioned semiconductor multi-die testing method does not allow the test time to increase due to the increase of the die, and because the digital test time is increased due to the fact that multiple dies are simultaneously carried out and then the test results are read sequentially when performing the digital test. It accounts for more than 95% of the total test time, so it also effectively reduces the total required test time, so that the present invention achieves the effect of improving the test speed.

Following is the accompanying drawing of the present invention:

1 is a block diagram of a conventional semiconductor multi-die testing system;

Fig. 2 is a flowchart of a traditional semiconductor multi-die testing method:

FIG. 3 shows a block diagram of a semiconductor multi-die test system with expandable channels in an embodiment of the present invention;

FIG. 4 shows a flowchart of a semiconductor multi-die testing method according to an embodiment of the invention.

Explanation of component symbols in the figure:

1 Test processor 11, 11a-11c die to be tested

13 Receiving device 14 Display

15a-15h test channel L1-L3 signal line

21. 21a-21c test module 22 test machine

3 interface device 4 multiplexer

p1-p8 pins to be tested

Below in conjunction with accompanying drawing, the present invention is described in further detail:

FIG. 3 shows a block diagram of the semiconductor multi-die testing system of the present invention, and the same or similar symbols are used for the same components in FIG. 3 as in FIG. 1 . The system includes a test processor 1 , a test device 2 , an interface device 3 and a multiplexer 4 .

The test handler 1 includes a receiving device 13, and a wafer (not shown) is placed in the receiving device 13. There are three dies 11a, 11b, 11c to be tested on the wafer to be tested. Each of the dies 11a, 11b, and 11c to be tested has eight pins p1-p8 to be tested. The display 14 respectively acquires and displays the test results of each pin p1-p8 from the eight test channels 15a-15h.

The testing device 2 includes testing modules 21 a , 21 b , 21 c and a testing machine 22 opposite to the dies 11 a , 11 b , 11 c to be tested. The biggest difference between the semiconductor multi-die testing system of the present invention in Fig. 3 and the traditional semiconductor multi-die testing system in Fig. 1 is that a multiplexer 4 is added between the test module and the testing machine so that the system can be used A set of test channels 15a-15h (the test capacity of which is only one die) cooperates with three test modules 21a, 21b, 21c to test the three dies 11a, 11b, 11c to be tested. The function of the multiplexer 4 is to sequentially switch and output the test results generated by the test modules 21a, 21b, and 21c to the testing machine 22, so that the testing machine 22 only accepts one set of test results at the same time. Therefore, when performing a digital test (such as an embedded memory test), due to the existence of the multiplexer 4, the tester 22 can make the test modules 21a, 21b, and 21c simultaneously send out a set of tests via the signal lines L1a, L1b, and L1c respectively. The signals are sent to the under-test pins p1 - p8 of the under-test dies 11 a , 11 b , 11 c to retrieve the test results at the same time, and then output them to the testing machine 22 sequentially through the switching of the multiplexer 4 . When performing the analog test, the tester 22 skips the test modules 21a, 21b, 21c and the multiplexer 4 and directly tests the dies 11a, 11b, 11c to be tested in a turn-by-turn manner.

The test machine 22 sends the test results to the interface device 3 via the signal line L2, and then sends the test results back to the test channels 15a-15h of the test processor 1 via the signal line L3 after the signal connector is converted by the interface device 3.

The test steps that the above-mentioned semiconductor multi-die test system of the present invention carries out are as follows:

As shown in FIG. 4 , in step 41 , an analog test is first performed on the eight test pins p1 - p8 of 11 a , that is, to test the analog properties of the test pins p1 - p8 , such as voltage value, current value and so on.

Next, in step 42 , if there are still dies on the wafer that have not completed the analog test, continue to repeat step 41 for the next die to be tested ( 11b or 11c ).

In step 43, the digital test is performed on the eight test pins p1-p8 of the three test cores 11a, 11b, 11c at the same time, that is, to test the logical operation functions of the test pins p1-p8, such as the output represents a specific A digital signal of a value, which can be used for testing embedded memory.

Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any changes and modifications made by those skilled in the art without departing from the spirit and scope of the present invention should be made within the scope of the present invention. within the protection scope of the present invention.

Claims (10)

1, in order to the multiple semiconductor die testing system of a kind of extendible channel of the plural pin to be measured of testing at least one tube core to be measured, it is characterized in that: this system comprises:

Has the test handler that sum is less than the plural testing channel of those pins to be measured and is read the test result of those pins to be measured by those testing channels;

This tube core to be measured is tested and produced a testing apparatus of the test result of those pins to be measured, and wherein this testing apparatus comprises that many groups send a test signal into those pins to be measured and read the test module of the test result of those pin feedbacks to be measured;

Switch in regular turn and receive those test results and make those test results export a multiplexer of those testing channels in turn to.

2. the multiple semiconductor die testing system of extendible channel as claimed in claim 1 is characterized in that: wherein this testing apparatus comprises a test machine in order to the action of controlling this test module.

3. the multiple semiconductor die testing system of extendible channel as claimed in claim 2 is characterized in that: wherein this multiplexer is connected between those test modules and this test machine.

4. in order to the multiple semiconductor die testing system of a kind of extendible channel of testing plural tube core to be measured, it is characterized in that: this system comprises:

Have one group of testing channel and read a test handler of one group of test result of each tube core to be measured via this group testing channel one by one;

Each tube core to be measured is tested and produced a testing apparatus of one group of test result of each tube core to be measured, and wherein this testing apparatus comprises a plurality of test modules that each test module is sent into a test signal each tube core to be measured and read the test result of each tube core feedback to be measured;

Receive each group test result in regular turn in turn and each is organized the multiplexer that test result exports this group testing channel in turn to.

5. the multiple semiconductor die testing system of extendible channel as claimed in claim 4 is characterized in that: wherein this testing apparatus comprises in order to control a test machine of those test modules actions.

6. the multiple semiconductor die testing system of extendible channel as claimed in claim 5 is characterized in that: wherein this test machine makes those test modules simultaneously this test signal be sent into each tube core to be measured and read the test result of each tube core feedback to be measured simultaneously.

7. the multiple semiconductor die testing system of extendible channel as claimed in claim 5 is characterized in that: wherein this multiplexer is connected between those test modules and this test machine.

8. multiple semiconductor die method of testing, it is characterized in that: it uses a test handler with one group of testing channel to cooperate plural number test module that plural number tube core to be measured is tested, wherein each test module is tested each tube core to be measured and is produced one group of test result respectively, this test handler reads one group of test result of each tube core to be measured via this group testing channel, and this method may further comprise the steps:

Make those test modules simultaneously those tube cores to be measured be tested, make each group test result in producing with the time;

Make this test handler use this group testing channel to read each group test result one by one in turn.

9. the multiple semiconductor die method of testing of extendible channel as claimed in claim 8, wherein this test handler carries out the numerical digit test to those tube cores to be measured.

10. the multiple semiconductor die method of testing of extendible channel as claimed in claim 9 wherein also comprises:

A category that one by one those tube cores to be measured is carried out analogy test and produce each tube core to be measured compares test result; And

This test handler when producing than test result, is read via this group testing channel each category.