CN1231064A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- CN1231064A CN1231064A CN97198006A CN97198006A CN1231064A CN 1231064 A CN1231064 A CN 1231064A CN 97198006 A CN97198006 A CN 97198006A CN 97198006 A CN97198006 A CN 97198006A CN 1231064 A CN1231064 A CN 1231064A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 76
- 238000004519 manufacturing process Methods 0.000 title claims description 47
- 239000000758 substrate Substances 0.000 claims abstract description 112
- 238000002955 isolation Methods 0.000 claims abstract description 43
- 238000007254 oxidation reaction Methods 0.000 claims description 127
- 230000003647 oxidation Effects 0.000 claims description 126
- 230000015572 biosynthetic process Effects 0.000 claims description 31
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 10
- 230000001590 oxidative effect Effects 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 5
- 238000007796 conventional method Methods 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 166
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 62
- 229910052710 silicon Inorganic materials 0.000 description 60
- 239000010703 silicon Substances 0.000 description 60
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 34
- 229920005591 polysilicon Polymers 0.000 description 34
- 238000009413 insulation Methods 0.000 description 31
- 239000012528 membrane Substances 0.000 description 28
- 238000000034 method Methods 0.000 description 20
- 229910052581 Si3N4 Inorganic materials 0.000 description 19
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 19
- 239000000463 material Substances 0.000 description 18
- 239000010410 layer Substances 0.000 description 16
- 230000007797 corrosion Effects 0.000 description 15
- 238000005260 corrosion Methods 0.000 description 15
- 238000005516 engineering process Methods 0.000 description 12
- 238000010276 construction Methods 0.000 description 11
- 229920002120 photoresistant polymer Polymers 0.000 description 11
- 210000003323 beak Anatomy 0.000 description 9
- 238000010586 diagram Methods 0.000 description 9
- 239000013078 crystal Substances 0.000 description 8
- 230000008569 process Effects 0.000 description 7
- 230000008878 coupling Effects 0.000 description 6
- 238000010168 coupling process Methods 0.000 description 6
- 238000005859 coupling reaction Methods 0.000 description 6
- 239000003963 antioxidant agent Substances 0.000 description 5
- 230000003078 antioxidant effect Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 5
- 230000001154 acute effect Effects 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 239000012141 concentrate Substances 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 4
- 238000007639 printing Methods 0.000 description 4
- 239000002253 acid Substances 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- 230000002829 reductive effect Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 230000000452 restraining effect Effects 0.000 description 2
- 230000000717 retained effect Effects 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000006399 behavior Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000003292 diminished effect Effects 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000006213 oxygenation reaction Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000009257 reactivity Effects 0.000 description 1
- SBEQWOXEGHQIMW-UHFFFAOYSA-N silicon Chemical compound [Si].[Si] SBEQWOXEGHQIMW-UHFFFAOYSA-N 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
- H01L21/76235—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls trench shape altered by a local oxidation of silicon process step, e.g. trench corner rounding by LOCOS
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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Abstract
在具有沟槽隔离结构的半导体器件中,在用常规方法选择氧化沟槽结构之后,再次氧化衬底的整个表面,同时只有衬底或沟槽表面的氧化膜暴露出来,并给沟槽上端部附近的氧化膜的形状提供曲率半径。
In a semiconductor device with a trench isolation structure, after the trench structure is selectively oxidized by a conventional method, the entire surface of the substrate is oxidized again, and only the oxide film on the surface of the substrate or the trench is exposed, and the upper end of the trench is exposed. The shape of the nearby oxide film provides the radius of curvature.
Description
The present invention relates to have the semiconductor device and the manufacture method thereof of the groove isolation construction of high reliability.
LOCOS (localized oxidation of silicon) structure is known as the structure that is used for the adjacent devices on electric insulation and the isolation of semiconductor substrate.This structure forms thick heat oxide film with the selective oxidation substrate surface and forms, and uses in various semiconductor device.But because this LOCOS structural manufacturing process precision is low, so it is not suitable for the insulation/isolation structure of highly integrated semiconductor device, deep-submicron device for example wherein needs to be used for the high technology dimensional accuracy of heat oxide film.Therefore, by forming shallow trench at substrate surface, the what is called " groove isolation construction " that selective oxidation trench portions then forms with the selective oxidation method that forms heat oxide film, replaced the LOCOS structure to be carried out the insulation/isolation structure of application as semiconductor device, this semiconductor device needs high integration, for example described in the JP-A-63-143835 like that.
Compare with the LOCOS structure, the advantage of this groove isolation construction is to form the device isolation oxide-film with less planar dimension.For this reason, this method is applicable to that manufacturing need be equal to or less than the deep-submicron device of the process precision of 0.5 μ m.
When the surface of silicon of using oxidation as Semiconductor substrate forms the silicon thermal oxidation film, for example, can produce great machinery stress at the heat oxide film and the near interface between the silicon substrate that form like this.This is because changing heat oxide film (SiO into
2) the oxidized and volume of time part silicon substrate (Si) about twice that can expand.When this mechanical stress increased, the reliability decrease of crystal defect such as for example displacement and lamination mistake and semiconductor device may take place.And clear, oxidation reaction itself (dispersal behavior of oxidation material, the reactivity on the oxygenation level, etc.) stress of the oxide-film of being grown and the influence of change of shape.Because stress is concentrated the end points (angle point) that is created in bidimensional or 3D shape, must pay special attention to the crystal defect and the change of shape of region of stress concentration.
Figure 1A-1D is the technology with conventional selective oxidation manufactured groove isolation construction.According to the described conventional method of Figure 1A, at first prevent film 3 in silicon substrate 1 surface deposition oxidation by liner oxide film (silicon thermal oxidation film) 2, then, prevent that in the oxidation that will form device isolation oxide-film zone film 3, liner oxide film 2 and silicon substrate 1 from partly being removed, thereby form groove (Figure 1B), the oxidation ditch rooved face forms silicon thermal oxidation film 5.
Then, form gate oxidation films 6, grid 7, interlayer dielectric 8, buried insulation film 9, ground floor wiring 10 and second layer interlayer dielectric 11 successively.
In this groove isolation construction, end points (angle point) is positioned near the groove upper end or groove bottom of substrate substantially.Therefore, owing to making region of stress concentration, thermal oxidation is formed near the end points (angle point).Because formed this region of stress concentration, so the shape of substrate, near the groove upper part, oxidized in some cases acutangulate pointed shape 4 is shown in Fig. 1 C especially.Form after the device isolation oxide-film, form electronic circuit in the device isolation regions with protective oxide layer 3 coverings, for example transistor, capacitor etc. are shown in Fig. 1 D.If but this acute angle portion 4 remains on substrate surface, then electric field is concentrated in this part in the circuit working process, and the breakdown voltage characteristics of the transistor of forming circuit and electric capacity etc. is descended, as at A.Bryant etc. at " TechnicalDigest of IEDM'94 ", pointed among the PP.671-674.
In having the semiconductor device of groove isolation construction, the present invention aims to provide semiconductor device and makes the method for this semiconductor device, can not cause that the transistor of forming circuit and the breakdown voltage characteristics of electric capacity descend, and have high reliability.
Above-mentioned purpose can realize by preventing that substrate shape becomes acute angle near the upper end of the device isolation groove on the semiconductor substrate surface.
Be used to realize that the method for above-mentioned purpose manufacturing semiconductor device may further comprise the steps.
(1) form at the circuit of Semiconductor substrate and form the step that oxidation prevents film on the surface:
Silicon substrates etc. can be used as Semiconductor substrate.
Oxidation prevents that the thickness of film from must so select: all oxidations prevent that film is all not oxidized in the oxidation step of the step (4) of back, (7) etc.
Polysilicon membrane, silicon nitride film etc. can prevent film as oxidation.Since easily the material of oxidation for example polysilicon membrane to having low restraining force from the volumetric expansion of the silicon oxide layer of the new growth of silicon substrate, so reduced the stress that concentrates on the groove upper end with oxidation.For example silicon nitride film amount of oxidation in oxidation technology is little owing to dysoxidizable material, has therefore reduced thickness.
Can also before preventing film, the formation oxidation on silicon substrate, form liner oxide film effectively.If there is liner oxide film, the oxidation that contacts with liner oxide film prevents near the upper end of the lower end of film and Semiconductor substrate part successively from the groove ends oxidation, and the contact portion between liner oxide film and Semiconductor substrate forms so-called " beak ".As a result, near the radius of curvature in bight, Semiconductor substrate upper end is increased.
(2) form the step that forms groove on the surperficial desired position at the Semiconductor substrate circuit with desired depth:
This groove can form with the ordinary flat printing process of for example using photoresist and corrosion.
(3) remove the step that forms the bight that lip-deep groove forms by the Semiconductor substrate circuit:
Not necessarily must carry out this step, if but remove the bight with this step, then in most of the cases just do not need the oxidation step of back (7).
(4) oxidation is formed on the step of the trench portions in the Semiconductor substrate:
Trench portions is several to tens nm and oxidized by oxidation.Because this oxidation,, and form radius of curvature in the bight in the groove upper end at trench portions growth beak.
(5) the buried insulation film is buried step in the oxidation groove into:
Preferably, the material that is used as the buried insulation film mainly is an insulating material, and has low-k.Has high dielectric constant materials if use, when the coupling capacitance that forms during the deposit wiring material in the step of back becomes big on this dielectric film.From then on find out in the scheme that silicon oxide layer etc. are preferably burying material, polysilicon etc. are not best.
(6) remove and be formed on the step that oxidation prevents the buried insulation film on the film:
Return corrosion buried insulation film with chemico-mechanical polishing (CMP) or dry etching.In this case, oxidation prevents that film is used as the corrosion stopper film, and prevents that in addition corrosion oxidation from preventing the function of the Semiconductor substrate below the film.
(7) remove be formed on oxidation prevent buried insulation film on the film after the step of oxide-semiconductor substrate:
This step grows into the radius of curvature of the groove upper end of Semiconductor substrate the enough radius of curvature that are used to prevent the leakage current increase.This oxidation step also has the effect that makes the buried insulation film close.
The increase of the leakage current that oxidation step (4) produces if the radius of curvature in the groove upper end of Semiconductor substrate has been enough to prevent has not just needed this step.
This step can be carried out before in step (6) or next step (8).When next step (8) carries out this step afterwards, semiconductor substrate surface is simultaneously also oxidized, but the oxide-film that is formed on the semiconductor substrate surface is removed after finishing additional oxidation, in this way, has just finished the formation step of device isolation oxide-film.
(8) remove and be formed on the Semiconductor substrate circuit and form the step that lip-deep oxidation prevents film:
The formation step of device isolation oxide-film is finished with this step.Therefore, by on the Semiconductor substrate that forms the device isolation oxide-film, forming for example transistor of circuit, form semiconductor device.
Be used to realize that the semiconductor device of the present invention of above-mentioned purpose is to have to be formed on the semiconductor device that the Semiconductor substrate circuit forms lip-deep device isolation oxide-film, and be groove isolation construction, wherein form angle θ between the side surface of surface and Semiconductor substrate at the circuit of Semiconductor substrate in ° scope of 90 °＜θ＜180 at the depth direction of the groove that constitutes groove isolation construction.Because this structure can prevent to concentrate on the groove upper end, thus can prevent since be formed on the Semiconductor substrate circuit for example the voltage endurance of transistor and the electric capacity leakage current that causes that descends increase.
By for example can reducing the coupling capacitance that is formed on the wiring on the Semiconductor substrate in the Si oxide inside of burying groove, and can further improve the reliability of semiconductor device with the insulating material of low-k.
Figure 1A, 1B, 1C and 1D are schematic diagrames, represent to make according to the selective oxidation method of prior art the technology of groove isolation construction respectively;
Fig. 2 A-2N is a schematic diagram, and each expression is according to the manufacturing process of first embodiment of the present invention MOS transistor;
Fig. 3 is the flow chart of expression according to the manufacturing process of first embodiment of the present invention MOS transistor;
Fig. 4 A-4N is a schematic diagram, and each represents the manufacturing process of MOS transistor according to a second embodiment of the present invention;
Fig. 5 represents the flow chart of the manufacturing process of MOS transistor according to a second embodiment of the present invention;
Fig. 6 A-6N is a schematic diagram, the manufacturing process of each expression a third embodiment in accordance with the invention MOS transistor;
Fig. 7 is the flow chart of the manufacturing process of expression a third embodiment in accordance with the invention MOS transistor;
Fig. 8 A-8N is a schematic diagram, the manufacturing process of each expression a fourth embodiment in accordance with the invention MOS transistor;
Fig. 9 is the flow chart of the manufacturing process of expression a fourth embodiment in accordance with the invention MOS transistor.
Explain the preferred embodiments of the present invention hereinafter with reference to accompanying drawing.
Below with reference to the manufacturing process of Fig. 2 A-2N and Fig. 3 explanation according to first embodiment of the present invention MOS transistor.Fig. 2 A-2N is the schematic diagram of expression according to the manufacturing process of first embodiment of the present invention MOS transistor, and Fig. 3 is the flow chart of the manufacturing process of this MOS transistor.
The manufacturing process of the MOS transistor of first embodiment is as follows.
(1) (102) are arrived so that form liner oxide film 2[Fig. 2 B and Fig. 3 (101) that thickness is 10 to tens nm in thermal oxidation silicon substrate 1 surface].
(2) on liner oxide film 2 deposition thickness be about 10 to the polysilicon membrane 18 of 200nm Fig. 2 B, figure (103)].When forming device isolation heat oxide film 5, this polysilicon membrane 18 prevents film as oxidation.Incidentally, polysilicon membrane 18 can form liner oxide film 2 and directly be deposited on the silicon substrate 1.
Incidentally, following explanation forms liner oxide film 2 based on hypothesis.Therefore, saving when forming liner oxide film 2, just need be about the processing step of liner oxide film 2.
(3) on polysilicon membrane 18, form photoresist 19[Fig. 2 B, Fig. 3 (104)].
(4) after the 19 usefulness ordinary flat printing processes of the photoresist in the zone that will form device isolation film are removed, remove the part of polysilicon membrane 18, liner oxide film 2 and silicon substrate 1 with anisotropic etch, so that formation shallow trench, its sidewall has predetermined angular (about basically 60 to about 90 degree) [Fig. 2 C-2D, Fig. 3 (105) is to (107)] on the surface of silicon substrate 1.
(5) after removing photoresist 19 fully, carry out thermal oxidation ,] so that by the trench portions oxidation on Semiconductor substrate 1 surface is several to form oxide-film 5[Fig. 2 E and Fig. 2 F to tens nm being formed on, Fig. 3 (108) is to (109).Incidentally, must guarantee to prevent enough thickness of the polysilicon membrane 18 of film deposit as oxidation, thereby it can play the effect that oxidation prevents film, surface one side that is used to prevent polysilicon membrane 18 when thermal oxidation by whole oxidations and prevent that silicon substrate 1 below the polysilicon membrane 18 is by exhaustive oxidation.When liner oxide film 2 exists, oxidized in polysilicon membrane 18 lower ends that keep contacting and near the continuation of the silicon silicon substrate 1 upper end from groove ends with liner oxide film 2, between contact portion, form by so-called " beak ".As a result, near the radius of curvature the upper end of silicon substrate 1 increases.From then on find out in the scheme, be preferably formed as liner oxide film 2.
(6) do not buried fully owing to groove inside by this groove oxidation, so in order to bury the groove inside that covers with heat oxide film fully, can use method deposits such as chemical vapor deposition, sputter for example the dielectric film 9 of silicon oxide layer (below, the dielectric film 9 that is used to bury groove inside is called " buried insulation film 9 ") [Fig. 2 G, Fig. 3 (110)].Basically, the material that is used as this buried insulation film 9 is an insulating material, and preferably has low-k.When use had high dielectric constant materials, it is big that the coupling capacitance that forms during the deposit wiring material on this film in the step of back becomes.For this scheme, preferably do not use polysilicon as burying material.
(7) use chemico-mechanical polishing (CMP) or dry etching to return corrosion buried insulation film 9[Fig. 2 G, Fig. 3 (111) then].In this case, prevent that as oxidation the polysilicon membrane 18 of film from playing the effect of etch stop layer, and serve as the role who prevents that polysilicon membrane 18 following silicon substrates 1 are corroded.
(8) when because the oxidation of the trench portions of silicon substrate 1 and the beak of between contact portion, growing, the radius of curvature of groove upper end 12 is enough to prevent the increase of leakage current, finish the formation step of device isolation oxide-film [Fig. 2 H, Fig. 3 (113)] by removing polysilicon membrane 18 and liner oxide film 2.
When the oxidation growth beak owing to the trench portions of silicon substrate 1 makes the radius of curvature of groove upper end 12 be not enough to prevent the leakage current that product specification determined of each product, for example, can after returning corrosion buried insulation film 9, carry out thermal oxidation (hereinafter referred to as additional oxidation) [Fig. 2 I, Fig. 3 (112)] again to next bulk article.
In this case, because buried insulation film 9 has been formed on the groove inside of silicon substrate 1, so oxidation technology is carried out near being difficult to from the groove upper end 12 and groove inside, reason is as follows.In other words, though groove inside will be by buried insulation film 9 and by thermal oxidation,, for make oxidation seed crystal (seeds) before reaching silicon substrate 1 in buried insulation film 9 diffusion inside, time that need be longer than direct oxidation silicon substrate.Therefore, in a few minutes, near channel bottom, be difficult to carry out oxidation basically.On the other hand, be present in groove upper end 12 with chemical vapor deposition or sputtering deposit to the weak boundary layer of the coupling unit of trenched side-wall and groove upper surface, the oxidation seed crystal can be with two-forty along this boundary layer diffusion.The result, at short notice (under 850 ℃ oxidizing temperature, being equal to or greater than 10 minutes) the oxidation seed crystal is transported to groove upper end 12, thus only near the part groove upper end 12 is by preferential oxidation, and promote the formation of groove upper end 12 radius of curvature.
In addition, this additional oxidation provides the effect that makes buried insulation film 9 compactnesses.Finish after this additional oxidation, finish the formation step of device isolation oxide-film [Fig. 2 M, Fig. 3 (113)] by removing polysilicon membrane 18 and liner oxide film 2.
Should additional oxidation can after removing polysilicon membrane 18, carry out.In this case, silicon substrate 1 surface is also simultaneously oxidized, but the formation step of device isolation oxide-film is formed on silicon substrate 1 lip-deep this oxide-film and finishes by removing after finishing additional oxidation.
(9) on silicon substrate 1, form transistor arrangement etc. [Fig. 2 J, K, L, N (h), Fig. 3 (114) is to (122)].
Can use the conventional manufacturing technology of transistor arrangement, and needn't limit especially, the typical manufacturing process of mos transistor structure is described by means of example below.
(a) on silicon substrate 1, form silicon oxide layer, silicon nitride film, acid nitrogenize (acid nitride) film and high dielectric thin film (permittivity ratio SiO
2High dielectric film, for example Ta
2O
5, PZT and BsT) in any skim or their stack, as gate oxidation films 6.
These films can form with methods such as for example CVD.Silicon oxide layer can form with the thermal oxidation of silicon substrate 1.
(b) form polysilicon membrane, metallic film for example tungsten film and silicide film any or their stack, wait with corrosion then and remove unwanted part, thus formation grid 7.
(c) implanted dopant, and form ground floor wiring 10, interlayer dielectric 11 etc.
In addition, if desired, can also form interlayer dielectric 14, wiring 15 and dielectric film 16.
Above-mentioned MOS transistor can be used for for example DRAM (dynamic random access memory) of memory circuitry, and the exclusive disjunction operating circuit is logical device for example.
Above-mentioned first embodiment is by forming radius part or obtuse angle part near the groove upper end of silicon substrate, can prevent when forming groove isolation construction that acute angle portion is retained near the groove upper end of silicon substrate as device isolation oxide-film structure, can also prevent that the leakage current that concentrates near the MOS transistor that causes the gate electrode film owing to the field from increasing and voltage endurance decline, and can improve transistorized electric reliability.
Incidentally and since in first embodiment before thermal oxidation the groove upper end of silicon substrate be the right angle basically, so near the not enough situation of radius of curvature the groove upper end of silicon substrate can occur.But,,,, do not need additional oxidation sometimes to low from the restraining force of the silicon substrate volumetric expansion of the Si oxide of growth newly so compare with the material of those very difficult oxidations because prevent the easy oxidation of polysilicon of film as oxidation.And the processing of groove is easy to, and this example is also very excellent aspect productivity ratio.
The manufacturing process of the MOS transistor of second embodiment of the invention is described below with reference to Fig. 4 A-4N and Fig. 5.Fig. 4 A-4N is the schematic diagram of manufacturing process of the MOS transistor of expression second embodiment, and Fig. 5 is the flow chart of the manufacturing process of this routine MOS transistor.
The manufacturing process of the MOS transistor of second embodiment has been revised the manufacturing step (4) of first embodiment in the following manner.Because the manufacturing step except step (4) is basically the same as those in the first embodiment, so no longer describe in detail.
(4) after removing the photoresist 19 in the zone that will form device isolation film, remove each part of polysilicon membrane 18, liner oxide film 2 and silicon substrate 1 with corrosion, and form shallow trench on silicon substrate 1 surface with common exposure method.When surface of silicon forms groove, near the groove upper end, apply isotropic etch, so that near the groove upper end, form radius of curvature, apply anisotropic etch then so that determine to have the groove shape of the sloping portion that resembles isotropic etch part 13.Incidentally, near the angle of the trenched side-wall the groove bottom is 90 degree not necessarily, can form predetermined inclination (basically in 60-90 degree scope) Fig. 4 C, D, E, Fig. 5 (205)-(207)].
Compare with second embodiment, this corrosion step, just, isotropic etch and anisotropic etch become more complicated when forming shallow trench.But, because isotropic etch part 13 is arranged on the groove upper end of silicon substrate when above-mentioned formation shallow trench, so promoted the oxidation of the groove upper end of silicon substrate 1 by thermal oxidation for the first time (formation radius of curvature), the necessity of additional oxidation diminished.
Explain the manufacturing process of the MOS transistor of the third embodiment of the present invention below with reference to Fig. 6 A-6N and Fig. 7.Fig. 6 A-6N is the schematic diagram according to the manufacturing process of the MOS transistor of the 3rd embodiment, and Fig. 7 is the flow chart of this routine MOS transistor manufacturing process.
Manufacturing process according to the MOS transistor of the 3rd embodiment is as follows.
(1) thermal oxidation silicon substrate 1 surface, and to form thickness be liner oxide film 2[Fig. 6 B of 10 to tens nm, Fig. 7 (301-(302)].
(2) deposition thickness is 10 to 200nm the silicon nitride film 17[Fig. 6 B with high antioxidant on liner oxide film 2, Fig. 7 (303)].This silicon oxide film 17 prevents film as oxidation when forming device isolation oxide-film 5.Incidentally, the silicon nitride film 17 with high antioxidant can save and form liner oxide film 2 and be formed directly on the silicon substrate 1.Perhaps, by liner oxide film 2 and polysilicon membrane, or only by polysilicon membrane deposition silicon nitride film 17.Under any circumstance, silicon nitride film 17 is positioned on the outmost surface of this structure.
Incidentally, following explanation forms polysilicon membrane and liner oxide film 2 based on hypothesis.Therefore, when saving formation polysilicon membrane and liner oxide film 2, just do not needed the processing step of polysilicon membrane and liner oxide film 2.
(3) on silicon nitride film 17, form photoresist 19[Fig. 6 B, Fig. 7 (304)].
(4) remove after the photoresist 19 in the zone that will form device isolation film with the ordinary flat printing process, remove silicon nitride film 17, liner oxide film 2 and polysilicon film with corrosion.Then, remove photoresist, form shallow trench on silicon substrate 1 surface with dry etching.When this groove is formed on surface of silicon, near the groove upper end part is applied isotropic etch, so that near the groove upper end, form radius of curvature, apply anisotropic etch then and form and to resemble the groove shape that has sloping portion the isotropic etch part 13.Incidentally, near the angle of the trenched side-wall the groove bottom is 90 degree not necessarily, also can form pre-determined tilt angle (basically in 60-90 degree scope) [Fig. 6 C, D, E, Fig. 7 (305) is to (308)].
(5) remove after the photoresist 9, carry out thermal oxidation, thus be formed on the trench portions oxidation on silicon substrate 1 surface several to tens nm thick Fig. 6 E, D, F, Fig. 7 (309)].In addition, prevent that as oxidation the thickness of the silicon nitride film 17 of film from must be to be enough to play the thickness that oxidation prevents the effect of film, oxidized fully when the thermal oxidation to prevent silicon nitride film 17, and prevent that silicon substrate 1 below the silicon nitride film 17 is by complete oxidation.Because this silicon nitride film 17 has high antioxidant, so that thickness can make is thinner than the polysilicon membrane 18 that is used among first and second embodiment.When having liner oxide film 2, at the upper end of the silicon substrate 1 that keeps contacting and near the silicon the polysilicon membrane bottom with liner oxide film 2 continuously from the groove ends oxidation, form so-called " beak ", thereby increase near the radius of curvature silicon substrate 1 upper end.Find out from this scheme, be preferably formed as liner oxide film 2.
(6) do not buried fully owing to groove inside by this groove oxidation, in order to bury the inside of the groove that covers with heat oxide film fully, with method deposit dielectric films 9 such as chemical vapor deposition, sputter silicon oxide layer for example, bury groove inside (below this, the dielectric film 9 that is used to bury groove inside is called " buried insulation film 9 ") [Fig. 6 G, Fig. 7 (310)].
Fundamentally, the material that is used for buried insulation film 9 preferably has the material of insulation characterisitic and low-k.Because when use has high dielectric constant materials, it is big that the coupling capacitance that forms during the deposit wiring material on membrane material in the technology of back becomes.Find out that from this scheme using polysilicon is not best as burying material.
(7) because the beak of the oxidation growth of the trench portions by silicon substrate 1 and radius of curvature when being enough to prevent that leakage current from increasing in the groove upper end, remove remaining silicon nitride film 17, polysilicon and liner oxide film 2 then by returning corrosion buried insulation film 9, finish the formation technology [Fig. 6 H, Fig. 7 (313)] of device isolation oxide-film.
When because the beak of the oxidation growth of the trench portions by silicon substrate 1 and radius of curvature in the groove upper end when being not enough to prevent that leakage current from increasing, were carried out thermal oxidation [Fig. 6 L, Fig. 7 (312)] once more before returning corrosion buried insulation film 9.
In this case, because buried insulation film 9 has been formed on the groove inside of silicon substrate 1, near the 12 and very difficult oxidations of groove interior oxidation technology from the groove upper end, reason is as follows.
In other words, carry out the thermal oxidation of groove inside by buried insulation film 9 in this case, the time when arriving time ratio that oxidation seed crystal before the silicon substrate 1 needs in buried insulation film 9 diffusion inside at the direct oxidation silicon substrate is long.Therefore, can not carry out in the short time in a few minutes basically near the oxidation channel bottom.On the other hand, the weak boundary layer of coupling unit that is deposited on the buried insulation film 9 of trenched side-wall with chemical vapor deposition or sputtering method is present in groove upper end 12.Thereby, the oxidation seed crystal can be along this weak boundary layer with high relatively speed diffusion, thereby the oxidation seed crystal is at short notice (under 850 ℃ of temperature, be equal to or greater than 10 minutes) be transported to groove upper end 12, near the groove upper end 12 part is preferentially oxidized, and promotes the formation of the radius of curvature of groove upper end 12.
Because the beak of the oxidation growth of the trench portions by silicon substrate 1 and radius of curvature when being enough to prevent that leakage current from increasing in the groove upper end, remove residual silicon nitride film 17, polysilicon and liner oxide film 2 then by returning corrosion buried insulation film 9, finish the formation technology [Fig. 6 M, Fig. 7 (313)] of device isolation oxide-film.
Incidentally, this additional oxidation not necessarily must be carried out before returning of buried insulation film 9 corroded, and also can carry out after returning of buried insulation film 9 corroded according to the product specification of product needed, and is identical with first embodiment.
(8) on silicon substrate 1, form transistor arrangement etc. [Fig. 6 J-6N, Fig. 7 (314)-(322)].
Can use transistorized conventional manufacturing technology, and not restriction especially, below by the typical manufacturing process of example explanation mos transistor structure.
(a) on silicon substrate 1, form any of silicon oxide layer, silicon nitride film, acid nitride film and high insulation film, or their stack, as gate oxidation films 6.
These films can form with for example CVD.Silicon oxide layer can form by the thermal oxidation of silicon substrate 1.
(b) forming for example tungsten film and silicide film any of polysilicon membrane, metal film, or after their stack, removing unwanted part, formation grid 7 with methods such as corrosion.
(c) implanted dopant and form ground floor wiring 10, interlayer dielectric 11 etc.Can also form the wiring and the dielectric film of second layer etc. if desired.
Above-mentioned MOS transistor can be used for for example DRAM (dynamic random access memory) of memory circuitry, and SRAM exclusive disjunction operating circuit is logical device (static RAM) etc. for example.
In the manufacturing process of MOS transistor, the 3rd embodiment prevents that when the groove isolation construction that forms as device isolation oxide-film structure acute angle portion is retained near the groove upper end of silicon substrate, and only forms radius of curvature part or obtuse angle part near the groove upper end of silicon substrate.Therefore, this example can prevent that near the MOS transistor leakage current that causes the end of grid increases and voltage endurance descends owing to the field concentrates on, and improves transistorized electric reliability.
Incidentally,, can reduce, and remove this oxidation and prevent film easilier in the processing step of back so oxidation prevents the thickness of film because the 3rd embodiment uses the silicon nitride film 17 with high antioxidant to prevent film as oxidation.
The same with second embodiment in the 3rd embodiment, etching process becomes complicated when forming shallow trench, but be arranged on the groove upper end of silicon substrate 1 because of isotropic etch part 13 when forming shallow trench as mentioned above, therefore in initial thermal oxidation technology, promoted the oxidation of the groove upper end of silicon substrate 1, and the necessity of carrying out the additional heat oxidation is reduced.
The manufacturing process of the MOS transistor of the fourth embodiment of the present invention is described below with reference to Fig. 8 A-8N and Fig. 9.Fig. 8 A-8N is the schematic diagram of manufacturing process of the MOS transistor of the 4th embodiment, and Fig. 9 is the flow chart of the manufacturing process of MOS transistor in this example.
The manufacturing process of the MOS transistor of the 4th embodiment has been revised the manufacturing step (4) of the 3rd embodiment in the following manner.Because the manufacturing step except step (4) is basically the same as those in the first embodiment, just no longer describe in detail.
(4) after removing the photoresist in the zone that will form device isolation film, remove silicon nitride film 17, liner oxide film 2 and polysilicon membrane with corrosion with the ordinary flat printing process.Then, remove photoresist, form shallow trench on silicon substrate 1 surface with dry etching.Near the angle of the trenched side-wall the groove upper end not necessarily must be 90 degree, also can form pre-determined tilt angle (basically in 60-90 degree scope) [Fig. 8 C, D, E, Fig. 9 (504)-(408)].
Use silicon nitride film 17 to prevent film because the 4th embodiment is the same with the 3rd embodiment, can reduce, and remove oxidation and prevent film in the end easilier in the processing step so oxidation prevents the thickness of film as oxidation with high antioxidant.
The 4th embodiment can only just can be easy to form groove by anisotropic etch, and has high production rate.
In having the semiconductor device of groove structure, embodiments of the invention can provide the manufacture method of a kind of semiconductor device and this semiconductor device, can not cause that the transistor of forming circuit and the breakdown voltage characteristics of electric capacity degenerate.
Claims (8)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24444596A JP3611226B2 (en) | 1996-09-17 | 1996-09-17 | Semiconductor device and manufacturing method thereof |
| JP244445/1996 | 1996-09-17 | ||
| JP244445/96 | 1996-09-17 |
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| Publication Number | Publication Date |
|---|---|
| CN1231064A true CN1231064A (en) | 1999-10-06 |
| CN1161837C CN1161837C (en) | 2004-08-11 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB971980063A Expired - Fee Related CN1161837C (en) | 1996-09-17 | 1997-09-16 | Semiconductor device and manufacturing method thereof |
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| Country | Link |
|---|---|
| JP (1) | JP3611226B2 (en) |
| KR (1) | KR100425064B1 (en) |
| CN (1) | CN1161837C (en) |
| MY (1) | MY129438A (en) |
| TW (1) | TW360945B (en) |
| WO (1) | WO1998012742A1 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7221030B2 (en) | 2002-08-30 | 2007-05-22 | Fujitsu Limited | Semiconductor device |
| CN100349295C (en) * | 2003-10-24 | 2007-11-14 | 富士通株式会社 | Semiconductor device group and producing method thereof, semiconductor device and producing method thereof |
| CN1681103B (en) * | 2004-03-05 | 2010-10-13 | 三星电子株式会社 | Methods of forming semiconductor devices having buried oxide patterns and devices related thereto |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW388100B (en) | 1997-02-18 | 2000-04-21 | Hitachi Ulsi Eng Corp | Semiconductor deivce and process for producing the same |
| US5811346A (en) * | 1997-04-14 | 1998-09-22 | Vlsi Technology, Inc. | Silicon corner rounding in shallow trench isolation process |
| WO1999044223A2 (en) * | 1998-02-27 | 1999-09-02 | Lsi Logic Corporation | Process of shallow trench isolating active devices to avoid sub-threshold kinks arising from corner effects without additional processing |
| JP3917327B2 (en) | 1999-06-01 | 2007-05-23 | 株式会社ルネサステクノロジ | Method and apparatus for manufacturing semiconductor device |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63234534A (en) * | 1987-03-24 | 1988-09-29 | Oki Electric Ind Co Ltd | Manufacture of semiconductor element |
| KR960006714B1 (en) * | 1990-05-28 | 1996-05-22 | 가부시끼가이샤 도시바 | Manufacturing Method of Semiconductor Device |
| JP3208575B2 (en) * | 1991-08-16 | 2001-09-17 | ソニー株式会社 | Semiconductor device manufacturing method |
| US5316965A (en) * | 1993-07-29 | 1994-05-31 | Digital Equipment Corporation | Method of decreasing the field oxide etch rate in isolation technology |
| JP2955459B2 (en) * | 1993-12-20 | 1999-10-04 | 株式会社東芝 | Method for manufacturing semiconductor device |
| US5536675A (en) * | 1993-12-30 | 1996-07-16 | Intel Corporation | Isolation structure formation for semiconductor circuit fabrication |
-
1996
- 1996-09-17 JP JP24444596A patent/JP3611226B2/en not_active Expired - Fee Related
-
1997
- 1997-09-15 TW TW086113393A patent/TW360945B/en not_active IP Right Cessation
- 1997-09-16 KR KR10-1999-7002156A patent/KR100425064B1/en not_active IP Right Cessation
- 1997-09-16 CN CNB971980063A patent/CN1161837C/en not_active Expired - Fee Related
- 1997-09-16 WO PCT/JP1997/003267 patent/WO1998012742A1/en active IP Right Grant
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7221030B2 (en) | 2002-08-30 | 2007-05-22 | Fujitsu Limited | Semiconductor device |
| CN100349295C (en) * | 2003-10-24 | 2007-11-14 | 富士通株式会社 | Semiconductor device group and producing method thereof, semiconductor device and producing method thereof |
| CN1681103B (en) * | 2004-03-05 | 2010-10-13 | 三星电子株式会社 | Methods of forming semiconductor devices having buried oxide patterns and devices related thereto |
Also Published As
| Publication number | Publication date |
|---|---|
| TW360945B (en) | 1999-06-11 |
| CN1161837C (en) | 2004-08-11 |
| KR20000036123A (en) | 2000-06-26 |
| WO1998012742A1 (en) | 1998-03-26 |
| JPH1092919A (en) | 1998-04-10 |
| JP3611226B2 (en) | 2005-01-19 |
| MY129438A (en) | 2007-04-30 |
| KR100425064B1 (en) | 2004-03-30 |
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