CN121285293A

CN121285293A - Package substrate, manufacturing method thereof and semiconductor package structure

Info

Publication number: CN121285293A
Application number: CN202511460280.9A
Authority: CN
Inventors: 姚雷阳; 陈玉龙; 杜树安; 杨光林; 杨柳
Original assignee: Hygon Information Technology Co Ltd
Current assignee: Hygon Information Technology Co Ltd
Priority date: 2025-10-13
Filing date: 2025-10-13
Publication date: 2026-01-06

Abstract

The present disclosure relates to a package substrate, a method of manufacturing the same, and a semiconductor package structure. The package substrate comprises a core layer, a first power layer, a second power layer and at least one first impedance adjusting structure. The core layer is provided with at least one first buried cavity. The first power layer and the second power layer are respectively arranged on the upper side and the lower side of the core layer. The first impedance adjusting structure is arranged in the first embedded cavity and comprises a plurality of first conductive layers and a plurality of second conductive layers which are alternately and alternately stacked at intervals along the first direction perpendicular to the core layer, and any adjacent first conductive layers and second conductive layers are insulated. The first conductive layers are electrically connected with at least one of the first power supply layer and the second power supply layer, and the second conductive layers are electrically connected with at least one of the first power supply layer and the second power supply layer. The power supply network impedance in the packaging substrate can be reduced, so that the power supply integrity of the packaging substrate can be ensured and improved.

Description

Package substrate, manufacturing method thereof and semiconductor package structure

Technical Field

The present disclosure relates to the field of integrated circuits, and in particular, to a package substrate, a method for manufacturing the package substrate, and a semiconductor package structure.

Background

With the continuous improvement of device performance, the integrated circuit has higher and higher integrated level, higher signal transmission rate, higher and higher Power consumption of the chip, higher and higher transient current requirement in the chip, and greater challenges to Power Integrity (PI) design of the package substrate.

Disclosure of Invention

Accordingly, there is a need for a package substrate, a method for manufacturing the same, and a semiconductor package structure for reducing the impedance of a power network in the package substrate so as to ensure and improve the power integrity of the package substrate.

In a first aspect, an embodiment of the present disclosure provides a package substrate including a core layer, a first power layer, a second power layer, and at least one first impedance adjusting structure. The core layer is provided with at least one first buried cavity. The first power layer and the second power layer are respectively arranged on the upper side and the lower side of the core layer. The first impedance adjusting structure is arranged in the first embedded cavity and comprises a plurality of first conductive layers and a plurality of second conductive layers which are alternately and alternately stacked at intervals along the first direction perpendicular to the core layer, and any adjacent first conductive layers and second conductive layers are insulated. The first conductive layers are electrically connected with at least one of the first power supply layer and the second power supply layer, and the second conductive layers are electrically connected with at least one of the first power supply layer and the second power supply layer.

In some embodiments of the present disclosure, the first impedance adjusting structure further comprises a first plating layer on a first sidewall of the first buried cavity and a second plating layer on a second sidewall of the first buried cavity, wherein the first sidewall and the second sidewall are opposite in a second direction parallel to the core layer. The first electroplated layers are electrically connected with the first conductive layers, and a space is arranged between the end part, away from the first electroplated layer, of each first conductive layer and the second electroplated layer in the second direction. The second electroplated layers are electrically connected with the second conductive layers, and a space is arranged between the end, away from the second electroplated layers, of the second conductive layers and the first electroplated layers in the second direction.

In some embodiments of the present disclosure, the first plating layer and the second plating layer extend in a first direction. The top surface of the first electroplated layer and the top surface of the second electroplated layer are respectively in contact connection with the first power supply layer. The bottom surface of the first electroplated layer and the bottom surface of the second electroplated layer are respectively in contact connection with the second power supply layer.

In some embodiments of the present disclosure, the first impedance adjusting structure further includes a first electrode plate co-located with the first power layer and electrically connected to the first power layer, and a second electrode plate co-located with the second power layer and electrically connected to the second power layer. The orthographic projection of the first polar plate and the second polar plate along the first direction is overlapped with the orthographic projection of the first conductive layer along the first direction, or the orthographic projection of the first polar plate and the second polar plate along the first direction is overlapped with the orthographic projection of the second conductive layer along the first direction.

In some embodiments of the present disclosure, the first plate is the same film thickness as the first power layer. The thickness of the film layer of the second polar plate is the same as that of the second power supply layer.

In some embodiments of the present disclosure, the package substrate further includes a rewiring structure disposed on a side of the first power plane facing away from the core plane and/or on a side of the second power plane facing away from the core plane.

In some embodiments of the present disclosure, at least one second buried cavity is provided in the rerouting structure. The package substrate further includes a second impedance adjusting structure disposed within the second buried cavity. The second resistance adjustment structure includes a plurality of third conductive layers and a plurality of fourth conductive layers alternately and alternately stacked at intervals in a first direction perpendicular to the core layer, and any adjacent third conductive layers and fourth conductive layers are insulated. The third conductive layers and the fourth conductive layers are respectively and electrically connected with the adjacent power supply layers.

In a second aspect, the present disclosure provides a method of manufacturing a package substrate for manufacturing a package substrate as described in any of the embodiments above. The manufacturing method comprises the following steps:

Preparing a core layer in which at least one first embedded cavity is formed;

Forming a first impedance adjusting structure in the first buried cavity, wherein the first impedance adjusting structure comprises a plurality of first conductive layers and a plurality of second conductive layers which are alternately and alternately stacked at intervals along a first direction perpendicular to the core layer, and any adjacent first conductive layers and second conductive layers are insulated;

And forming a first power layer and a second power layer on the upper side and the lower side of the core layer respectively, so that the multiple first conductive layers are electrically connected with at least one of the first power layer and the second power layer, and the multiple second conductive layers are electrically connected with at least one of the first power layer and the second power layer.

In some embodiments of the present disclosure, the first impedance adjusting structure further includes a first plating layer electrically connected to each of the first conductive layers and a second plating layer electrically connected to each of the second conductive layers. Accordingly, forming a first impedance adjusting structure within the first buried cavity, comprising:

forming a first electroplated layer on a first side wall of the first embedded cavity and forming a second electroplated layer on a second side wall of the first embedded cavity, wherein the first side wall and the second side wall are opposite in a second direction parallel to the core layer;

A plurality of insulating dielectric layers and a plurality of conductive dielectric layers are alternately stacked in the first embedded cavity, and the conductive dielectric layers electrically connected with the first electroplated layer and spaced from the second electroplated layer form a first conductive layer, and the conductive dielectric layers electrically connected with the second electroplated layer and spaced from the first electroplated layer form a second conductive layer.

In some embodiments of the present disclosure, the first power supply layer and the second power supply layer are formed in a first sidewall of the first buried cavity to form a first plating layer, after the second plating layer is formed in a second sidewall of the first buried cavity, and before the plurality of insulating dielectric layers and the plurality of conductive dielectric layers are alternately stacked in the first buried cavity. The first power supply layer also covers the top surface of the first electroplated layer and the top surface of the second electroplated layer, and the second power supply layer also covers the bottom surface of the first electroplated layer and the bottom surface of the second electroplated layer.

In some embodiments of the present disclosure, the first impedance adjusting structure further includes a first electrode plate located on the same layer as the first power layer and electrically connected to the first power layer, and a second electrode plate located on the same layer as the second power layer and electrically connected to the second power layer. After alternately stacking a plurality of insulating dielectric layers and a plurality of conductive dielectric layers in the first buried cavity, forming a first impedance adjusting structure in the first buried cavity, further comprising:

forming a first polar plate on one side of the core layer, which is provided with a first power layer, and electrically connecting the first polar plate with the first power layer;

And forming the second polar plate on one side of the core layer, which is provided with the second power supply layer, and electrically connecting the second polar plate with the second power supply layer.

Optionally, the orthographic projection of the first polar plate and the second polar plate along the first direction coincides with the orthographic projection of the first conductive layer along the first direction, or the orthographic projection of the first polar plate and the second polar plate along the first direction coincides with the orthographic projection of the second conductive layer along the first direction.

In some embodiments of the present disclosure, the method of manufacturing a package substrate further includes:

Patterning the first power layer and the second power layer respectively;

And forming a rewiring structure on one side of the first power supply layer, which is away from the core layer, and/or one side of the second power supply layer, which is away from the core layer.

Forming at least one second buried cavity in the rerouting structure;

The second impedance adjusting structure comprises a plurality of third conductive layers and a plurality of fourth conductive layers which are alternately and alternately stacked at intervals along the first direction, any adjacent third conductive layers and fourth conductive layers are insulated, and the plurality of third conductive layers and the plurality of fourth conductive layers are respectively and electrically connected with adjacent power supply layers.

In a third aspect, the present disclosure provides a semiconductor package structure including a package substrate as described in any of the embodiments above, and a chip and a printed circuit board respectively packaged on upper and lower sides of the package substrate.

In some embodiments of the present disclosure, the chip has a conductive portion.

Optionally, an orthographic projection of the first impedance adjusting structure along the first direction overlaps an orthographic projection of the conductive portion along the first direction;

or, the interval between the orthographic projection of the first impedance adjusting structure along the first direction and the orthographic projection of the conductive part along the first direction in the direction parallel to the core layer is smaller than the target threshold.

Embodiments of the present disclosure may/have at least the following advantages:

In the embodiment of the disclosure, by arranging at least one first embedded cavity in the core layer and arranging the first impedance adjusting structure based on the first embedded cavity, a capacitor-like structure can be constructed by a plurality of first conductive layers and a plurality of second conductive layers which are alternately and alternately stacked along the first direction in the first impedance adjusting structure, and meanwhile, the connection between each first conductive layer and the corresponding power supply layer is realized, and the electrical connection between each second conductive layer and the corresponding power supply layer is realized. Therefore, the number of layers of the first conductive layer and the second conductive layer in the first impedance adjusting structure is regulated, the equivalent capacitor in the power supply network is effectively increased to correspondingly increase the loop capacitance of the power supply network, and meanwhile, the loop inductance of the power supply network can be correspondingly reduced by regulating the plane size of the first embedded cavity and the opposite plane area between the adjacent first conductive layer and second conductive layer in the first direction, so that the impedance of the power supply network in the packaging substrate can be reduced, the ripple wave of the power supply network can be reduced, the through-flow cross-sectional area of the power supply network can be increased, the performance of the packaging substrate can be improved in terms of the direct-current voltage drop and the current density of the power supply network, and the power supply integrity of the packaging substrate can be further ensured and improved.

In addition, compared with the surface-mounted capacitor on the upper and lower surfaces of the package substrate or the embedding of the capacitor in the core layer, the first impedance adjusting structure in the embodiment of the disclosure does not occupy the space on the upper and lower surfaces of the package substrate, is not limited by the package size and the capacitance selection of the capacitor, and can have a more flexible capacitance adding range.

The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the disclosure will be apparent from the description and drawings, and from the claims.

Drawings

In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the related art, the drawings that are required to be used in the embodiments of the present disclosure or the description of the related art will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and other related drawings may be obtained according to these drawings without inventive effort to those of ordinary skill in the art.

FIG. 1 is a schematic cross-sectional view of a package substrate according to some embodiments;

FIG. 2 is a schematic cross-sectional view of another package substrate according to some embodiments;

FIG. 3 is a schematic cross-sectional view of a semiconductor package according to some embodiments;

fig. 4 is a flowchart illustrating a method for manufacturing a package substrate according to some embodiments;

FIG. 5 is a flow chart of another method for manufacturing a package substrate according to some embodiments;

FIG. 6 is a schematic top view of a core layer provided in some embodiments;

FIG. 7 is a schematic top view of a structure after forming vias and trenches in the core layer, as provided by some embodiments;

FIG. 8 is a schematic top view of a structure after forming a layer of plating material within the vias and trenches of the core layer, as provided by some embodiments;

FIG. 9 is a schematic top view of a structure provided in some embodiments after forming a first buried cavity and first and second electroplated layers in a core layer;

FIG. 10 is a schematic top view of a resulting structure after formation of holes in the disk in the core layer, as provided by some embodiments;

FIG. 11 is a schematic cross-sectional view of a structure after forming a first power plane and a second power plane and providing an auxiliary support structure, as provided by some embodiments;

FIG. 12 is a schematic cross-sectional view of a structure after forming a first insulating dielectric layer in a first buried cavity according to some embodiments;

FIG. 13 is a schematic cross-sectional view of a structure provided in some embodiments after a first layer of a second conductive layer is formed within a first buried cavity;

FIG. 14 is a schematic cross-sectional view of a structure after forming a second insulating dielectric layer in a first buried cavity according to some embodiments;

FIG. 15 is a schematic cross-sectional view of a structure provided in some embodiments after a first conductive layer is formed within a first buried cavity;

FIG. 16 is a schematic cross-sectional view of a structure after forming a third dielectric layer in the first buried cavity, according to some embodiments;

FIG. 17 is a schematic cross-sectional view of a structure provided in some embodiments after forming a second conductive layer in the first buried cavity;

FIG. 18 is a schematic cross-sectional view of a structure obtained after forming multiple first conductive layers, multiple second conductive layers, and multiple insulating dielectric layers in a first buried cavity according to some embodiments;

FIG. 19 is a schematic cross-sectional view of a resulting structure after formation of a first plate, as provided in some embodiments;

FIG. 20 is a schematic cross-sectional view of some embodiments after removal of the auxiliary support structure and flip-up and flip-down of the resulting structure;

FIG. 21 is a schematic cross-sectional view of a structure obtained after etching back an insulating medium layer to form a second plate accommodating opening according to some embodiments;

FIG. 22 is a schematic cross-sectional view of a structure after formation of a second pole plate, as provided in some embodiments;

FIG. 23 is a flow chart of a method of fabricating a package substrate according to another embodiment;

FIG. 24 is a flow chart of a method of fabricating a package substrate according to another embodiment;

FIG. 25 is a schematic cross-sectional view of a structure after patterning a first power plane and a second power plane provided in some embodiments;

FIG. 26 is a schematic cross-sectional view of a resulting structure after formation of a first spacer material layer in a reroute structure in accordance with some embodiments;

FIG. 27 is a schematic cross-sectional view of a structure after patterning a spacer material layer according to some embodiments;

FIG. 28 is a schematic cross-sectional view of a resulting structure after formation of a first conductive material layer in a rerouting structure in accordance with some embodiments;

Fig. 29 is a schematic cross-sectional view of a structure after patterning a conductive material layer, as provided in some embodiments.

Reference numerals illustrate:

10-core layer, 20-first power layer, 30-second power layer, 40-first impedance adjusting structure, 401-first conductive layer, 402-second conductive layer, 403-insulating dielectric layer, 404-first electroplated layer, 405-second electroplated layer, 406-first plate, 407-second plate, 50-dished mesoporous, 501-electroplated sidewall, 502-filler layer, 60-rewiring structure, 610-isolation material layer, 601-isolation pattern layer, 620-conductive material layer, 602-conductive pattern layer, 603-first solder pad, 604-second solder pad, 605-third solder pad, 70-chip, 701-copper pillar, 702-micro bump, 80-printed circuit board, 801-solder ball, 90-surface mount device, H-via, G-through trench, 110-electroplated material layer, 120-auxiliary support structure, Q-first buried cavity, K-opening.

Detailed Description

In order to make the objects, technical solutions and advantages of the present disclosure more apparent, the present disclosure will be further described in detail with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present disclosure.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

It will be understood that when an element is referred to as being "connected" to another element, it can be directly connected to the other element or be connected to the other element through intervening elements. Further, "connection" in the following embodiments should be understood as "electrical connection", "communication connection", and the like if there is transmission of electrical signals or data between objects to be connected.

It should be understood that the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," and/or the like, specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof. Also, as used herein, the term "and/or" includes any and all combinations of the associated listed items.

At present, the power supply integrity of the packaging substrate is mainly represented by two indexes of direct current voltage drop (DC drop) and alternating current ripple (AC ripple), namely, the voltage drop and the ripple of a substrate power supply network can be ensured to fluctuate within an allowable range in a limited space, wherein the direct current voltage drop is a direct current index, and the alternating current ripple is an alternating current index.

Illustratively, the impedance of a power network (Power Distribution Network, PDN for short) in the package substrate is related to both the aforementioned dc voltage drop and ac ripple. The impedance of the power supply network in the packaging substrate is kept within a preset range, and the direct current voltage drop and the alternating current ripple can be ensured not to exceed the standard. Since the impedance of the power supply network refers to the frequency domain impedance of each power supply network, the impedance of the power supply network is directly proportional to the loop inductance (equivalent inductance of the whole loop formed by connecting a certain power supply network with a capacitor and a ground network) of the power supply network, and inversely proportional to the loop capacitance (equivalent capacitance of the whole loop formed by connecting a certain power supply network with a capacitor and a ground network), so that the loop inductance of each power supply network needs to be reduced and the loop capacitance of each power supply network needs to be increased to realize that the impedance of the power supply network is in a smaller range.

Based on this, the embodiment of the disclosure provides a packaging substrate, a manufacturing method thereof and a semiconductor packaging structure, which can flexibly and effectively increase the loop capacitance of a power supply network, reduce the loop inductance of the power supply network, and facilitate reducing the impedance of the power supply network in the packaging substrate, thereby ensuring and improving the power supply integrity of the packaging substrate.

Referring to fig. 1, a package substrate according to an embodiment of the disclosure includes a core layer 10, a first power layer 20, a second power layer 30, and at least one first impedance adjusting structure 40.

The core layer 10 is provided with at least one first buried cavity. The core layer 10 is, for example, a BT resin layer. The BT resin is a thermosetting resin formed by using Bismaleimide (BMI) and triazine as main resin components and adding an epoxy resin, a polyphenylene ether resin (PPE), an allyl compound, or the like as a modifying component. The size and number of first embedded cavities can be selected to match the requirements.

The first power layer 20 and the second power layer 30 are disposed on the upper and lower sides of the core layer 10, respectively. The first power supply layer 20 and the second power supply layer 30 are, for example, patterned conductive copper layers.

The first impedance adjusting structure 40 is disposed in the first buried cavity, and includes a plurality of first conductive layers 401 and a plurality of second conductive layers 402 alternately stacked at intervals along a first direction (e.g., Z direction) perpendicular to the core layer 10, and any adjacent first conductive layers 401 and second conductive layers 402 are insulated, for example, by an insulating dielectric layer 403 filled in the first buried cavity. Wherein, an insulating dielectric layer 403 is filled between every two adjacent first conductive layers 401 and second conductive layers 402.

Optionally, the first conductive layer 401 is electrically connected to at least one of the first power layer 20 and the second power layer 30, and the second conductive layer 402 is electrically connected to at least one of the first power layer 20 and the second power layer 30.

It will be appreciated that the first power plane 20 and the second power plane 30 are used to build a power network and may be patterned into a plurality of separate conductive patterns, respectively. Therefore, each first conductive layer 401 in the first impedance adjusting structure 40 may be correspondingly connected to a corresponding conductive pattern of at least one of the first power layer 20 and the second power layer 30, each second conductive layer 402 in the first impedance adjusting structure 40 may be correspondingly connected to a corresponding conductive pattern of at least one of the first power layer 20 and the second power layer 30, and the specific connection relationship thereof is not limited in the embodiments of the present disclosure, so that the corresponding connection may be realized by matching the design of the power network.

In the embodiment of the disclosure, by providing at least one first buried cavity in the core layer 10 and providing the first impedance adjusting structure 40 based on the first buried cavity, a capacitor-like structure may be constructed by alternately and alternately stacking multiple first conductive layers 401 and multiple second conductive layers 402 along the first direction (e.g., the Z direction) in the first impedance adjusting structure 40, and simultaneously, the connection between each first conductive layer 401 and the corresponding power layer is achieved, and the electrical connection between each second conductive layer 402 and the corresponding power layer is achieved. In this way, the number of layers of the first conductive layer 401 and the second conductive layer 402 in the first impedance adjusting structure 40 is adjusted, so that an equivalent capacitor in the power supply network is effectively increased, loop capacitance of the power supply network is correspondingly increased, and meanwhile, loop inductance of the power supply network is correspondingly reduced by adjusting and controlling the plane size of the first embedded cavity and the opposite plane area between the adjacent first conductive layer 401 and the adjacent second conductive layer 402 in the first direction, so that impedance of the power supply network in the package substrate can be reduced, ripple of the power supply network is reduced, the through-flow cross-sectional area of the power supply network can be increased, performance of the package substrate is improved in terms of direct-current voltage drop and current density of the power supply network, and power supply integrity of the package substrate is further ensured and improved.

It will be appreciated that in some embodiments of the related art, the package substrate may have a core layer as an intermediate layer and the core layer as a support structure for film stacking. The capacitor is mainly surface-mounted on the upper and lower surfaces of the package substrate. However, the integration level of the chip (DIE) is higher and higher, the area occupied by the chip and the interconnect line between the chips is larger and larger, and the package substrate is generally required to consider the compatibility of the product line test fixture, so that the space of the surface-mounted capacitors on the upper surface and the lower surface of the package substrate is severely limited, and the number of the surface-mounted capacitors on the upper surface and the lower surface of the package substrate is limited. In addition, in many product applications, the thickness of the package substrate is required to be thinner, and if the capacitor is considered to be embedded in the core layer of the package substrate, the placement space and the selection range of the capacitor are greatly limited by the thickness of the core layer, and the process requirements of filling media and heat dissipation materials need to be met. If the core layer has a larger thickness, the space of the core layer is easily wasted due to the embedded capacitor.

Therefore, compared to the above-mentioned surface-mounted capacitors on the upper and lower surfaces of the package substrate or embedding the capacitors in the core layer, the first impedance adjusting structure 40 in the embodiment of the disclosure does not need to occupy the space on the upper and lower surfaces of the package substrate, and flexible construction of different capacitance values can be achieved by adjusting the planar areas of the first conductive layer 401 and the second conductive layer 402, the filling thickness of the insulating dielectric layer 403, and the material type of the insulating dielectric layer 403, so as to avoid many limitations on package size and capacitance value selection due to embedding the capacitors, and to enable a more flexible capacitance value addition range.

In some embodiments of the present disclosure, with continued reference to FIG. 1, the first impedance adjusting structure 40 further includes a first plating layer 404 on a first sidewall of the first buried cavity and a second plating layer 405 on a second sidewall of the first buried cavity, wherein the first sidewall and the second sidewall are opposite in a second direction (e.g., X-direction) parallel to the core layer. The first plating layers 404 are electrically connected to the first conductive layers 401, and an end portion of the first conductive layers 401 remote from the first plating layers 404 is spaced from the second plating layers 405 in a second direction (for example, X direction). The second plating layers 405 are electrically connected to the second conductive layers 402, and an end of the second conductive layer 402 away from the second plating layers 405 is spaced apart from the first plating layers 404 in a second direction (for example, X direction).

In the embodiment of the disclosure, the first conductive layers 401 and the second conductive layers 402 are arranged in parallel and cross, the first conductive layers 401 are connected through the first electroplated layers 404 arranged on the first side wall of the first embedded cavity, the second electroplated layers 405 arranged on the second side wall of the first embedded cavity are connected with the second conductive layers 402, and the led-out connection of the first conductive layers 401 and the second conductive layers 402 is conveniently realized, and meanwhile, the process is simplified.

Alternatively, as shown in fig. 1, the first plating layer 404 and the second plating layer 405 extend in a first direction (e.g., Z direction). The top surface of the first plating layer 404 and the top surface of the second plating layer 405 are respectively in contact with the first power supply layer 20. The bottom surface of the first plating layer 404 and the bottom surface of the second plating layer 405 are respectively in contact with the second power supply layer 30.

In some embodiments of the present disclosure, referring to fig. 1, the first impedance adjusting structure 40 further includes a first electrode plate 406 disposed on the same layer as the first power layer 20 and electrically connected to the first power layer 20, and a second electrode plate 407 disposed on the same layer as the second power layer 30 and electrically connected to the second power layer 30.

Optionally, the orthographic projection of first plate 406 and second plate 407 in the first direction (e.g., Z-direction) coincides with the orthographic projection of first conductive layer 401 in the first direction (e.g., Z-direction).

Optionally, the orthographic projection of first plate 406 and second plate 407 in a first direction (e.g., Z-direction) coincides with the orthographic projection of second conductive layer 402 in the first direction (e.g., Z-direction).

In some embodiments of the present disclosure, the first plate 406 is the same thickness of the film as the first power layer 20. The second plate 407 has the same film thickness as the second power supply layer 30. That is, the surface of the first pole plate 406 facing away from the core layer 10 is flush with the surface of the first power supply layer 20 facing away from the core layer 10, and the surface of the second pole plate 407 facing away from the core layer 10 is flush with the surface of the second power supply layer 30 facing away from the core layer 10. In this manner, subsequent stacking or lamination of other films on the first and second power supply layers 20 and 30 is facilitated to prepare other functional layers, such as a re-wiring structure.

In some embodiments of the present disclosure, referring to fig. 2, the package substrate further includes a redistribution structure 60 disposed on a side of the first power layer 20 facing away from the core layer 10 and/or on a side of the second power layer 30 facing away from the core layer 10.

In fig. 2, a rerouting structure 60 is illustrated by way of example on both the side of the first power plane 20 facing away from the core plane 10 and the side of the second power plane 30 facing away from the core plane 10.

Alternatively, the redistribution structure 60 includes a plurality of isolation pattern layers 601 and a plurality of conductive pattern layers 602 alternately stacked along a first direction (e.g. a Z direction), wherein each conductive pattern layer 602 is electrically connected in sequence according to a predetermined connection relationship.

Optionally, the rewiring structure 60 on the side of the first power supply layer 20 facing away from the core layer 10 and on the side of the second power supply layer 30 facing away from the core layer 10 has the same number of isolation pattern layers 601 and the same number of conductive pattern layers 602.

Alternatively, the isolation pattern layer 601 includes, but is not limited to, a patterned electronic grade resin-based Film, which may be, for example, an ABF (Ajinomoto Build-up Film) pattern layer.

Optionally, the conductive pattern layer 602 includes, but is not limited to, a copper pattern layer.

In some embodiments of the present disclosure, at least one second buried cavity is provided in the rewiring structure 60. The package substrate further includes a second impedance adjusting structure disposed within the second buried cavity. The second resistance adjustment structure includes a plurality of third conductive layers and a plurality of fourth conductive layers alternately and alternately stacked in a first direction (e.g., Z-direction) perpendicular to the core layer 10, and any adjacent third conductive layers and fourth conductive layers are insulated. The third conductive layers and the fourth conductive layers are respectively and electrically connected with the adjacent power supply layers.

Alternatively, a second buried cavity may be correspondingly formed within the target layer isolation pattern layer 601. Compared to the first resistance adjustment structure 40, the second resistance adjustment structure is independently fabricated within the second buried cavity of the target layer isolation pattern layer 601, requiring a more precise electroplating process, a dielectric filling process, to achieve a closely spaced cross-parallel plate metal plated planar structure, even though the spacing between adjacent third and fourth conductive layers is smaller.

Illustratively, the target layer isolation pattern layer 601 is one or more isolation pattern layers 601.

Illustratively, the thickness of the different isolation pattern layers 601 is different. The target layer isolation pattern layer 601 is an isolation pattern layer 601 having a maximum thickness or a thickness greater than a target threshold value among the isolation pattern layers.

It will be appreciated that the second impedance adjusting structure is similar in structure and function to the first impedance adjusting structure 40, i.e. specific limitations of the second impedance adjusting structure may be found in the above definition of the first impedance adjusting structure 40. And, the second impedance adjusting structure can achieve the same or similar technical effect as the first impedance adjusting structure 40. And will not be described in detail herein.

Based on the same inventive concept, embodiments of the present disclosure also provide a semiconductor package structure including the package substrate as described in any of the embodiments above. The embodiments of the semiconductor package structure for solving the problems are similar to those described in the above package substrate, so the specific limitation of the semiconductor package structure can be referred to the limitation of the package substrate hereinabove, and the description thereof will not be repeated here.

In some embodiments of the present disclosure, referring to fig. 3, the semiconductor package structure further includes a chip 70 encapsulated on one side of the package substrate.

In some examples of the present disclosure, chip 70 has conductive portions. For example, as shown in fig. 3, the conductive portion is located on a side of the chip 70 near the package substrate, and includes, for example, a copper pillar (copper pillar) 701. Copper pillars (copper pillars) 701 may be electrically connected to corresponding pads or circuits by micro bump solder balls (uBump) 702. The micro bump solder balls 702 include, but are not limited to, solder balls.

Optionally, an orthographic projection of the first impedance adjusting structure 40 along a first direction (e.g., the Z-direction) overlaps an orthographic projection of the conductive portion along the first direction (e.g., the Z-direction).

Optionally, the spacing between the orthographic projection of the first impedance adjusting structure 40 in the first direction (e.g., the Z-direction) and the orthographic projection of the conductive portion in the first direction (e.g., the Z-direction) in the direction parallel to the core layer 10 is less than the target threshold.

In the embodiment of the disclosure, the first impedance adjusting structure 40 is disposed under the orthographic projection of the conductive portion of the chip 70 along the first direction (e.g. the Z direction) or in the peripheral area of the orthographic projection, which is beneficial to further improving the power integrity of the package substrate by pulling the distance between the first impedance adjusting structure 40 and the conductive portion of the chip 70, and meanwhile, the power noise in the chip 70 can be decoupled better.

In some embodiments of the present disclosure, referring still to fig. 3, the semiconductor package further includes a printed circuit board (Print Circuit Board, abbreviated as PCB) 80 encapsulated on a side of the package substrate facing away from the chip 70. That is, the chip 70 and the printed circuit board 80 may be respectively packaged on the upper and lower sides of the package substrate.

Optionally, the printed circuit board 80 is packaged on the package substrate by solder balls 801. Solder balls 801 include, but are not limited to, solder balls.

In some embodiments of the present disclosure, with continued reference to fig. 3, the semiconductor package further includes a surface mount device 90 on the same side as the chip 70 and packaged on the package substrate.

Alternatively, surface mount device 90 includes, but is not limited to, a surface mount capacitor. The surface mount device 90 may be surface mounted on the package substrate by means of Surface Mount (SMT).

Optionally, as shown in fig. 3, the surface of the rerouting structure 60 of the package substrate is provided with a plurality of pads, wherein the plurality of pads match different electrical functions, including for example a first pad 603 for connecting to the chip 70, a second pad 604 for connecting to the printed circuit board 80, and a third pad 605 for connecting to the surface mount device 90.

It should be noted that in some embodiments of the present disclosure, the number of core layers 10 in the package substrate may be multiple layers. Accordingly, the first impedance adjusting structures 40 may be respectively disposed within the multi-layered core layer 10.

In some embodiments of the present disclosure, the package substrate comprises a glass core substrate, i.e., the core layer 10 is a glass substrate. After the first buried cavity is provided in the core layer 10, the first impedance adjusting structure 40 may be buried in the first buried cavity.

In other embodiments of the present disclosure, the core layer 10 is an interposer or interposer.

In still other embodiments of the present disclosure, the package substrate is a coreless substrate that is stacked on a single side, i.e., the core layer 10 may be located at the topmost layer of the package substrate. Accordingly, both the chip 70 and the first impedance adjusting structure 40 may be embedded inside the core layer 10 by embedding.

Based on the same inventive concept, embodiments of the present disclosure also provide a method of manufacturing a package substrate for manufacturing the package substrate as described in any of the above embodiments. The embodiments of the method for manufacturing a package substrate to solve the problems are similar to the embodiments described in the above package substrate, so the specific limitation of the related structure in the method for manufacturing a package substrate can be referred to the above limitation of the package substrate, and the description thereof will not be repeated here.

Referring to fig. 4, the method for manufacturing the package substrate may include the following steps S100 to S300.

S100, preparing a core layer, wherein at least one first embedded cavity is formed in the core layer.

And S200, forming a first impedance adjusting structure in the first embedded cavity, wherein the first impedance adjusting structure comprises a plurality of first conductive layers and a plurality of second conductive layers which are alternately and alternately stacked at intervals along a first direction perpendicular to the core layer, and any adjacent first conductive layers and second conductive layers are insulated.

S300, forming a first power layer and a second power layer on the upper side and the lower side of the core layer respectively, wherein the multiple first conductive layers are electrically connected with at least one of the first power layer and the second power layer, and the multiple second conductive layers are electrically connected with at least one of the first power layer and the second power layer.

In some embodiments of the present disclosure, the first impedance adjusting structure further includes a first plating layer electrically connected to each of the first conductive layers and a second plating layer electrically connected to each of the second conductive layers. Accordingly, referring to fig. 5, forming a first impedance adjusting structure in the first buried cavity in step S200 may include the following steps S210 and S220.

S210, forming a first electroplated layer on a first side wall of the first embedded cavity and forming a second electroplated layer on a second side wall of the first embedded cavity, wherein the first side wall and the second side wall are opposite in a second direction parallel to the core layer.

S220, alternately laminating a plurality of insulating dielectric layers and a plurality of conductive dielectric layers in the first embedded cavity, and enabling the conductive dielectric layers which are electrically connected with the first electroplated layer and are spaced from the second electroplated layer to form a first conductive layer, and enabling the conductive dielectric layers which are electrically connected with the second electroplated layer and are spaced from the first electroplated layer to form a second conductive layer.

It should be noted that, in some embodiments of the present disclosure, please continue to refer to fig. 5, the step S300 includes a step S310 of forming a first power layer and a second power layer on the upper and lower sides of the core layer, respectively. Here, the first power layer and the second power layer are initial power material layers, i.e. have not been subjected to patterning. Accordingly, the first power supply layer and the second power supply layer are formed on the first side wall of the first buried cavity to form a first electroplated layer, after the second electroplated layer is formed on the second side wall of the first buried cavity, and before the plurality of insulating dielectric layers and the plurality of conductive dielectric layers are alternately stacked in the first buried cavity. That is, step S310 may be performed after step S210 is performed and before step S220 is performed. Thus, the first power layer covers the top surface of the first plating layer and the top surface of the second plating layer, and the second power layer covers the bottom surface of the first plating layer and the bottom surface of the second plating layer.

In some embodiments of the present disclosure, the first impedance adjusting structure further includes a first electrode plate located on the same layer as the first power layer and electrically connected to the first power layer, and a second electrode plate located on the same layer as the second power layer and electrically connected to the second power layer. With continued reference to fig. 5, after the step S220 of alternately stacking a plurality of insulating dielectric layers and a plurality of conductive dielectric layers in the first buried cavity, the step S200 of forming a first impedance adjusting structure in the first buried cavity may further include the following steps S230 and S240.

S230, forming a first polar plate on one side of the core layer provided with the first power layer, and electrically connecting the first polar plate with the first power layer.

S240, forming a second polar plate on one side of the core layer provided with the second power layer, and enabling the second polar plate to be electrically connected with the second power layer.

Optionally, the orthographic projection of the first plate and the second plate along the first direction coincides with the orthographic projection of the first conductive layer along the first direction.

Optionally, the orthographic projection of the first electrode plate and the second electrode plate along the first direction coincides with the orthographic projection of the second conductive layer along the first direction.

In order to more clearly illustrate the manufacturing method of the package substrate provided by the embodiment of the present disclosure, the manufacturing method shown in fig. 5 is exemplarily expressed with reference to fig. 6 to 22.

In steps S100 and S210, as shown in fig. 6 to 10, a core layer 10 is prepared, and at least one first buried cavity Q is formed in the core layer 10. A first plating layer 404 is formed on a first sidewall of the first buried cavity Q and a second plating layer 405 is formed on a second sidewall of the first buried cavity Q, the first and second sidewalls being opposite in a second direction (e.g., X-direction) parallel to the core layer 10.

Illustratively, as shown in fig. 6, a substrate of the core layer 10 is provided, cut to a package substrate size, and subjected to surface treatment. As shown in fig. 7, a drilling process is performed on the core layer 10 according to design requirements to form a through hole H and a through groove G, wherein the through hole H and the through groove G penetrate through the core layer 10 in a first direction (i.e., a thickness direction of the core layer 10), and the through groove G may be used to construct a first buried cavity Q, for example, by digging two adjacent through grooves G to construct the first buried cavity Q.

Illustratively, as shown in fig. 8, an electroplating process is performed on the inner walls of the through-holes H and the through-grooves G, forming a plating material layer 110.

In some examples, the first buried cavity Q is drilled through based on two adjacent through slots G. The through groove G is, for example, a rectangular mechanical through hole, four corners of the through groove G are chamfered, and the chamfer radius thereof is, for example, >0.5mm. After the inner walls of the adjacent two through grooves G are formed with the plating material layer 110, as shown in fig. 9, the material of the core layer 10 in the region between the adjacent two through grooves G is removed by a drilling process, so that the adjacent two through grooves G are communicated to form the first buried cavity Q, and the plating material layer on the left side wall in the left through groove G may be reserved as the first plating layer 404, the plating material layer on the right side wall in the right through groove G may be reserved as the second plating layer 405, or the plating material layer on the right side wall in the right through groove G may be reserved as the first plating layer 404, and the plating material layer on the left side wall in the left through groove G may be reserved as the second plating layer 405.

Illustratively, as shown in FIG. 10, after the first buried cavity Q is formed, the drilling debris is washed, and then a resin plug hole plating and filling process is performed on the through hole H, a Plate Over FILLED VIA (POFV) 50 can be obtained, the Plate Over hole 50 including a plated sidewall 501 composed of the plating material layer 110 remaining in the through hole H, and a filling layer 502 covering the plated sidewall 501 and filling the through hole H.

In step S310, referring to fig. 11, a first power layer 20 and a second power layer 30 are respectively formed on the upper and lower sides of the core layer 10.

Illustratively, the first power layer 20 and the second power layer 30 are copper-clad layers on the upper and lower sides of the core layer 10, respectively.

Illustratively, as shown in fig. 11, an auxiliary support structure 120 is provided, and the surface of the area of the auxiliary support structure 120 facing the first buried cavity Q is subjected to surface treatment such as polishing. The auxiliary support structure 120 is then placed under the second power plane 30 for load bearing support.

In step S220, referring to fig. 12 to 18, a plurality of insulating dielectric layers 403 and a plurality of conductive dielectric layers are alternately stacked in the first buried cavity Q, such that the conductive dielectric layers electrically connected to the first plating layer 404 and spaced apart from the second plating layer 405 form a first conductive layer 401, and such that the conductive dielectric layers electrically connected to the second plating layer 405 and spaced apart from the first plating layer 404 form a second conductive layer 402.

Here, the upper and lower surfaces and the left and right side walls of the package substrate can be exchanged by matching the placement orientation of the package substrate. In fig. 12 to 19, taking the first power layer 20 on the upper surface of the package substrate, the second power layer 30 on the lower surface of the package substrate, the first plating layer 404 on the right side wall of the first embedded cavity Q, and the second plating layer 405 on the left side wall of the first embedded cavity Q as an example, the package substrate is carried on the auxiliary supporting structure 120.

Illustratively, as shown in fig. 12, a first insulating dielectric layer 403 is formed on the surface of the auxiliary support structure 120 exposed within the first buried cavity Q. Then, the surface treatment is performed on the first insulating dielectric layer 403, a copper layer with uniform thickness may be deposited on the surface of the first insulating dielectric layer 403, that is, a copper seed layer may be formed first by means of electroless copper plating, so as to ensure that the electroplating process is successfully performed on the insulating dielectric layer 403 subsequently, thereby forming a corresponding conductive layer. Thereafter, as shown in fig. 13, a copper layer is electroplated on the insulating dielectric layer 403, for example, to form a first layer of a second conductive layer 402, the second conductive layer 402 being connected to the sidewalls of the second electroplated layer 405 with a space therebetween to the sidewalls of the first electroplated layer 404. As shown in fig. 14, the insulating dielectric layer 403 is continuously filled, and a copper seed layer (not shown in fig. 14) may be formed on the insulating dielectric layer 403. As shown in fig. 15, a copper layer is electroplated on the insulating dielectric layer 403, for example, to form a first layer of a first conductive layer 401, the first conductive layer 401 being connected to the sidewalls of the first electroplated layer 404 and having a space from the sidewalls of the second electroplated layer 405. As shown in fig. 16, the insulating dielectric layer 403 is continuously filled, and a copper seed layer (not shown in fig. 16) may be formed on the insulating dielectric layer 403. As shown in fig. 17, a copper layer is electroplated on the insulating dielectric layer 403, for example, to form a second conductive layer 402, the second conductive layer 402 being connected to the sidewalls of the second electroplated layer 405 with a space therebetween from the sidewalls of the first electroplated layer 404. As such, as shown in fig. 18, the filling of the insulating dielectric layer 403 and the plating of the conductive layer are repeated a plurality of times, and may be stopped after the surface of the top insulating dielectric layer 403 is flush (in the same plane) with the upper surface of the core layer 10.

Optionally, each first conductive layer 401 is electrically connected to the power supply voltage network in the first power supply layer 20 and the second power supply layer 30 through the first plating layer 404, and each second conductive layer 402 is electrically connected to the ground voltage network in the first power supply layer 20 and the second power supply layer 30 through the second plating layer 405.

In step S230, referring to fig. 19, a first electrode plate 406 is formed on the side of the core layer 10 with the first power layer 20, and the first electrode plate 406 is electrically connected to the first power layer 20.

Illustratively, the exposed dielectric layer 403 within the first buried cavity Q may be surface treated, such as by electroless copper plating, to form a copper seed layer and then electroplating to form the first plate 406. The first plate 406 is, for example, an electroplated copper layer.

Optionally, the first electrode 406 is electrically connected to a supply voltage network in the first power layer 20.

Optionally, the thickness of the film layer of the first polar plate 406 is the same as the thickness of the film layer of the first power layer 20, i.e. the upper surface of the first polar plate 406 is flush (in the same plane) with the upper surface of the first power layer 20.

Optionally, the orthographic projection of the first plate 406 in the first direction (e.g., Z-direction) coincides with the orthographic projection of the first conductive layer 401 in the first direction (e.g., Z-direction). Accordingly, after the first plate 406 is formed, the insulating dielectric layer 403 may be continuously filled in the space between the outer side of the sidewall of the first plate 406 and the first power supply layer 20.

In step S240, referring to fig. 20 to 22, a second plate 407 is formed on the side of the core layer 10 with the second power layer 30, and the second plate 407 is electrically connected to the second power layer 30.

Illustratively, as shown in fig. 20, the auxiliary support structure 120 is removed, and then the package substrate is flipped over such that the second power layer 30 is located on the upper side of the package substrate, and the exposed upper surface of the first insulating dielectric layer 403 is polished to ensure that the upper surface of the insulating dielectric layer 403 is flush (in the same plane) with the upper surface of the second power layer 30. As shown in fig. 21, the insulating dielectric layer 403 is etched back to form an opening K. The bottom surface of the opening K is flush with the top surface of the core layer 10, for example, and the opening K is used for accommodating the second plate 407. As shown in fig. 22, the insulating dielectric layer 403 exposed by the opening K may be first surface treated, for example, by electroless copper plating to form a copper seed layer, and then electroplating to form the second plate 407. The second plate 407 is, for example, an electroplated copper layer.

Optionally, the second plate 407 is electrically connected to a supply voltage network in the second power plane 30.

Optionally, the thickness of the film layer of the second plate 407 is the same as the thickness of the film layer of the second power layer 30, i.e. the upper surface of the second plate 407 is flush (in the same plane) with the upper surface of the second power layer 30.

Optionally, the orthographic projection of the second plate 407 in the first direction (e.g., Z-direction) coincides with the orthographic projection of the first conductive layer 401 in the first direction (e.g., Z-direction). Accordingly, after forming the second plate 407, the insulating dielectric layer 403 may continue to fill in the space between the outside of the sidewall of the second plate 407 and the second power supply layer 30.

It should be noted that, in some embodiments of the present disclosure, referring to fig. 23, the method for manufacturing a package substrate may further include the following steps S320 and S400.

S320, respectively patterning the first power layer and the second power layer.

S400, forming a rewiring structure on one side of the first power layer, which is away from the core layer, and/or one side of the second power layer, which is away from the core layer.

In some embodiments of the present disclosure, referring to fig. 24, the method for manufacturing a package substrate may further include the following steps S500 and S600.

S500, at least one second buried cavity is formed in the rerouting structure.

And S600, forming a second impedance adjusting structure in the second embedded cavity, wherein the second impedance adjusting structure comprises a plurality of third conductive layers and a plurality of fourth conductive layers which are alternately and alternately stacked at intervals along the first direction, any adjacent third conductive layer and fourth conductive layer are insulated, and the plurality of third conductive layers and the plurality of fourth conductive layers are respectively and electrically connected with adjacent power supply layers.

It should be understood that, although the steps in the flowcharts related to the embodiments described above are sequentially shown as indicated by arrows, these steps are not necessarily sequentially performed in the order indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least some of the steps in the flowcharts described in the above embodiments may include a plurality of steps or a plurality of stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of the steps or stages is not necessarily performed sequentially, but may be performed alternately or alternately with at least some of the other steps or stages.

In order to more clearly illustrate the manufacturing method of the package substrate provided in the embodiment of the present disclosure, the following exemplary expressions are given to steps S320 and S400 in the manufacturing method shown in fig. 23 in conjunction with fig. 25 to 29 and fig. 2.

In step S320, referring to fig. 25, the first power layer 20 and the second power layer 30 are patterned respectively.

Illustratively, dry films (Dry films) are formed on surfaces of the first and second power supply layers 20 and 30, respectively, and then exposed and developed, such that the patterned Dry films may be used as masks to pattern the corresponding power supply layers.

In step S400, referring to fig. 26 to 29 and fig. 2, a redistribution structure 60 is formed on a side of the first power layer 20 facing away from the core layer 10 and/or a side of the second power layer 30 facing away from the core layer 10.

Fig. 26 to 29 illustrate examples in which the rerouting structure 60 is formed on both the side of the first power layer 20 facing away from the core layer 10 and the side of the second power layer 30 facing away from the core layer 10. The rewiring structure 60 is constituted by alternately laminating a plurality of isolation pattern layers 601 and a plurality of conductive pattern layers 602, for example. The isolation pattern layer 601 is, for example, an ABF (Ajinomoto Build-up Film) pattern layer, and the conductive pattern layer 602 is, for example, a copper pattern layer.

Illustratively, as shown in fig. 26, the insulating material layer 610 is laminated on the surfaces of the first power supply layer 20 and the second power supply layer 30, respectively. As shown in fig. 27, the isolation material layer 610 is patterned, forming an isolation pattern layer 601. Alternatively, a laser hole may be formed in the isolation material layer 610 by means of laser light to form the isolation pattern layer 601.

Thereafter, as shown in fig. 28, a conductive material layer 620 may be deposited and/or electroplated on the surface of the isolation pattern layer 601 (including within the laser holes). As shown in fig. 29, the conductive material layer 620 is patterned to form a conductive pattern layer 602. Alternatively, the conductive material layer 620 is, for example, an electroplated copper layer. In some examples, the surface roughness of the isolation pattern layer 601 (including in the laser holes) may be treated and the copper seed layer may be formed by electroless copper plating, then the conductive material layer 620 may be formed by electroplating, and then the conductive material layer 620 may be patterned, or in other examples, the copper seed layer may be patterned to form an initial pattern profile of the conductive pattern layer 602 after the copper seed layer is formed, and then the copper material may be electroplated to a target thickness to obtain the conductive pattern layer 602.

Illustratively, patterning the conductive material layer 620 or the patterned copper seed layer may be performed by forming a dry film on a material surface and then exposing and developing the dry film, which may be used as a mask to pattern a corresponding material.

It should be added that after the conductive pattern layer 602 is formed, a stripping process and a rapid etching process (including but not limited to a cleaning process) may be performed to ensure that excess glue film and copper dust are removed.

Based on this, the above-described preparation process of the isolation pattern layer 601 and the conductive pattern layer 602 may be repeated to alternately laminate the isolation pattern layer 601 and the conductive pattern layer 602 of the target number of layers by performing the layer addition a plurality of times as required, thereby obtaining the rerouting structure 60 of the package substrate as shown in fig. 2. In addition, before each lamination of the isolation material layer 610, the surface of the conductive pattern layer 602 needs to be subjected to roughness treatment, so as to ensure that the isolation material layer 610 can be better laminated and connected with the conductive pattern layer 602 in the lamination process, thereby being beneficial to improving the reliability of the rerouting structure 60 and the package substrate.

It is understood that in S500 and S600, the formation of the second buried cavity in the re-wiring structure and the formation of the second impedance adjusting structure may be performed correspondingly to the formation of the first buried cavity in the core layer and the formation of the first impedance adjusting structure in some embodiments described above, which are not described herein.

It should be noted that, as will be understood with reference to fig. 3, after the package substrate is formed, a solder mask windowing process may be performed at a position where the redistribution structure 60 needs to be provided with a pad, so as to expose the soldered pad, and the surface treatment of the pad may be performed to protect and strengthen the pad, so as to avoid oxidation of the pad or damage due to stress.

Illustratively, the plurality of pads includes, for example, a first pad 603 for connecting to chip 70, a second pad 604 for connecting to printed circuit board 80, and a third pad 605 for connecting to surface mount device 90. Wherein, optionally, the second pad 604 and the first pad 603 are respectively disposed on the upper and lower sides of the package substrate, and the first pad 603 and the third pad 605 are disposed on the same side of the package substrate.

Accordingly, in some examples, micro bump solder balls 702 may be disposed on the first pads 603, and conductive portions (e.g., copper pillars 701) of the chip 70 may be electrically connected to the first pads 603 through the micro bump solder balls 702 to achieve the encapsulation of the chip 70 on the package substrate.

In some examples, solder balls 801 may be provided on the printed circuit board 80 and the second pads 604 may be electrically connected to the printed circuit board 80 through the solder balls 801. Solder balls 801 include, but are not limited to, solder balls.

In some examples, surface mount device 90 may be connected by way of Surface Mount (SMT) on third pad 605. Surface mount device 90 includes, but is not limited to, a surface mount capacitor.

The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the disclosure.

The foregoing examples have expressed only a few embodiments of the present disclosure, which are described in more detail and detail, but are not to be construed as limiting the scope of the present disclosure. It should be noted that variations and modifications can be made by those skilled in the art without departing from the spirit of the disclosure, which are within the scope of the disclosure. Accordingly, the scope of the present disclosure should be determined from the following claims.

Claims

1. A package substrate, comprising:

the core layer is provided with at least one first embedded cavity;

the first power supply layer and the second power supply layer are respectively arranged on the upper side and the lower side of the core layer;

The first impedance adjusting structure is arranged in the first embedded cavity and comprises a plurality of first conductive layers and a plurality of second conductive layers which are alternately and alternately stacked at intervals along a first direction perpendicular to the core layer, and any adjacent first conductive layers and second conductive layers are insulated;

Wherein the first plurality of conductive layers is electrically connected to at least one of the first power supply layer and the second power supply layer, and the second plurality of conductive layers is electrically connected to at least one of the first power supply layer and the second power supply layer.

2. The package substrate of claim 1, wherein the first impedance adjusting structure further comprises a first plating layer on a first sidewall of the first buried cavity and a second plating layer on a second sidewall of the first buried cavity;

the first side wall and the second side wall are opposite in a second direction parallel to the core layer, the first electroplated layers are electrically connected with the first conductive layers, a space is arranged between the end, away from the first electroplated layers, of the first conductive layers and the second electroplated layers in the second direction, the second electroplated layers are electrically connected with the second conductive layers, and a space is arranged between the end, away from the second electroplated layers, of the second conductive layers and the first electroplated layers in the second direction.

3. The package substrate of claim 2, wherein the first plating layer and the second plating layer extend in the first direction, wherein a top surface of the first plating layer and a top surface of the second plating layer are in contact with the first power supply layer, respectively, and wherein a bottom surface of the first plating layer and a bottom surface of the second plating layer are in contact with the second power supply layer, respectively.

4. The package substrate of claim 1, wherein the first impedance adjusting structure further comprises a first electrode plate disposed on the same layer as the first power layer and electrically connected to the first power layer, and a second electrode plate disposed on the same layer as the second power layer and electrically connected to the second power layer;

Wherein, the orthographic projection of the first polar plate and the second polar plate along the first direction coincides with the orthographic projection of the first conductive layer along the first direction;

Or, the orthographic projection of the first polar plate and the second polar plate along the first direction is coincident with the orthographic projection of the second conductive layer along the first direction.

5. The package substrate of claim 4, wherein,

The thickness of the film layers of the first polar plate and the first power supply layer is the same;

The thickness of the film layer of the second polar plate is the same as that of the film layer of the second power supply layer.

6. The package substrate of any one of claims 1-5, further comprising a rewiring structure disposed on a side of the first power plane facing away from the core plane and/or on a side of the second power plane facing away from the core plane.

7. The package substrate of claim 6, wherein at least one second embedded cavity is provided in the redistribution structure, the package substrate further comprises a second impedance adjusting structure disposed in the second embedded cavity, the second impedance adjusting structure comprises a plurality of third conductive layers and a plurality of fourth conductive layers alternately stacked at intervals along a first direction perpendicular to the core layer, any adjacent third conductive layers and fourth conductive layers are insulated, and the plurality of third conductive layers and the plurality of fourth conductive layers are electrically connected to adjacent power supply layers, respectively.

8. A method of manufacturing a package substrate, comprising:

preparing a core layer, wherein at least one first embedded cavity is formed in the core layer;

And forming a first power layer and a second power layer on the upper side and the lower side of the core layer respectively, so that the plurality of first conductive layers are electrically connected with at least one of the first power layer and the second power layer, and the plurality of second conductive layers are electrically connected with at least one of the first power layer and the second power layer.

9. The method of manufacturing a package substrate according to claim 8, wherein the first impedance adjusting structure further comprises a first plating layer electrically connected to each of the first conductive layers and a second plating layer electrically connected to each of the second conductive layers;

wherein forming a first impedance adjusting structure in the first buried cavity comprises:

And alternately stacking a plurality of insulating medium layers and a plurality of conductive medium layers in the first embedded cavity, wherein the conductive medium layers electrically connected with the first electroplated layer and spaced from the second electroplated layer form the first conductive layer, and the conductive medium layers electrically connected with the second electroplated layer and spaced from the first electroplated layer form the second conductive layer.

10. The method of manufacturing a package substrate according to claim 9, wherein the first power supply layer and the second power supply layer are formed after the first plating layer is formed on the first sidewall of the first buried cavity, after the second plating layer is formed on the second sidewall of the first buried cavity, and before the plurality of insulating dielectric layers and the plurality of conductive dielectric layers are alternately stacked in the first buried cavity;

the first power supply layer also covers the top surface of the first electroplated layer and the top surface of the second electroplated layer, and the second power supply layer also covers the bottom surface of the first electroplated layer and the bottom surface of the second electroplated layer.

11. The method of manufacturing a package substrate according to claim 8, wherein the first resistance adjustment structure further comprises a first electrode plate co-located with and electrically connected to the first power supply layer and a second electrode plate co-located with and electrically connected to the second power supply layer, wherein after alternately stacking a plurality of insulating dielectric layers and a plurality of conductive dielectric layers in the first buried cavity, the first resistance adjustment structure is formed in the first buried cavity, and further comprising:

Forming the first polar plate on one side of the core layer, which is provided with the first power supply layer, and electrically connecting the first polar plate with the first power supply layer;

Forming the second polar plate on one side of the core layer provided with the second power supply layer, and electrically connecting the second polar plate with the second power supply layer;

12. The method for manufacturing a package substrate according to any one of claims 8 to 11, further comprising:

Patterning the first power layer and the second power layer, respectively;

13. The method of manufacturing a package substrate according to claim 12, further comprising:

forming at least one second buried cavity in the rerouting structure;

and forming a second impedance adjusting structure in the second embedded cavity, wherein the second impedance adjusting structure comprises a plurality of third conductive layers and a plurality of fourth conductive layers which are alternately and alternately stacked at intervals along the first direction, any adjacent third conductive layer and fourth conductive layer are insulated, and the plurality of third conductive layers and the plurality of fourth conductive layers are respectively and electrically connected with adjacent power supply layers.

14. A semiconductor package structure according to any one of claims 1 to 7, comprising a package substrate, and a chip and a printed circuit board respectively packaged on upper and lower sides of the package substrate.

15. The semiconductor package according to claim 14, wherein the chip has a conductive portion, wherein,

An orthographic projection of the first impedance adjusting structure along the first direction overlaps an orthographic projection of the conductive portion along the first direction;

Or, a distance between an orthographic projection of the first impedance adjusting structure along the first direction and an orthographic projection of the conductive portion along the first direction in a direction parallel to the core layer is smaller than a target threshold.