CN120993449B - A Fast Phase Matching Solution System and Method for Rectangular Planar Phased Array Antennas Based on FPGA - Google Patents
A Fast Phase Matching Solution System and Method for Rectangular Planar Phased Array Antennas Based on FPGAInfo
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Abstract
本发明公开了一种基于FPGA的矩形平面相控阵天线快速配相解算系统及方法，涉及相控阵天线波束指向控制技术领域，该方案通过将波束指向控制中的相位求余运算转换为对数值1的归一化处理，并采用行列分步计算架构，在保证相位解算精度的同时大幅降低FPGA资源消耗。利用查表法结合预存储三角函数值实现输入的方位角和俯仰角信息转换为对应的三角函数值，再与对应的频点和阵元间距信息相乘后，得到相邻阵元间相位差信息，通过累加运算，生成行/列相位矩阵后进行组合运算，最终在微秒级完成1024个以上阵元的配相解算。
This invention discloses a fast phase matching solution system and method for rectangular planar phased array antennas based on FPGA, relating to the field of phased array antenna beam pointing control technology. This scheme transforms the phase remainder operation in beam pointing control into a logarithmic normalization process and adopts a row-column step-by-step calculation architecture, significantly reducing FPGA resource consumption while ensuring phase solution accuracy. Using a lookup table method combined with pre-stored trigonometric function values, the input azimuth and elevation angle information is converted into corresponding trigonometric function values. These values are then multiplied by the corresponding frequency point and element spacing information to obtain the phase difference information between adjacent elements. Through accumulation operations, a row/column phase matrix is generated and then combined for calculation, ultimately completing the phase matching solution for more than 1024 elements in microseconds.
Description
Technical Field
The invention relates to the technical field of phased array antenna beam pointing control, in particular to an efficient phase matching solution scheme based on an FPGA, which is suitable for a large-scale rectangular planar phased array antenna in high dynamic application scenes such as low-orbit satellite communication, communication in motion and the like.
Background
With the development of low-orbit satellite communications and 5G/6G networks, terminals are placing demands on phased array antennas for miniaturization, low cost, fast beam switching (in the order of microseconds). The traditional phase matching resolving method based on Digital Signal Processing (DSP) or software is faced with the problems of large calculation amount, high delay, large resource occupation and the like in a large-scale array (more than 1024 array elements, for example), and is difficult to meet the requirement of dynamic satellite tracking.
In the prior art, phase matching calculation needs to calculate the phase difference for each array element independently and perform the residual operation, so that a large number of multipliers and storage units are consumed when the FPGA is realized. For example, a conventional scheme may require N multipliers (N is the number of elements) and trigonometric function look-up table resources increase linearly with array size.
Disclosure of Invention
Aiming at the technical problems, the invention aims to provide an efficient phase matching resolving system and algorithm based on an FPGA, which can obviously reduce hardware resource consumption while guaranteeing microsecond computing speed, and is suitable for a large-scale rectangular plane phased array antenna system with low cost and low power consumption.
In order to achieve the aim of the invention, the technical scheme adopted by the invention is that the rectangular plane phased array antenna rapid phase matching and resolving device based on the FPGA comprises:
input module for receiving beam pointing pitch angle And azimuth angle;
Trigonometric function table look-up module, which adopts symmetrical compression storage strategy to store onlySine and cosine values in the enclosure are expanded to a full period through address mapping, and the method is used for quickly acquiring trigonometric function parameters required by phase calculation;
the row-column decomposition calculation module is used for decomposing the two-dimensional rectangular plane phased array into one-dimensional linear arrays in the directions of an x axis and a y axis, and calculating the phase difference between adjacent array elements according to the pitch angle and the azimuth angle of beam pointing;
The phase difference between adjacent array elements in the x-axis direction is as follows:
(1)
adjacent array element in y-axis direction the phase difference between them is:
(2)
Wherein the method comprises the steps of ,Is the distance between the adjacent array elements,For transmitting signal carrier wavelengths.
The phase accumulation module is used for accumulating adjacent phase differences obtained by column-row decomposition to generate row/column phase vectors and storing the row/column phase vectors, wherein the accumulation operation is expressed as multiplication operation in a formula, and the phase difference between an m-th array element and a 0-coordinate array element in the row vectors is expressed as follows:
(3)
The phase difference between the nth element and the 0-coordinate element in the column vector is expressed as:
(4)
The array element phase calculation module is used for carrying out combination operation according to the row/column phase vector obtained by the phase accumulation module and the formula (5) to obtain a phase value of each array element in the array;
(5)
the residual calculating module converts the traditional residual calculating operation into normalized numerical residual calculating processing of the numerical value 1 so as to simplify the calculation time and the resource consumption of the FPGA.
The traditional calculation phase formula is:
(6)
in calculating the phase according to the nature of the remainder Modulo with subsequent remainder operationThe formula is rewritten, however:
(7)
and the quantization output module is used for carrying out quantization processing on the phase after the remainder according to the bit width of the digital phase shifter and generating an array element phase matching control code.
As a preferred mode of the invention, the row-column decomposition calculation module further comprises a parallel pipeline architecture, which respectively and independently processes phase difference accumulation operation in the x-axis direction and the y-axis direction, and stores intermediate results through a dual-port BRAM to support subsequent array element phase synthesis.
As a preferred mode of the invention, the specific implementation process of the residual module comprises the steps of converting absolute phase values in a formula into normalized coefficients and determining final phase values by calculating a remainder of 1.
As an optimal mode of the invention, the trigonometric function table look-up module adopts 16bit quantization precision, wherein the high order is a sign bit, and the parallel resolving of the phases of multiple array elements is realized through time sequence control.
The invention also provides a resolving method based on the rapid phase matching resolving device, which comprises the following steps:
step one, will 、The input trigonometric function table lookup module obtains the normalized trigonometric function value、And;
Step two, calculating a row direction normalization coefficient according to a formula (10) and a formula (11):
(10)
(11)
Wherein the method comprises the steps of 、The distance between array elements in the row-column direction, c is the speed of light,Is the carrier frequency;
Step three, calculating the phase difference between adjacent array elements in the row/column direction according to the results of the step one and the step two through a formula (12) and a formula (13):
(12)
(13)
Generating a basic phase sequence through a row/column accumulator according to the result of the step three and then according to a formula (14) and a formula (15), and storing the basic phase sequence;
(14)
(15)
Step five, according to the result of step four, carry on the phase synthesis of phase matching to each array element (m, n) according to the formula (16);
(16)
Step six, carrying out remainder of 1 on the synthesized phase to obtain 0-2 pi internal phase;
And step seven, quantizing the phase according to the quantization precision of the phase shifter to obtain a phase shifter control code.
The invention also provides a low-orbit satellite communication terminal antenna system which comprises the FPGA-based rectangular planar phased array antenna rapid phase matching and resolving device, and the configuration meets the technical requirement that the beam pointing switching period is less than or equal to 100ms and the gain is more than or equal to 25 dBi.
Compared with the prior art, the technical scheme provided by the invention has the following technical effects:
1. The phase matching resolving system provided by the invention supports the rectangular plane phased array with the number of the adaptive array elements being more than or equal to 1024 and the single phase matching resolving time being less than or equal to 20 mu s under the condition that the clock frequency is more than or equal to 100 MHz.
2. The invention realizes the hardware optimization of the phase matching resolving system, and utilizes the trigonometric function property to realize the followingIs mapped to the trigonometric function value of (2)And saving 87.5% of storage resources.
3. The invention decomposes phase calculation into the phases of table lookup, multiplication, accumulation, array element synthesis, remainder calculation, quantization and the like, and improves throughput rate.
4. The invention is particularly suitable for the fast beam pointing switching requirement of the low-orbit satellite communication terminal, and meets the requirement of high real-time performance while reducing the hardware cost.
Drawings
Fig. 1 is a block diagram of a rectangular planar phased array antenna phase matching calculation system based on an FPGA in this embodiment.
Fig. 2 is a flow chart of a rectangular planar phased array antenna phase matching calculation method based on an FPGA in this embodiment.
Detailed Description
For a better understanding of the invention, reference will now be made in detail to the drawings and to the accompanying examples.
As shown in fig. 1, a block diagram of a rectangular planar phased array antenna phase matching resolving system based on an FPGA specifically includes:
input module for receiving beam pointing pitch angle And azimuth angle;
Trigonometric function table look-up module, which adopts symmetrical compression storage strategy to store onlySine and cosine values in the range are expanded to a full period through address mapping, and the method is used for quickly acquiring trigonometric function parameters required by phase calculation;
the row-column decomposition calculation module is used for decomposing the two-dimensional rectangular plane phased array into one-dimensional linear arrays in the directions of an x axis and a y axis, and calculating the phase difference between adjacent array elements according to the pitch angle and the azimuth angle of beam pointing;
The phase difference between adjacent array elements in the x-axis direction is as follows:
(1)
adjacent array element in y-axis direction the phase difference between them is:
(2)
Wherein the method comprises the steps of ,Is the distance between the adjacent array elements,For transmitting signal carrier wavelengths.
The phase accumulation module is used for accumulating adjacent phase differences obtained by column-row decomposition to generate row/column phase vectors and storing the row/column phase vectors, wherein the accumulation operation is expressed as multiplication operation in a formula, and the phase difference between an m-th array element and a 0-coordinate array element in the row vectors is expressed as follows:
(3)
The phase difference between the nth element and the 0-coordinate element in the column vector is expressed as:
(4)
The array element phase calculation module is used for carrying out combination operation according to the row/column phase vector obtained by the phase accumulation module and the formula (5) to obtain a phase value of each array element in the array;
(5)
the residual calculating module converts the traditional residual calculating operation into normalized numerical residual calculating processing of the numerical value 1 so as to simplify the calculation time and the resource consumption of the FPGA.
The traditional calculation phase formula is:
(6)
in calculating the phase according to the nature of the remainder Modulo with subsequent remainder operationThe formula is rewritten, however:
(7)
and the quantization output module is used for carrying out quantization processing on the phase after the remainder according to the bit width of the digital phase shifter and generating an array element phase matching control code.
As shown in fig. 2, a flow chart of a rectangular planar phased array antenna phase matching resolving method based on an FPGA specifically includes the following steps:
step one, will 、The input trigonometric function table lookup module obtains the normalized trigonometric function value、And;
Step two, calculating a row direction normalization coefficient according to a formula (10) and a formula (11):
(10)
(11)
Wherein the method comprises the steps of 、The distance between array elements in the row-column direction, c is the speed of light,Is the carrier frequency;
Step three, calculating the phase difference between adjacent array elements in the row/column direction according to the results of the step one and the step two through a formula (12) and a formula (13):
(12)
(13)
Generating a basic phase sequence through a row/column accumulator according to the result of the step three and then according to a formula (14) and a formula (15), and storing the basic phase sequence;
(14)
(15)
Step five, according to the result of step four, carry on the phase synthesis of phase matching to each array element (m, n) according to the formula (16);
(16)
Step six, carrying out remainder of 1 on the synthesized phase to obtain 0-2 pi internal phase;
And step seven, quantizing the phase according to the quantization precision of the phase shifter to obtain a phase shifter control code.
The actual measurement data shows that when the Xilinx Zynq-7045 chip is adopted, only 4 DSP multipliers and 70.5BRAM resources are occupied, the resource amount is small, and the Xilinx Zynq-7045 chip can be transplanted to a low-end FPGA (such as Artix series).
The speed is about 12 for completing 1024 array element phase matching calculation by 100MHz clock。
The expansibility is that the expansion of the array scale is supported by adjusting the bit width of the accumulator, and the expansion can be extended to other polygonal arrays by discarding the calculated value of a specific array element.
The present invention is not limited to the above-mentioned embodiments, and any changes or substitutions that are easily contemplated by those skilled in the art within the scope of the present invention are intended to be included in the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.
Claims (10)
1. The utility model provides a rectangular plane phased array antenna quick phase distribution resolving system based on FPGA which characterized in that includes:
input module for receiving beam pointing pitch angle And azimuth angle;
Trigonometric function table look-up module, which adopts symmetrical compression storage strategy to store onlySine and cosine values in the range are expanded to a full period through address mapping, and the method is used for quickly acquiring trigonometric function parameters required by phase calculation;
the row-column decomposition calculation module is used for decomposing the two-dimensional rectangular plane phased array into one-dimensional linear arrays in the directions of an x axis and a y axis, and calculating the phase difference between adjacent array elements according to the pitch angle and the azimuth angle of beam pointing;
The phase accumulation module is used for accumulating adjacent phase differences obtained by column-row decomposition, generating row/column phase vectors and storing the row/column phase vectors;
the array element phase calculation module is used for carrying out combination operation according to the row/column phase vectors obtained by the phase accumulation module to obtain a phase value of each array element in the array;
The residual calculating module converts the traditional residual calculating operation into normalized value residual calculating operation of 1, and calculates phase according to the residual essence Modulo with subsequent remainder operationCanceling, and rewriting the formula;
and the quantization output module is used for carrying out quantization processing on the phase after the remainder according to the bit width of the digital phase shifter and generating an array element phase matching control code.
2. The fast phase matching and resolving system of a rectangular planar phased array antenna based on an FPGA as claimed in claim 1, wherein in the rank decomposition and computation module, the phase difference between adjacent array elements in the x-axis direction is:
(1);
adjacent array element in y-axis direction the phase difference between them is:
(2);
Wherein the method comprises the steps of ,Is the distance between the adjacent array elements,For transmitting signal carrier wavelengths.
3. The rapid phase matching and resolving system of the rectangular planar phased array antenna based on the FPGA as claimed in claim 2, wherein in the phase accumulation module, accumulation operation is expressed as multiplication operation in a formula, and phase difference between an mth array element and a 0-coordinate array element in a row vector is expressed as:
(3);
The phase difference between the nth element and the 0-coordinate element in the column vector is expressed as:
(4)。
4. the FPGA-based rectangular planar phased array antenna fast phase matching solution system according to claim 3, wherein in the array element phase calculation module, a combination operation is performed according to formula (5):
(5)。
5. The FPGA-based rectangular planar phased array antenna fast phase matching solution system of claim 4, wherein in the residual module, a traditional calculation phase formula is:
(6);
The formula is rewritten as:
(7)。
6. the FPGA-based rectangular planar phased array antenna fast phase matching solution system according to claim 2, wherein the rank decomposition calculation module further comprises a parallel pipeline architecture, and the rank decomposition calculation module independently processes phase difference accumulation operations in the x-axis and y-axis directions, and stores intermediate results through a dual-port BRAM to support subsequent array element phase synthesis.
7. The rapid phase matching and resolving system of the rectangular planar phased array antenna based on the FPGA of claim 5, wherein the specific implementation process of the residual solving module comprises the steps of converting absolute phase values in a formula into normalized coefficients and determining final phase values by calculating remainder of logarithmic value 1.
8. The rapid phase matching and resolving system of the FPGA-based rectangular planar phased array antenna of claim 1, wherein the trigonometric function table look-up module adopts 16bit quantization precision, wherein high order is a sign bit, and the parallel resolving of multiple array element phases is realized through time sequence control.
9. A solution method based on the fast phase matching solution system according to any one of claims 1-8, characterized by comprising the steps of:
step one, will 、The input trigonometric function table lookup module obtains the normalized trigonometric function value、And;
Step two, calculating a row direction normalization coefficient according to a formula (10) and a formula (11):
(10);
(11);
Wherein the method comprises the steps of 、The distance between array elements in the row-column direction, c is the speed of light,Is the carrier frequency;
Step three, calculating the phase difference between adjacent array elements in the row/column direction according to the results of the step one and the step two through a formula (12) and a formula (13):
(12);
(13);
Generating a basic phase sequence through a row/column accumulator according to the result of the step three and then according to a formula (14) and a formula (15), and storing the basic phase sequence;
(14);
(15);
Step five, according to the result of step four, carry on the phase synthesis of phase matching to each array element (m, n) according to the formula (16);
(16);
Step six, carrying out remainder of 1 on the synthesized phase to obtain 0-2 pi internal phase;
And step seven, quantizing the phase according to the quantization precision of the phase shifter to obtain a phase shifter control code.
10. A low-orbit satellite communication terminal antenna system is characterized by comprising the FPGA-based rectangular planar phased array antenna rapid phase matching resolving system according to any one of claims 1-8, wherein the configuration meets the technical requirements that the beam pointing switching period is less than or equal to 100ms and the gain is more than or equal to 25 dBi.
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| CN105204003A (en) * | 2015-09-08 | 2015-12-30 | 四川鸿创电子科技有限公司 | Novel FPGA-based beam steering operation method |
| CN113759777A (en) * | 2021-08-31 | 2021-12-07 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Phased Array Antenna Beam Steering Method |
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| US7260141B2 (en) * | 2001-02-28 | 2007-08-21 | Itt Manufacturing Enterprises, Inc. | Integrated beamformer/modem architecture |
| US7068219B2 (en) * | 2004-06-10 | 2006-06-27 | Harris Corporation | Communications system including phased array antenna providing nulling and related methods |
| CN120560606A (en) * | 2025-05-26 | 2025-08-29 | 湖南斯北图科技有限公司 | Phase calculation method and device for phased array antenna based on programmable logic gate array |
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| CN105204003A (en) * | 2015-09-08 | 2015-12-30 | 四川鸿创电子科技有限公司 | Novel FPGA-based beam steering operation method |
| CN113759777A (en) * | 2021-08-31 | 2021-12-07 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Phased Array Antenna Beam Steering Method |
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