CN120895070A - A 2T2FC ferroelectric memory cell and its fabrication method - Google Patents
A 2T2FC ferroelectric memory cell and its fabrication methodInfo
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- CN120895070A CN120895070A CN202511066282.XA CN202511066282A CN120895070A CN 120895070 A CN120895070 A CN 120895070A CN 202511066282 A CN202511066282 A CN 202511066282A CN 120895070 A CN120895070 A CN 120895070A
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- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
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- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
- G11C11/221—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements using ferroelectric capacitors
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- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
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Abstract
本申请公开了一种2T2FC铁电存储单元及其制备方法，其中，所述2T2FC铁电存储单元包括：存储晶体管；控制晶体管，其源极连接至所述存储晶体管漏极；第一铁电电容器，其一端连接第一板线，另一端耦合至所述存储晶体管栅极；第二铁电电容器，其一端连接第二板线，另一端耦合至所述存储晶体管栅极；字线，连接至所述存储晶体管栅极；位线，连接至所述控制晶体管漏极；源线，连接至所述存储晶体管源极；控制线，连接至所述控制晶体管栅极；所述控制晶体管配置为选择性启用或禁用对所述存储晶体管的访问。本申请通过采用一个存储晶体管和一个控制晶体管，实现存储路径与控制路径分离，提高了数据读写的可靠性，同时减少了漏电流并增大内存。
This application discloses a 2T2FC ferroelectric memory cell and its fabrication method. The 2T2FC ferroelectric memory cell includes: a storage transistor; a control transistor, the source of which is connected to the drain of the storage transistor; a first ferroelectric capacitor, one end of which is connected to a first plate line and the other end coupled to the gate of the storage transistor; a second ferroelectric capacitor, one end of which is connected to a second plate line and the other end coupled to the gate of the storage transistor; a word line connected to the gate of the storage transistor; a bit line connected to the drain of the control transistor; a source line connected to the source of the storage transistor; and a control line connected to the gate of the control transistor. The control transistor is configured to selectively enable or disable access to the storage transistor. This application achieves separation of the storage path and the control path by employing one storage transistor and one control transistor, improving the reliability of data read/write operations while reducing leakage current and increasing memory capacity.
Description
Technical Field
The application relates to the technical field of ferroelectric memories, in particular to a 2T2FC ferroelectric memory cell and a preparation method thereof.
Background
Emerging AI (artificial intelligence) and neuromorphic computing architectures require memory with fast, non-volatile, in-memory computing capabilities. The ferroelectric Memory (frim, ferroelectric RAM) is used as a new Non-Volatile Memory (NVM) capable of capturing and storing critical data immediately upon power interruption, and is very suitable for mission critical data recording applications, and the ferroelectric Memory is designed to be low-power consumption and miniaturized, and can provide instant Non-Volatile and almost infinite endurance without affecting speed or energy efficiency.
Existing ferroelectric memories rely primarily on ferroelectric field effect transistor (FeFET) architecture to provide promising non-volatile characteristics, but suffer from data retention degradation and scalability limitations due to the polarization shielding effect and process compatibility limitations of fefets.
Disclosure of Invention
In order to solve the defects in the prior art, the application aims to provide a 2T2FC ferroelectric memory cell and a preparation method thereof, and the two transistors and the two ferroelectric capacitors are adopted, so that the data retention capacity and the durability are improved, and meanwhile, the 2T2FC ferroelectric memory cell is compatible with advanced CMOS process nodes.
To achieve the above object, the present application provides a 2T2FC ferroelectric memory cell comprising:
a memory transistor;
A control transistor having a source connected to the drain of the memory transistor;
a first ferroelectric capacitor having one end connected to a first plate line and the other end coupled to the gate of the memory transistor;
a second ferroelectric capacitor having one end connected to a second plate line and the other end coupled to the gate of the memory transistor;
a word line connected to the memory transistor gate;
a bit line connected to the drain of the control transistor;
A source line connected to the memory transistor source;
A control line connected to the control transistor gate;
the control transistor is configured to selectively enable or disable access to the storage transistor.
Further, the polarization state of the ferroelectric capacitor is modulated by applying voltages of opposite polarities to the first ferroelectric capacitor and the second ferroelectric capacitor to switch the encoded logic state.
Further, when the 2T2FC ferroelectric memory cell writes a logic "1", a positive polarization voltage is applied to the first ferroelectric capacitor so that the polarization direction thereof faces the memory transistor gate, and a negative polarization voltage is applied to the second ferroelectric capacitor so that the polarization direction thereof faces away from the memory transistor gate.
Further, when the 2T2FC ferroelectric memory cell writes a logic "0", a negative polarization voltage is applied to the first ferroelectric capacitor so that the polarization direction thereof is away from the gate of the memory transistor, and a positive polarization voltage is applied to the second ferroelectric capacitor so that the polarization direction thereof is directed toward the gate of the memory transistor.
Further, the 2T2FC ferroelectric memory cell drives the word line, the control line, the bit line, the source line, the first plate line, and the second plate line to 0V after writing logic to prevent charge leakage of the ferroelectric capacitor from causing data degradation.
Further, when the 2T2FC ferroelectric memory cell reads data:
Enabling the control transistor through the control line;
Applying a read voltage to one of the first and second plate lines and maintaining the other of the first and second plate lines to ground;
applying a read bias voltage to the bit line;
and judging the stored logic state according to the detected drain current of the storage transistor.
Further, the basis for determining the logic state is that a high current represents a logic "1" and a low current represents a logic "0";
The high current refers to drain current detected by the storage transistor when the gate voltage exceeds a threshold voltage and a channel forms a conductive path;
the low current refers to a drain current detected by the memory transistor when a gate voltage is below a threshold voltage and a channel does not form a conductive path.
Further, after the 2T2FC ferroelectric memory cell reads data, the word line, the control line, the bit line, the source line, the first plate line, and the second plate line are all driven to 0V to discharge, and the residual gate charges are eliminated, so as to prevent data read interference or long-term data retention degradation.
In order to achieve the above purpose, the present application also provides a method for preparing a 2T2FC ferroelectric memory cell, comprising the steps of:
sequentially depositing a gate oxide layer, a high-dielectric constant dielectric layer and a gate metal layer on a silicon substrate to form a gate stack of a storage transistor and a control transistor respectively;
Forming a source diffusion region and a drain diffusion region on the silicon substrate through ion implantation and activation, respectively;
respectively depositing an interlayer dielectric layer on the source diffusion region and the drain diffusion region;
symmetrically forming two ferroelectric capacitors on two sides of a gate stack of the memory transistor;
The two ferroelectric capacitors are connected to a plate line.
Further, after the forming of the gate stacks of the memory transistor and the control transistor, a step of forming a word line and a control line is further included.
Further, after the depositing the interlayer dielectric layer, the method further comprises the step of forming a bit line and a source line.
Further, the step of symmetrically forming two ferroelectric capacitors on both sides of the gate stack of the memory transistor further comprises:
Sequentially depositing a TiN bottom electrode, a ferroelectric layer and a TiN top electrode on two sides of the grid metal layer to form a first ferroelectric capacitor and a second ferroelectric capacitor which are symmetrical,
The ferroelectric layer is formed by atomic layer deposition, and the TiN bottom electrode and the TiN top electrode are formed by plasma enhanced atomic layer deposition.
Further, the 2T2FC ferroelectric memory cell is patterned into a layout that occupies an 8F2 area, where F is the minimum feature size of the fabrication process node.
In order to achieve the above object, the present application also provides a 2T2FC ferroelectric memory cell obtained according to the preparation method as described above.
To achieve the above object, the present application also provides a memory array including a plurality of the 2T2FC ferroelectric memory cells as described above.
Further, a write control unit configured to apply multi-step gradation voltages to the plate lines and the word lines of the 2T2FC ferroelectric memory cells to selectively program a target cell and prevent disturbance of half selected cells is also included.
To achieve the above object, the present application also provides an AI chip including the memory array as described above.
According to the 2T2FC ferroelectric memory unit provided by the application, the separation of the memory path and the control path is realized by adopting one memory transistor and one control transistor, so that the reliability of data reading and writing is improved, and meanwhile, the leakage current is reduced and the memory is increased.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application.
Drawings
The accompanying drawings are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate the application and together with the embodiments of the application, and do not limit the application. In the drawings:
FIG. 1 is a schematic diagram of a 2T2FC ferroelectric memory cell according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a differential write logic value according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a read logic according to an embodiment of the present application;
FIG. 4 is a flow chart of a method of fabricating a 2T2FC ferroelectric memory cell according to an embodiment of the present application;
FIG. 5 is a schematic view of an active device region according to an embodiment of the present application;
FIG. 6 is a schematic diagram of a gate stack according to an embodiment of the present application;
FIG. 7 is a schematic diagram illustrating formation of an interlayer dielectric layer and a contact hole according to an embodiment of the present application;
FIG. 8 is a schematic diagram of bit line and source line contact formation in accordance with an embodiment of the present application;
FIG. 9 is a schematic diagram of a contact hole of a patterned ferroelectric capacitor on a gate according to an embodiment of the present application;
fig. 10 is a schematic diagram of a common bottom metal pad for forming a ferroelectric capacitor according to an embodiment of the present application;
fig. 11 is a schematic diagram of a stacked structure of a ferroelectric capacitor according to an embodiment of the present application;
FIG. 12 is a schematic view of a resulting plate line according to an embodiment of the present application;
FIG. 13 is a first stage schematic of a memory array writing a "0" according to some embodiments of the application;
FIG. 14 is a second stage schematic of a memory array writing a "0" according to some embodiments of the application;
FIG. 15 is a first stage schematic of a memory array writing a "1" according to some embodiments of the application;
FIG. 16 is a second stage schematic of a memory array writing a "1" according to some embodiments of the application;
FIG. 17 is a schematic diagram of a first stage of writing a "0" to a memory array according to other embodiments of the application;
FIG. 18 is a second stage of writing a "0" to the memory array according to other embodiments of the application;
FIG. 19 is a schematic diagram of a first stage of writing a "1" to a memory array according to other embodiments of the application;
FIG. 20 is a second phase diagram of writing a "1" to a memory array according to other embodiments of the application;
FIG. 21 is a schematic diagram of a first stage of reading data from a memory array according to other embodiments of the application;
FIG. 22 is a second stage of reading data from the memory array according to other embodiments of the application.
Reference numerals:
401-active device region, 402-oxide, 403-gate oxide, 404-high k dielectric layer, 405-TiN gate electrode, 406-source diffusion region, 407-drain source diffusion region, 408-drain diffusion region, 409-contact hole, 410-common bottom metal pad, 411-TiN bottom electrode, 412-ferroelectric layer, 413-TiN top electrode, 414, 415-plate line.
Detailed Description
The preferred embodiments of the present application will be described below with reference to the accompanying drawings, it being understood that the preferred embodiments described herein are for illustration and explanation of the present application only, and are not intended to limit the present application.
Embodiments of the present application will be described in more detail below with reference to the accompanying drawings. While the application is susceptible of embodiment in the drawings, it is to be understood that the application may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but rather are provided to provide a more thorough and complete understanding of the application. It should be understood that the drawings and embodiments of the application are for illustration purposes only and are not intended to limit the scope of the present application.
The term "including" and variations thereof as used herein are intended to be open-ended, i.e., including, but not limited to. The term "based on" is based at least in part on. The term "one embodiment" means "at least one embodiment," another embodiment "means" at least one additional embodiment, "and" some embodiments "means" at least some embodiments. Related definitions of other terms will be given in the description below.
It should be noted that the concepts of "first," "second," etc. may be used in the present application merely to distinguish between different devices, components or sections and are not intended to limit the order or interdependence of functions performed by these devices, components or sections.
It should be noted that the modifications of "a" and "an" as may be mentioned in the present disclosure are illustrative rather than limiting, and those of ordinary skill in the art will appreciate that "one or more" should be understood to mean "one or more" unless the context clearly indicates otherwise. "plurality" is understood to mean two or more.
The following terms may be mentioned in the present application:
2T2FC (two transistors and two ferroelectric capacitors) ferroelectric memory cell comprising 2 transistors and 2 ferroelectric capacitors;
CFA, first ferroelectric capacitor;
CFB, a second ferroelectric capacitor;
PL (Plate Line) plate wires connected with the plates of the ferroelectric capacitor and used for transmitting read-write voltage;
ML (Metal Line) a metal line connected to the bottom electrode of the ferroelectric capacitor;
CT (Control Transistor) a control transistor to enable or disable access to the storage path;
ST (Storage Transistor) a memory transistor as a primary switch for storing and sensing (sensing) memory states;
PLA, first plate line;
PLB, second plate line;
WL (Word Line) Word Line connected to the gate of the memory transistor for controlling the on and off of the memory transistor;
BL (Bit Line), a wire connected with the drain electrode of the control transistor, a channel for data reading;
SL (Source Line) a source line connected with a lead of the source electrode of the storage transistor and used as a current loop or a voltage reference line to finish data read-write operation in cooperation with the bit line;
CL (Control Line) a control line connected with the wire of the grid electrode of the control transistor and used for controlling the on and off of the control transistor;
+Vpp, positive polarization voltage;
-Vpp negative polarization voltage.
Related definitions of other terms will be given in the description below.
Example 1
In an embodiment of the application, a 2T2FC ferroelectric memory cell is provided, comprising a memory transistor, a control transistor, a first ferroelectric capacitor, a second ferroelectric capacitor, a word line, a bit line, a source line, a control line and a control transistor, wherein the source electrode of the control transistor is connected to the drain electrode of the memory transistor, one end of the first ferroelectric capacitor is connected with a first plate line, the other end of the first ferroelectric capacitor is coupled to the gate electrode of the memory transistor, one end of the second ferroelectric capacitor is connected with a second plate line, the other end of the second ferroelectric capacitor is coupled to the gate electrode of the memory transistor, the word line is connected to the gate electrode of the memory transistor, the bit line is connected to the drain electrode of the control transistor, the source line is connected to the source electrode of the memory transistor, the control line is connected to the gate electrode of the control transistor, and the control transistor is configured to selectively enable or disable access to the memory transistor.
Fig. 1 is a schematic diagram of a 2T2FC ferroelectric memory cell according to an embodiment of the present application, as shown in fig. 1, the 2T2FC ferroelectric memory cell of the present application includes a memory transistor ST, a control transistor CT coupled to the memory transistor ST, and two planar ferroelectric capacitors (FeCAPs) respectively a first ferroelectric capacitor CFA and a second ferroelectric capacitor CFB. One ends of the CFA and the CFB are coupled to the gate of the storage transistor ST, and the other ends are connected to the first plate line PLA and the second plate line PLB, respectively. The source of the control transistor CT is connected to the drain of the storage transistor ST, the drain is connected to the bit line BL, and the gate is connected to the control line CL. The memory transistor ST has a gate connected to the word line WL and a source connected to the source line SL.
In an embodiment of the present application, the memory transistor ST serves as an important switch for storing and sensing (sensing) the memory state, and the logic state is distinguished by using a threshold voltage change caused by ferroelectric polarization in the memory transistor ST. The control transistor CT is used to gate the access to the storage path, and is configured to selectively enable or disable the access to the storage transistor ST, so as to separate the storage path from the control path, support the independent control access and the data retention, and suppress leakage in standby and half-selected states. At the same time, the endurance and data retention of the memory cell is improved due to reduced stress on the gate dielectric layer (GATE DIELECTRIC) of the individual transistors. The memory transistor ST and the control transistor CT are used to support a larger memory capacity while reducing leakage current.
In an embodiment of the application, the encoded logic state is switched by modulating the polarization state of the ferroelectric capacitor. By applying voltages of opposite polarities to the two ferroelectric capacitors, the two ferroelectric capacitors are reversely polarized, thereby generating different electric fields at the gate of the storage transistor ST to modulate the threshold voltage, thereby affecting the on-current in the write operation. For example, when writing a logic "1", +vpp is applied to the PLB to make the CFB polarization direction upward (away from the memory transistor ST gate), +vpp is applied to the PLA to make the CFA polarization direction downward (toward the memory transistor ST gate), and when writing a logic "0", +vpp is applied to the PLB, and +vpp is applied to the PLA to generate a polarization state opposite to that when writing a logic "1". In reading data, a read voltage is applied to the plate line connected to one ferroelectric capacitor while the plate line connected to the other ferroelectric capacitor is grounded, a current is caused to flow through the memory transistor ST by activating the control line CL, and a memory logic state is judged based on the detected bit line current. For example, a high current level (channel on) or a low current level (channel off) reflects that the stored logic state based on the differential polarization condition is a "1" or a "0". This differential polarization scheme improves noise immunity, read accuracy, and is suitable for multi-bit storage levels of AI (artificial intelligence) related workloads (workloads).
Fig. 2 is a schematic diagram of differential write logic values according to an embodiment of the present application, as shown in fig. 2, storing binary data by differential polarization of two ferroelectric capacitors, involving applying high positive and negative voltage pulses to plate lines (PLA and PLB), in the following manner:
logic "0" is written by applying +Vpp to the CFB to polarize it downward, and "1" is written by applying-Vpp to the CFA to polarize it upward.
A logical "1" is written by writing a "1" to the CFB, applying-Vpp to polarize it upward, and a "0" is written to the CFA, applying +Vpp to polarize it downward.
This configuration of the dual ferroelectric capacitor achieves a high sensing margin by distinguishing logic states using polarization induced threshold voltage difference changes (shift) in the memory transistor. The polarization state of the dual ferroelectric capacitor is maintained at power-off, enabling non-volatile storage.
In embodiments of the present application, 2T2FC ferroelectric memory cells can be accessed in a multi-step voltage fashion to optimize write operations, such as step-wise application of partial voltages (e.g., ±2/3Vpp, ±1/3 Vpp), avoiding write disturb to unselected and half-selected cells in a large memory array.
In an embodiment of the present application, to prevent charge leakage of CFA and CFB after writing of a 2T2FC ferroelectric memory cell from causing data degradation, a post-writing zeroing scheme is employed in which all active terminals, i.e., word line WL, bit line BL, source line SL, first plate line PLA, second plate line PLB, and control line CL are driven to 0V. This state is maintained prior to the read operation to ensure that all stored charges remain intact. This approach eliminates capacitive memory effects (CAPACITIVE MEMORY EFFECTS) that may affect subsequent read accuracy or lead to long-term retention loss (induce long-term retention loss).
In the embodiment of the present application, a word line WL (applied voltage less than 1.2V) connected to the gate of the memory transistor ST is used for current sensing (current sensing). A high current (on) indicates that the polarization configuration results in a low effective threshold voltage, and a low current (off) indicates that the reverse polarization configuration results in a high threshold voltage. When writing a logic value, the two ferroelectric capacitors represent logic states "0" and "1" in opposite polarities. When reading data, the current through the memory transistor ST is detected, a high current representing a logic "1", and a low current representing a logic "0". The high current refers to the drain current of the memory transistor ST when the gate voltage exceeds the threshold voltage and the channel forms a conductive path, and the low current refers to the drain current of the memory transistor ST when the gate voltage is lower than the threshold voltage and the channel does not form a conductive path. This current-based read scheme is reliable, supports differential sensing, and is scalable to support multi-level cell (MLC) behavior.
In the embodiment of the present application, when the control line CL is activated, the control transistor CT is turned on to form a current path of the bit line bl→the control transistor ct→the storage transistor st→the source line SL. The turn-on level of the memory transistor ST is determined by its gate voltage (modulated by the polarization state of FeCAPs), and finally controls the current of the whole loop.
In the embodiment of the application, the data of the 2T2FC ferroelectric memory cell is read by judging the logic state based on current detection (current-based sensing) through a memory transistor ST, and the reading steps are as follows:
Enabling the control transistor CT by activating the control line CL;
Applying a small read voltage (Vread) of 0.7v to 0.9v to one of the plate lines (e.g., PLB);
Grounding another plate line (e.g., PLA) to establish a voltage gradient;
floating the memory transistor ST gate, making it affected by the net polarization states of CFA and CFB;
applying a read bias voltage (0.2V to 0.7V in this embodiment) to the bit line BL;
The logic state is determined based on the measured drain current of the memory transistor ST.
FIG. 3 is a schematic diagram of reading logic values according to an embodiment of the present application, as shown in FIG. 3:
During reading, vread (read voltage) is applied to PLB, PLA is held at ground (0V), vd (0.2V to 0.7V) is applied to BL, and logic state "0" or "1" is read according to drain current of the memory transistor ST. During reading, the 2T2FC ferroelectric memory cell operates as a ferroelectric field effect transistor (floating gate), which detects the drain current generated by the gate modulation, +vpp generates a high current (on state), -Vpp generates a low current (off state), and thus determines the stored logic state.
In an embodiment of the present application, in order to prevent the data degradation caused by the residual charges of the gate or floating node after the 2T2FC ferroelectric memory cell is read, a post-read discharging scheme is adopted in which all active terminals, i.e., word line WL, bit line BL, source line SL, first plate line PLA, second plate line PLB and control line CL are driven to 0V. This state is maintained for a period of time to ensure that all stored charge is neutralized. This approach eliminates capacitive memory effects that may affect subsequent reads or lead to long-term retention loss.
In embodiments of the present application, 2T2FC ferroelectric memory cells are compatible with standard CMOS Back End of Line (BEOL). The ferroelectric capacitor is designed to be stacked on top of the logic device, using materials and layers commonly found in back-end-of-line processes, for example, by forming TiN electrodes by Plasma Enhanced Atomic Layer Deposition (PEALD), by forming ferroelectric HfZrO 2 (HZO) layers by Atomic Layer Deposition (ALD) (see fig. 1). In combination with Shallow Trench Isolation (STI) and standard gate-first transistor processes in front-end-of-line (Front End Of Line, FEOL), the final cell occupies an area of 8F2 (2f×4f), where F is the minimum feature size of the technology node. This makes the 2T2FC ferroelectric memory cell highly scalable, suitable for integration into CMOS nodes of 22nm, 14nm or even below 10 nm.
In the embodiment of the application, two ferroelectric capacitors are positioned at two sides of the grid electrode of the storage transistor ST and are made of high-k ferroelectric materials. A plate (PLATE TERMINALS) on top of the two ferroelectric capacitors is connected to PLA and PLB, respectively, for passing write and read voltages.
The 2T2FC ferroelectric memory cell of the embodiment of the application has the following advantages:
1) Each ferroelectric capacitor is allowed to be independently ferroelectric polarized, the writing reliability is improved by utilizing a differential polarization scheme, the high-density in-memory computing operation is supported, the noise immunity and the reading accuracy are improved, and the method is suitable for multi-bit storage level of AI (artificial intelligence) related workload (workloads);
2) The following advantages are achieved by the separation of the storage path from the control path:
Independently controlling access and data retention;
suppressing leakage current in standby and non-fully selected states;
durability is improved due to reduced stress in the single gate dielectric layer;
3) The method has the characteristics of low power consumption and high reliability, and is suitable for in-memory Computing (CIM) and neuromorphic computing environments:
the read gating function is realized by adopting an independent control transistor CT, so that the 2T2FC ferroelectric memory cell is activated only when explicitly accessed;
Leakage current suppression, critical to large arrays;
inter-cell interference is reduced, particularly when part of the cells are accessed;
The endurance is improved because the programming voltage is distributed over the two ferroelectric capacitors;
4) Compatible with standard CMOS back-end technology, only needs small area ferroelectric capacitor to realize high sensing margin, realizes compact cell size (8F 2), and is suitable for neuromorphic and AI-centered memory architecture;
5) By utilizing two ferroelectric capacitors and independent storage and control transistors, the problems of expansibility limitation and insufficient retention are solved, thereby improving data reliability, reducing read/write interference and providing higher energy efficiency;
the 2T2FC ferroelectric memory cell of the embodiment of the application remarkably improves the reliability, especially in low-voltage or battery limited environments (such as an edge AI chip and an Internet of things memory module (IoT memory modules)).
Example 2
The embodiment of the application provides a preparation method of a 2T2FC ferroelectric memory cell, which comprises the following steps of sequentially depositing a gate oxide layer, a high dielectric constant dielectric layer and a gate metal layer on a silicon substrate to respectively form a gate stack of a memory transistor and a control transistor, respectively forming a source diffusion region and a drain diffusion region on the silicon substrate through ion implantation and activation, respectively depositing interlayer dielectric layers on the source diffusion region and the drain diffusion region, respectively, symmetrically forming two ferroelectric capacitors on two sides of the gate stack of the memory transistor, and connecting the two ferroelectric capacitors to a plate line.
Fig. 4 is a flowchart of a method for manufacturing a 2T2FC ferroelectric memory cell according to an embodiment of the present application, and a method for manufacturing a 2T2FC ferroelectric memory cell according to an embodiment of the present application will be described in detail with reference to fig. 4.
First, in step 201, active region device regions (ACTIVE AREAS) are defined and isolated on a silicon substrate using shallow trench isolation (Shallow Trench Isolation, STI).
In an embodiment of the application, the method comprises the steps of defining a shallow trench isolation region on a silicon substrate through photoetching, and forming an STI (Shallow Trench Isolation ) trench with a preset depth through dry etching (such as HBr/Cl 2 plasma) of the shallow trench isolation region. A plurality of active device regions 401 are isolated on the silicon substrate by trenches, thereby defining an isolation region around the active device regions 401 on the silicon substrate to prevent leakage and parasitic coupling.
In step 202, a pretreatment is performed on the surface of a silicon substrate.
In an embodiment of the application, this step includes depositing an oxide 402, such as SiO 2, in the formed trench to fill the trench by high-density plasma chemical vapor deposition (HDP-CVD), removing excess material by Chemical Mechanical Polishing (CMP), leaving a planar surface. As shown in fig. 5, a plurality of active device regions 401 are formed on a silicon substrate by depositing an oxide 402 in the trenches.
In step 203, a gate stack of the storage transistor and the control transistor is generated over the active device region.
In an embodiment of the application, the steps include:
Two gate oxide layers 403 are grown or deposited over the active device region 401, such as a gate oxide (SiON gate oxide) dielectric having a high dielectric constant (high-K) (improving the high-K dielectric interface state);
Depositing a high-k dielectric layer (high-K DIELECTRIC) and a TiN Gate metal layer (TIN GATE METAL) to form a Gate stack, namely forming a high-k dielectric layer 404 and a TiN Gate electrode 405 (TiN Gate) on the two Gate oxide layers 403 through Atomic Layer Deposition (ALD), forming a Gate stack, and forming a storage transistor Gate and a control transistor Gate through photoetching and dry etching;
Patterning the memory transistor gates to form Word Lines (WL), patterning the control transistor gates to form Control Lines (CL);
Ion implantation, annealing is performed to form n+ source diffusion 406, drain-source diffusion 407 (which serves as the memory transistor drain and control transistor source), and drain diffusion 408, thermal annealing activates doping and forms a low resistance junction. As shown in fig. 6, two gate stacks of a gate oxide layer 403, a high-k dielectric layer 404, and a TiN gate electrode 405 are sequentially grown on an active device region 401, and a Word Line (WL) and a Control Line (CL) are formed, and an n+ source diffusion region 406, a drain source diffusion region 407, and a drain diffusion region 408 are formed by ion implantation, and finally annealed at a high temperature to activate dopants and form a low resistance junction.
At step 204, bit lines and source lines are generated on the drain and source diffusion regions.
In an embodiment of the present application, this step includes depositing an interlayer dielectric layer (INTERLAYER DIELECTRIC, ILD) over the source and drain diffusion regions 406, 408 and etching contact holes connecting the source and drain diffusion regions 406, 408, respectively, and filling the contact holes with a conductive metal (e.g., tungsten W or copper Cu) to form Source Lines (SL) and Bit Lines (BL).
As shown in fig. 7 and 8, an interlayer dielectric layer (ILD) is deposited on the source diffusion region 406 and the drain diffusion region 408, respectively, and a Source Line (SL) and a Bit Line (BL) are formed on the interlayer dielectric layer, respectively.
In an embodiment of the present application, step 204 further includes:
ILD deposition by depositing an oxide (e.g., siO 2) over the source diffusion region 406, drain-source diffusion region 407, and drain diffusion region 408 and planarizing by CMP to create an interlayer dielectric layer;
Forming contact holes by photoetching the interlayer dielectric layer until the source diffusion region 406 and the drain diffusion region 408 are etched to form contact holes;
metal filling, namely filling the contact holes with conductive metal to form Source Lines (SL) and Bit Lines (BL).
In step 205, ferroelectric capacitors are generated on both sides of the memory transistor gate.
In an embodiment of the application, the steps include:
A ferroelectric capacitor contact hole 409 is patterned on the memory transistor gate and filled with a conductive material as shown in fig. 9, a common bottom metal pad 410 of the ferroelectric capacitor is formed over the contact hole 409 as shown in fig. 10, a TiN bottom electrode 411 is sequentially deposited on the common bottom metal pad 410, a ferroelectric layer 412 is grown, a TiN top electrode 413 is deposited as shown in fig. 11, and the ferroelectric layer 412 is activated by annealing to form ferroelectric domains, completing the stacked structure of the two ferroelectric capacitors.
Specifically, the storage transistor gate is aligned at two sides by lithography, ILD is etched to the gate to form a deep hole, a TiN bottom electrode 411 is deposited on the deep hole by Plasma Enhanced ALD (PEALD), a HfZrO 2 ferroelectric (Ferroelectric) film is deposited by ALD to form a ferroelectric layer 412, a TiN top electrode 413 is deposited by ALD, and finally an electrode pattern is defined by lithography lift-off.
In step 206, metal wiring is performed.
In an embodiment of the application, separate plate lines PLA and PLB are connected using metal wiring layers for CFA and CFB, metallization and patterning, defining Word Lines (WL) and Control Lines (CL) and connecting to transistor gates. As shown in fig. 12, plate lines 414, 415, i.e., PLA and PLB, are formed on the TiN top electrode 413 through an interconnection metal layer, and word lines WL, control lines CL, and other wiring layers, e.g., bit lines BL, source lines SL, are connected through vias.
Further, it includes depositing SiN (silicon nitride) etching stop layer, connecting the TiN top electrode 413 of the ferroelectric capacitor through the photoetching through hole, etching the groove and electroplating copper to form the plate line and the word line.
In step 207, back-end integration is completed.
In the embodiment of the application, passivation and planarization required by the semiconductor back end process (BE) packaging are finally carried out, and the integration of the 2T2FC ferroelectric memory cell is completed. The 2T2FC ferroelectric memory cell is patterned into a layout that occupies an 8F2 area, where F is the minimum feature size of the fabrication process node. Further, the method comprises the following steps:
Size verification by electron beam inspection confirm 2F x 4F (=8f 2) layout (e.g. 14nm node: lateral gate length 28nm x longitudinal metal pitch 56 nm);
Depositing a passivation layer, namely depositing a SiN passivation layer and opening a welding disc window.
The preparation method of the 1T2FC ferroelectric memory cell provided by the embodiment of the application ensures that the 1T2FC ferroelectric memory cell can be seamlessly integrated on a standard CMOS logic device, ensures high-density expandability, is compatible with 28 nanometers, 22 nanometers and more advanced nodes, and is completely compatible with CMOS back-end processing, thereby supporting high-density and high-performance system-on-chip (SoC) application.
Example 3
In an embodiment of the application, a memory array is provided comprising a plurality of 2T2FC ferroelectric memory cells as described above.
In an embodiment of the application, the control transistors of a plurality of 2T2FC ferroelectric memory cells share Control Lines (CL) control, and two ferroelectric capacitors share plate lines (PLA, PLB) between rows or columns.
In embodiments of the present application, the memory array is accessed in a multi-step voltage fashion by applying multi-step gradation voltages to the plate and word lines of a 2T2FC ferroelectric memory cell to selectively program the target cell and prevent disturbance of half-selected cells.
In a memory array, half-selected cells refer to memory cells that are only column gated (word line WL activated) or row gated (bit line BL activated) in read and write operations, but not fully selected, and such cells are in a potentially noisy state.
The multi-step voltage access scheme is described in detail below with respect to a3 x 4 memory array, from the write process and the read process, respectively.
Fig. 13-16 show an example of writing of the memory array, first, writing a "0" to a 2T2FC ferroelectric memory cell in the memory array, in two phases:
In the first stage, as shown in FIG. 13, WL (1) is 0V, WL (2-4) is applied 2/3Vpp, all BL and SL are 0V, CL (1) is applied Vdd, CL (2-4) is 0V, PLA (1-3) is applied 1/3Vpp, PLB (2) is applied Vpp, PLB (1) and PLB (3) are applied 1/3Vpp;
in the second stage, PLB (1-3) applies-1/3 Vpp, PLA (2) applies-Vpp, PLA (1) and PLA (3) apply-1/3 Vpp, and WL (2-4) applies-2/3 Vpp, as shown in FIG. 14.
Writing a "1" to a 2T2FC ferroelectric memory cell in the memory array, in two phases:
The first stage, as shown in FIG. 15, with WL (1) applied at 0V, WL (2-4) applied at 2/3Vpp, all BL and SL at 0V, CL (1) applied at Vdd, CL (2-4) applied at 0V, PLB (1-3) applied at 1/3Vpp, PLA (2) applied at Vpp, PLA (1) and PLA (3) applied at 1/3Vpp;
In the second stage, as shown in FIG. 16, PLA (1-3) is applied with-1/3 Vpp, PLB (2) is applied with-Vpp, PLB (1) and PLB (3) are applied with-1/3 Vpp, and WL (2-4) is applied with-2/3 Vpp.
Fig. 17 to 20 show another writing example of the memory array, in which first, a "0" is written to a 2T2FC ferroelectric memory cell in the memory array in two stages:
In the first stage, as shown in FIG. 17, only WL (1) is applied with-1/2 Vpp, the other WLs (2-4) are 0V, all BL and SL are 0V, CL (1) is applied with Vdd, CL (2-4) is 0V, PLB (2) is applied with 1/2Vpp, and the other plate lines are all connected with 0V;
in the second stage, as shown in FIG. 18, WL (1) is applied with 1/2Vpp, PLA (2) is applied with-1/2 Vpp, and PLB (2) is connected with 0V.
Writing a "1" to a 2T2FC ferroelectric memory cell in the memory array, in two phases:
In the first stage, as shown in FIG. 19, WL (1) is applied with-1/2 Vpp, PLA (2) is applied with 1/2Vpp, PLB (2) is connected with 0V;
In the second stage, as shown in FIG. 20, WL (1) applies 1/2Vpp, PLB (2) applies-1/2 Vpp, PLA (2) connects 0V.
Fig. 21 to 22 show an example of reading of the memory array, and the reading process is divided into two stages:
In the first stage, as shown in FIG. 21, only WL (1) applies Vdd, the rest WL (2-4) applies Vdd, BL (2) applies Vdd, the rest BL is 0V, CL (1) applies Vdd, CL (2-4) is 0V, PLB (2) applies Vread, the rest plate lines are all connected with 0V, vread < Vc, vd=0.2V-0.7V (< Vdd);
In the second stage, PLA (2) applies Vread and PLB (2) receives 0V, vread < Vc, vd=0.2V-0.7V (< Vdd).
Wherein Vc represents a forced voltage (coercive voltage) defined as the minimum voltage required to flip the polarization direction of the ferroelectric domains, and Vc is the voltage at which the polarization value crosses zero during voltage sweep in the polarization-voltage (P-V) hysteresis loop. It marks the inflection point of the ferroelectric material switching between a positive remnant polarization +Pr (after +V > Vc is applied) and a negative remnant polarization-Pr (after-V < -Vc is applied).
Further, the memory array of the present application further includes a write control unit configured to apply multi-step gradation voltages to the plate lines and the word lines of the 2T2FC ferroelectric memory cells to selectively program the target cells and prevent disturbance of half selected cells.
Example 4
In an embodiment of the application, an AI chip is provided, comprising a memory array as described above. The AI chip adopting the memory array has the characteristics of low power consumption and high reliability.
It will be understood by those skilled in the art that the foregoing description is only a preferred embodiment of the present application, and that the present application is not limited to the above-described embodiment, but may be modified or substituted for some of the features described in the above-described embodiments. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.
Claims (17)
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| CN119068937A (en) * | 2023-05-30 | 2024-12-03 | 华为技术有限公司 | Storage array, reading and writing method thereof, and preparation method thereof, memory, and electronic device |
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| CN209231927U (en) * | 2019-01-18 | 2019-08-09 | 清华大学 | Merge the dynamic controllable devices unit of non-volatile multilevel storage Yu logical operation function |
| CN116935919A (en) * | 2022-03-31 | 2023-10-24 | 华为技术有限公司 | Ferroelectric memory array, ferroelectric memory and operation method thereof |
| CN117651421A (en) * | 2022-08-19 | 2024-03-05 | 华为技术有限公司 | Storage array and preparation method thereof, memory, electronic equipment |
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