CN120880572B - DDS-based narrow-band spectrum time gating method, system, medium and device - Google Patents
DDS-based narrow-band spectrum time gating method, system, medium and deviceInfo
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Abstract
The application discloses a narrow-band spectrum time gating method, a narrow-band spectrum time gating system, a narrow-band spectrum time gating medium and narrow-band spectrum time gating equipment based on DDS, and relates to the technical field of spectrum analysis. The application realizes time gating by utilizing the DDS direct frequency synthesizer in the FPGA, on one hand, the whole time gating function is realized in the FPGA and is not connected with the front-end radio frequency circuit, a plurality of registers in the VCO in the front-end radio frequency circuit are not required to be configured, a configuration interface is simplified, the control efficiency is improved, the digital circuit is not required to be synchronously controlled with the radio frequency circuit, and the system structure is simplified, on the other hand, the DDS is used as a core for realizing scanning, the locking delay is very low and controllable, the analysis speed of the system is greatly improved, the delay can be processed in the FPGA, the control flow of the system is further simplified, and the narrow-band spectrum time gating level is improved.
Description
Technical Field
The application relates to the technical field of spectrum analysis, in particular to a narrow-band spectrum time gating method, a narrow-band spectrum time gating system, a narrow-band spectrum time gating medium and narrow-band spectrum time gating equipment based on DDS.
Background
The narrow-band time division multiplexing signal refers to a signal formed by overlapping sub-signals with multiple bandwidths in the range of tens of MHz by occupying the same frequency band in a time sharing manner, such as a pulse modulation signal, a time division multiple access signal and the like. The general spectrum analysis for narrow-band time division multiplexed signals mainly relies on a time gating function in modern spectrum analyzers, which can realize spectrum analysis of only specific sub-signals in the narrow-band time division multiplexed signals at specific times.
However, the existing method is low in level, and whenever the state of the GATE time GATE signal changes to a high level, the upper computer must reconfigure a plurality of registers, resulting in lower control efficiency, and must poll the lock flag of the VCO to determine that the VCO is locked stably, resulting in slower response speed.
Disclosure of Invention
In summary, the main purpose of the present application is to provide a method, a system, a medium and a device for time gating of a narrowband spectrum based on DDS, which aims to solve the problem of low time gating level of the narrowband spectrum in the prior art.
In order to achieve the above object, the technical scheme adopted by the embodiment of the application is as follows:
in a first aspect, an embodiment of the present application provides a DDS-based narrowband spectrum time gating method, applied to an FPGA, including the following steps:
Receiving and storing calculation parameters from an upper computer, wherein the calculation parameters comprise a frequency control word corresponding to the initial frequency, a scanning slope, a high level starting time of a time gate signal and a high level duration time of the time gate signal;
generating a time gate signal according to the high level start time of the time gate signal and the high level duration time of the time gate signal;
according to the time gate signal, the scanning state of the DDS and the on-off of the digital detector are controlled;
obtaining a target frequency control word according to the scanning state of the DDS;
and according to the target frequency control word, realizing narrow-band frequency time gating.
In a possible implementation manner of the first aspect, obtaining the target frequency control word according to the scanning state of the DDS includes:
obtaining the state of a gate signal according to the scanning state of the DDS;
And controlling the change of the frequency control word of the DDS according to the state of the gate signal, the frequency control word corresponding to the initial frequency and the scanning slope to obtain the target frequency control word.
In one possible implementation manner of the first aspect, according to a state of the gate signal, a frequency control word corresponding to the start frequency, and a scan slope, controlling a change of the frequency control word of the DDS, to obtain a target frequency control word, including:
And according to the state of the gate signal, the frequency control word corresponding to the initial frequency and the scanning slope, controlling the frequency control word of the DDS to be increased or maintained until the scanning is completed, and obtaining the target frequency control word.
In one possible implementation manner of the first aspect, the frequency control word for controlling the DDS is incremented or maintained, including:
When the gate signal is at a high level, incremental calculation is realized according to the sum of the frequency control words corresponding to the initial frequency and the product of the self-increment output value of the counter and the scanning slope so as to control the increment of the frequency control word of the DDS;
when the gate signal is at low level, the frequency control word of the DDS is kept as the last output value calculated in the last increment according to the last self-increment output value of the counter.
In one possible implementation manner of the first aspect, controlling the scanning state of the DDS and the on-off of the digital detector according to the time gate signal includes:
and according to the time gate signal, controlling the scanning state of the DDS to be switched between different states and the on-off state of the digital detector.
In one possible implementation manner of the first aspect, according to the time gate signal, controlling the switching of the scanning state of the DDS between different states and the on-off of the digital detector includes:
Controlling the scanning state of the DDS to jump from the first state to the second state according to the arrival of the scanning start pulse;
pulling the time gate signal high according to the count of the high level start time of the time gate signal full, and simultaneously starting to count the value of the high level duration time of the time gate signal;
and according to whether the high level duration time of the time gate signal is full, pulling down the time gate signal, and according to whether the detection data output by the digital detector is matched with the number required by the upper computer, jumping to a third state or a first state until the scanning end pulse arrives.
In one possible implementation manner of the first aspect, before receiving and storing the calculation parameters from the upper computer, the method further includes:
configuring a plurality of registers;
Receiving and storing computing parameters from a host computer, including:
And respectively receiving and storing a calculation parameter from the upper computer according to the configured multiple registers.
In a second aspect, an embodiment of the present application provides a DDS-based narrowband spectrum time gating system, applied to an FPGA, including:
The parameter configuration module is used for receiving and storing calculation parameters from the upper computer, wherein the calculation parameters comprise a frequency control word corresponding to the initial frequency, a scanning slope, high-level starting time of a time gate signal and high-level duration time of the time gate signal;
The GATE generation module is used for generating a time GATE signal according to the high level starting time of the time GATE signal and the high level duration time of the time GATE signal;
And the DDS control module is used for controlling the scanning state of the DDS and the on-off of the digital detector according to the time gate signal, obtaining a target frequency control word according to the scanning state of the DDS and realizing the time gating of the narrow-band frequency according to the target frequency control word.
In a third aspect, an embodiment of the present application provides a computer readable storage medium storing a computer program, which when loaded and executed by a processor, implements the DDS-based narrowband spectrum time gating method provided in any one of the first aspects above.
In a fourth aspect, an embodiment of the present application provides an electronic device, including a processor and a memory, where,
The memory is used for storing a computer program;
the processor is configured to load and execute a computer program to cause the electronic device to perform the DDS based narrowband spectral time gating method as provided in any of the first aspects above.
Compared with the prior art, the application has the beneficial effects that:
the embodiment of the application provides a narrow-band spectrum time gating method, a system, a medium and equipment based on DDS, wherein the method comprises the steps of receiving and storing calculation parameters from an upper computer; the method comprises the steps of calculating parameters including a frequency control word corresponding to an initial frequency, a scanning slope, a high level starting time of a time gate signal and a high level duration of the time gate signal, generating the time gate signal according to the high level starting time of the time gate signal and the high level duration of the time gate signal, controlling the scanning state of the DDS and the on-off of a digital detector according to the time gate signal, obtaining a target frequency control word according to the scanning state of the DDS, and realizing narrow-band frequency time gating according to the target frequency control word. The application realizes time gating by utilizing the DDS direct frequency synthesizer in the FPGA, on one hand, the whole time gating function is realized in the FPGA and is not connected with the front-end radio frequency circuit, a plurality of registers in the VCO in the front-end radio frequency circuit are not required to be configured, a configuration interface is simplified, the control efficiency is improved, the digital circuit is not required to be synchronously controlled with the radio frequency circuit, and the system structure is simplified, on the other hand, the DDS is used as a core for realizing scanning, the locking delay is very low and controllable, the analysis speed of the system is greatly improved, the delay can be processed in the FPGA, the control flow of the system is further simplified, and the narrow-band spectrum time gating level is improved.
Drawings
FIG. 1 is a schematic diagram of an electronic device in a hardware operating environment according to an embodiment of the present application;
FIG. 2 is a block diagram of a system implementing time gating in the prior art;
Fig. 3 is a schematic flow chart of a DDS-based narrowband spectrum time gating method according to an embodiment of the present application;
Fig. 4 is a schematic diagram illustrating transition of a scanning state of a DDS in a DDS-based narrowband spectrum time gating method according to an embodiment of the present application;
Fig. 5 is a schematic diagram of realizing gating based on DDS in the DDS-based narrowband spectrum time gating method according to the embodiment of the present application;
fig. 6 is a schematic diagram of a relationship between a frequency control word FW and a GATE signal GATE in a DDS-based narrowband spectrum time gating method according to an embodiment of the present application;
fig. 7 is a schematic diagram of module configuration of a DDS control module in a DDS-based narrowband spectrum time gating method according to an embodiment of the present application;
fig. 8 is a schematic block diagram of a DDS-based narrowband spectrum time gating system according to an embodiment of the present application;
The figure shows 101-a processor, 102-a communication bus, 103-a network interface, 104-a user interface, 105-a memory.
Detailed Description
It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
Referring to fig. 1, fig. 1 is a schematic diagram of an electronic device in a hardware operating environment according to an embodiment of the present application, where the electronic device may include a processor 101, such as a central processing unit (Central Processing Unit, CPU), a communication bus 102, a user interface 104, a network interface 103, and a memory 105. Wherein the communication bus 102 is used to enable connected communication between these components. The user interface 104 may include a Display, an input unit such as a Keyboard (Keyboard), and the optional user interface 104 may also include standard wired, wireless interfaces. The network interface 103 may alternatively comprise a standard wired interface, a wireless interface, such as a wireless FIdelity (WI-FI) interface. The Memory 105 may alternatively be a storage device independent of the aforementioned processor 101, and the Memory 105 may be a high-speed random access Memory (Random Access Memory, RAM) Memory or a stable Non-Volatile Memory (NVM), for example, at least one disk Memory, and the processor 101 may be a general-purpose processor including a central processing unit, a network processor, etc., or may be a digital signal processor, an application specific integrated circuit, a field programmable gate array or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component.
It will be appreciated by those skilled in the art that the structure shown in fig. 1 is not limiting of the electronic device and may include more or fewer components than shown, or may combine certain components, or may be arranged in different components.
As shown in fig. 1, an operating system, a network communication module, a user interface module, and a DDS-based narrowband spectrum time gating system may be included in the memory 105 as a storage medium.
In the electronic device shown in fig. 1, the network interface 103 is mainly used for data communication with a network server, the user interface 104 is mainly used for data interaction with a user, the processor 101 and the memory 105 in the application can be arranged in the electronic device, and the electronic device calls the narrow-band spectrum time gating system based on the DDS stored in the memory 105 through the processor 101 and executes the narrow-band spectrum time gating method based on the DDS provided by the embodiment of the application.
The narrow-band time division multiplexing signal refers to a signal formed by overlapping sub-signals with multiple bandwidths in the range of tens of MHz by occupying the same frequency band in a time sharing manner, such as a pulse modulation signal, a time division multiple access signal and the like. The general spectrum analysis for the narrow-band time division multiplexing signal mainly depends on a time gating function in a modern spectrum analyzer, the function can realize that only specific sub-signals in the narrow-band time division multiplexing signal are subjected to spectrum analysis at specific moments, the basic implementation scheme is as shown in fig. 2, a 1-bit time GATE signal (GATE) is usually generated in an FPGA, the high-level starting time and the high-level duration of the GATE are calculated by an upper computer according to the specific sub-signal characteristics and then are sent to the FPGA, then the FPGA controls a voltage-controlled oscillation chip (VCO) in a radio frequency circuit and a digital detector in the FPGA according to the state of the GATE, the VCO is enabled to scan only when the GATE is at a high level, otherwise, the frequency of the local oscillator signal output by the VCO is kept at the last time when the VCO stops scanning only when the GATE is at the high level, and otherwise, the digital detector in the FPGA is turned off, namely the sub-signals in the high-level duration of the GATE are analyzed.
As can be seen from fig. 2, the first drawback of this solution is that the control is complex, the GATE spans the rf circuit and the rf circuit directly controls the VCO, which results in that the scanning process in the rf circuit must be synchronized with the process in the digital circuit when the system is in operation, and the VCO needs to be configured with a plurality of internal registers, for example, up to 21 internal registers, which need to be configured, in the existing HMC703 series VCO, when the state of the GATE is changed to a high level, which means that the upper computer must reconfigure these registers, which is inefficient and cumbersome to control.
The second drawback of this solution is that the response speed is slow, because the rf local oscillator module consisting of VCO is essentially a phase locked loop, which must ensure that the frequency of the output local oscillator signal is locked to the sweep start frequency before the sweep starts, whereas the VCO is locked for a period of time, typically several hundred milliseconds, which is not controllable, meaning that the upper computer must poll the VCO lock flag whenever the GATE state goes high, until the VCO has determined stable locking, which forms a measurement speed bottleneck for the narrowband time division multiplexed signal.
Therefore, in order to solve the above problems, the embodiment of the application provides a scheme for realizing time gating by using a DDS direct frequency synthesizer in an FPGA, on one hand, the whole time gating function is realized in the FPGA and is not connected with a front-end radio frequency circuit, a plurality of registers in a VCO in the front-end radio frequency circuit are not required to be configured, a configuration interface is simplified, the control efficiency is improved, a digital circuit is not required to be synchronously controlled with the radio frequency circuit, the system structure is simplified, and on the other hand, the DDS is used as a core for realizing scanning, the locking delay is very low and controllable, the analysis speed of the system is greatly improved, the delay can be processed in the FPGA, the control flow of the system is further simplified, and the time gating level of a narrow-band spectrum is improved.
Referring to fig. 3, based on the hardware device of the foregoing embodiment, an embodiment of the present application provides a DDS-based narrowband spectrum time gating method, which is applied to an FPGA, and includes the following steps:
And S10, receiving and storing calculation parameters from an upper computer, wherein the calculation parameters comprise a frequency control word corresponding to the initial frequency, a scanning slope, a high level starting time of a time gate signal and a high level duration of the time gate signal.
In the implementation process, when the system starts to work, the upper computer first calculates four parameters required by the present narrow-band time gating analysis, namely, a frequency control word FW 0 corresponding to the starting frequency f, a scanning slope k, a high-level start time gate_dly of the time gate signal, and a high-level duration time gate_len of the time gate signal. The method specifically comprises the steps of calculating the values of FW 0 and k corresponding to the current scanning according to the analysis center frequency, the scanning time and the SPAN appointed by a user, calculating the values of gate_dly and gate_len corresponding to the current scanning according to the narrow-band time division multiplexing sub-signal characteristics appointed by the user, and then issuing the four parameters into a parameter configuration module in the FPGA by an upper computer to be stored, and starting the analysis. Because only four calculation parameters exist, the number of registers to be configured is also greatly reduced, in the application, only four registers are needed to be configured, and then one register correspondingly receives and stores one calculation parameter, namely, before receiving and storing the calculation parameters from an upper computer, the method further comprises the following steps:
configuring a plurality of registers;
Receiving and storing computing parameters from a host computer, including:
And respectively receiving and storing a calculation parameter from the upper computer according to the configured multiple registers.
And S20, generating a time gate signal according to the high level starting time of the time gate signal and the high level duration time of the time gate signal.
In the implementation process, the GATE generating module generates a GATE according to the stored values of gate_dly and gate_len, so as to control the scanning state of a direct frequency synthesizer (DDS) and the on-off of a digital detector.
S30, controlling the scanning state of the DDS and the on-off of the digital detector according to the time gate signal.
In the implementation process, the DDS (specifically, the frequency control word for controlling the DDS) and the digital detector are controlled according to the state of the GATE, the DDS is only scanned when the GATE is at a high level, otherwise, the signal output by the DDS is kept at the frequency when the scanning is stopped last time, and meanwhile, the digital detector in the FPGA is turned on only when the GATE is at the high level, otherwise, the digital detector is turned off.
The logic of the DDS scanning state control and the on-off control of the digital detector can be abstracted into a state machine, and the scanning state of the DDS is controlled to be switched between different states, namely, the scanning state of the DDS and the on-off of the digital detector are controlled according to a time gate signal, and the method comprises the following steps:
and according to the time gate signal, controlling the scanning state of the DDS to be switched between different states and the on-off state of the digital detector.
The DDS scanning states comprise a first state, a second state and a third state, the state transition is shown in figure 4, specifically, the DDS scanning states are controlled to be switched between different states and the on-off of the digital detector according to a time gate signal, and the DDS scanning states comprise:
Controlling the scanning state of the DDS to jump from the first state to the second state according to the arrival of the scanning start pulse;
pulling the time gate signal high according to the count of the high level start time of the time gate signal full, and simultaneously starting to count the value of the high level duration time of the time gate signal;
and according to whether the high level duration time of the time gate signal is full, pulling down the time gate signal, and according to whether the detection data output by the digital detector is matched with the number required by the upper computer, jumping to a third state or a first state until the scanning end pulse arrives.
In the implementation process, the module waits for the scanning start pulse of the upper computer in the IDLE state, namely the first state, jumps to the GEN state when the scanning start pulse arrives, namely the second state, the module counts the value of gate_dly first in the GEN state, pulls GATE high after full counting, simultaneously starts counting the value of gate_len, pulls GATE low after full counting, completes one generation of GATE high level, and meanwhile, the GATE can be output to the DDS control module and the digital detector, if the number of detection data output by the digital detector is equal to the number required by the upper computer, jumps to the DONE state, namely the third state, otherwise jumps back to the IDLE state and continues the next generation of GATE, and the module waits for the scanning end pulse of the upper computer in the DONE state, jumps back to the IDLE state when the scanning end pulse arrives, thereby completing one scanning.
S40, obtaining a target frequency control word according to the scanning state of the DDS.
In the specific implementation process, the application replaces VCO with DDS (direct frequency synthesizer) in FPGA to realize gating, in the narrow-band system, the scheme is very simple to control, the locking time is very short and controllable, thus the application has the technical advantages of fast response speed, high control efficiency and the like, the implementation principle is shown in figure 5, the whole time gating function is realized in FPGA without connection with the front-end radio frequency circuit, so the digital circuit is not required to be synchronous with the radio frequency circuit, in the original scheme, the DDS is only used for generating a fixed frequency single-tone signal with the same frequency as the narrow-band intermediate frequency signal to realize down-conversion, in the scheme, the output of the DDS is not a single-tone signal but a scanning signal similar to the linear frequency modulation signal, the FPGA needs to control the DDS to scan, the scanned bandwidth is the display width (SPAN) of the spectrum analysis, and the GATE is also generated in FPGA. The mathematical principle is as follows:
Let the initial frequency of the scan signal output by the DDS be f, the scan slope be k, the time be t, for convenience of description, let GATE have only one segment of high level, the rise time and fall time of high level be ta and tb respectively, j be imaginary units, then the scan signal N output by the DDS under the time gating function can be expressed as:
From equation (1), it can be seen that N is divided into a piecewise function by the high level of GATE, where N is a chirp function during the high level duration of GATE and a constant value is the last function value of the last chirp function during other times, and this conclusion applies equally when GATE has multiple levels of high.
According to the digital signal processing theory, the frequency of the output signal N of the DDS at a certain moment is uniquely determined by a frequency control word at the moment, the frequency control word of the DDS is taken as FW, the frequency control word corresponding to the initial frequency f is taken as FW 0, and then the floating point expression of FW can be written by the formula (1):
The above formula (2) shows that, in mathematical principles, if FW can be controlled to be increased only when GATE is at high level, N can be controlled to satisfy formula (1), so that a DDS narrowband time gating function is realized, and the relationship between frequency control word FW and time GATE signal GATE can be made according to formula (2) as shown in fig. 6.
Based on the foregoing theoretical basis, to implement time gating, according to the scanning state of the DDS, a target frequency control word is obtained, including:
obtaining the state of a gate signal according to the scanning state of the DDS;
And controlling the change of the frequency control word of the DDS according to the state of the gate signal, the frequency control word corresponding to the initial frequency and the scanning slope to obtain the target frequency control word.
In the implementation process, the increment or the maintenance of the frequency control word of the DDS is controlled according to the values of FW 0 and k and the state of GATE, namely, the change of the frequency control word of the DDS is controlled according to the state of a GATE signal, the frequency control word corresponding to the initial frequency and the scanning slope, and the target frequency control word is obtained, wherein the method comprises the following steps:
And according to the state of the gate signal, the frequency control word corresponding to the initial frequency and the scanning slope, controlling the frequency control word of the DDS to be increased or maintained until the scanning is completed, and obtaining the target frequency control word.
The DDS control module comprises a DDS circuit, a counter, a multiplier and an adder, which are all realized by using time sequence logic, wherein the module is formed by the digital circuit as shown in the figure 7, when the GATE is in a high level, each clock counter is self-increased by 1, the output value of the counter is multiplied by k issued by an upper computer and then added with FW 0 to finish the increment calculation of a frequency control word FW, when the GATE is in a low level, the counter stops self-increase and keeps the last value of the last self-increase, at the moment, the FW also keeps the last value of the last increment, and the FW is input into the DDS circuit to finish the digital circuit of the principle represented by the formulas (1) and (2), thereby realizing the whole narrow-band time gating function, namely, the step S50 is realized according to the target frequency control word.
In the embodiment, the DDS inside the FPGA is utilized to realize time gating, on one hand, the whole time gating function is realized inside the FPGA and is not connected with a front-end radio frequency circuit, a plurality of registers in a VCO in the front-end radio frequency circuit are not required to be configured, a configuration interface is simplified, the control efficiency is improved, a digital circuit is not required to be synchronously controlled with the radio frequency circuit, and the system structure is simplified, on the other hand, the DDS is used as a core for realizing scanning, the locking delay is very low and controllable, the analysis speed of the system is greatly improved, the delay can be processed inside the FPGA, the control flow of the system is further simplified, and the time gating level of a narrow-band spectrum is improved.
Referring to fig. 8, based on the same inventive concept as in the previous embodiment, an embodiment of the present application further provides a DDS-based narrowband spectrum time gating system, applied to an FPGA, including:
The parameter configuration module is used for receiving and storing calculation parameters from the upper computer, wherein the calculation parameters comprise a frequency control word corresponding to the initial frequency, a scanning slope, high-level starting time of a time gate signal and high-level duration time of the time gate signal;
The GATE generation module is used for generating a time GATE signal according to the high level starting time of the time GATE signal and the high level duration time of the time GATE signal;
And the DDS control module is used for controlling the scanning state of the DDS and the on-off of the digital detector according to the time gate signal, obtaining a target frequency control word according to the scanning state of the DDS and realizing the time gating of the narrow-band frequency according to the target frequency control word.
It should be understood by those skilled in the art that the division of each module in the embodiment is merely a division of a logic function, and may be fully or partially integrated onto one or more actual carriers in practical application, and the modules may be fully implemented in a form of software called by a processing unit, or may be fully implemented in a form of hardware, or may be implemented in a form of combination of software and hardware, and it should be noted that each module in the DDS-based narrowband spectrum time gating system in the embodiment is in one-to-one correspondence with each step in the DDS-based narrowband spectrum time gating method in the foregoing embodiment, so that a specific implementation of the embodiment may refer to an implementation manner of the DDS-based narrowband spectrum time gating method.
Based on the same inventive concept as in the previous embodiments, embodiments of the present application further provide a computer readable storage medium storing a computer program, which when loaded and executed by a processor, implements the DDS-based narrowband spectrum time gating method as provided in the embodiments of the present application.
Based on the same inventive concept as in the previous embodiments, an embodiment of the present application further provides an electronic device, including a processor and a memory, wherein,
The memory is used for storing a computer program;
the processor is configured to load and execute the computer program to cause the electronic device to execute the DDS-based narrowband spectrum time gating method as provided by the embodiment of the application.
In some embodiments, the computer readable storage medium may be FRAM, ROM, PROM, EPROM, EEPROM, flash memory, magnetic surface memory, optical disk, or CD-ROM, or various devices including one or any combination of the above. The computer may be a variety of computing devices including smart terminals and servers.
In some embodiments, the executable instructions may be in the form of programs, software modules, scripts, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and they may be deployed in any form, including as stand-alone programs or as modules, components, subroutines, or other units suitable for use in a computing environment.
As an example, the executable instructions may, but need not, correspond to files in a file system, may be stored as part of a file that holds other programs or data, such as in one or more scripts in a hypertext markup language (HTML, hyper Text Markup Language) document, in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files that store one or more modules, sub-programs, or portions of code).
As an example, executable instructions may be deployed to be executed on one computing device or on multiple computing devices located at one site or distributed across multiple sites and interconnected by a communication network.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or system. Without further limitation, an element defined by the phrase "comprising one does not exclude the presence of other like elements in a process, method, article, or system that comprises the element.
The foregoing embodiment numbers of the present application are merely for the purpose of description, and do not represent the advantages or disadvantages of the embodiments.
From the above description of embodiments, it will be clear to a person skilled in the art that the above embodiment method may be implemented by means of software plus a necessary general hardware platform, but may of course also be implemented by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art in the form of a software product stored in a storage medium (e.g. read-only memory/random-access memory, magnetic disk, optical disk), comprising instructions for causing a multimedia terminal device (which may be a mobile phone, a computer, a television receiver, or a network device, etc.) to perform the method according to the embodiments of the present application.
In summary, the method, the system, the medium and the device for narrow-band spectrum time gating based on the DDS comprise the steps of receiving and storing calculation parameters from an upper computer, wherein the calculation parameters comprise a frequency control word corresponding to a starting frequency, a scanning slope, high-level starting time of a time gate signal and high-level duration of the time gate signal, generating the time gate signal according to the high-level starting time of the time gate signal and the high-level duration of the time gate signal, controlling scanning state of the DDS and on-off of a digital detector according to the time gate signal, obtaining a target frequency control word according to the scanning state of the DDS, and realizing narrow-band frequency time gating according to the target frequency control word. The application realizes time gating by utilizing the DDS direct frequency synthesizer in the FPGA, on one hand, the whole time gating function is realized in the FPGA and is not connected with the front-end radio frequency circuit, a plurality of registers in the VCO in the front-end radio frequency circuit are not required to be configured, a configuration interface is simplified, the control efficiency is improved, the digital circuit is not required to be synchronously controlled with the radio frequency circuit, and the system structure is simplified, on the other hand, the DDS is used as a core for realizing scanning, the locking delay is very low and controllable, the analysis speed of the system is greatly improved, the delay can be processed in the FPGA, the control flow of the system is further simplified, and the narrow-band spectrum time gating level is improved.
The foregoing description of the preferred embodiments of the application is not intended to limit the application to the precise form disclosed, and any such modifications, equivalents, and alternatives falling within the spirit and scope of the application are intended to be included within the scope of the application.
Claims (7)
1. The DDS-based narrow-band spectrum time gating method is characterized by being applied to an FPGA and comprising the following steps of:
Receiving and storing calculation parameters from an upper computer, wherein the calculation parameters comprise a frequency control word corresponding to the initial frequency, a scanning slope, a high level starting time of a time gate signal and a high level duration time of the time gate signal;
Generating a time gate signal according to the high level start time of the time gate signal and the high level duration time of the time gate signal;
And controlling the scanning state of the DDS and the on-off of the digital detector according to the time gate signal, wherein the method comprises the following steps of:
according to the time gate signal, the scanning state of the DDS is controlled to be switched between different states and the on-off state of the digital detector is controlled;
According to the time gate signal, the DDS scanning state is controlled to be switched between different states and the on-off state of the digital detector is controlled, and the method comprises the following steps:
the method comprises the steps of controlling a DDS scanning state to jump from a first state to a second state according to the arrival of a scanning start pulse, wherein the first state is an IDLE state, and the second state is a GEN state;
Pulling the time gate signal high according to the count of the high level start time of the time gate signal full, and simultaneously starting to count the value of the high level duration time of the time gate signal;
Pulling down the time gate signal according to the full value of the high-level duration time of the time gate signal, and jumping to a third state or the first state according to whether the number of detection data output by the digital detector is matched with the number required by an upper computer or not until a scanning end pulse arrives, wherein the third state is a DONE state;
Obtaining a target frequency control word according to the scanning state of the DDS, wherein the obtaining the target frequency control word according to the scanning state of the DDS comprises the following steps:
obtaining the state of the gate signal according to the scanning state of the DDS;
according to the state of the gate signal, the frequency control word corresponding to the initial frequency and the scanning slope, controlling the frequency control word change of the DDS to obtain a target frequency control word;
And according to the target frequency control word, realizing narrow-band frequency time gating.
2. The DDS-based narrowband spectrum time gating method of claim 1, wherein the controlling the change of the frequency control word of the DDS according to the state of the gate signal, the frequency control word corresponding to the start frequency, and the scan slope, to obtain a target frequency control word, includes:
and controlling the frequency control word of the DDS to be increased or maintained according to the state of the gate signal, the frequency control word corresponding to the initial frequency and the scanning slope until the scanning is completed, and obtaining a target frequency control word.
3. The DDS based narrowband spectro-temporal gating method of claim 2, wherein the controlling the frequency control word of the DDS to increment or hold comprises:
when the gate signal is at a high level, incremental calculation is realized according to the sum of the frequency control words corresponding to the initial frequency and the product of the self-increment output value of the counter and the scanning slope so as to control the frequency control word of the DDS to be incremented;
when the gate signal is at a low level, the frequency control word of the DDS is kept to be the last output value calculated in the last increment according to the last self-increment output value of the counter.
4. The DDS based narrowband spectro-temporal gating method of claim 1, wherein prior to the receiving and storing the calculated parameters from the host computer, the method further comprises:
configuring a plurality of registers;
the receiving and storing the calculation parameters from the upper computer comprises the following steps:
And respectively receiving and storing one calculation parameter from the upper computer according to the configured multiple registers.
5. A DDS-based narrowband spectrotemporal gating system, characterized by being applied to an FPGA, comprising:
The parameter configuration module is used for receiving and storing calculation parameters from an upper computer, wherein the calculation parameters comprise a frequency control word corresponding to the starting frequency, a scanning slope, high-level starting time of a time gate signal and high-level duration time of the time gate signal;
The GATE generation module is used for generating a time GATE signal according to the high level starting time of the time GATE signal and the high level duration time of the time GATE signal;
The DDS control module is used for controlling the scanning state of the DDS and the on-off of the digital detector according to the time gate signal, obtaining a target frequency control word according to the scanning state of the DDS and realizing narrow-band frequency time gating according to the target frequency control word, and controlling the scanning state of the DDS and the on-off of the digital detector according to the time gate signal, and comprises the following steps:
according to the time gate signal, the scanning state of the DDS is controlled to be switched between different states and the on-off state of the digital detector is controlled;
According to the time gate signal, the DDS scanning state is controlled to be switched between different states and the on-off state of the digital detector is controlled, and the method comprises the following steps:
the method comprises the steps of controlling a DDS scanning state to jump from a first state to a second state according to the arrival of a scanning start pulse, wherein the first state is an IDLE state, and the second state is a GEN state;
Pulling the time gate signal high according to the count of the high level start time of the time gate signal full, and simultaneously starting to count the value of the high level duration time of the time gate signal;
Pulling down the time gate signal according to the full value of the high-level duration time of the time gate signal, and jumping to a third state or the first state according to whether the number of detection data output by the digital detector is matched with the number required by an upper computer or not until a scanning end pulse arrives, wherein the third state is a DONE state;
The obtaining the target frequency control word according to the scanning state of the DDS includes:
obtaining the state of the gate signal according to the scanning state of the DDS;
And controlling the change of the frequency control word of the DDS according to the state of the gate signal, the frequency control word corresponding to the initial frequency and the scanning slope to obtain a target frequency control word.
6. A computer readable storage medium storing a computer program, wherein the computer program, when loaded and executed by a processor, implements a DDS based narrowband spectral time gating method according to any of claims 1-4.
7. An electronic device comprising a processor and a memory, wherein,
The memory is used for storing a computer program;
the processor is configured to load and execute the computer program to cause the electronic device to perform the DDS-based narrowband spectral time gating method according to any of claims 1-4.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US5701598A (en) * | 1990-09-14 | 1997-12-23 | Atkinson; Noel D. | Scanning receiver with direct digital frequency synthesis and digital signal processing |
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| WO2006055585A1 (en) * | 2004-11-22 | 2006-05-26 | Masterwave, Inc. | System and method for narrow bandwidth amplitude modulation |
| US7957423B2 (en) * | 2008-01-02 | 2011-06-07 | Cisco Technology, Inc. | Packet error correction |
| US8385483B2 (en) * | 2008-11-11 | 2013-02-26 | Isco International, Llc | Self-adaptive digital RF bandpass and bandstop filter architecture |
| CN102684689B (en) * | 2012-05-08 | 2014-12-24 | 安徽白鹭电子科技有限公司 | Direct digital synthesis-based (DDS-based) device and method for synthesizing broadband microwave local-oscillation multi-ring frequency |
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