CN120854381A - Method for preparing metal interconnect structure and semiconductor device - Google Patents

Abstract

The application relates to a preparation method of a metal interconnection structure and a semiconductor device. The preparation method of the metal interconnection structure comprises the steps of sequentially forming a first insulating layer, a stop layer and a second insulating layer on a semiconductor laminated structure, exposing a conductive structure from the semiconductor laminated structure, etching the second insulating layer, forming a first groove by the stop layer and the first insulating layer, exposing the conductive structure by the first groove, filling metal into the first groove to form a first metal interconnection structure, enabling the first metal interconnection structure to be in contact with the conductive structure, enabling a first cavity to exist in the first metal interconnection structure, grinding until the stop layer is formed, forming a second groove after the first cavity is ground, filling metal into the second groove to form a second metal interconnection structure, and grinding until the stop layer is removed, so that the third metal interconnection structure is obtained. The application can reduce void defects when preparing the metal interconnection structure.

Description

Method for preparing metal interconnection structure and semiconductor device

Technical Field

The invention relates to the technical field of semiconductors, in particular to a preparation method of a metal interconnection structure and a semiconductor device.

Background

In the related art, in Integrated Circuit (IC) fabrication, it is required to prepare metal interconnect structures, such as metal interconnect lines and metal contact plugs, for electrical connection, such as copper (Cu) metal interconnect lines and copper contact plugs, which are widely used. However, since some metals (such as copper) are difficult to pattern by etching, electrochemical plating (ECP) with damascene process is a major fabrication process for metal interconnect lines in integrated circuit fabrication.

However, as Critical Dimensions (CD) of integrated circuits shrink, void (void) defects exist in metal interconnect structures fabricated using electrochemical plating, and filling of the voids becomes a significant challenge.

Therefore, how to reduce the occurrence of void defects in the preparation of metal interconnect structures is a technical problem to be solved.

Disclosure of Invention

The embodiment of the application provides a preparation method of a metal interconnection structure and a semiconductor device, which can reduce an overhang structure formed at the edge of a groove and the depth-to-width ratio of the groove when filling a metal material into the groove to prepare the metal interconnection structure, further reduce void defects, reduce interconnection resistance and stabilize the process.

According to a first aspect of an embodiment of the present application, there is provided a method for manufacturing a metal interconnection structure, including:

Sequentially forming a first insulating layer, a stop layer and a second insulating layer on the semiconductor laminated structure from bottom to top, wherein the semiconductor laminated structure comprises a conductive structure which is positioned in the semiconductor laminated structure and is exposed from the semiconductor laminated structure;

etching the second insulating layer, the stop layer and the first insulating layer to form a first groove, wherein the first groove exposes the conductive structure;

Filling a metal material into the first groove to form a first metal interconnection structure, so as to obtain a first intermediate structure, wherein the first metal interconnection structure is in contact with the conductive structure, and a first cavity is formed in the first metal interconnection structure;

Grinding the first intermediate structure from top to bottom until the first intermediate structure reaches the stop layer, wherein the first cavity is ground to form a second groove;

Filling the metal material into the second groove to form a second metal interconnection structure, so as to obtain a second intermediate structure;

And grinding the second intermediate structure from top to bottom until the stop layer is removed, and forming a third metal interconnection structure after grinding the second metal interconnection structure.

In one embodiment, the first insulating layer includes at least one insulating layer, and the second insulating layer includes at least one insulating layer.

In one embodiment, the stop layer includes a first barrier layer and a first adhesive layer laminated in order from bottom to top, the first adhesive layer being for adhering the metal material.

In one embodiment, the filling the first trench with a metal material forms a first metal interconnection structure, so as to obtain a first intermediate structure, which includes:

sequentially forming a second barrier layer and a second bonding layer inside and outside the first groove, wherein the second bonding layer is used for bonding the metal material;

Forming a first seed layer, the first seed layer covering the second adhesion layer;

electroplating the metal material on the first seed layer to form the first metal interconnect structure.

In one embodiment, the filling the second trench with the metal material forms a second metal interconnection structure, so as to obtain a second intermediate structure, which includes:

forming a second seed layer inside and outside the second groove, wherein the second seed layer covers the inner surface of the second groove and the first bonding layer outside the first groove;

And electroplating on the second seed layer to form the second metal interconnection structure.

In one embodiment, the conductive structure is an electrode and the third metal interconnect structure is an interconnect line;

The semiconductor laminated structure comprises a source electrode, the electrode is in contact with the source electrode, or

The semiconductor laminated structure includes a drain electrode with which the electrode is in contact, or

The semiconductor stack structure includes a gate electrode, and the electrode is in contact with the gate electrode.

In one embodiment, the material of the conductive structure comprises tungsten, copper, aluminum, or copper aluminum alloy.

In one embodiment, the conductive structure is a source, drain or gate and the third metal interconnect structure is a contact plug.

In one embodiment, the metallic material comprises tungsten, copper, aluminum, or copper aluminum alloy.

In one embodiment, when the metal material comprises copper, the material of the first barrier layer comprises tantalum nitride (TaN) and the material of the first adhesion layer comprises tantalum (Ta);

the material of the second barrier layer comprises tantalum nitride (TaN), and the material of the second adhesion layer comprises tantalum (Ta);

when the metal material includes tungsten, the material of the first barrier layer includes titanium (Ti), and the material of the first adhesion layer includes titanium nitride (TiN);

The material of the second barrier layer includes titanium (Ti), and the material of the second adhesion layer includes titanium nitride (TiN).

According to a third aspect of an embodiment of the present application, there is provided a semiconductor device including:

A semiconductor stack structure including a conductive structure, the conductive structure being located in the semiconductor stack structure and exposed from the semiconductor stack structure;

the first insulating layer is positioned on the semiconductor laminated structure, a first groove is formed in the first insulating layer, and the first groove exposes the conductive structure;

and the third metal interconnection structure is filled in the first groove and is contacted with the conductive structure, and the third metal interconnection structure is prepared by adopting the method.

Compared with the prior art, the application has the beneficial effects that: sequentially forming a first insulating layer, a stop layer and a second insulating layer on a semiconductor laminated structure from bottom to top, wherein the semiconductor laminated structure comprises a conductive structure which is positioned in the semiconductor laminated structure and exposed out of the semiconductor laminated structure, etching the second insulating layer, the stop layer and the first insulating layer to form a first groove, exposing the conductive structure by the first groove, filling a metal material into the first groove to form a first metal interconnection structure to obtain a first intermediate structure, contacting the first metal interconnection structure with the conductive structure, forming a first cavity in the first metal interconnection structure, grinding the first intermediate structure from top to bottom to the stop layer, forming a second groove after grinding the first cavity, filling a metal material into the second groove to form a second metal interconnection structure to obtain a second intermediate structure, then, the second intermediate structure is ground from top to bottom until the stop layer is removed, and the third metal interconnection structure is formed after the second metal interconnection structure is ground, so that the position of the stop layer can be set according to the requirement, when the first intermediate structure is ground from top to bottom to obtain the second groove, the position for stopping grinding can be accurately controlled, and then the opening width of the second groove can be accurately controlled, so that when the second metal interconnection structure is formed by filling metal materials into the second groove, the overhang structure formed at the edge of the second groove is reduced, and because compared with the depth-to-width ratio of the groove when the metal interconnection structure is prepared in the related art, the opening width of the second groove can be accurately controlled, and further the depth-to-width ratio of the second groove can be accurately controlled, the depth-to-width ratio of the second groove can be reduced, so that the occurrence of void defects can be reduced, and the process stability is good. Wherein the aspect ratio of the second trench is the ratio of the depth of the second trench to the width at a position half of the depth of the second trench. Moreover, since the opening width of the second trench can be accurately controlled, the opening width of the second trench can be controlled to be substantially the maximum width of the first cavity in the bottom-up direction, and the process window can be widened.

In summary, according to the technical scheme provided by the invention, when the metal material is filled into the groove to prepare the metal interconnection structure, the overhang structure formed at the edge of the groove is reduced, the depth-to-width ratio of the groove is reduced, the void defect is further reduced, the interconnection resistance is reduced, and the process stability is good.

Drawings

Fig. 1 is a schematic view of an overhang structure according to the related art.

Fig. 2 is a schematic diagram of a cavity according to the related art.

Fig. 3 is a flow chart illustrating a method of fabricating a metal interconnect structure according to an exemplary embodiment.

Fig. 4 is a schematic diagram illustrating an intermediate structure produced during the fabrication of a metal interconnect structure according to an exemplary embodiment.

Fig. 5 is a schematic diagram illustrating an intermediate structure produced during the fabrication of a metal interconnect structure according to another exemplary embodiment.

Fig. 6 is a flow chart illustrating a method of fabricating a metal interconnect structure according to another exemplary embodiment.

Fig. 7 is a schematic diagram illustrating an intermediate structure produced during the fabrication of a metal interconnect structure according to another exemplary embodiment.

Fig. 8 is a schematic diagram illustrating an intermediate structure produced during the fabrication of a metal interconnect structure according to another exemplary embodiment.

Fig. 9 is a schematic structural diagram of a metal interconnect structure, according to an example embodiment.

Reference numerals illustrate:

11, metal material layer, 111, overhang structure, 12, second cavity, 41, semiconductor stacked structure, 42, conductive structure, 43, first insulating layer, 431, first dielectric layer, 432, second dielectric layer, 433, third dielectric layer, 44, stop layer, 441, first barrier layer, 442, first adhesive layer, 45, second insulating layer, 451, fourth dielectric layer, 452, fifth dielectric layer, 453, sixth dielectric layer, 454, seventh dielectric layer, 46, first photoresist layer, 47, second photoresist layer, 48, window, 50, first intermediate structure, 51, first metal interconnect structure, 511, second barrier layer, 512, second adhesive layer, 513, first electroplated layer, 515, second electroplated layer, 516, third electroplated layer, 52, first cavity, 70, third intermediate structure, 71, second trench, H, depth of second trench, width at half the depth of W, 80, second intermediate structure, 81, second metal interconnect structure, 91, third metal interconnect structure.

Detailed Description

Unless defined otherwise, technical or scientific terms used in the specification and claims should be given the ordinary meaning as understood by one of ordinary skill in the art to which the invention pertains. In the following, specific embodiments of the present invention will be described with reference to the drawings, and it should be noted that in the course of the detailed description of these embodiments, it is not possible in the present specification to describe all features of an actual embodiment in detail for the sake of brevity. Modifications and substitutions of embodiments of the invention may be made by those skilled in the art without departing from the spirit and scope of the invention, and the resulting embodiments are also within the scope of the invention.

In the related art, as Critical Dimensions (CD) of integrated circuits shrink, void (void) defects exist in metal interconnect structures fabricated by electrochemical plating. As shown in fig. 1 and 2, an excessive thickness of the metal material layer 11, such as a seed layer, prior to electroplating may cause the overhang structure 111 or the post-electroplating filling material to have the second void 12. Filling of voids becomes a significant challenge. In the preparation of metal interconnect structures, how to reduce the occurrence of void defects is a technical problem to be solved.

In order to solve the technical problems, the application provides a preparation method of a metal interconnection structure and a semiconductor device, which can reduce the generation of void defects and reduce interconnection resistance.

An embodiment of the application provides a preparation method of a metal interconnection structure. The preparation method of the metal interconnection structure can be used for preparing interconnection lines in semiconductor devices and contact plugs for connecting a grid electrode, a source electrode and a drain electrode with external devices. The following describes in detail the method for manufacturing the metal interconnection structure provided by the present application, taking the manufacturing of the interconnection line as an example.

Referring to fig. 3, the method for preparing the metal interconnection structure may include the following steps S301 to S306:

Step S301, a first insulating layer, a stop layer and a second insulating layer are sequentially formed on the semiconductor laminated structure from bottom to top, wherein the semiconductor laminated structure comprises a conductive structure, and the conductive structure is located in the semiconductor laminated structure and is exposed from the semiconductor laminated structure.

As shown in fig. 4, the semiconductor stacked structure 41 includes a conductive structure 42 thereon, and the conductive structure 42 is located in the semiconductor stacked structure 41 and exposed from the semiconductor stacked structure 41.

In the present exemplary embodiment, the semiconductor stacked structure 41 may include a source, a drain, and a gate, and further include a conductive structure 42 in one-to-one contact with the source, the drain, and the gate. The conductive structure 42 is an electrode. Of course, in other embodiments, the method for fabricating a metal interconnect structure provided by the present invention may fabricate the conductive structure 42 in contact with one or both of the source, drain, and gate.

In the present exemplary embodiment, the material of the conductive structure 42 includes tungsten.

In one embodiment, the material of the conductive structure 42 may include copper. In one embodiment, the material of the conductive structure 42 may include aluminum. In one embodiment, the material of conductive structure 42 may comprise copper aluminum alloy.

In the present exemplary embodiment, the conductive structures 42 need to be connected to the interconnect lines. The interconnect material includes copper and the interconnect is fabricated by electroplating. Copper has low resistivity and good electromigration resistance, and can improve the conductivity of the interconnection line.

In one embodiment, the material of the interconnect line may comprise tungsten. In one embodiment, the material of the interconnect line may comprise aluminum. In one embodiment, the material of the interconnect line may comprise copper aluminum alloy.

In this step, as shown in fig. 4, a first insulating layer 43, a stop layer 44, and a second insulating layer 45 are sequentially formed on the semiconductor stacked structure 41 from bottom to top.

The first insulating layer 43 may be one insulating layer, or may include two or more insulating layers. The second insulating layer 45 may be one insulating layer, or may include two or more insulating layers.

In the present exemplary embodiment, as shown in fig. 4, the first insulating layer 43 may include a first dielectric layer 431, a second dielectric layer 432, and a third dielectric layer 433, which are sequentially stacked from bottom to top.

In the present exemplary embodiment, the material of the first dielectric layer 431 may include silicon oxycarbide (SiCO), but is not limited thereto.

In the present exemplary embodiment, the material of the second dielectric layer 431 may include Tetraethoxysilane (TEOS) but is not limited thereto.

In the present exemplary embodiment, the material of the third dielectric layer 433 may include silicon carbide (Black Di amond, BD for short) having a low dielectric constant, but is not limited thereto.

In the present exemplary embodiment, the stop layer 44 is used as a stop layer for the third dielectric layer 433. As shown in fig. 4, the stop layer 44 may include a first barrier layer 441 and a first adhesive layer 442 sequentially stacked from bottom to top, the first adhesive layer being used to adhere a metal material used for preparing the interconnect line.

In one embodiment, the stop layer 44 may be prepared using a copper barrier seed process.

In the present exemplary embodiment, the material of the first barrier layer 441 includes tantalum nitride (TaN), and the material of the first adhesion layer 442 includes tantalum (Ta).

In other embodiments, when the material of the interconnect line includes tungsten, the material of the first barrier layer 441 includes titanium (Ti), and the material of the first adhesion layer 442 includes titanium nitride (TiN).

In the present exemplary embodiment, as shown in fig. 4, the second insulating layer 45 may include a fourth dielectric layer 451, a fifth dielectric layer 452, a sixth dielectric layer 453, and a seventh dielectric layer 454, which are sequentially stacked from bottom to top.

In the present exemplary embodiment, the material of the fourth dielectric layer 451 may include silicon carbide (Black Di amond, BD for short) having a low dielectric constant, but is not limited thereto.

In the present exemplary embodiment, the material of the fifth dielectric layer 452 may include silicon carbide (Black Di amond, abbreviated as BD) having a low dielectric constant, but is not limited thereto.

In the present exemplary embodiment, the sixth dielectric layer 453 may be a Nitrogen-free dielectric anti-reflective coating (Nitrogen-FREEDIELECTRICANT-refIectivecoating, NFDARC for short), but is not limited thereto.

In the present exemplary embodiment, the material of the seventh dielectric layer 454 may include titanium nitride (TiN), but is not limited thereto.

In step S302, the second insulating layer, the stop layer and the first insulating layer are etched to form a first trench, and the first trench exposes the conductive structure.

In this step, a photolithography process may be used to perform an integrated etching (All In One etching, abbreviated as AIO-ET) on the second insulating layer 45, the stop layer 44, and the first insulating layer 43, so as to form a first trench, where the first trench is used to expose the conductive structure 42.

In this step, the first photoresist layer 46 and the second photoresist layer 47 may be formed on the second insulating layer 45 in order from bottom to top. The material of the first photoresist layer 46 includes organic Spin-On-Carbon (SOC). The material of the second photoresist material layer 47 includes Photoresist (PR). Then, the second photoresist layer 47 is patterned, a window 48 is formed on the second photoresist layer 47, then the first photoresist layer 46, the second insulating layer 45, the stop layer 44 and the first insulating layer 43 under the window 48 are etched, and then the first photoresist layer 46 and the second photoresist layer 47 are removed to form a first trench.

Step S303, filling metal materials into the first groove to form a first metal interconnection structure, so as to obtain a first intermediate structure, wherein the first metal interconnection structure is in contact with the conductive structure, and a first cavity is formed in the first metal interconnection structure.

In this step, as shown in fig. 5, a first metal interconnection structure 51 is formed by filling a metal material into the first trench by electroplating, so as to obtain a first intermediate structure 50, where the first metal interconnection structure 51 contacts the conductive structure 42. Wherein, the first electroplated layer 513 is formed by electroplating to the metal material filled in the first trench, and the first void 52 exists in the first electroplated layer 513 in the first metal interconnection structure 51.

In one embodiment, the first hollow 52 is spindle-shaped, and the width of the lower end and the width of the upper end of the first hollow 52 are smaller than the width of the middle portion. In a bottom-up direction, the stop layer 44 may be substantially aligned with a middle portion of the first cavity 52, but is not limited thereto.

In order to substantially align the middle portion of the first cavity 52 generated in this step with the stop layer 44, the thicknesses of the first insulating layer 43 and the stop layer 44 may be controlled to be formed in step S301 described above.

In this step, as shown in fig. 6, the following steps S3031 to S3033 may be included:

in step S3031, a second barrier layer and a second adhesive layer are sequentially formed inside and outside the first trench, wherein the second adhesive layer is used for adhering the metal material.

As shown in fig. 6, in this step, a second barrier layer 511 and a second adhesive layer 512 for bonding a metal material (copper) are sequentially formed inside and outside the first trench.

In one embodiment, the second barrier layer 511 and the second adhesion layer 512 may be prepared using a copper barrier process, which may provide robust conditions for electroplated copper, and may provide a larger process window for a subsequent Electroplated Copper Process (ECP).

In the present exemplary embodiment, the material of the second barrier layer 511 includes tantalum nitride (TaN), and the material of the second adhesion layer 512 includes tantalum (Ta). The adhesion of copper to the third dielectric layer 433 is much lower than that of the second adhesive layer 512, and the subsequent copper can be uniformly covered on the second adhesive layer 512, so that the non-uniformity of the copper film layer is reduced, and the generation of voids is reduced.

In other embodiments, when the material of the interconnect line includes tungsten, the material of the second barrier layer 511 includes titanium (Ti), and the material of the second adhesion layer 512 includes titanium nitride (TiN).

In step S3032, a first seed layer is formed, the first seed layer covering the second adhesion layer.

In this step, a first seed layer, which is a copper seed layer, is formed on the second adhesive layer 512. Due to the presence of the second adhesive layer 512, adhesion to the first seed layer may be increased. Due to the presence of the second barrier layer 511, the copper material may be prevented from diffusing into the fourth dielectric layer 451.

In step S3033, a first metal interconnect structure is formed by electroplating a metal material on the first seed layer.

In this step, a first metal interconnect structure 51 is formed by electroplating a metal material (copper) on the first seed layer.

As shown in fig. 5, a metal material is filled into the first trench through an electroplating process, and the filled metal material covers the bottom of the first trench, so that the aspect ratio of the first trench can be obviously reduced, and the aspect ratio of the subsequent second trench can be further reduced.

Step S304, the first intermediate structure is ground to the stop layer from top to bottom, and the first cavity is ground to form a second groove.

In this step, as shown in fig. 7, chemical Mechanical Polishing (CMP) is performed on the first intermediate structure 50 from top to bottom until the polishing reaches the stop layer 44, resulting in a third intermediate structure 70. Since the polishing rate of the middle portion of the first intermediate structure 50 is different from that of the remaining portion, uniformity of the thickness of the third intermediate structure 70 obtained after polishing can be ensured due to the presence of the stop layer 44.

In addition, since the dielectric constant of the third dielectric layer 433 is low, the material is loose, and the hardness of the stop layer 44 is large, the patterns on the third dielectric layer 433 can be protected from being damaged by grinding to a certain extent, and the stability of the structure can be ensured.

As shown in fig. 7, after polishing, the structure obtained after polishing may be cleaned with a cleaning liquid, and in theory, the cleaning liquid does not dissolve copper, but it is uncertain whether the opening width of the second trench 71 after cleaning becomes large or not, and therefore, the opening width of the second trench 71 after cleaning becomes large or remains unchanged.

Since the stop layer 44 is substantially aligned with the middle of the first cavity, when the first intermediate structure 50 is polished from top to bottom to obtain the second trench 71, the opening width of the second trench 71 can be accurately controlled to be substantially the maximum width of the first cavity in the bottom-up direction, and the opening width of the second trench 71 formed after the polishing of the first cavity 52 is greater than the width at the position of half the depth of the second trench 71. Thus, formation of an overhang structure at the opening of the second trench 71 can be avoided at the time of subsequent copper plating, and further generation of void defects can be reduced.

Moreover, the aspect ratio of the second trench 71 is reduced compared to the aspect ratio of the trench in the related art for manufacturing the metal interconnection structure, and thus the occurrence of void defects can be reduced. As shown in fig. 7, the aspect ratio of the second trench 71 is a ratio of the depth H of the second trench 71 to the width W at a position half of the depth H of the second trench 71.

Since the opening width of the second trench 71 is substantially the maximum width of the first cavity in the bottom-up direction, the process window can be widened.

Since the stop layer 44 is substantially aligned with the middle portion of the first cavity, when the first intermediate structure 50 is polished from top to bottom to obtain the second trench 71, the opening width of the second trench 71 can be accurately controlled to be substantially the maximum width of the first cavity in the bottom-up direction, and the process stability is good.

And step S305, filling a metal material into the second groove to form a second metal interconnection structure, so as to obtain a second intermediate structure.

In this step, as shown in fig. 8, a second metal interconnection structure 81 may be formed by filling a metal material into the second trench 71 using an electroplating method, resulting in a second intermediate structure 80. Specifically, a second seed layer may be formed inside and outside the second trench 71, and the second seed layer covers the inner surface of the second trench 71 and the first adhesive layer 442 outside the first trench. The second seed layer may be a copper seed layer, and then copper is electroplated on the second seed layer to form the second metal interconnection structure 81, wherein the metal material filled in the second trench is electroplated to form the second electroplated layer 515 together with the first electroplated layer 513. The second plating layer 515 has no void defects.

In step S306, the second intermediate structure is polished from top to bottom until the stop layer is removed, and the second metal interconnection structure is polished to form a third metal interconnection structure.

In this step, as shown in fig. 9, the second intermediate structure 80 may be polished from top to bottom by using a chemical mechanical polishing method until the stop layer 44 is removed, and the second metal interconnection structure 81 is polished to form a third metal interconnection structure 91. The second plating layer 515 is polished to form a third plating layer 516. The third plating layer 516 has no void defects therein.

In the embodiment of the invention, since the stop layer is basically aligned with the middle part of the first cavity, when the first intermediate structure is ground from top to bottom to obtain the second groove, the opening width of the second groove can be accurately controlled to be basically the maximum width of the first cavity in the bottom-up direction, and the opening width of the second groove formed after the first cavity is ground is larger than the width of the position of half of the depth of the second groove, so that when the second groove is filled with metal to form the second metal interconnection structure, the overhang structure formed at the edge of the second groove can be reduced, and the depth-width ratio of the second groove is reduced compared with the depth-width ratio of the groove when the metal interconnection structure is prepared in the related art.

Moreover, since the stop layer 44 is substantially aligned with the middle portion of the first cavity, when the first intermediate structure 50 is polished from top to bottom to obtain the second trench 71, the opening width of the second trench 71 can be accurately controlled to be substantially the maximum width of the first cavity in the bottom-up direction, and the process is stable.

The method of fabricating the interconnect lines in the semiconductor device is described in detail above. In other embodiments, the invention may also be used to prepare contact plugs for electrically connecting the gate, source, drain and external devices. In this embodiment, the conductive structure 42 may be a source, drain, or gate.

Another embodiment of the present application also provides a semiconductor device. As shown in fig. 9, the semiconductor device includes a semiconductor stacked structure 41, a first insulating layer 43, and a third metal interconnection structure 91.

As shown in fig. 9, the semiconductor stacked structure 41 includes a conductive structure 42, and the conductive structure 42 is located in the semiconductor stacked structure 41 and exposed from the semiconductor stacked structure 41.

The first insulating layer 43 is located on the semiconductor stacked structure 41, and a first trench (not shown) is formed in the first insulating layer 43, and the first trench exposes the conductive structure 42.

The third metal interconnect structure 91 fills in the first trench, contacting the conductive structure 42. The third metal interconnect structure 91 is fabricated using the methods described above.

In the embodiment of the invention, since the stop layer is substantially aligned with the middle part of the first cavity, when the first intermediate structure is ground from top to bottom to obtain the second trench, the opening width of the second trench can be accurately controlled to be substantially the maximum width of the first cavity in the bottom-to-top direction, and the opening width of the second trench formed after the grinding of the first cavity is greater than the width at the position of half the depth of the second trench, therefore, when the second trench is filled with metal to form the second metal interconnection structure, the overhang structure formed at the edge of the second trench can be reduced, and the depth-to-width ratio of the second trench is reduced compared with the depth-to-width ratio of the trench when the metal interconnection structure is prepared in the related art.

In the present invention, the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. The term "plurality" refers to two or more, unless explicitly defined otherwise.

The embodiments are described above in order to facilitate the understanding and application of the present application by those of ordinary skill in the art. It will be apparent to those skilled in the art that various modifications can be readily made to these embodiments and the generic principles described herein may be applied to other embodiments without the use of the inventive faculty. Accordingly, the present application is not limited to the embodiments herein, and those skilled in the art, based on the present disclosure, make improvements and modifications within the scope and spirit of the application.

Claims (10)

1. A method of fabricating a metal interconnect structure, comprising:

Sequentially forming a first insulating layer, a stop layer and a second insulating layer on the semiconductor laminated structure from bottom to top, wherein the semiconductor laminated structure comprises a conductive structure which is positioned in the semiconductor laminated structure and is exposed from the semiconductor laminated structure;

etching the second insulating layer, the stop layer and the first insulating layer to form a first groove, wherein the first groove exposes the conductive structure;

Filling a metal material into the first groove to form a first metal interconnection structure, so as to obtain a first intermediate structure, wherein the first metal interconnection structure is in contact with the conductive structure, and a first cavity is formed in the first metal interconnection structure;

Grinding the first intermediate structure from top to bottom until the first intermediate structure reaches the stop layer, wherein the first cavity is ground to form a second groove;

Filling the metal material into the second groove to form a second metal interconnection structure, so as to obtain a second intermediate structure;

And grinding the second intermediate structure from top to bottom until the stop layer is removed, and forming a third metal interconnection structure after grinding the second metal interconnection structure.

2. The method of manufacturing a metal interconnect structure of claim 1, wherein the first insulating layer comprises at least one insulating layer and the second insulating layer comprises at least one insulating layer.

3. The method of manufacturing a metal interconnect structure of claim 2, wherein the stop layer comprises a first barrier layer and a first adhesion layer laminated in sequence from bottom to top, the first adhesion layer being for adhering the metal material.

4. The method for manufacturing a metal interconnection structure according to claim 3, wherein the filling the first trench with the metal material to form the first metal interconnection structure, to obtain the first intermediate structure, includes:

sequentially forming a second barrier layer and a second bonding layer inside and outside the first groove, wherein the second bonding layer is used for bonding the metal material;

Forming a first seed layer, the first seed layer covering the second adhesion layer;

electroplating the metal material on the first seed layer to form the first metal interconnect structure.

5. The method for manufacturing a metal interconnection structure according to claim 4, wherein the filling the second trench with the metal material to form a second metal interconnection structure, obtaining a second intermediate structure, includes:

forming a second seed layer inside and outside the second groove, wherein the second seed layer covers the inner surface of the second groove and the first bonding layer outside the first groove;

And electroplating on the second seed layer to form the second metal interconnection structure.

6. The method of manufacturing a metal interconnect structure of claim 1, wherein the conductive structure is an electrode and the third metal interconnect structure is an interconnect line;

The semiconductor laminated structure comprises a source electrode, the electrode is in contact with the source electrode, or

The semiconductor laminated structure includes a drain electrode with which the electrode is in contact, or

The semiconductor stack structure includes a gate electrode, and the electrode is in contact with the gate electrode.

7. The method of claim 1, wherein the conductive structure is a source, a drain, or a gate, and the third metal interconnect structure is a contact plug.

8. The method of manufacturing a metal interconnect structure of claim 5, wherein the metal material comprises tungsten, copper, aluminum, or copper aluminum alloy.

9. The method of manufacturing a metal interconnect structure of claim 8, wherein when the metal material comprises copper, the material of the first barrier layer comprises tantalum nitride TaN and the material of the first adhesion layer comprises tantalum Ta;

The material of the second barrier layer comprises tantalum nitride TaN, and the material of the second bonding layer comprises tantalum Ta;

When the metal material comprises tungsten, the material of the first barrier layer comprises titanium Ti and the material of the first adhesion layer comprises titanium nitride TiN;

the material of the second barrier layer comprises titanium Ti and the material of the second adhesion layer comprises titanium nitride TiN.

10. A semiconductor device, comprising:

A semiconductor stack structure including a conductive structure, the conductive structure being located in the semiconductor stack structure and exposed from the semiconductor stack structure;

the first insulating layer is positioned on the semiconductor laminated structure, a first groove is formed in the first insulating layer, and the first groove exposes the conductive structure;

and a third metal interconnection structure filled in the first trench and in contact with the conductive structure, wherein the third metal interconnection structure is prepared by the method as claimed in any one of claims 1 to 9.