CN120787328A - Array substrate, display panel and display device - Google Patents

Abstract

An array substrate, a display panel and a display device. The array substrate comprises a plurality of first shading patterns (21) which are sequentially arranged at intervals along a first direction (X), at least one first shading pattern (21) in the plurality of first shading patterns (21) comprises a plurality of first shading main parts (211) and a plurality of first shading connecting parts (212), in the same first shading pattern (21), the first shading main parts (211) and the first shading connecting parts (212) are alternately arranged, the first electrode layer (3) comprises first hollowed-out parts (30), the first hollowed-out parts (30) comprise corner parts (G), the corner parts (G) are in orthographic projection of a first substrate (1) and are located between two adjacent first shading connecting parts (212) in the first direction (X), wherein the first shading main parts (211) are provided with first outer edges (w 1) which extend along a second direction (Y), and extension lines of the first outer edges (w 1) are in orthographic projection of the first substrate (1) and orthographic projection areas of the corner parts (G) on the first substrate (1).

Description

Array substrate, display panel and display device Technical Field

The disclosure relates to the technical field of semiconductors, and in particular relates to an array substrate, a display panel and a display device.

Background

Virtual reality technology is a new technology that integrates real world information and virtual world information "seamlessly". The most obvious feature of virtual reality display products is their ultra-high resolution relative to conventional display products. The optimal solution for realizing ultra-high resolution display is the Liquid crystal display (Liquid CRYSTAL DISPLAY, LCD) technology at present, because in the LCD display structure, the pixel area circuit has only one switching transistor (Thin Film Transistor, TFT), which is very beneficial to realizing high PPI.

Disclosure of Invention

The embodiment of the disclosure provides an array substrate, a display panel and a display device. The array substrate, wherein, include:

A first substrate;

The first light shielding layer is positioned on one side of the first substrate and comprises a plurality of first light shielding patterns which are sequentially arranged at intervals along a first direction, wherein at least one first light shielding pattern in the plurality of first light shielding patterns comprises a plurality of first light shielding main parts and a plurality of first light shielding connecting parts, and the first light shielding main parts and the first light shielding connecting parts are alternately arranged in the same first light shielding pattern, and the extending direction of the first light shielding connecting parts is intersected with the extending direction of the first light shielding main parts;

The first electrode layer is positioned on one side of the first shading layer, which is away from the first substrate, and comprises a first hollowed-out part, wherein the first hollowed-out part comprises a corner part, the orthographic projection of the corner part on the first substrate is positioned between two adjacent first shading connecting parts in the first direction;

The first shading main part is provided with a first outer edge extending along a second direction, an extension line of the first outer edge is in orthographic projection of the first substrate, an overlapping area is formed between the extension line and orthographic projection of the corner part on the first substrate, and the second direction is intersected with the first direction.

In one possible embodiment, the corner portions are projected in front of the first substrate, and are all located between two adjacent first light-shielding connection portions in the first direction.

In one possible embodiment, a portion of the first light-shielding connection portion is orthographic projected on the first substrate, overlapping a portion of the boundary of the corner portion at the first substrate orthographic projection.

In one possible embodiment, at least part of the end of the first light-shielding main portion is orthographic projected on the first substrate, and is located in orthographic projection of the corner portion on the first substrate.

In one possible embodiment, the maximum width of the first light-shielding connection portion in the first direction is smaller than the maximum width of the first light-shielding main portion in the first direction.

In one possible embodiment, the first light shielding connection part comprises a first sub-connection part, a second sub-connection part positioned at one side of the first sub-connection part, and a third sub-connection part positioned at the other side of the first sub-connection part;

One end of the second sub-connecting part is connected with the first shading main part, and the other end of the second sub-connecting part is connected with one end of the first sub-connecting part;

One end of the third sub-connecting part is connected with the other first shading main part, and the other end of the third sub-connecting part is connected with the other end of the first sub-connecting part.

In one possible implementation, the second sub-connection part extends along the second direction, and the first sub-connection part and the third sub-connection part extend along a third direction, wherein the third direction intersects with the first direction and the second direction.

In a possible embodiment, the first sub-connection portion, the second sub-connection portion, and the third sub-connection portion each extend along a third direction, wherein the third direction intersects the first direction and the second direction.

In one possible implementation mode, the first electrode layer further comprises a first electrode part, wherein the orthographic projection of the first electrode part on the first substrate is complementary with the orthographic projection of the first hollowed-out part on the first substrate;

And the front projection of the first electrode part on the first substrate covers the front projection of the first shading pattern on the first substrate.

In one possible implementation manner, the plurality of first shading patterns comprise a plurality of first shading main part rows, at least one first shading main part row of the plurality of first shading main part rows comprises a plurality of first shading main parts which are sequentially arranged along the first direction, the plurality of first hollowed-out rows comprise a plurality of first hollowed-out rows, at least one hollowed-out row of the plurality of first hollowed-out rows comprises a plurality of first hollowed-out rows which are sequentially arranged along the first direction, and the orthographic projection of the Nth first shading main part row on the substrate has an overlapping area with the orthographic projection of the Nth hollowed-out row on the first substrate;

The first hollowed-out part comprises a first sub hollowed-out part, a second sub hollowed-out part and a third sub hollowed-out part, wherein the second sub hollowed-out part of the nth hollowed-out row is positioned at one side of the first sub hollowed-out part facing the N-1 th hollowed-out row, the third sub hollowed-out part of the nth hollowed-out row is positioned at one side of the first sub hollowed-out part facing the (n+1) th hollowed-out row, the extending direction of the second sub hollowed-out part is crossed with the extending direction of the first sub hollowed-out part, and the extending direction of the third sub hollowed-out part is crossed with the extending direction of the first sub hollowed-out part;

The N-th orthographic projection of the extension line of the first outer edge of the first light-shielding main portion in the first light-shielding main portion row on the first substrate overlaps with the orthographic projection of the third sub-hollowed-out portion of the nth hollowed-out row on the first substrate, and overlaps with the orthographic projection of the second sub-hollowed-out portion of the n+1th hollowed-out row on the first substrate.

In one possible implementation, the array substrate further comprises a second electrode layer positioned on one side of the first light shielding layer facing the first substrate;

The second electrode layer comprises a plurality of second electrode rows extending along the first direction and arranged along the second direction, at least one second electrode row in the plurality of second electrode rows comprises a plurality of second electrodes, and the orthographic projection of the second electrodes on the first substrate is rectangular.

In one possible implementation manner, the orthographic projection of the nth second electrode row on the first substrate and the orthographic projection of the nth hollowed-out row on the first substrate have overlapping areas, and the orthographic projection of the second electrode of the nth second electrode row on the first substrate covers at least part of the orthographic projection of the second sub-hollowed-out part of the nth hollowed-out row on the first substrate, wherein N is a positive integer greater than or equal to 1.

In one possible implementation manner, the second electrode of the nth second electrode row has a second outer edge which is close to the (N-1) th second electrode row and extends along the first direction, the second sub-hollowed-out part of the nth hollowed-out row has a third outer edge which extends along the first direction, and the second outer edge is projected on the front side of the first substrate and is positioned on the side, facing the (N-1) th second electrode row, of the front projection of the third outer edge on the first substrate.

In one possible embodiment, the second electrode includes a second electrode main portion, and a second electrode extension connected to the second electrode main portion;

And the second electrode extension part is in orthographic projection on the first substrate and covers at least part of orthographic projection of the second sub-hollowed-out part on the first substrate.

In one possible embodiment, the extending direction of the second electrode extension is the same as the extending direction of the second sub-hollowed-out portion.

In one possible embodiment, the line width of the second electrode extension in the direction perpendicular to the extension direction is smaller than the width of the second sub-hollow portion in the direction perpendicular to the extension direction.

In one possible implementation manner, the orthographic projection of the second electrode main part on the first substrate and the orthographic projection of the second sub-hollowed-out part on the first substrate are not overlapped.

In one possible implementation, the array substrate further comprises an active layer positioned between the second electrode layer and the first substrate, and a first insulating layer positioned between the second electrode layer and the active layer, wherein the first insulating layer is provided with a first via hole, and the second electrode is electrically connected with part of the active layer at least through the first via hole;

The array substrate further comprises a second insulating layer filled in the first via hole.

In one possible embodiment, the orthographic projection of the first via on the first substrate has an overlapping area with the orthographic projection of the first light shielding connection on the first substrate.

In one possible embodiment, the array substrate further includes a third electrode layer between the active layer and the second electrode layer, and a third insulating layer between the third electrode layer and the active layer; the third electrode layer comprises a plurality of third electrodes, wherein the third insulating layer is provided with a second via hole;

The second electrode is electrically connected with the third electrode through the first via hole, and the third electrode is electrically connected with the active layer through the second via hole.

In one possible embodiment, the array substrate further includes a first signal line extending along the first direction, and a second signal line extending along the second direction;

The first shading main part is positioned between the orthographic projections of two adjacent first signal lines on the first substrate, and the orthographic projections of the first shading main part on the first substrate and the orthographic projections of the second signal lines on the first substrate have overlapping areas.

In one possible implementation manner, in the same first light shielding pattern, the orthographic projection of the first light shielding main part on the first substrate along the T th direction overlaps with the orthographic projection of the second signal line on the first substrate along the J th direction, the orthographic projection of the first light shielding main part on the first substrate along the t+1th direction overlaps with the orthographic projection of the second signal line on the first substrate along the j+1th direction, wherein T is a positive integer greater than or equal to 1, and J is a positive integer greater than or equal to 1.

In one possible embodiment, the front projection of the first light shielding connection portion on the first substrate has an overlapping area with the front projection of the first signal line on the first substrate.

In one possible embodiment, at least a portion of the first light-shielding connection portion is orthographic projected on the first substrate, and does not overlap with orthographic projection of the second signal line on the first substrate.

In one possible implementation manner, the front projection of the first hollowed-out portion on the first substrate and the front projection of the second signal line on the first substrate have an overlapping area.

In one possible implementation mode, the array substrate further comprises a second light shielding layer, wherein the second light shielding layer comprises a second light shielding pattern extending along the first direction, and the orthographic projection of the second light shielding pattern on the first substrate covers the orthographic projection of the first signal line on the first substrate;

the first shading main part is in orthographic projection of the first substrate, and is positioned between the orthographic projections of two adjacent second shading patterns on the first substrate.

In one possible embodiment, the length of the first light shielding main portion in the second direction is equal to the pitch of two adjacent second light shielding patterns in the second direction.

In one possible implementation, the second signal line is positioned between the third electrode layer and the active layer, the first signal line is positioned between the layer where the second signal line is positioned and the active layer, the third insulating layer comprises a first sub-insulating layer positioned between the first signal line and the active layer, and a second sub-insulating layer positioned between the first signal line and the second signal line;

The active layer comprises a first part extending along the second direction and a second part extending from one end of the first part, wherein the front projection of the first part on the first substrate and the front projection of the third electrode on the substrate have a first overlapping area, and the first overlapping area is electrically connected with the third electrode through the second via hole, and the front projection of the second part on the first substrate and the front projection of the second signal line have a second overlapping area, and the second overlapping area is electrically connected with the second signal line through the third via hole penetrating through the first sub-insulating layer and the second sub-insulating layer.

In one possible implementation manner, the array substrate further comprises a color film layer positioned on one side of the second electrode layer facing the first substrate;

The color film layer comprises a first color resistance part, a second color resistance part and a third color resistance part.

The embodiment of the disclosure also provides a display panel, which comprises the array substrate provided by the embodiment of the disclosure, and further comprises a counter substrate arranged opposite to the array substrate.

In one possible embodiment, the opposite substrate comprises a second substrate and a shading structure positioned on one side of the second substrate facing the first substrate;

the shading structure comprises a first film layer and a second film layer positioned on one side of the shading layer facing the second substrate, wherein the first film layer is a metal layer, and the second film layer at least comprises a non-metal layer.

In a possible implementation manner, the second film layer comprises a first sub-film layer and a second sub-film layer, wherein the first sub-film layer and the third sub-film layer are sequentially stacked, the second sub-film layer is located on one side of the first sub-film layer, which faces the array substrate, and the third sub-film layer is located on one side of the second sub-film layer, which faces the array substrate, wherein the first sub-film layer and the third sub-film layer are non-metal layers, and the second sub-film layer is a metal layer.

In one possible embodiment, the second film layer comprises an organic film layer, and the thickness of the organic film layer is smaller than the thickness of the first film layer.

The embodiment of the disclosure also provides a display device, which comprises the display panel provided by the embodiment of the disclosure.

Drawings

FIG. 1 is a schematic diagram of an array substrate according to an embodiment of the disclosure;

FIG. 2 is a schematic diagram of a second embodiment of an array substrate;

FIG. 3 is a third schematic diagram of an array substrate according to an embodiment of the disclosure;

FIG. 4A is a schematic diagram of an array substrate according to an embodiment of the disclosure;

Fig. 4B is a schematic design diagram of a first hollow provided in an embodiment of the disclosure;

FIG. 4C is a schematic diagram of an array substrate according to an embodiment of the disclosure;

FIG. 4D is a schematic diagram of a lamination of the first light shielding layer and the first electrode layer according to an embodiment of the disclosure;

FIG. 5 is a schematic diagram of an array substrate according to an embodiment of the disclosure;

FIG. 6A is one of the schematic cross-sectional views of FIG. 8A along the dashed line A1A 2;

FIG. 6B is one of the schematic cross-sectional views of the array substrate provided in the embodiments of the present disclosure;

FIG. 6C is a schematic diagram of a second cross-section of an array substrate according to an embodiment of the disclosure;

FIG. 7A is one of the schematic cross-sectional views of a display panel provided by embodiments of the present disclosure;

FIG. 7B is a second schematic cross-sectional view of a display panel according to an embodiment of the disclosure;

FIG. 8A is a schematic diagram of an array substrate according to an embodiment of the disclosure;

FIG. 8B is a schematic view of a single film layer of the layer of FIG. 8A with the second light shielding pattern;

FIG. 8C is a single layer schematic of the active layer of FIG. 8A;

FIG. 8D is a schematic diagram of a single layer of the first signal line in FIG. 8A;

FIG. 8E is a schematic diagram of a single layer of the second signal line in FIG. 8A;

FIG. 8F is a schematic diagram of a single film layer of the third electrode layer of FIG. 8A;

FIG. 8G is a schematic diagram of a single film layer of the second electrode layer of FIG. 8A;

FIG. 8H is a schematic view of a single film layer of the light shielding layer of FIG. 8A;

FIG. 8I is a schematic diagram of a single film layer of the first electrode layer of FIG. 8A;

FIG. 8J is a schematic diagram of an array substrate with a color film layer;

FIG. 8K is a schematic view of a single film layer of the color film layer of FIG. 8J;

FIG. 9 is a schematic diagram of an array substrate according to an embodiment of the disclosure;

FIG. 10 is a schematic diagram of an array substrate according to an embodiment of the disclosure;

FIG. 11A is a schematic diagram of the light efficiency corresponding to a conventional array substrate;

FIG. 11B is a schematic view of the light efficiency corresponding to the array substrate of FIG. 1;

FIG. 11C is a schematic view of the light efficiency corresponding to the array substrate of FIG. 4A;

FIG. 11D is a schematic view of the light efficiency corresponding to the array substrate of FIG. 5;

Fig. 11E is a schematic view of light efficiency corresponding to the array substrate corresponding to fig. 4C.

Detailed Description

Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Embodiments may be implemented in a number of different forms. One of ordinary skill in the art will readily recognize the fact that the patterns and matters may be changed into one or more forms without departing from the spirit and scope of the present disclosure. Accordingly, the present disclosure should not be construed as being limited to the following description of the embodiments. Embodiments of the present disclosure and features of embodiments may be combined with each other arbitrarily without conflict.

In the drawings, the size of one or more constituent elements, thicknesses of layers or regions may be exaggerated for clarity. Accordingly, one aspect of the present disclosure is not necessarily limited to this dimension, and the shapes and sizes of the various components in the drawings do not reflect actual proportions. Further, the drawings schematically show ideal examples, and one mode of the present disclosure is not limited to the shapes or numerical values shown in the drawings, and the like.

The ordinal numbers of "first", "second", "third", etc. in the present specification are provided to avoid mixing of constituent elements, and are not intended to be limited in number. The term "plurality" in this disclosure may include two as well as more than two numbers.

In the present specification, for convenience, words such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, which indicate an azimuth or a positional relationship, are used to describe positional relationships of constituent elements with reference to the drawings, only for convenience of description and simplification of the description, and do not indicate or imply that the apparatus or elements referred to must have a specific azimuth, be configured and operated in a specific azimuth, and thus are not to be construed as limiting the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which the constituent elements are described. Therefore, the present invention is not limited to the words described in the specification, and may be appropriately replaced according to circumstances.

In this specification, the terms "mounted," "connected," and "connected" are to be construed broadly, unless explicitly stated or limited otherwise. For example, they may be fixedly connected or detachably connected or integrally connected, they may be mechanically connected or electrically connected, they may be directly connected or indirectly connected through an intermediate member, or they may be in communication with the inside of two elements. The meaning of the above terms in the present disclosure can be understood by one of ordinary skill in the art as appropriate.

In this specification, "electrically connected" includes a case where constituent elements are connected together by an element having some electric action. The "element having a certain electric action" is not particularly limited as long as it can transmit an electric signal between the connected constituent elements. Examples of the "element having some electric action" include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, other elements having one or more functions, and the like.

In this specification, a transistor refers to an element including at least three terminals of a gate electrode (gate electrode), a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain) and a source electrode (source electrode terminal, source region, or source), and a current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, a channel region refers to a region through which current mainly flows.

In this specification, in order to distinguish between two electrodes of a transistor other than a gate electrode, one of the electrodes is referred to as a first electrode, which may be a source or a drain, and the other electrode is referred to as a second electrode, which may be a drain or a source. In addition, the gate of the transistor may be referred to as a control electrode. In the case of using a transistor having opposite polarity, or in the case of a change in the direction of current during circuit operation, the functions of the "source electrode" and the "drain electrode" may be interchanged. Therefore, in this specification, "source electrode" and "drain electrode" may be exchanged with each other.

In the present specification, "parallel" refers to a state in which two straight lines form an angle of-10 ° or more and 10 ° or less, and thus, may include a state in which the angle is-5 ° or more and 5 ° or less. Further, "vertical" refers to a state in which an angle formed by two straight lines is 80 ° or more and 100 ° or less, and thus may include a state in which an angle is 85 ° or more and 95 ° or less.

In the present specification, triangle, rectangle, trapezoid, pentagon, hexagon, or the like is not strictly defined, and may be approximated to triangle, rectangle, trapezoid, pentagon, hexagon, or the like, and there may be some small deformation due to tolerance, and there may be lead angles, arc edges, deformation, or the like.

In this specification, "film" and "layer" may be exchanged with each other. For example, the "conductive layer" may be sometimes replaced with a "conductive film". In the same manner, the "insulating film" may be replaced with the "insulating layer" in some cases.

The terms "about" and "approximately" as used herein refer to a situation where the limits are not strictly defined and where process and measurement errors are permitted. In the present specification, "substantially the same" may refer to a case where the numerical values differ by 10% or less.

For better immersion experience, screen window effect in use of Virtual Reality technology (VR) is reduced, resolution (Pixels Per Inch, PPI) of VR products is continuously improved, but the higher the PPI is, the smaller the pixel size is, the lower the transmittance of the display panel is, so the requirement for transmittance improvement is more and more urgent.

In view of this, an embodiment of the present disclosure provides an array substrate, as shown in fig. 1, where the array substrate includes:

A first substrate 1;

The first light shielding layer 2 is positioned on one side of the first substrate 1 and comprises a plurality of first light shielding patterns 21 which are sequentially arranged at intervals along a first direction X, wherein at least one first light shielding pattern 21 in the plurality of first light shielding patterns 21 comprises a plurality of first light shielding main parts 211 and a plurality of first light shielding connecting parts 212, and the first light shielding main parts 211 and the first light shielding connecting parts 212 are alternately arranged in the same first light shielding pattern 21, and the extending direction of the first light shielding connecting parts 212 is intersected with the extending direction of the first light shielding main parts 211;

The first electrode layer 3 is positioned on one side of the first shading layer 2 facing away from the first substrate 1, the first electrode layer 3 comprises a first hollowed-out part 30, the first hollowed-out part 30 comprises a corner part G, the orthographic projection of the corner part G on the first substrate 1 is positioned between two adjacent first shading connecting parts 212 in the first direction X, the first hollowed-out part 30 can comprise a first sub hollowed-out part 301, a second sub hollowed-out part 302 and a third sub hollowed-out part 303, and the corner part G can comprise a second sub hollowed-out part 302 and a third sub hollowed-out part 303, as shown in combination with fig. 5;

The first light-shielding main portion 211 has a first outer edge w1 extending in a second direction Y, and an orthographic projection of an extension line of the first outer edge w1 on the first substrate 1 has an overlapping area with an orthographic projection of the corner portion G on the first substrate 1, and the second direction Y intersects with the first direction X. Optionally, the second direction Y is perpendicular to the first direction X.

In the embodiment of the disclosure, the first light shielding layer 2 includes a plurality of first light shielding patterns 21, the first light shielding patterns 21 include first light shielding main portions 211 and first light shielding connection portions 212 alternately arranged along the second direction Y, the extending direction of the first light shielding connection portions 212 intersects with the extending direction of the first light shielding main portions 211, the first light shielding main portions 211 have a first outer edge w1 extending along the second direction Y, an extension line of the first outer edge w1 has an overlapping region with an orthographic projection of the corner portion G on the first substrate 1, and at least a portion of the orthographic projection of the first light shielding connection portions 212 does not overlap with an orthographic projection of the first hollow portions 30, that is, the first light shielding patterns 21 adopt a bending design, avoid the region of the first hollow portions 30, reduce the influence of the first light shielding layer 2 on an electric field driving liquid crystal deflection, and can optimize a dark region in a sub-pixel region and improve transmittance.

Specifically, the first light-shielding main portion 211 may extend in the second direction Y, and a portion of the first light-shielding pattern 21 extending in the second direction Y may be referred to as a first light-shielding main portion 211, and a portion connecting two adjacent first light-shielding main portions 211 may be referred to as a first light-shielding connecting portion 212.

Referring to fig. 11A, in the conventional array substrate structure, the first light shielding pattern is linear and extends vertically along the second direction, and due to the overlapping of the first light shielding pattern and the hollow area in the first electrode layer and the effect of the fringe electric field of the pixel electrode layer, a larger dark area exists in the sub-pixel opening area, and dark areas exist in the upper left corner and the lower right corner of the sub-pixel opening area, as shown by S1 and S2 in fig. 11A, the dark area is generated because the deflection direction of the liquid crystal in the area is opposite, so that the liquid crystal molecules in the area cannot deflect, and the dark area is formed. In the embodiment of the disclosure, by providing the array substrate structure shown in fig. 1, that is, the first light shielding patterns are provided in the shape of bent strips, the first light shielding patterns 21 of each strip are spaced from each other, and at least part of the first light shielding connection portion 212 is avoided from overlapping with the first hollow in the first electrode layer, so that the dark area at the S2 position in the sub-pixel opening area can be improved, as shown in fig. 11B.

In one possible embodiment, each of the first light shielding patterns 21 may be stripe-shaped, extend entirely along the second direction Y, and may be disconnected from each other in the first direction X.

In one possible implementation manner, the first light shielding layer 2 may be a film layer located on one side of the first electrode layer 3 away from the first substrate 1 and in direct contact with the first electrode layer 3, in one possible implementation manner, the first light shielding layer 2 may be a metal layer, on one hand, may perform light shielding to prevent cross color between adjacent sub-pixels, and reduce cross color level of the adjacent sub-pixels without increasing the black matrix opening, and on the other hand, the first light shielding layer 2 is a metal layer, and may reduce resistance of the first electrode layer 3.

In one possible embodiment, when the first light shielding layer 2 is a metal layer, the material of the first light shielding layer 2 may include any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), black chromium (Cr), and molybdenum (Mo), or an alloy material of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), may be a single layer structure, or a multi-layer composite structure, such as Ti/Al/Ti, etc.;

In one possible embodiment, the material of the first light shielding layer 2 may also be non-metal, for example, the first light shielding layer 2 may be a film layer coated with black pigment, such as a film layer of the same material as the black matrix.

In one possible embodiment, the first electrode layer 3 may be a common electrode layer, and the first electrode layer 3 may be a transparent electrode layer, and in one possible embodiment, the material of the first electrode layer 3 may include a metal oxide (e.g., indium tin oxide, indium doped zinc oxide (AZO), fluorine doped tin oxide (AZO), aluminum doped zinc oxide (AZO), indium doped cadmium oxide).

In one possible embodiment, as shown in fig. 1, two adjacent first light-shielding connection portions 212 are spaced apart from each other in the second direction Y, for example, a first light-shielding main portion 211 is spaced therebetween, and the front projection of the first hollow 30 on the first substrate 1 and the front projection of all the first light-shielding connection portions 212 on the first substrate 1 do not overlap each other. Therefore, the orthographic projection of the first light shielding connection portion 212 and the orthographic projection of the first hollow 30 can be avoided, so that the area of the first hollow 30 can be avoided to a greater extent, and the transmittance can be improved to a greater extent.

In one possible embodiment, referring to fig. 1, the front projection of the corner portion G on the first substrate 1 is located between two adjacent first light-shielding connection portions 211 in the first direction X, that is, the front projection of the first hollow 30 on the first substrate 1 and the front projection of the first light-shielding main portion 211 on the first substrate 1 do not overlap each other. That is, the front projection of the first light shielding pattern 21 on the first substrate 1 and the front projection of the first hollow 30 on the first substrate 1 do not overlap each other, so that the front projection of the first light shielding pattern 21 and the front projection of the first hollow 30 can be avoided from overlapping, the area of the first hollow 30 can be avoided to the greatest extent, and the transmittance is improved to the greatest extent.

In a possible embodiment, the orthographic projection of the corner portion G on the first substrate 1 may also be a orthographic projection of a portion of the first light-shielding connection 212 on the first substrate 1, which is partially located between two adjacent first light-shielding connection portions 211 in the first direction X, as shown in fig. 2, and a portion of the boundary of the corner portion G overlaps the orthographic projection of the first substrate 1.

In one possible embodiment, referring to fig. 2, at least part of the end of the first light-shielding main portion 211 is orthographically projected on the first substrate 1, and is located in the orthographic projection of the corner portion G on the first substrate 1.

In one possible embodiment, referring to fig. 1, the first light-shielding main portions 211 extend along the second direction Y, the first light-shielding main portions 211 have first outer edges w1 extending along the second direction Y, and in the same first light-shielding pattern 21, the extension lines of the first outer edges w1 of adjacent two first light-shielding main portions 211 do not overlap. That is, since the first light shielding patterns 21 are distributed in a bent shape as a whole, two adjacent first light shielding main portions 211 are not located in the same extending direction.

In one possible embodiment, referring to fig. 1, in the same first light shielding pattern 21, each first light shielding main portion 211 is along the second direction Y, but the extending directions of at least two adjacent first light shielding main portions 211 do not coincide.

As shown in fig. 1, since the shape of the first hollow-out portion 30 is generally a bent shape, the two end portions extend to two opposite directions respectively, so that a larger space is occupied in the first direction X, in a possible implementation manner, in this embodiment of the disclosure, the maximum width a1 of the first light-shielding connection portion 212 in the first direction X is smaller than the maximum width a2 of the first light-shielding main portion 211 in the first direction X, that is, the line width of the first light-shielding pattern 21 at the area where the end portion of the first hollow-out portion 30 is located is reduced, so that overlapping between the end portion of the first light-shielding pattern 21 and the first hollow-out portion 30 can be avoided, and the transmittance of the display panel is further improved.

In one possible embodiment, referring to fig. 1, the first light-shielding connection part 212 includes a first sub-connection part L1, a second sub-connection part L2 located at one side of the first sub-connection part L1, and a third sub-connection part L3 located at the other side of the first sub-connection part L1, one end of the second sub-connection part L2 is connected to a first light-shielding main part 211, for example, as shown in fig. 1, and the other end is connected to one end of the first sub-connection part L2, for example, as shown in fig. 1, and is connected to an upper end of the first sub-connection part L2, and one end of the third sub-connection part L3 is connected to another first light-shielding main part 211, for example, as shown in fig. 1, and the other end is connected to the other end of the first sub-connection part L1, for example, as shown in fig. 1, and is connected to a lower end of the first sub-connection part L2.

In one possible embodiment, referring to fig. 1, the extending directions of the first sub-connection portion L1, the second sub-connection portion L2, and the third sub-connection portion L3 are not overlapped with each other, so that the end portion of the first hollow portion 30 is completely avoided, and the first light shielding pattern 21 is prevented from overlapping with the end portion of the first hollow portion 30, so as to further improve the transmittance of the display panel.

In one possible embodiment, referring to fig. 1, the second sub-connection portion L2 extends along the second direction Y, the first sub-connection portion L1 and the third sub-connection portion L3 extend along the third direction Z, wherein the third direction Z intersects the first direction X and the second direction X, the first sub-connection portion L1 may extend along the second direction Y, the first angle α1 formed by the second sub-connection portion L2 and the first sub-connection portion L1 may be 35 ° to 60 °, for example, 35 ° 40 °,45 °,50 °,55 °,60 °, and the second angle α2 formed by the third sub-connection portion L3 and the first sub-connection portion L1 may be 35 ° to 60 °, for example, 35 °,40 °,45 °,50 °,55 °,60 °, but the second sub-connection portion L2 and the third sub-connection portion L3 are located on different sides of the first sub-connection portion L1, respectively. Optionally, the included angle formed by the third direction Z and the second direction Y may be 35 ° to 60 °, for example, may be 35 °,40 °,45 °,50 °,55 °,60 °;

In one possible embodiment, referring to fig. 2, the first sub-connection portion L1, the second sub-connection portion L2, and the third sub-connection portion L3 all extend along the third direction Z, where the third direction Z intersects the first direction X and the second direction Y, and the extending directions of the first sub-connection portion L1, the second sub-connection portion L2, and the third sub-connection portion L3 may also coincide, that is, the third included angle α3 formed by the three and the first light-shielding main portion 211 may be 35 ° to 60 °, for example, may be 35 °,40 °,45 °,50 °,55 °, or 60 °.

In one possible embodiment, referring to fig. 3, the first light shielding pattern 21 may include only the first light shielding main portions 211, and the first light shielding main portions 211 are not connected to each other at intervals in the same first light shielding pattern 21. Thus, the first light shielding pattern 21 and the first hollow 30 can be prevented from overlapping, and the transmittance of the display panel can be further provided.

In a possible embodiment, see fig. 1, the first electrode layer 3 further comprises a first electrode portion 31, an orthographic projection of the first electrode portion 31 on the first substrate 1 is complementary to an orthographic projection of the first hollow 30 on the first substrate 1, that is, a part of the area of the first electrode layer 3 is hollowed out as the first hollow 30, and the rest is the first electrode portion 31, an orthographic projection of the first electrode portion 31 on the first substrate 1 covers an orthographic projection of the first light shielding pattern 21 on the first substrate 1, and an orthographic projection of the first light shielding pattern 21 on the first substrate 1 may be located within the orthographic projection of the first electrode portion 31 on the first substrate 1.

In one possible embodiment, referring to fig. 4D, the plurality of first light-shielding patterns 21 include a plurality of first light-shielding main portion rows 200, at least one first light-shielding main portion row 200 of the plurality of first light-shielding main portion rows 200 includes a plurality of first light-shielding main portions 211 sequentially arranged along a first direction, an array substrate may include a plurality of first hollow portions 300 sequentially arranged along a second direction Y and extending along a first direction X, at least one hollow portion 300 of the plurality of first hollow portions 300 includes a plurality of first hollow portions 30 sequentially arranged along the first direction X, the first hollow portions 30 include a first sub hollow portion 301, a second sub hollow portion 302, and a third sub hollow portion 303, the extending direction of the second sub hollow portion 302 is intersected with the extending direction of the first sub hollow portion 301, the extending direction of the third sub hollow portion 303 is intersected with the extending direction of the first sub hollow portion 301, the second sub hollow portion 302 and the third sub hollow portion 300 are located on the first side of the first hollow portion 300, i.e., the first hollow portion 300 is located on the first side of the first hollow portion 1 to the first hollow portion 300N;

The orthographic projection of the first outer edge extension w1 of the first light-shielding main portion 211 in the nth first light-shielding main portion row 200 on the first substrate 1 overlaps the orthographic projection of the third sub-hollowed-out portion 303 of the nth hollowed-out row 300 on the first substrate 1, and overlaps the orthographic projection of the second sub-hollowed-out portion 302 of the n+1th hollowed-out row 300 on the first substrate 1.

In one possible embodiment, the n+1th hollowed-out row 300 may be the next hollowed-out row 300 of the N-th hollowed-out row 300 in the gate signal scanning direction.

In one possible embodiment, as shown in fig. 4B, the included angle θ1 formed by the first hollow portion 30 and the first direction X may be 80 ° to 100 °, for example, may be 80 ° to 145 °,85 °,90 °,95 °, or 100 °, in one possible embodiment, as shown in fig. 4B, the included angle θ2 formed by the second sub-hollow portion 302 and the first sub-hollow portion 301 may be 140 ° to 145 °, for example, may be 140 °,141 °,142 °,143 °, or 145 °, in one possible embodiment, as shown in fig. 4B, the included angle θ3 formed by the third sub-hollow portion 303 and the first sub-hollow portion 301 may be 140 ° to 145 °, for example, may be 140 °,141 °,142 °,143 °,144 °, or 145 °, in one possible embodiment, as shown in fig. 4B, the length h1 of the second sub-hollow portion 302 in the second direction Y may be 1.5 μm to 3 μm, for example, may be 140 °,141 °,142 °,144 °, or 145 °, in the first direction Y2.5 μm may be 1.5 μm, and 2.3 μm may be 1, or 2 μm may be 2.5 μm, and 2.3 μm may be 2.3, as shown in the first direction, and 2.5 μm may be 2 μm, and the length of the second sub-hollow portion may be 2.3 may be 2.5 μm, and may be 2.5 μm, for example, the length may be 2 μm, and the length may be 3. The included angle θ2 formed by the second sub-hollowed-out portion 302 and the first sub-hollowed-out portion 301, the included angle θ3 formed by the third sub-hollowed-out portion 303 and the first sub-hollowed-out portion 301, the length h1 of the second sub-hollowed-out portion 302 in the second direction Y, and the length h2 of the third sub-hollowed-out portion 303 in the second direction Y can represent the appearance of the corner of the first hollowed-out portion 30 at the upper and lower positions, and the scratch (trace mura) and the corner appearance can be comprehensively considered to perform the design as above.

In one possible embodiment, referring to FIG. 4A, the array substrate further includes a second electrode layer 4 positioned at a side of the first light shielding layer 2 facing the first substrate 1, the second electrode layer 4 including a plurality of second electrode rows 400 extending in the first direction X and arranged in the second direction Y, at least one second electrode row 400 of the plurality of second electrode rows 400 including a plurality of second electrodes 41;

The front projection of the mth second electrode row 400 on the first substrate 1 and the front projection of the nth hollow row 300 on the first substrate 1 have an overlapping area, that is, the mth second electrode row 400 and the nth hollow row 300 may be located in the same row, the front projection of the second electrode 41 of the mth second electrode row 400 on the first substrate 1 covers at least part of the front projection of the second sub hollow portion 302 of the nth hollow row on the first substrate 1, where M is a positive integer greater than or equal to 1, and N is a positive integer greater than or equal to 1.

In the embodiment of the disclosure, the second electrode 41 of the mth second electrode row 400 is projected forward on the first substrate 1, and the second sub-hollowed-out portion 302 covering the nth hollowed-out row is projected forward on at least a portion of the first substrate 1, that is, the second electrode layer 4 is moved upward relative to the first electrode layer 3, so that the second electrode 41 covers at least a portion of the second sub-hollowed-out portion 302, and as a result, the electric field is moved outward, and the dark area is moved outside the sub-pixel opening area, so that the dark area in the sub-pixel area can be reduced, and the transmittance is improved. Specifically, referring to fig. 11C, in the embodiment of the disclosure, by setting the array substrate structure shown in fig. 4A, that is, moving the second electrode layer 4 upward, a dark area at the S1 position can be improved, so as to further improve the transmittance of the display panel, and specifically, the transmittance of the display panel can be improved by 8%.

In one possible embodiment, the (m+1) th second electrode row 400 may be a next second electrode row 400 of the (M) th second electrode row 400 in the gate signal scanning direction.

In one possible embodiment, the second electrode layer 4 may be a pixel electrode layer, in one possible embodiment, the second electrode layer 4 may be a transparent electrode layer, and in one possible embodiment, the material of the second electrode layer 4 may include a metal oxide (e.g., indium tin oxide, indium doped zinc oxide (AZO), fluorine doped tin oxide (AZO), aluminum doped zinc oxide (AZO), indium doped cadmium oxide.

In one possible embodiment, referring to fig. 4A, the second electrode 41 is rectangular in front projection on the first substrate 1.

In one possible embodiment, referring to fig. 4A, the length of the second electrode 41 in the second direction Y may be greater than the length in the first direction X.

In one possible embodiment, referring to fig. 4A, the length d1 of the second electrode 41 in the second direction Y may be substantially equal to the length d2 of the first hollow 30 in the second direction Y.

In one possible embodiment, referring to fig. 4A, the front projection of the second electrode 42 on the first substrate 1 may cover the front projection of the first sub-hollowed-out portion 301 on the first substrate 1.

In one possible embodiment, referring to fig. 4A, the second electrode 41 of the mth second electrode row 400 has a second outer edge w2 adjacent to the mth-1 second electrode row 400 and extending along the first direction X, the second sub-hollowed-out portion 302 of the nth hollowed-out row 300 has a third outer edge w3 extending along the first direction X, and the second outer edge w2 of the mth second electrode row 400 is projected forward on the first substrate 1, and the third outer edge w3 of the nth hollowed-out row 300 is projected forward on the first substrate 1 toward the N-1 second electrode row 400. Therefore, the electric field is moved outwards, the dark area is moved to the outside of the sub-pixel opening area, the dark area in the sub-pixel area is reduced, and the transmittance of the display panel is improved.

In a possible embodiment, the front projection of the second outer edge w2 of the mth second electrode row 400 on the first substrate 1 may coincide with the front projection of the third outer edge w3 of the nth hollowed-out row 300 on the first substrate 1.

In a possible embodiment, the second outer edge w2 of the mth second electrode row 400 may be located on a side of the first corner facing the N-1 th second electrode row 400 in the orthographic projection of the first substrate 1, where the first corner may be a position where the first sub-hollowed-out portion 301 is joined with the second sub-hollowed-out portion 302.

In one possible embodiment, referring to fig. 5, the second electrode 41 includes a second electrode main portion 411 and a second electrode extension portion 412 connected to the second electrode main portion 411, and the second electrode extension portion 412 is projected on the front surface of the first substrate 1, and covers at least a portion of the second sub-hollowed-out portion 302 projected on the front surface of the first substrate 1. In the embodiment of the disclosure, by disposing the second electrode extension portion 412 at one end of the second electrode main portion 411, the electric field forming the dark area is also moved outwards, so that the dark area is moved to the outside of the sub-pixel opening area, the dark area in the sub-pixel area is reduced, and the transmittance of the display panel is improved. Specifically, referring to fig. 11D, in the embodiment of the disclosure, by setting the array substrate structure shown in fig. 5, that is, moving the second electrode layer 4 upwards, the dark area at the S1 position can be improved, so as to further improve the transmittance of the display panel, and specifically, the transmittance of the display panel can be improved by 3%.

In one possible embodiment, referring to fig. 5, the extending direction of the second electrode extension portion 412 is the same as the extending direction of the second sub-hollowed-out portion 302. In this embodiment of the disclosure, the extending direction of the second electrode extending portion 412 is set to be approximately the same as the extending direction of the second sub-hollowed portion 302, so that the second electrode extending portion 412 can avoid the setting position of the partial via hole (for example, as shown in fig. 5, the via hole that is conducted between the second electrode 41 and the active layer is set directly above the second electrode 41), and further, the influence on the flatness of the second electrode 41 can be avoided, and further, the influence on the display effect is avoided.

In one possible embodiment, referring to fig. 5, the line width b1 of the second electrode extension 412 in the direction perpendicular to the extension direction is smaller than the width b2 of the second sub-hollowed-out portion 302 in the direction perpendicular to the extension direction. In the embodiment of the disclosure, the second electrode extension 412 is set smaller in the line width b1 perpendicular to the extension direction, so that the second electrode extension 412 can avoid the setting position of the partial via hole (for example, as shown in fig. 5, the via hole conducting between the second electrode 41 and the active layer is set right above the second electrode 41), thereby avoiding affecting the flatness of the second electrode 41 and further avoiding affecting the display effect.

In one possible embodiment, referring to fig. 5, the front projection of the second electrode main portion 411 on the first substrate 1 and the front projection of the second sub-hollowed-out portion 302 on the first substrate 1 do not overlap each other. That is, in the embodiment of the present disclosure, the outer movement of the electric field forming the dark region may be achieved by providing the second electrode extension 412 instead of the entire upward movement of the second electrode layer 4, thereby improving the transmittance of the display panel.

In one possible embodiment, referring to fig. 5, the fourth angle α4 formed by the second electrode extension 412 and the second electrode main portion 411 may range from 95 ° to 160 °, for example, may be 95 °,100 °,110 °,120 °,130 °,140 °,145 °,150 °, or 160 °.

In one possible embodiment, referring to fig. 4C, the first light shielding pattern 21 may be configured as a bent structure, and the second electrode 41 may be moved upward, to improve the transmittance of the display panel, and in particular, referring to fig. 11E, by using the array substrate structure shown in fig. 4C, the dark areas at the S1 and S2 positions may be improved, and the transmittance of the display panel may be improved by 18%.

In a possible implementation manner, referring to fig. 6A and fig. 8A-8H, where fig. 6A may be a schematic cross-sectional view along a dashed line A1A2 in fig. 8A, fig. 8A is one of schematic structural views of an array substrate provided by an embodiment of the disclosure, fig. 8B is a schematic single-layer view of a layer where the second light shielding pattern is located in fig. 8A, fig. 8C is a schematic single-layer view of an active layer in fig. 8A, fig. 8D is a schematic single-layer view of a layer where the first signal line is located in fig. 8A, fig. 8E is a schematic single-layer view of a layer where the second signal line is located in fig. 8A, fig. 8F is a schematic single-layer view of a third electrode layer in fig. 8A, fig. 8G is a schematic single-layer view of a second electrode layer in fig. 8A, fig. 8H is a schematic single-layer view of a light shielding layer in fig. 8I is a schematic single-layer of a first electrode layer in fig. 8A, and the array substrate further includes a single-layer between the second electrode layer 4 and the first substrate 1 and the active layer 5 between the first electrode 4 and the active layer 61; the first insulating layer 61 has a first via hole K1, the second electrode 41 is electrically connected with a part of the active layer 5 at least through the first via hole K1, the array substrate further comprises a second insulating layer 62 filled in the first via hole K1, and the difference in level between the surface of the second insulating layer 62 facing away from the first substrate 1 and the surface of the first insulating layer 61 facing away from the first substrate 1 is less than 0.2 μm. In the embodiment of the disclosure, the display substrate further includes a second insulating layer 62 filled in the first via hole K1, where the second insulating layer 62 faces away from the surface of the first substrate 1, and the level difference between the second insulating layer 62 and the surface of the first insulating layer 61 facing away from the first substrate 1 is smaller than 0.2 μm, so that the first via hole K1 is filled and leveled, and when the second electrode 41 is moved up by the array substrate structure shown in fig. 5 to realize the outward movement of the electric field forming the dark area, the second electrode 41 can be prevented from being leveled in the upward movement process of the second electrode 41, so that the flatness of the second electrode 41 is prevented from being affected, and further the display effect is prevented from being affected, and the level difference between the second insulating layer 62 and the surface of the first insulating layer 61 facing away from the first substrate 1 is smaller than 0.2 μm, so that if the level difference is above 0.2 μm, the liquid crystal orientation of the first via hole K1 is prevented from being generated during the alignment process, and the problem of the peripheral via hole K1 is prevented from being abnormally leaked.

In one possible embodiment, referring to fig. 8A, the front projection of the first via K1 on the first substrate 1 has an overlapping area with the front projection of the first light shielding connection 212 on the first substrate 1.

In one possible embodiment, referring to fig. 6B, the second electrode 41 may include a first sub-electrode 401 and a second sub-electrode 402, where the first sub-electrode 401 is partially located at the bottom of the first via K1, partially located at the sidewall of the first via K1, and partially extends to the surface of the first insulating layer 61 on the side facing away from the first substrate 1;

In one possible implementation, the orthographic projection of the second sub-electrode 402 on the first substrate 1 may cover at least part of the orthographic projection of the first via K1 on the first substrate 1, and since the second electrode 41 is distributed in the first via K1, the second electrode 41 may form an electric field with an electrode layer above the second electrode 41 (for example, the first electrode layer 3) in the hole, and thus may interfere with a normal electric field formed by the second electrode 41 and the first electrode layer 3, and thus affect normal deflection loaded on the liquid crystal, and the orthographic projection of the first via K1 on the first substrate 1 is covered by the second sub-electrode 402, so that the electric field in the hole may be shielded to achieve a stable electric field effect.

In one possible embodiment, referring to fig. 6B and 8A-8H, the array substrate further includes a third electrode layer 7 between the active layer 5 and the second electrode layer 4, and a third insulating layer 63 between the third electrode layer 7 and the active layer 5, the third electrode layer 7 includes a plurality of third electrodes 71, the third insulating layer 63 has a second via K2, and specifically, as shown in fig. 6B and 9, the second electrode 41 is electrically connected to the third electrode 71 through the first via K1, and the third electrode 71 is electrically connected to the active layer 5 through the second via K2.

In one possible embodiment, and in particular as shown in connection with fig. 6B and 9, the third electrode layer 7 may be a switching electrode layer, in one possible embodiment the third electrode layer 7 may be a transparent electrode layer, and in one possible embodiment the material of the third electrode layer 7 may comprise a metal oxide (e.g. indium tin oxide, indium doped zinc oxide (AZO), fluorine doped tin oxide (AZO), aluminum doped zinc oxide (AZO), indium doped cadmium oxide).

In one possible implementation, referring to fig. 10, where fig. 10 is a schematic stacked view of a portion of the film layer in fig. 8A, the array substrate further includes a first signal line 81 extending along a first direction X and a second signal line 82 extending along a second direction Y, the front projection of the first light-shielding main portion 211 on the first substrate 1 is located between the front projections of two adjacent first signal lines 81 on the first substrate 1, and the front projection of the first light-shielding main portion 211 on the first substrate 1 and the front projection of the second signal line 82 on the first substrate 1 have overlapping areas.

In one possible embodiment, referring to fig. 10, in the same first light shielding pattern 21, the orthographic projection of the T-th first light shielding main portion 211 along the second direction Y on the first substrate 1 overlaps the orthographic projection of the J-th second signal line 82 along the first direction X on the first substrate 1, and the orthographic projection of the t+1th first light shielding main portion 211 along the second direction Y on the first substrate 1 overlaps the orthographic projection of the j+1th second signal line 82 along the first direction X on the first substrate 1, wherein M is a positive integer greater than or equal to 1, and J is a positive integer greater than or equal to 1. That is, in the same first light shielding pattern 21, two adjacent first light shielding main portions 211 overlap two adjacent second signal lines 82, that is, the plurality of first light shielding main portions 211 of the first light shielding pattern 21 are respectively displaced in different sub-pixel rows, and each time a sub-pixel row is moved down, the first light shielding main portions 211 are displaced once, so that the bending structure is formed, and at the same time, the light transmission affecting the sub-pixel opening area can be avoided.

In one possible embodiment, referring to fig. 10, the front projection of the first light shielding connection portion 212 on the first substrate 1 has an overlapping area with the front projection of the first signal line 81 on the first substrate 1.

In one possible embodiment, referring to fig. 10, at least a portion of the first light-shielding connection portion 212 projected on the first substrate 1 does not overlap with the projected portion of the second signal line 82 on the first substrate 1. In one possible embodiment, referring to fig. 10, the first light-shielding connection portion 212 is orthographically projected on the first substrate 1, and is located between orthographically projections of two adjacent second signal lines 82 on the first substrate 1.

In one possible embodiment, referring to fig. 10, the front projection of the first hollow 30 on the first substrate 1 has an overlapping area with the front projection of the second signal line 82 on the first substrate 1.

In one possible embodiment, referring to fig. 10, the array substrate further includes a second light shielding layer including second light shielding patterns 83 extending along the first direction X, an orthographic projection of the second light shielding patterns 83 on the first substrate 1 covers an orthographic projection of the first signal lines 81 on the first substrate 1, and an orthographic projection of the first light shielding main portion 211 on the first substrate 1 is located between orthographic projections of adjacent two second light shielding patterns 83 on the first substrate 1.

In one possible embodiment, referring to fig. 10, a length c1 of the first light shielding main portion in the second direction Y is equal to a pitch c2 of two adjacent second light shielding patterns 83 in the second direction Y.

In one possible embodiment, referring to fig. 6B and 8A-8H, the second signal line 82 is located between the third electrode layer 7 and the active layer 5, the first signal line 81 is located between the layer where the second signal line 82 is located and the active layer 5, the third insulating layer 63 includes a first sub-insulating layer 631 located between the first signal line 81 and the active layer 5, and a second sub-insulating layer located between the first signal line 81 and the second signal line 82, the active layer 5 includes a first portion 51 extending in the second direction Y, and a second portion 52 extending from one end of the first portion 51, a front projection of the first portion 51 on the first substrate 1 has a first overlapping region with a front projection of the third electrode 71 on the first substrate 1 and is electrically connected to the third electrode 71 through the second via K2 in the first overlapping region, and a portion of the second portion 52 on the front projection of the first substrate 1 has a second overlapping region with the second signal line 82 on the first substrate 1 and is electrically connected to the second sub-insulating layer 632 through the second sub-insulating layer 82 in the second overlapping region 631.

In one possible embodiment, the first signal line 81 may be a gate line, the second signal line 82 may be a data line, the second light shielding pattern 83 may be a light shielding layer, and in one possible embodiment, the orthographic projection of the third light shielding pattern 83 on the first substrate 1 may cover at least a portion of the orthographic projection of the active layer 5 on the first substrate 1, so as to avoid that external light irradiates the channel region of the active layer 5, thereby affecting the transistor characteristics.

In one possible implementation, referring to fig. 6B, the array substrate further includes a first spacer 91 located on a side of the first electrode layer 3 facing away from the first light shielding layer 2, and an orthographic projection of the first spacer 91 on the first substrate 1 overlaps an orthographic projection of the first via K1 on the first substrate 1.

In one possible embodiment, referring to fig. 8J, 8K and 6B, the array substrate further includes a color film layer 93 located on a side of the second electrode layer 4 facing the first substrate 4, and the color film layer 93 includes a first color resist 931, a second color resist 932 and a third color resist 933. In the embodiment of the disclosure, the array substrate further includes a color film layer 93 to avoid cross color between different sub-pixels, which can be suitable for display products above 1500 PPI.

In a possible implementation manner, referring to fig. 6C, the array substrate may not be provided with a color film layer, and the cross color between different sub-pixels may be improved by the first light shielding layer 2, so that the cross color level is reduced without increasing the black matrix.

In one possible implementation, the material of the active layer 5 includes a metal oxide semiconductor material, the metal oxide semiconductor material may include any one or more of amorphous indium gallium zinc oxide material (a-IGZO), zinc oxynitride (ZnON), or Indium Zinc Tin Oxide (IZTO), indium Gallium Zinc Oxide (IGZO), indium Gallium Oxide (IGO), indium Gallium Zinc Tin Oxide (IGZTO), indium Zinc Oxide (IZO), and rare earth element doped metal oxide (RE-OS), wherein the rare earth element doped metal oxide may include lanthanide doped metal oxide (Ln-OS), the active layer material may be amorphous, partially crystalline, or polycrystalline, and in the embodiment of the disclosure, the active layer 5 may have stable performance even if being illuminated, and further may not need to provide a light shielding layer in the pixel light transmitting region, so as to further improve the aperture ratio of the display panel. In the embodiment of the present disclosure, the active layer 5 of the display area transistor may be an oxide active layer, that is, a thin film transistor of the oxide active layer has advantages of low leakage current, and the like.

The present disclosure is applicable to transistors fabricated based on Oxide (Oxide) technology, silicon technology, or organic technology.

In one possible embodiment, the first insulating layer 62 may be a first flat layer, the second insulating layer 63 may be a second flat layer, the first sub-insulating layer 631 may be a first gate insulating layer, the second sub-insulating layer 632 may be a first interlayer dielectric layer, and the third sub-insulating layer 633 may be a second interlayer dielectric layer.

In one possible embodiment, as shown in fig. 6B or 6C, the array substrate may further include a third interlayer dielectric layer 14 between the active layer 5 and the layer where the second light shielding pattern 83 is located, and a second gate insulating layer 13 between the layer where the second light shielding pattern 83 is located and the first substrate 1, and a buffer layer 12 between the second gate insulating layer 13 and the first substrate 1, and a passivation layer 15 between the second electrode layer 4 and the first light shielding layer 2.

The embodiment of the disclosure also provides a display panel, which is shown in fig. 7A, and includes an array substrate as provided in the embodiment of the disclosure, and further includes an opposite substrate disposed opposite to the array substrate. And a liquid crystal layer 94 between the array substrate and the opposite substrate.

Aiming at the high PPI VR display product, along with the smaller and smaller aperture opening ratio, the black matrix of the organic resin material is easy to remain in the photoetching patterning process, so that the defects of dirt of the whole machine and half pixel bright points appear, in the related technology, the problem is improved by adopting the black matrix of the metal material, but the problem of ghost easily appears due to high reflectivity of the black matrix of the metal material, so that the problem of reducing the reflectivity of the black matrix of the metal material is urgently needed to be solved.

In view of this, referring to fig. 7A, the opposite substrate includes a second substrate 19, and a light shielding structure 18 located on a side of the second substrate 19 facing the first substrate 1, specifically, the light shielding structure 18 may be a black matrix, the light shielding structure 18 includes a first film layer 181, and a second film layer 182 located on a side of the first film layer 181 facing the second substrate 19, the first film layer 181 is a metal layer, and the second film layer 182 includes at least a non-metal layer. In the embodiment of the disclosure, the light shielding structure 18 includes the first film layer 181 and the second film layer 182, where the first film layer 181 is a metal layer, and the second film layer 182 includes at least a non-metal layer, where the second film layer 82 may be a film layer with reduced reflectivity, that is, by disposing the second film layer including the non-metal layer on a side of the first film layer 181 made of a metal material facing the array substrate, the reflectivity of the light shielding structure 18 may be reduced, thereby reducing the reflectivity of the display panel and improving the problem of ghost.

In one possible implementation, the second film 182 may also be a composite film structure, as shown in fig. 7B, where the second film 182 includes a first sub-film 183, a second sub-film 184 located on a side of the first sub-film 183 facing the array substrate, and a third sub-film 185 located on a side of the second sub-film 184 facing the array substrate, where the first sub-film 183 and the third sub-film 185 are non-metal layers, and the second sub-film 184 is a metal layer. In the embodiment of the disclosure, multi-film deposition is performed on the side of the first film 181 of the metal material facing the array substrate, and the reflectivity of the first film 181 of the metal material is reduced by using the multi-film interference principle. The film collocation can reduce the reflectivity of the shading structure from 45% to 6%, and the same level as that of the black matrix of the resin material is achieved.

In one possible embodiment, the thickness of the first film 181 may range from In this way, to ensure the light shielding performance of the light shielding structure 18, specifically, the thickness of the first film layer 181 may beOr (b)

In one possible embodiment, the thickness of the first sub-film layer 183 in a direction perpendicular to the second substrate 19 may be greater than the thickness of the third sub-film layer 185 in a direction perpendicular to the second substrate 19. In one possible embodiment, the thickness of the second sub-film 184 in a direction perpendicular to the second substrate 19 may be smaller than the thickness of the first film 181 in a direction perpendicular to the second substrate 19.

In one possible embodiment, the thickness of the first sub-film layer 183 in the direction perpendicular to the second substrate 19 may be in the range ofFor example, it may be Or (b)In one possible embodiment, the thickness of the second sub-film 184 in the direction perpendicular to the second substrate 19 may be in the range ofFor example, it may be Or (b)In one possible embodiment, the thickness of the third sub-film 185 in a direction perpendicular to the second substrate 19 may be in the range ofFor example, it may beOr (b)

In one possible embodiment, the material of the first sub-film layer 183 and the material of the third sub-film layer may be the same, for example, both may be silicon nitride (SiN).

In one possible embodiment, the second film 182 may also be a single film structure, and in particular, the second film 182 may include an organic film. Specifically, the second film 182 may be a resin material.

In one possible embodiment, the thickness of the organic film layer is less than the thickness of the first film layer 181. In one possible embodiment, the thickness of the organic film layer may also be equal to the thickness of the first film layer 181. In one possible embodiment, the thickness of the organic film layer may also be greater than the thickness of the first film layer 181.

In one possible embodiment, referring to fig. 7A, the opposite substrate may further include a first protective layer 16 on a side of the light shielding structure 18 facing away from the second substrate 19, and a second spacer 92 on a side of the first protective layer 16 facing away from the second substrate 19.

In one possible embodiment, referring to fig. 7A, the orthographic projection of the second spacer 92 on the first substrate 1 may overlap with the orthographic projection of the first spacer 91 on the first substrate 1.

Based on the same inventive concept, the embodiments of the present disclosure also provide a display device, including a display panel provided by the embodiments of the present disclosure.

While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the invention.

It will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments of the present invention without departing from the spirit or scope of the embodiments of the invention. Thus, if such modifications and variations of the embodiments of the present invention fall within the scope of the claims and the equivalents thereof, the present invention is also intended to include such modifications and variations.

Claims (34)

1. An array substrate, comprising:

   A first substrate;

   The first light shielding layer is positioned on one side of the first substrate and comprises a plurality of first light shielding patterns which are sequentially arranged at intervals along a first direction, wherein at least one first light shielding pattern in the plurality of first light shielding patterns comprises a plurality of first light shielding main parts and a plurality of first light shielding connecting parts, and the first light shielding main parts and the first light shielding connecting parts are alternately arranged in the same first light shielding pattern, and the extending direction of the first light shielding connecting parts is intersected with the extending direction of the first light shielding main parts;

   The first electrode layer is positioned on one side of the first shading layer, which is away from the first substrate, and comprises a first hollowed-out part, wherein the first hollowed-out part comprises a corner part, the orthographic projection of the corner part on the first substrate is positioned between two adjacent first shading connecting parts in the first direction;

   The first shading main part is provided with a first outer edge extending along a second direction, an extension line of the first outer edge is in orthographic projection of the first substrate, an overlapping area is formed between the extension line and orthographic projection of the corner part on the first substrate, and the second direction is intersected with the first direction.
2. The array substrate of claim 1, wherein orthographic projections of the corner portions on the first substrate are all located between adjacent two of the first light shielding connection portions in the first direction.
3. The array substrate of claim 1, wherein a portion of the first light-shielding connection portion is orthographic projected on the first substrate to overlap a portion of a boundary of the corner portion is orthographic projected on the first substrate.
4. The array substrate of claim 3, wherein at least a portion of the first light-shielding main portion end portion is orthographic projected on the first substrate within orthographic projection of the corner portion on the first substrate.
5. The array substrate of any one of claims 1 to 4, wherein a maximum width of the first light-shielding connection portion in the first direction is smaller than a maximum width of the first light-shielding main portion in the first direction.
6. The array substrate of any one of claims 1 to 5, wherein the first light shielding connection part comprises a first sub-connection part, a second sub-connection part positioned at one side of the first sub-connection part, and a third sub-connection part positioned at the other side of the first sub-connection part;

   One end of the second sub-connecting part is connected with the first shading main part, and the other end of the second sub-connecting part is connected with one end of the first sub-connecting part;

   One end of the third sub-connecting part is connected with the other first shading main part, and the other end of the third sub-connecting part is connected with the other end of the first sub-connecting part.
7. The array substrate of claim 6, wherein the second sub-connection portion extends in the second direction, and the first and third sub-connection portions extend in a third direction intersecting the first and second directions.
8. The array substrate of claim 4, wherein the first sub-connection portion, the second sub-connection portion, and the third sub-connection portion each extend along a third direction, wherein the third direction intersects the first direction and the second direction.
9. The array substrate of any one of claims 1-8, wherein the first electrode layer further comprises a first electrode portion, wherein the orthographic projection of the first electrode portion on the first substrate is complementary to the orthographic projection of the first hollowed-out portion on the first substrate;

   And the front projection of the first electrode part on the first substrate covers the front projection of the first shading pattern on the first substrate.
10. The array substrate of any one of claims 1-9, wherein the plurality of first light shielding patterns comprises a plurality of first light shielding main part rows, wherein at least one first light shielding main part row of the plurality of first light shielding main part rows comprises a plurality of first light shielding main parts sequentially arranged along the first direction, wherein the plurality of first hollowed-out rows comprise a plurality of first hollowed-out rows, wherein at least one hollowed-out row of the plurality of first hollowed-out rows comprises a plurality of first hollowed-out rows sequentially arranged along the first direction, wherein the orthographic projection of the Nth first light shielding main part row on the substrate has an overlapping area with the orthographic projection of the Nth hollowed-out row on the first substrate;

    The first hollowed-out part comprises a first sub hollowed-out part, a second sub hollowed-out part and a third sub hollowed-out part, wherein the second sub hollowed-out part of the nth hollowed-out row is positioned at one side of the first sub hollowed-out part facing the N-1 th hollowed-out row, the third sub hollowed-out part of the nth hollowed-out row is positioned at one side of the first sub hollowed-out part facing the (n+1) th hollowed-out row, the extending direction of the second sub hollowed-out part is crossed with the extending direction of the first sub hollowed-out part, and the extending direction of the third sub hollowed-out part is crossed with the extending direction of the first sub hollowed-out part;

    The N-th front projection of the extension line of the first outer edge of the first light-shielding main part in the first light-shielding main part row overlaps with the front projection of the third sub-hollowed-out part of the nth hollowed-out row on the substrate, and overlaps with the front projection of the second sub-hollowed-out part of the (n+1) -th hollowed-out row on the first substrate.
11. The array substrate of claim 10, wherein the array substrate further comprises a second electrode layer positioned at a side of the first light shielding layer facing the first substrate;

    The second electrode layer comprises a plurality of second electrode rows extending along the first direction and arranged along the second direction, at least one second electrode row in the plurality of second electrode rows comprises a plurality of second electrodes, and the orthographic projection of the second electrodes on the first substrate is rectangular.
12. The array substrate of claim 11, wherein the orthographic projection of the nth second electrode row on the first substrate and the orthographic projection of the nth hollowed-out row on the first substrate have overlapping areas, and the orthographic projection of the second electrode of the nth second electrode row on the first substrate covers at least part of the orthographic projection of the second sub-hollowed-out portion of the nth hollowed-out row on the first substrate, wherein N is a positive integer greater than or equal to 1.
13. The array substrate of claim 11 or 12, wherein the second electrode of the nth second electrode row has a second outer edge extending in the first direction near the (N-1) th second electrode row, the second sub-hollowed-out portion of the nth hollowed-out row has a third outer edge extending in the first direction, and an orthographic projection of the second outer edge on the first substrate is located on a side of the orthographic projection of the third outer edge on the first substrate toward the (N-1) th second electrode row.
14. The array substrate of claim 13, wherein the second electrode comprises a second electrode main portion, and a second electrode extension connected to the second electrode main portion;

    And the second electrode extension part is in orthographic projection on the first substrate and covers at least part of orthographic projection of the second sub-hollowed-out part on the first substrate.
15. The array substrate of claim 14, wherein the extending direction of the second electrode extension is the same as the extending direction of the second sub-hollowed-out portion.
16. The array substrate of claim 15, wherein a line width of the second electrode extension portion in a direction perpendicular to the extension direction is smaller than a width of the second sub-hollowed-out portion in the direction perpendicular to the extension direction.
17. The array substrate of any one of claims 13 to 16, wherein the orthographic projection of the second electrode main portion on the first substrate and the orthographic projection of the second sub-hollowed-out portion on the first substrate do not overlap each other.
18. The array substrate of any one of claims 11 to 17, wherein the array substrate further comprises an active layer between the second electrode layer and the first substrate, and a first insulating layer between the second electrode layer and the active layer, the first insulating layer having a first via through which the second electrode is electrically connected to at least a portion of the active layer;

    The array substrate further comprises a second insulating layer filled in the first via hole.
19. The array substrate of claim 18, wherein the orthographic projection of the first via on the first substrate has an overlapping area with the orthographic projection of the first light shielding connection on the first substrate.
20. The array substrate of claim 19, wherein the array substrate further comprises a third electrode layer between the active layer and the second electrode layer, and a third insulating layer between the third electrode layer and the active layer, the third electrode layer comprising a plurality of third electrodes;

    The second electrode is electrically connected with the third electrode through the first via hole, and the third electrode is electrically connected with the active layer through the second via hole.
21. The array substrate of claim 20, wherein the array substrate further comprises a first signal line extending in the first direction and a second signal line extending in the second direction;

    The first shading main part is positioned between the orthographic projections of two adjacent first signal lines on the first substrate, and the orthographic projections of the first shading main part on the first substrate and the orthographic projections of the second signal lines on the first substrate have overlapping areas.
22. The array substrate of claim 21, wherein in the same first light shielding pattern, a forward projection of a (T) th first light shielding main portion in the second direction on the first substrate overlaps with a forward projection of a (J) th second signal line in the first direction on the first substrate, and a forward projection of a (t+1) th first light shielding main portion in the second direction on the first substrate overlaps with a forward projection of a (j+1) th second signal line in the first direction on the first substrate, wherein T is a positive integer greater than or equal to 1, and J is a positive integer greater than or equal to 1.
23. The array substrate of claim 21 or 22, wherein the front projection of the first light shielding connection part on the first substrate has an overlapping area with the front projection of the first signal line on the first substrate.
24. The array substrate of any one of claims 21 to 23, wherein at least a portion of the first light-shielding connection portion is orthographic projected on the first substrate, and does not overlap with orthographic projection of the second signal line on the first substrate.
25. The array substrate of any one of claims 22-24, wherein the front projection of the first hollowed-out portion on the first substrate has an overlapping area with the front projection of the second signal line on the first substrate.
26. The array substrate of any one of claims 20 to 25, wherein the array substrate further comprises a second light shielding layer comprising a second light shielding pattern extending along the first direction, wherein an orthographic projection of the second light shielding pattern on the first substrate covers an orthographic projection of the first signal line on the first substrate;

    the first shading main part is in orthographic projection of the first substrate, and is positioned between the orthographic projections of two adjacent second shading patterns on the first substrate.
27. The array substrate of claim 26, wherein a length of the first light shielding main portion in the second direction is equal to a pitch of two adjacent second light shielding patterns in the second direction.
28. The array substrate of any one of claims 22 to 27, wherein the second signal line is positioned between the third electrode layer and the active layer, the first signal line is positioned between the layer where the second signal line is positioned and the active layer, the third insulating layer includes a first sub-insulating layer positioned between the first signal line and the active layer, and a second sub-insulating layer positioned between the first signal line and the second signal line;

    The active layer comprises a first part extending along the second direction and a second part extending from one end of the first part, wherein the front projection of the first part on the first substrate and the front projection of the third electrode on the substrate have a first overlapping area, and the first overlapping area is electrically connected with the third electrode through the second via hole, and the front projection of the second part on the first substrate and the front projection of the second signal line have a second overlapping area, and the second overlapping area is electrically connected with the second signal line through the third via hole penetrating through the first sub-insulating layer and the second sub-insulating layer.
29. The array substrate of any one of claims 9 to 28, wherein the array substrate further comprises a color film layer positioned on a side of the second electrode layer facing the first substrate;

    The color film layer comprises a first color resistance part, a second color resistance part and a third color resistance part.
30. A display panel comprising the array substrate according to any one of claims 1 to 29, further comprising an opposite substrate disposed opposite to the array substrate.
31. The display panel according to claim 30, wherein the counter substrate comprises a second substrate, and a light shielding structure on a side of the second substrate facing the first substrate;

    the shading structure comprises a first film layer and a second film layer positioned on one side of the shading layer facing the second substrate, wherein the first film layer is a metal layer, and the second film layer at least comprises a non-metal layer.
32. The display panel of claim 31, wherein the second film layer comprises a first sub-film layer and a second sub-film layer, wherein the first sub-film layer and the third sub-film layer are sequentially stacked, the second sub-film layer is positioned on one side of the first sub-film layer facing the array substrate, the third sub-film layer is positioned on one side of the second sub-film layer facing the array substrate, and the first sub-film layer and the third sub-film layer are non-metal layers, and the second sub-film layer is a metal layer.
33. The display panel of claim 32, wherein the second film layer comprises an organic film layer having a thickness less than a thickness of the first film layer.
34. A display device comprising the display panel of any one of claims 30-33.