CN1207775C - Buffer configuration and chip - Google Patents
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- CN1207775C CN1207775C CN 03101822 CN03101822A CN1207775C CN 1207775 C CN1207775 C CN 1207775C CN 03101822 CN03101822 CN 03101822 CN 03101822 A CN03101822 A CN 03101822A CN 1207775 C CN1207775 C CN 1207775C
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Abstract
The present invention discloses a configuration method of buffers and a chip thereof. The configuration method is used for configuring a plurality of buffers on one chip. The chip is provided with a signal source end and X output solder pads, wherein X is a positive integer. The configuration method of the present invention comprises: (a) configuring N-th layer buffers near to a middle position between every two output solder pads, and making each output solder pad to be electrically connected with the corresponding N-th layer buffers; (b) configuring (N+1)-th layer buffers near to a middle position between every two N-th layer buffers, and making each N-th layer buffer to be electrically connected with the corresponding (N+1)th layer buffer; judging whether the number of the (N+1)th layer buffers is 1 or not, if true, finishing the method, or else executing step c; (c) adding 1 to N, and repeating step (b).
Description
Technical field
The present invention relates to a kind of collocation method of buffer, particularly a kind of collocation method of buffer of the binary tree that forms one dimension.
Background technology
Integrated circuit (IC) industry can be said so and be grown up in recent years and develop industry the most fast.Technically, the progress that the semiconductor subassembly performance is maked rapid progress makes the multifunctionality of electronic product and conformability grow with each passing day, and the integrated circuit product that to be these constantly weed out the old and bring forth the new indispensable assembly, also therefore IC industry as the rising star that can be regarded as high-tech industry.
At present, (ElectronicDesign Automation, EDA) instrument are arranged (placement) and the step of connect up (routing) with ancillary works's teacher executive module can to use some electric design automations in the design process of integrated circuit.When these electronic design automation tools when the circuit layout on the chip is done optimized design, the condition of consideration comprises annexation and the path delay (path delay) between assembly (cell).But, only comprise gate delay (gate delay) path delay that general design tool is considered, do not contain connection delay (interconnect delay).But, owing to caused by connection delay the path delay of the signal of deep-sub-micrometer chip, so, the circuit design that these electronic design automation tools can't optimization deep-sub-micrometer chip.
Please refer to Fig. 1, it shows the schematic diagram of a use circuit layout that electronic design automation tool synthesized.As shown in Figure 1, have output weld pad (pad) 110,120,130,140,150,160,170 and 180, one signals source end (root) R on the chip 100, and buffer (buffer) B1, B2, B3, B4, B5 and B6.The spacing of adjacent output weld pad equates.Because the signal source end signal demand that R produced is transferred into the output weld pad 110,120,130,140,150,160,170 and 180 of chip 100 simultaneously, so need buffer B1, B2, B3, B4, B5 and B6 to amplify the source end signal that R exported, make that the signal after being exaggerated can promote a plurality of output weld pads.If exporting the signal of output weld pad 110,120,130,140,150,160,170 and 180 to from signal source end R is a clock signal (clock signal), and clock signal is a kind of signal that synchronisation requirement is arranged.So-called synchronisation requirement is meant, this clock signal is by the end R output of signal source, and is necessary identical with the time point that B6 arrives output weld pad 110,120,130,140,150,160,170 and 180 via buffer B1, B2, B3, B4, B5.
With output weld pad 110 and output weld pad 180 is example, and clock signal is cabling P1 from the connection cabling that signal source end R exports 110 processes of output weld pad to, cabling P2 and cabling P3, and clock signal to the connection delay of exporting weld pad 110 is T1.And clock signal is cabling P4 from the connection cabling that signal source end R exports 180 processes of output weld pad to, cabling P5 and cabling P6, and clock signal to the connection delay of exporting weld pad 180 is T2.Because chip internal still has the block of other circuit occupied; so the configuration regular meeting of buffer is restricted; therefore the path to the cabling of exporting weld pad 110 and 180 processes of output weld pad must be different from signal source end R for clock signal; that is to say; the length sum of cabling P1, cabling P2 and cabling P3 is not equal to the length sum of cabling P4, cabling P5 and cabling P6; so clock signal can be not identical by the connection delay of two paths, T1 ≠ T2.Also therefore, the signal source end clock signal that R exported can't arrive output weld pad 110 and output weld pad 180 simultaneously.In like manner, clock signal is also inequality to the time length of the connection delay of other output weld pad from signal source end R.So, from the example of Fig. 1 as can be known, only use electronic design automation tool to come the chip of combiner circuit can't reach the synchronization of clock signals demand.
In order to solve the above problems, the present practice is that whether test meets the synchronisation requirement of signal again after using electronic design automation tool to come combiner circuit earlier, if not, then adjust, afterwards, carry out the work of retest and adjustment again, till the synchronisation requirement that meets signal.As shown in Figure 1, under general situation, the engineer need adjust the position of a plurality of buffers, and meeting the synchronization of clock signals demand, and because the position of buffer on chip is two-dimentional, its position can change along the direction of x axle or y axle.Therefore consider the various positions that may put buffer, and the work of calculating each buffer and the length that is connected cabling of signal source end and output weld pad, be a complexity height and work consuming time.The mode of adding adjustment is to carry out in artificial mode, and therefore, the time that repeats to adjust and test will become very long.But because product life cycle of integrated circuit (IC) design industry is short, fluctuation of price is fast and competitive strong, and therefore, under the present practice, the time of carrying out research and development of products is long, and this not only can improve R﹠D costs and also can lower the ageing and competitive of product.
Summary of the invention
In view of this, task of the present invention is exactly that a kind of collocation method of buffer is being provided, make signal can arrive the output weld pad simultaneously with synchronisation requirement, and then avoid the work that unnecessary repeating adjusted and tested on the circuit design, to shorten the required time of integrated circuit (IC) design and to reduce R﹠D costs.
According to task of the present invention, a kind of collocation method of buffer is proposed, in order to a plurality of buffer configuration on a chip.This chip has signal source end and X output weld pad, and wherein, X is a positive integer.Collocation method of the present invention comprises: near (a) configuration one N layer buffer place in the middle of per two output weld pads, and each output weld pad is electrically connected with pairing N layer buffer; (b) near configuration one N+1 layer buffer place in the middle of per two N layer buffers, and each N layer buffer is electrically connected with pairing N+1 layer buffer, and judge whether the number of above-mentioned N+1 layer buffer is 1, if, then finish this method, if not, then enter step c; And (c) the N value is added 1, and repeating step (b), wherein, the X value is 2 positive integer power, this N layer buffer and this N+1 layer buffer are located on the same line.
According to another task of the present invention, a kind of collocation method of buffer is proposed, in order to a plurality of buffer configuration on a chip.This chip has signal source end, and X output weld pad, and wherein, X is a positive integer.Collocation method of the present invention comprises: (a) configuration Y dummy load (dummyload), and with each output weld pad and each dummy load respectively as a node; (b) near place in the middle of per two nodes, dispose a N layer buffer, and each node is electrically connected with pairing N layer buffer; (c) near the configuration one N+1 layer buffer center of per two N layer buffers, and each N layer buffer is electrically connected with pairing N+1 layer buffer, and judge whether the number of above-mentioned N+1 layer buffer is 1, if, then finish this method, if not, then enter steps d; And (d) the N value is added 1, and repeating step (c), wherein, X and Y sum are 2 positive integer power, this N layer buffer and this N+1 layer buffer are located on the same line.
The present invention also proposes a kind of chip, comprising:
X output weld pad and Y dummy load, each output weld pad and each dummy load are respectively as a node, and wherein, X and Y sum equal 2
M, M is a positive integer;
A plurality of buffers, comprise i layer buffer, i=1～M, i are positive integer, dispose the 1st a layer of buffer near the place in the middle of per two these nodes, each this node is electrically connected with pairing the 1st layer of buffer, dispose a j layer buffer near the place in the middle of per two j-1 layer buffers, each this j-1 layer buffer is electrically connected with pairing this j layer buffer, wherein, 1＜j＜M+1, j are positive integer; And
One signal source end, in order to export a signal, this signal is transferred into this X output weld pad via this buffer,
Wherein, these a plurality of buffers are located on the same line.
For above-mentioned task of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. elaborate.
Description of drawings
Fig. 1 shows the schematic diagram of a use circuit layout that electronic design automation tool synthesized.
Fig. 2 A to Fig. 2 C shows the schematic diagram according to a buffer configuration flow process of the present invention.
Fig. 3 shows the flow chart of the collocation method of buffer according to one preferred embodiment of the present invention.
Fig. 4 shows the flow chart of the collocation method of the buffer of the present invention when the number of exporting weld pad is not 2 positive integer power.
After Fig. 5 shows the flow process of execution graph 4, the schematic diagram of resulting chip.
Description of reference numerals
100,200,500: chip
110,120,130,140,150,160,170,180,210,220,230,240,250,260,270,280,510,520,530,540,550,560: the output weld pad
215,235,255,275,225,265,245,515,535,555,575,525,565,545: buffer
570,580: dummy load
Embodiment
Please refer to Fig. 2 A to Fig. 2 C, it shows the schematic diagram according to a buffer configuration flow process of the present invention.Shown in Fig. 2 A, chip 200 has output weld pad (pad) 210,220,230,240,250,260,270 and 280, and signal source end R.The spacing of adjacent output weld pad equates.At first, will export per two of weld pad and be divided into one group, the 1st layer of buffer of place's configuration in the middle of same group of output weld pad makes the track lengths of the 1st layer of buffer to two an output weld pad identical.Wherein, the place is meant same group of output weld pad along place, the below of the axial intermediate point of x in the middle of the same group of output weld pad, and intermediate point has the point of identical x coordinate figure therewith.In addition, the present invention requires to make the y axial coordinate of the 1st layer of all buffers all identical, so the position of each the 1st layer of buffer only may be gone up at single direction (along the direction of x axle) and be adjusted.
For instance, one the 1st layer of buffer 215 of place's configuration in the middle of output weld pad 210 and output weld pad 220, wherein, the 1st layer of buffer 215 is identical to the track lengths of output weld pad 220 with the 1st layer of buffer 215 to the track lengths of output weld pad 210, and it is L1.In like manner, the 1st layer of buffer 235 to the track lengths of exporting weld pad 230 and output weld pad 240 also is L1, the 1st layer of buffer 255 to the track lengths of exporting weld pad 250 and output weld pad 260 also is L1, and the 1st layer of buffer 275 to the track lengths of exporting weld pad 270 and output weld pad 280 also is all L1.
Please refer to Fig. 2 B, the 1st layer of buffer 215 and the 1st layer of buffer 235 are divided into one group, and the 1st layer of buffer 255 and the 1st layer of buffer 275 are divided into one group.The 2nd layer of buffer 225 of place's configuration in the middle of the 1st layer of buffer 215 and the 1st layer of buffer 235 make buffer 225 isometric to the track lengths of buffer 235 to the track lengths and the buffer 225 of buffer 215, and its length is L2.In like manner, buffer 265 be configured in buffer 255 and buffer 275 in the middle of the place, and buffer 265 also is L2 to the track lengths of buffer 255 and buffer 275.
Please refer to Fig. 2 C, one the 3rd layer of buffer 245 of place's configuration in the middle of the 2nd layer of buffer 225 and the 2nd layer of buffer 265.Track lengths between the 3rd layer of buffer 245 and the 2nd layer of buffer 225 is L3, and the track lengths between the 3rd layer of buffer 245 and the 2nd layer of buffer 265 also is L3.Signal source end R to the track lengths of buffer 245 be L4.
For instance, one by the signal source end clock signal that R exported, through buffer 245, buffer 225 and buffer 235, to the track lengths of exporting weld pad 230 be the L1+L2+L3+L4 sum.And,, also be the L1+L2+L3+L4 sum to the track lengths of exporting weld pad 280 through buffer 245, buffer 265 and buffer 275 by the signal source end clock signal that R sent.In like manner, all identical to exporting weld pad 210,220,230,240,250,260,270 respectively by signal source end R with 280 track lengths sum.This is because the design that all buffers and cabling have formed the binary tree of an one dimension, owing to walk line length homogeneous phase etc. for two that each buffer connected, so, clock signal by signal source end R export to different output weld pads the path length of every paths of process all equate, also therefore, the connection delay by every paths is also identical.And among comparison diagram 1 and Fig. 2 C buffer configuration mode as can be known, the arrangement that is arranged as one dimension of the buffer among Fig. 2 C, hence one can see that, method of the present invention changes complicated originally two-dimensional arrangements into the one dimension arrangement, because the moving range of buffer is only limited to one dimension, therefore, can lower the complexity and the operand of buffer configuration in a large number.
In order more clearly to describe the present invention, please refer to Fig. 3, it shows the flow chart of the collocation method of buffer according to one preferred embodiment of the present invention.In step 302, near configuration one N layer buffer place in the middle of per two output weld pads, and each output weld pad is electrically connected with pairing this N layer buffer.Preferably, N layer buffer is configured in the middle place of per two output weld pads.If need receive the number of the output weld pad of the signal source end signal that R exported simultaneously is X, then will export per two of weld pad and be divided into one group, N layer buffer of place's configuration in the middle of same group of output weld pad makes that the track lengths of N layer buffer to two an output weld pad is identical.Wherein, the number of N layer buffer is X/2.In step 304, be that per two N layer buffers are divided into one group, and in the middle of each organizes the position of N layer buffer, dispose a N+1 layer buffer near the place, and each N layer buffer is electrically connected with pairing N+1 layer buffer.Preferably, this N+1 layer buffer is configured in place in the middle of each position of organizing N layer buffer.In step 306, judge whether only to have the buffer of 1 N+1 layer, if not, then enter step 308, if then finish the method.And in step 308, the N value is added 1.After the execution of step 308, then repeated execution of steps 304.
Please be simultaneously with reference to Fig. 2 and Fig. 3.Be 1 to be that example is done explanation now with the initial value of N value.Shown in step 302, configuration one the 1st layer of buffer, just the 1st layer of buffer 215,235,255 and 275 between per two output weld pads.Then step 304 promptly is the 2nd layer of buffer 225 and 265 of configuration at one the 2nd layer of buffer of middle place's configuration of the position of per two the 1st layer of buffers.And because the number of this 2nd layer of buffer is not 1, therefore, with N directly add again 1 after, place's configuration one the 3rd layer of buffer, just the 3rd layer of buffer 245 in the middle of the 2nd layer of buffer 225 and 265.Because the number of the 3rd layer of buffer is 1, therefore, promptly finishes the method.
So, please also refer to Fig. 2 C, after the flow process of execution graph 3, available chip 200 comprises that (Fig. 2 C equals 2 with the X value to X output weld pad
M, M equals 3 and does explanation for example), a plurality of buffer and signal source end R.X output weld pad comprises output weld pad 210,220,230,240,250,260,270 and 280.A plurality of buffers comprise the 1st layer of buffer, the 2nd layer of buffer ... M layer buffer.Dispose the 1st a layer of buffer near the place in the middle of per two output weld pads, each output weld pad system is electrically connected with pairing the 1st layer of buffer.For example the 1st layer of buffer 215 is configured in the middle place that exports weld pad 210 and 212, and is electrically connected with 212 with output weld pad 210.In addition, set a parameter j, 1＜j＜M+1, j are positive integer.Dispose a j layer buffer near the place in the middle of per two j-1 layer buffers, each j-1 layer buffer is electrically connected with pairing j layer buffer.For example, the 2nd layer of buffer 225 is configured in the middle place of the 1st layer of buffer 215 and 235, and is electrically connected with 235 with the 1st layer of buffer 215.And the signal source end signal (not shown) that R exported is transferred into X output weld pad via these buffers.For example, the end signal that R exported in signal source can be transferred into output weld pad 210 via the 3rd layer of buffer 245, the 2nd layer of buffer 225 and the 1st layer of buffer 215.Wherein, each output weld pad is electrically connected with pairing the 1st layer of buffer via cabling, and each j-1 layer buffer also is electrically connected with pairing j layer buffer via cabling.And all buffers are located on the same line.
The number that above step only limits to when the output weld pad is X, and X is just implemented when being 2 positive integer power.And when the number X of exporting weld pad was not 2 positive integer power, the flow chart of the collocation method of buffer of the present invention promptly as shown in Figure 4.The different place of the flow chart of Fig. 4 and Fig. 3 only is step 401 and step 402.Because the number X of output weld pad is not 2 positive integer power, but, the collocation method of the buffer of the binary tree of this invention only limits to use when the output weld pad of the number of 2 positive integer power, therefore, need to increase step 401, additional configuration Y dummy load (dummyload), and X and Y sum are 2 positive integer power, and each dummy load simulates is the load (loading) of an output weld pad.In other words, the resistance value of each dummy load equivalence equates with the output weld pad.And in step 401, more each is exported weld pad and each dummy load respectively as a node.And in step 402, near place in the middle of per two nodes, dispose a N layer buffer, and each node is electrically connected with pairing N layer buffer.Preferably, this N layer buffer is configured in the middle place of per two nodes.The step 304,306 of following step 404,406,408 and Fig. 3,308 identical.In step 404, near configuration one N+1 layer buffer place in the middle of per two N layer buffers, and each N layer buffer is electrically connected with pairing N+1 layer buffer.In step 406, judge whether only to have the buffer of 1 N+1 layer, if not, then enter step 408, if then finish the method.And in step 408, the N value is added 1.
So, ask the while with reference to Fig. 5, after it shows the flow process of execution graph 4, the schematic diagram of resulting chip.Chip 500 comprises X output weld pad, a Y dummy load, a plurality of buffer and signal source end R.Fig. 5 equals 6 with the X value, and the Y value equals 2, and X and Y sum equal 2
M, M equals 3 and does explanation for example.Each output weld pad and each dummy load are respectively as a node.X output weld pad comprise output weld pad 510,520,530,540,550, with 560.Y dummy load then comprises dummy load 570 and 580.A plurality of buffers comprise the 1st layer of buffer, the 2nd layer of buffer ... M layer buffer.Dispose the 1st a layer of buffer near the place in the middle of per two nodes, each node is electrically connected with pairing the 1st layer of buffer.For example the 1st layer of buffer 515 is configured in the middle place that exports weld pad 510 and 520, and is electrically connected with 520 with output weld pad 510.The 1st layer of buffer 575 then is configured in the middle place of dummy load 570 and 580, and is electrically connected with 580 with dummy load 570.In addition, set a parameter j, 1＜j＜M+1, j are positive integer.Dispose a j layer buffer near the place in the middle of per two j-1 layer buffers, each j-1 layer buffer is electrically connected with pairing j layer buffer.For example, the 2nd layer of buffer 525 is configured in the middle place of the 1st layer of buffer 515 and 535, and is electrically connected with 535 with the 1st layer of buffer 515.And the signal source end signal (not shown) that R exported is transferred into X output weld pad via the 1st～M layer buffer.For example, the end signal that R exported in signal source can pass via the 3rd layer of buffer 545, the 2nd layer of buffer 565 and the 1st layer of buffer 555 and be sent to output weld pad 550.Wherein, each the 1st layer of buffer is electrically connected with two nodes via cabling.Each node system is electrically connected with pairing the 1st layer of buffer via cabling, and each j-1 layer buffer also is electrically connected with pairing j layer buffer via cabling.And all buffers are located on the same line.
The collocation method of the disclosed buffer of the above embodiment of the present invention, make signal can arrive the output weld pad simultaneously with synchronisation requirement, and then avoid the work that unnecessary repeating adjusted and tested on the circuit design, to shorten the required time of integrated circuit (IC) design, and then the reduction R﹠D costs, and improve the ageing and competitive of product.
In sum; though the present invention by a preferred embodiment openly as above; right its is not in order to limit the present invention; those skilled in the art; without departing from the spirit and scope of the present invention; should do various improvement and adjustment, so protection scope of the present invention should be as the criterion with the scope that claims were defined.
Claims (8)
1. the collocation method of a buffer, in order to a plurality of buffer configuration on a chip, and this chip has signal source end and X and exports weld pad, this method comprises:
A. should dispose a N layer buffer near the middle place of output weld pad at per two, and each this output weld pad is electrically connected with pairing this N layer buffer;
B. near place in the middle of per two these N layer buffers, dispose a N+1 layer buffer, and each this N layer buffer is electrically connected with pairing this N+1 layer buffer, and whether the number of judging above-mentioned N+1 layer buffer is 1, if, then finish this method, if not, then enter step c; And
C. the N value is added 1, and repeats this step b,
Wherein, the X value is 2 positive integer power, and this N layer buffer and this N+1 layer buffer are located on the same line.
2. the collocation method of a buffer, in order to a plurality of buffer configuration on a chip, and this chip has signal source end, and X exported weld pad, this method comprises:
A. dispose Y dummy load, and with each output weld pad and each dummy load each as a node;
B. near place in the middle of per two these nodes, dispose a N layer buffer, and each this node is electrically connected with pairing this N layer buffer;
C. near the center of per two these N layer buffers, dispose a N+1 layer buffer, and each this N layer buffer is electrically connected with pairing this N+1 layer buffer, and whether the number of judging above-mentioned N+1 layer buffer is 1, if, then finish this method, if not, then enter steps d; And
D. the N value is added 1, and repeats this step c,
Wherein, X and Y sum are 2 positive integer power, and this N layer buffer and this N+1 layer buffer are located on the same line.
3. chip comprises:
2
MIndividual output weld pad, M are positive integer;
A plurality of buffers, comprise i layer buffer, i=1～M, i are positive integer, dispose the 1st a layer of buffer near the place in the middle of per two these output weld pads, each should be electrically connected with pairing the 1st layer of buffer by the output weld pad, dispose a j layer buffer near the place in the middle of per two j-1 layer buffers, each this j-1 layer buffer is electrically connected with pairing this j layer buffer, wherein, 1＜j＜M+1, j are positive integer; And
One signal source end, in order to exporting a signal, this signal via this buffer be transferred into this 2
MIndividual output weld pad,
Wherein, these a plurality of buffers are located on the same line.
4. chip as claimed in claim 3, wherein, each should be electrically connected with pairing the 1st layer of buffer via a cabling by the output weld pad.
5. chip as claimed in claim 3, wherein, each this j-1 layer buffer is electrically connected with pairing this j layer buffer via a cabling.
6. chip comprises:
X output weld pad and Y dummy load, each output weld pad and each dummy load are respectively as a node, and wherein, X and Y sum equal 2
M, M is a positive integer;
A plurality of buffers, comprise i layer buffer, i=1～M, i are positive integer, dispose the 1st a layer of buffer near the place in the middle of per two these nodes, each this node is electrically connected with pairing the 1st layer of buffer, dispose a j layer buffer near the place in the middle of per two j-1 layer buffers, each this j-1 layer buffer is electrically connected with pairing this j layer buffer, wherein, 1＜j＜M+1, j are positive integer; And
One signal source end, in order to export a signal, this signal is transferred into this X output weld pad via this buffer,
Wherein, these a plurality of buffers are located on the same line.
7. chip as claimed in claim 6, wherein, each should be electrically connected with pairing the 1st layer of buffer via a cabling by the output weld pad.
8. chip as claimed in claim 6, wherein, each this j-1 layer buffer is electrically connected with pairing this j layer buffer via a cabling.
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| CN 03101822 CN1207775C (en) | 2003-01-20 | 2003-01-20 | Buffer configuration and chip |
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| CN 03101822 CN1207775C (en) | 2003-01-20 | 2003-01-20 | Buffer configuration and chip |
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