CN120582626A - System and method for super-resolution digital-to-analog converter based on redundant sensing - Google Patents

Abstract

The present disclosure provides a digital-to-analog converter apparatus. The digital-to-analog converter device includes a set of components, each component included in the set of components including a plurality of unit cells, each unit cell associated with a unit cell size representing a manufacturing specification of the unit cell, a plurality of switches, each switch included in the plurality of switches coupled to a component included in the set of components, and an output electrode coupled to the plurality of switches, the converter device configured to output an output signal on the output electrode. The first unit cell size associated with the first unit cell included in the component set is different from the second unit cell size associated with the second unit cell included in the component set.

Description

System and method for super resolution digital to analog converter based on redundant sensing

The application is a divisional application of an application patent application with the application date of 2019, 10-month 9, the application number of 201910955516.4 and the application of a system and a method of a super-resolution digital-to-analog converter based on redundant sensing.

Cross-reference to related applications

Is not applicable.

Technical Field

The field of the invention is electrical converters comprising a digital-to-analog converter (DAC) and an analog-to-digital converter (ADC). More particularly, the present invention relates to super resolution DACs using redundant sensing techniques.

Background

The quantization process, analog-to-digital conversion (ADC), and the inverse operation, dequantization, digital-to-analog conversion (DAC), are the basis for all modern sensing data acquisition systems. They allow "digital" human systems to perceive and interact with an "analog" physical world. Quantization is essentially a lossy data compression process in which information from a higher resolution space is represented in a corresponding object of lower resolution. In practical implementations, the accuracy of this process is always limited by system resource limitations (such as size, power, bandwidth, and memory). For example, in many ADC and DAC integrated circuit designs, an increase in resolution by a factor of 1 bit or 2 typically requires a 4-fold increase in chip area and power consumption. While ultra-high resolution ADC/DACs up to 32 bits are possible, their large size and power consumption limit the use of these devices in many practical applications. Similarly, higher resolution image sensors require more pixel counts and buffer memory, thus also resulting in greater device and power consumption. While pixel density can be increased, smaller pixel sizes are associated with noise that limits the increase in dynamic range of the sensor.

Super Resolution (SR) is a technique aimed at achieving effective resolution beyond the accuracy typically allowed by the system resource limitations. They find wide application in various fields of engineering and science involving imaging and instrumentation, where higher resolution data acquisition is always required. Previous SR techniques focus on restoring fine details of the object of interest by integrating information obtained from the coarse observations. These techniques can generally be divided into two main categories, modeling-based and oversampling-based, which are also referred to as single-frame and multi-frame in image processing.

Modeling-based (single frame) techniques focus on modeling input sources from available data points and reconstructing lost information by approximation. In these techniques, SR is achieved by relying on known statistical properties of the input signal, such as sparse properties used in compressed sensing, or properties extracted from a large amount of example data used in many machine learning based methods. On the other hand, over-sampling-based (multi-frame) techniques acquire and combine multiple samples of input obtained at various spatial or temporal instants to extract the next-to-smallest significant change information. In these techniques, SR is possible because low resolution data contains aliasing that embeds high resolution content that can be extracted in sufficient data volume by algorithms (e.g., noise reduction, deconvolution, etc.) or machine learning based methods. For compressed sensing or other data driven methods (including most existing machine learning based techniques), after the low resolution data is acquired, optimization or approximation is performed during reconstruction.

In addition, mismatch errors are one of the main obstacles impeding the implementation of high precision DAC/ADC in sub-micron CMOS processes. Mismatch errors are random deviations that occur during the fabrication of Integrated Circuits (ICs). Mismatch errors can cause random variations in the inherent characteristics of the IC components, including active electronic components (such as transistors) and/or passive electronic components (such as capacitors and/or resistors), which can lead to unpredictable behavior of the circuit and reduced overall system accuracy. For example, a DAC/ADC designed for a 10-bit resolution may actually have only an effective resolution of about 8-9 bits due to mismatch errors.

It is therefore desirable to provide a system and method for setting up a digital to analog converter that provides super resolution without post processing and with mismatch errors.

Disclosure of Invention

In one aspect, the present disclosure provides a digital-to-analog converter apparatus. The digital-to-analog converter device includes a set of components, each component included in the set of components including a number of unit cells, and at least one component including a number of unit cells that is not a power of 2, a plurality of switches, each switch included in the plurality of switches coupled to a component included in the set of components, an output electrode coupled to the plurality of switches, the converter device configured to output an output signal at the output electrode, and a controller coupled to the plurality of switches and configured to receive a desired output current, determine an anode component configuration including at least one component included in the set of components based on the desired output current, determine a cathode component configuration including at least one component included in the set of components based on the desired output current, and cause a current pulse to be output at an output electrode channel based on the anode component configuration and the cathode component configuration.

In a digital-to-analog converter device, the current pulses may include positive current pulses and negative current pulses.

In a digital-to-analog converter device, a controller includes a memory including a set of positive and negative current values associated with a set of component configurations, the anode component configuration and the cathode component configuration being included in the set of component configurations.

In the digital-to-analog converter device, the anode component configuration comprises at least one component not comprised in the cathode component configuration.

The effective resolution of the digital-to-analog converter device may be at least four times greater than the inherent resolution of the digital-to-analog converter device. The effective resolution of the device may be equal to the shannon entropy of the digital to analog converter device and the inherent resolution may be equal to the base 2 logarithm of the number of unit cells plus 1.

The digital-to-analog converter device may be included in a neurostimulator device.

In the digital-to-analog converter device, a first unit cell size associated with a first unit cell included in the component set may be different from a second unit cell size associated with a second unit cell included in the component set, the first unit cell size including a length and a width of the first unit cell.

In the digital-to-analog converter device, each unit cell may include at least one transistor.

In another aspect, the present disclosure provides a digital-to-analog converter apparatus. The digital-to-analog converter device includes a set of components, each component included in the set of components including a plurality of unit cells, each unit cell associated with a unit cell size representing a manufacturing specification of the unit cell, a plurality of switches, each switch included in the plurality of switches coupled to a component included in the set of components, and an output electrode coupled to the plurality of switches, the converter device configured to output an output signal on the output electrode. The first unit cell size associated with the first unit cell included in the component set is different from the second unit cell size associated with the second unit cell included in the component set.

In the digital-to-analog converter device, the unit cell size may include a length value and a width value.

In a digital-to-analog converter device, the unit cell size may be associated with a transistor process size.

In the digital-to-analog converter device, at least one component included in the component set includes a number of unit cells that is not a power of 2.

In another aspect, the present disclosure provides a method for determining manufacturing parameters of a digital-to-analog converter device comprising a set of components, each component included in the set of components comprising at least one unit cell, and each unit cell being associated with a unit cell size. The method includes determining a required mismatch error for unit cells included in the component set based on a target effective resolution value, determining an initial unit cell size based on the required mismatch error, setting a unit cell size of each unit cell included in the component set equal to the initial unit cell size, determining an effective resolution of the analog-to-digital converter device by performing simulation, determining that the effective resolution is below the target effective resolution, adjusting the unit cell size of one or more unit cells included in the component set in response to determining that the effective resolution is below the target effective resolution, and providing each unit cell size associated with each unit cell to a manufacturing facility.

In this method, the target effective resolution may be at least four times higher than the intrinsic resolution.

In the method, the unit cell size may include a length value and a width value, and each unit cell may include at least one transistor.

In the method, at least one component included in the set of components includes a number of unit cells that is not a power of 2.

In this method, the simulation may be a Monte Carlo simulation.

The foregoing and other aspects and advantages of the invention will appear from the following description. In this description, reference is made to the accompanying drawings which form a part hereof and which illustrate preferred embodiments of the present invention. Such embodiments, however, do not necessarily represent the full scope of the invention, and reference is therefore made to the claims and herein for interpreting the scope of the invention.

Drawings

Fig. 1 is an exemplary 3-bit Redundant Sense (RS) structure.

Fig. 2 is a graph of a comparison of reference distributions between a "half-split" (HS) grouping method and a "uniform" (UN) grouping method over a shared sample space.

Fig. 3A is a graph of the entropy average of an N ₀ = 10 bit device using the "half-split" (HS) grouping method versus the mismatch rate for each target resolution N _k＝N₀ + k with k ranging from [ 1..10 ].

Fig. 3B is a graph of the entropy average of an inherent resolution N ₀ = 10 bit device using the "uniform" (UN) grouping method versus the mismatch rate for each target resolution N _k＝N₀ + k with k ranging from [ 1..10 ].

Fig. 3C is a graph of the standard deviation of the entropy of an intrinsic resolution N ₀ = 10-bit device using the HS grouping method versus the mismatch rate of each target resolution N _k＝N₀ + k with k ranging from [1,..10 ].

Fig. 3D is a graph of the standard deviation of the entropy of an intrinsic resolution N ₀ = 10-bit device using the UN grouping method versus the mismatch rate of each target resolution N _k＝N₀ + k with k ranging from [1,..10 ].

Fig. 4A is a graph of Root Mean Square Error (RMSE) calculated over sample space for a target resolution N _k = 12 using the HS and UN grouping method.

Fig. 4B is a graph of RMSE calculated over sample space for a target resolution N _k = 18 using the HS and UN grouping method.

Fig. 5A is a graph of the entropy average of an N ₀ =10-bit device at δ=95% sample space using the (HS) grouping method versus the mismatch rate for each target resolution N _k＝N₀ +k for a k range of [1,..10 ].

Fig. 5B is a graph of the mismatch ratio of the entropy average of an N ₀ =10-bit device at δ=95% of the sampling space with respect to each target resolution N _k＝N₀ +k in the k range [1,..10 ] using the UN grouping method.

Fig. 5C is a graph of the standard deviation of the entropy of an N ₀ =10-bit device at δ=95% sample space using the HS grouping method versus the mismatch rate for each target resolution N _k＝N₀ +k with k ranging from [1,..10 ].

Fig. 5D is a graph of the standard deviation value of the entropy of an N ₀ =10-bit device at δ=95% sample space using the UN grouping method versus the mismatch rate of each target resolution N _k＝N₀ +k over k.

Fig. 6A is an exemplary current digital-to-analog converter (DAC) circuit.

Fig. 6B is a graph of effective resolution versus target resolution from simulation results.

Fig. 7A is an exemplary DAC channel.

Fig. 7B is an exemplary output current waveform.

Fig. 8A is an exemplary p-type operational amplifier.

Fig. 8B is an exemplary n-type operational amplifier.

Fig. 8C is an exemplary bias circuit.

Fig. 9 is an exemplary voltage-to-current converter circuit.

Fig. 10 is an exemplary voltage level translator circuit.

Fig. 11 is an exemplary process for calibrating DAC channels to achieve Super Resolution (SR).

Fig. 12 is an exemplary process for controlling the DAC channels to output a desired current.

Fig. 13 is an exemplary process for determining manufacturing parameters of a DAC with SR in the presence of mismatch errors.

Fig. 14 is an exemplary analog-to-digital converter.

Detailed Description

The present disclosure provides systems and methods for generating a digital-to-analog converter (DAC) that provides super resolution without post-processing and in the presence of mismatch errors.

In the present disclosure, a new method of Redundant Sensing (RS) based SR is presented that requires neither modeling nor oversampling of the input signal. RS theory is a design framework that exploits redundancy to improve the performance of an artificial system. It can be applied to biomedical devices such as neurostimulators. The RS structure is essentially a redundant system of information representations, where each result in the sample space can be generated by a variety of different system configurations. In practice, these configurations are always subject to random mismatch errors, which are generally considered to be "problems" that lead to conversion errors and reduce the overall accuracy of the system. However, the present disclosure shows that mismatch errors allow the actual values of the redundant configuration of the system to "spread" into the adjacent sample space, such that at a sufficient level, the RS structure has the ability to quantize the data at an effective resolution that exceeds conventional resource limitations.

The UN packet based SR technique detailed here is fundamentally different from some previous approaches, as it does not involve reconstructing lost information nor relies on any statistical properties of the incoming data. Because of its redundant architecture, the SR function is already embedded into the internal structure of the sensor once manufactured. In order to achieve SR data acquisition, the potential for such "hiding" must be revealed through optimization. The optimization process for each sensor needs to be performed only once and is independent of the input signal. Once optimized, the sensor can capture any type of signal at super-resolution, regardless of its statistical distribution. For compressed sensing or other data driven methods (including most existing machine learning based techniques), after the low resolution data is acquired, optimization or approximation is performed during the reconstruction process. In contrast, with the UN grouping method, optimization is performed on the sensor before any data is acquired, and the fine detailed information content of the input signal is not lost during quantization. This is not only due to the RS architecture itself, but also by smart control of mismatch errors-an undesirable accuracy limiting factor in conventional designs.

In the "super resolution" section below, a mechanism is proposed to facilitate new theory of SR in the RS architecture. The Monte Carlo (Monte Carlo) method is used to illustrate the advantages of UN technology. When the tradition proves to be too complex or not viable, the monte carlo analysis is an effective and widely used method, especially in this case, which can prove to be an optimization problem for NP-hard. The analysis is performed at both the level of abstraction assuming a simple probability distribution for the component and at the circuit level where all non-idealities due to process variations are considered. A component is a combination of one or more unit cells that behaves like a single entity. A component set (which may also be referred to as a component set) is a set of components that a sensor uses to generate its internal reference. For example, a binary weighted sensor has a component set {1,2,4,..2 ^N-1 }, consisting of 2 ^N -1 identical unit cells, where the unit cells have a weight of 1 (units). The unit cell may output an electrical signal (such as a voltage or a current). The results show that over a 10-bit quantizer of 95% sample space, additional 8-9 bit resolution or 256-512x precision can be achieved. In the "practical considerations and applications" section, potential applications and practical considerations of the proposed SR technology in fully integrated micro-biomedical devices are described, wherein the complexity of the structure can be reduced by approximation or can be conveniently circumvented. An example design is shown in which UN grouping techniques may be applied to increase the resolution of the current DAC in the neurostimulator, thereby giving more precise control over the output stimulation current.

Super resolution

Quantization and mismatch errors

Quantization is the process of mapping a continuous set (analog) to a finite set of discrete values (digital). Without loss of generality, it can be assumed that the N ₀ quantizer divides the consecutive interval [0, 1] intoPartitions, which are defined by a set of referencesDefinition in which each partition is mapped to a range from 0 toIs represented by the numerical code d:

where x _A is the analog input and x _D is the digital output. The effective resolution of the quantizer may be determined by shannon entropy Quantization was performed as follows:

Where M is the normalized total mean square error integrated over each digital code. As can be seen, for all values of the reference theta _d, Only whenThe references are equally spaced, i.e., This basic maximum of entropy is called the shannon limit, where the effective resolution of the device is theoretically limited only by its inherent quantization error.

In practice, the accuracy of the quantizer is also affected by randomly occurring mismatch errors, resulting in undesired deviations of the reference and degradation of entropy. For example, some integrated ADC or DAC chips generate their references by simply treating them as an array of identical basic components of a unit cell. N ₀ bit devices typically haveThe unit cell may be a micro capacitor, a resistor, or a transistor. Random mismatch of individual unit cells due to variations in manufacturing processes and other non-ideal factors is one of the major sources of mismatch errors that can significantly reduce the accuracy of the device.

In order to effectively control a unit cell, the cells are typically grouped into bundles that are simply considered as components. The grouping significantly reduces the number of control signals required. For example, using conventional binary weighting methods, the method will The unit cells are arranged to have a nominal weight ofIs a single piece, and is ₀ pieces. Such a system is orthogonal in that for N ₀ binary control signals, i.e. 0/1 bits, corresponds toEach of the digital codes in (a)The references may be uniquely created by selecting and combining components according to a binary digital system.

Redundant sensing

RS is a design framework aimed at engineering redundancy for improving the performance of the system in terms of accuracy and precision, rather than reliability and fault tolerance as in other designs. The actual RS implementation must meet two criteria, namely, expressed redundancy (RPR) and entangled redundancy (ETR).

RPR refers to a non-orthogonal information representation scheme in which each result in the sample space is encoded by a number of different system configurations. Each configuration responds differently to mismatch errors, so in any given case there is almost always one or more configurations with less error than the conventional representation.

TR refers to the implementation of an RS structure such that the statistical distribution of different system configurations is partially correlated (i.e., entangled) allowing for large redundancy without incurring excessive resource overhead. ETR should be distinguished from conventional copy-based approaches to achieve redundancy, where redundancy is linearly proportional to resource utilization.

Fig. 1 shows an example of a 3-bit RS structure having RPR and ETR characteristics, which can be implemented by using a non-orthogonal grouping method without duplication. While using the same number of physical resources (i.e., 7 unit cells), each digital code may be created from a plurality of different component combinations in the RS structure, each representing a different, partially correlated distribution with respect to random mismatch errors. Redundant systems of this information representation have been shown to suppress mismatch errors by allowing searching for optimal component assemblies with minimal error with respect to each digital code. Redundancy mechanisms can be well exploited to achieve an effective resolution beyond the conventional limit bounded by quantization errors, N ₀.

Code diffusion

The mismatch σ _m is defined as the standard deviation of each unit cell, assuming it has a gaussian distribution with a mean value of 1. In the absence of mismatch errors or σ _m =0, no matter how the unit cells are grouped and assembled,An array of identical units can only generate a limited number of references belonging to the following discrete value sets:

Is considered as an intrinsic reference set corresponding to the intrinsic resolution N ₀.

Since σ _m is assumed to be a non-zero value, as the actual values generated by the different component assemblies begin to "diffuse" into the adjacent sample space toThe probability density function segment centered on each element of (c) becomes wider. This characteristic is unique to the RS structure because (i) there are many different component assemblies that can generate references with the same nominal value, i.e., RPR, and (ii) the distribution of these assemblies is partially independent of random mismatch errors, i.e., ETR. The spreading of the probability density function then occurs in each mismatch error trial and not just the result of the monte carlo sampling.

Code spreading is a property of an RS structure in which the actual values of the internal references of the RS structure are spread into the adjacent sample space due to random mismatch errors. In non-SR quantizers, code spreading is undesirable because it can deviate the referenceResulting in degradation of shannon entropy as shown in equation (2). Some previous systems were designed to be closest by searchingTo reverse the diffusion process.

But from another perspective, code diffusion means that the same system can generate references within a region of sample space that belong to the inherent reference set of higher resolution N _k＝N₀ +k:

Wherein the method comprises the steps of With a sufficient level of mismatch, the probability density function of the reference can cover almost all sample space with a relatively uniform opportunity. Then, there is a suitable possibility that a group of very close proximity can be foundThese assemblies will allow sampling at an effective resolution N _k that exceeds the system native resolution N ₀. It is also interesting to note that mismatch errors are generally considered as undesirable non-ideal factors, being a key element in achieving SR. The maximum SR efficiency is only obtained when the mismatch reaches a certain level (e.g., -10%), which is considered to be excessive in many common applications.

Such a mechanism is only possible because, due to redundancy, the number of different references that can be generated by the RS structure is significantly larger thanAndThe cardinality of both. In an orthogonal structure such as binary, the number of different references is strictly for all kWhich is smaller thanFurthermore, not only the number of different component assemblies, but also the interrelationship between them plays an important role. Ideally, the assembly will be spread evenly across all sample spaces to maximize approximationThis feature is determined by the internal architecture of the device, i.e. how the components are designed.

Grouping mode

The grouping method is a method of arranging unit cells into components. Almost all conventional designs can be categorized as Binary Weighted (BW) structures, where quantized partitions are uniquely coded according to a binary digital system. In contrast, the proposed RS architecture employs different strategies to implement redundancy with RPR and ETR characteristics. There is no limitation on how the unit cells are grouped. Although the grouping method does not change the number of unit cells and thus has little impact on resource constraints, it determines the internal architecture of the system and greatly affects the number and distribution of references. The design of the grouping method distinguishes one redundancy structure from another.

It is assumed that a given grouping method willThe unit cells are assembled into n groups with nominal weights And the actual weight with respect to random mismatch error is c= { C ₁,c₂,...,c_n } is represented by a binary stringEach subset of codes, C, generates a normalized reference θ _d, as follows:

Let Φ be the set of all references that the system can generate. To achieve effective resolution, N _k is essentially a search in close proximity Is a subset of (a)Obviously, SR can be only performed as followsOr N > N _k.

The previously proposed RS architecture employs a class of grouping methods inspired by the binocular structure of the human visual system. They derive nominal weights according to the following formulaWherein the parameter (s, N _0′) satisfies 1≤N' ₀＜N₀,1≤s≤N₀-N′₀:

wherein i is E [0, N ₁-1],j∈[0,N₀ -1]. At the position of Wherein N' ₀＝N₀ -1 and s=1 is referred to as a "half-split" (HS) array having the following nominal weightsWherein:

In the RS structure, the HS design has the largest number of components, so the HS design has the greatest redundancy and contains reasonable component numbers Moreover, the simplicity of design allows it to be implemented in hardware with minimal complexity. The distribution of Φ _HS is shown in fig. 2, which will be described in more detail below. Although HS methods have high redundancy, their distribution is not necessarily optimal for achieving SR. These references are mostly concentrated in the middle region of the sample space, making both ends insufficiently covered and prone to error.

In this disclosure, enhanced grouping methods specifically designed to support SR are detailed. It has a more uniform reference distribution to maximize coverage of the sample space. The "uniform" (UN) method yields the following nominal weightsWherein:

Wherein the method comprises the steps of The intuition behind UN design is to divide the components of the binary weighted array into multiple sub-arrays of different resolutions (N ₁,N₂,) that are reduced by a logarithmic base by a logarithmic multiple of 2. This maximizes the distribution of the largest and smallest components over the digital code while keeping the total number of components at a reasonable value of 2N ₀ similar to the HS structure. All the remaining components form a basic array

As a comparison, in the case of N ₀ = 10, the BW, HS, and UN methods yield the following nominal part sets:

Fig. 2 is a graph of a comparison of reference distributions between HS and UN grouping methods over a shared sample space. More specifically, the distribution of the HS method 200 and the distribution of the UN method 204 are shown. The UN method produces a more uniform (e.g. "flat") distribution in different areas of the sample space (especially at both ends), which translates into better SR potential. A flatter distribution of the UN method will translate into a more uniform code spread over different areas of the sample space. The following sections will show that this feature helps to suppress errors near both ends of the sample space and generally creates greater SR potential.

Exceeding shannon limit

SR in the context of the present disclosure should be understood as a resource constraint problem. From the following componentsThe accuracy of a sensor consisting of unit cells was previously considered to be defined by the shannon limit of N ₀ determined by the quantization error. By arranging the unit cells in a specific way to achieve a redundant structure and employing statistical properties of random mismatch errors, an effective resolution beyond this conventional "limit" is achieved.

Shannon limit exists because the general expression of entropy as shown in equation (2) is for onlyPersonal valueIs a maximum number of different reference numbers that a conventional binary-weighted array can generate. This limitation does not apply to redundant architectures. The reference set (Φ) is a set of all internal reference values that can be generated by the system. The reference set for a system with k components would be 2 ^k elements. The HS or UN structure has a reference set Φ _HS/Φ_UN with andAs many different elements. Key to implementing SR is finding a subset from Φ _HS/Φ_UN So that at a resolution of N _k Very close to the intrinsic reference setThis can only be achieved when there is a random mismatch error that allows the elements of Φ _HS/Φ_UN to spread across the sample space. Thus, the concept of SR is not contradictory to the conventional shannon limit, but rather a new explanation of shannon theory beyond its usual understanding, which is only applied in practical redundancy architectures.

The shannon entropy in equation (2) can be conveniently modified to represent the effective resolution at the target resolution N _k by substituting N ₀←N_k, and extending the range to θ _d to includeIs used as a reference to the values of the other components. Fig. 3 shows the average and standard deviation (STD) of estimated entropy of an N ₀ = 10-bit device using monte carlo simulation (N = 1000) at each target resolution and mismatch rate. More specifically, fig. 3A is an average value of entropy of an N ₀ =10-bit device using the HS grouping methodA plot of the mismatch ratio σ _m relative to each target resolution N _k＝N₀ +k for the k range [ 1..10 ]. Fig. 3B is an average of entropy of an N ₀ = 10-bit device using the UN grouping methodA plot of the mismatch ratio σ _m relative to each target resolution N _k＝N₀ +k for the k range [ 1..10 ]. Fig. 3C is the standard deviation of the entropy of an N ₀ = 10-bit device using the HS grouping methodA plot of the mismatch ratio σ _m relative to each target resolution N _k＝N₀ +k for the k range. Fig. 3D is the standard deviation of the entropy of an N ₀ = 10-bit device using the UN grouping methodA plot of the mismatch ratio σ _m relative to each target resolution N _k＝N₀ +k for the k range. With sufficient mismatch, an increase in effective resolution of 3-4 bits or an increase in accuracy of 8-16 times is possible for both the HS and UN packet methods. Finding optimal collections using exhaustive search

As suggested by analysis of code diffusion, the best SR performance is obtained with a mismatch higher than 10%. Both the HS and UN grouping methods provide a 3-4 bit increase in effective resolution or an 8-16 fold increase in accuracy. Within a 10-50% mismatch, the STD of entropy is less than 0.2 bits, with the UN method having slightly better results. These notations suggest that the SR solution is consistent, which in practical applications will translate into good yields of the device with random errors.

Furthermore, the consistency of the mechanism means that mismatch errors may not need to be truly "random". In some applications, a 10% random bias may seem unrealistic. Alternatively, the bias may be intentionally added to the structure during the design process. Even though these artificial pseudo-random deviations may introduce some level of error, the consistency of the SR mechanism ensures that solutions can always be found.

Downscaling sampling

FIG. 4 shows the Root Mean Square Error (RMSE) at each digital code d in equation (2) prior to distribution or summation over the sample spaceIs a value of (2). More specifically, fig. 4A is a graph of Root Mean Square Error (RMSE) calculated over a sample space (N ₀＝10,σ_m =10%) for N _k =12 using the HS and UN grouping method. Fig. 4B is a graph of Root Mean Square Error (RMSE) calculated over a sample space (N ₀＝10,σ_m =10%) for N _k =18 using the HS and UN grouping method. Note that the x-axis shows only the first and last 5% of the sample space. At high resolution, errors mostly occur at both ends where the redundancy level is low. This may lead to significant degradation of overall entropy. The UN method is designed to have a flatter code distribution, which helps shape the error to the extreme.

The UN method is designed to have better code expansion than the HS design, and thus can help mitigate some errors by shaping the code to the extreme. However, due to the nature of the grouping, it is mathematically impossible to cover the entire sample space equally. The UN method is preferred over the HS architecture because it is specifically designed to minimize the error at both ends. An increase in 8-9 bit effective resolution or 256-512 times improvement in accuracy is possible with the UN architecture by sacrificing a 5% sample space-reasonable engineering tradeoff.

However, for a number of practical reasons, many applications may not actually utilize the entire sample space equally. Many sensors are calibrated so that the signal to be captured falls in the middle of the sample space. This is because most signals are unevenly distributed across the sample, and "centering" the data minimizes the likelihood that the signal will be out of the sampling range, resulting in distortion and loss of information. If both extremes are omitted, the proposed method allows to achieve a continuous sampling range centered in the middle of the sample space, where the overall effective resolution can be significantly enhanced.

Let δ ε [0,1] be the length of the continuous area centered in the middle of the sample space in which data is captured. This effectively reduces the full and dynamic range of the device, which results in a lower shannon limit:

now, the normalized total mean square error and entropy are integrated over only a small range of digital codes:

Fig. 5 shows the estimated entropy for the same system in fig. 3 but at delta=95% sample space. More specifically, fig. 5A is an average of entropy of an N ₀ =10-bit device at δ=95% sample space using HS grouping method A plot of the mismatch ratio σ _m for each target resolution N _k＝N₀ +k over k ranges [ 1. Fig. 5B is an average of entropy of an N ₀ = 10-bit device at delta = 95% sample space using UN grouping methodA plot of the mismatch ratio σ _m for each target resolution N _k＝N₀ +k over k ranges [ 1. Fig. 5C is the standard deviation of entropy of an N ₀ = 10-bit device at delta = 95% sample space using HS grouping methodA plot of the mismatch ratio σ _m for each target resolution N _k＝N₀ +k over k ranges [ 1. Fig. 5D is the standard deviation of entropy of an N ₀ = 10-bit device at delta = 95% sample space using UN grouping methodA plot of the mismatch ratio σ _m for each target resolution N _k＝N₀ +k over the k range.

Practical considerations and applications

In practice, the biggest challenge with the proposed SR and any RS architecture is to determine the correct configuration of the system among numerous redundancy possibilities. In the context of the present disclosure, implementing the SR under N _k requires solving the following optimization problems: Finding a subset of the component set c= { C ₁,c₂,...c_n } such that the subset generates a resulting error Minimized reference

This is essentially a version of the 0-1 backpack problem, which has been shown to be NP-hard. Because ofIt is as difficult to achieve SR at any target resolution N _k as in the non-SR case of N ₀, given that the actual weights of all components are known. However, this does not necessarily negate the utility of the proposed method. The actual solution to the problem that appears to be unsolvable may be specific to each application.

Implementing the proposed SR method (via the UN method) in an ADC design will enable a great improvement in the performance of various biomedical imaging and instrumentation systems, especially those benefiting from high precision and high dynamic range. For example, in a neuromodulation system, a high dynamic range implementation equivalent to a 14-18 bit ADC would be preferred for obtaining high quality neural data while minimizing circuit saturation due to the large amplitude difference between the peripheral nerve signal (tens of μv) and the stimulus artifact (hundreds of mV). In Magnetic Resonance Imaging (MRI) systems, ultra-high dynamic range ADCs of up to 20-24 bits have been shown to replace the default ADC (typically 16 bits) in commercial machines as part of the RF receiver to help improve the effective contrast and spatial resolution of the resulting image.

Furthermore, the proposed SR method can also be applied to enhance the performance of numerous biomedical devices employing DACs. For example, electrical nerve stimulators typically require a DAC to generate an internal reference current. A higher resolution DAC is always desirable because it allows for more precise control of the stimulation current over a wider range, which may mean better modulation of different neural circuits. In another example, many ultrasound imaging modalities employ DACs during their transmit phase to generate the necessary analog signals. High precision commercial DACs of up to 12 bits and beyond have been utilized in various systems to facilitate their operation. Implementing such high precision DACs (10-12 bits) on chip is often challenging and expensive because they occupy a large silicon area, especially in high voltage processes (> 30V). The proposed UN method can greatly benefit these designs by helping to achieve similar resolution at much lower cost.

Referring now to fig. 6A, an exemplary current DAC circuit 600 is shown. The current DAC circuit 600 may be included in a neurostimulator device. In some embodiments, the current DAC circuit may be coupled to a neurostimulator device. The current DAC circuit 600 may include unit cells grouped into components 604. Using the UN grouping described in equation (8) above, the current DAC circuit 600 may include any number of components and unit cells based on the inherent resolution of the device (e.g., N ₀). For example, current DAC circuit 600 may have an inherent resolution of N ₀ = 8, which results in fifteen components { i ₀,i₁,...,i_n } each having {1,1,1,1,2,2,2,4,4,8,8,15,30,59,117} unit cells. The first component 604A may comprise a unit cell and may comprise a transistor or transistor pair 608, each of which may be a MOS transistor. The second component 604B may include 117 transistors or transistor pairs, each of which may be a MOS transistor, which may be a component of the DAC circuit having the largest number of unit cells with eight bits of inherent resolution. Each component may be coupled to a switch such as a transistor for controlling the current output by each component. For example, the first component 604A may be coupled to a switch 612. Although transistor mismatch is mostly time-invariant, it is particularly complex because it depends not only on the physical size (W/L) of the device, but also on operating conditions such as bias voltage, load current, parasitics, etc. As a demonstration of the proof of concept, SRDAC was designed and built in a lattice Luo Fangde (GlobalFoundries) BCDLite 0.18.18 μm process using 30V transistors with minimum feature size (W/l=4.0/0.5 μm). By selecting an appropriate set of components, the proposed SR method can be seamlessly embedded into a standard cascode current DAC. Current DAC current 600 employs UN grouping method at an inherent resolution of N ₀ =8 bits, which yields a component set of {1,1,1,1,2,2,2,4,4,8,8,15,30,59,117} (Σ= 2^8-1=255). Monte carlo simulation (n=16) was performed at the schematic level using foundry provided transistor statistical models (both process and variants) without adding any pseudo random mismatch. The model takes into account most of the mismatch except the parasitic resistance of the metal connections in the layout. Fig. 6B shows a graph of effective resolution versus target resolution according to simulation results, where an average 12-bit effective resolution or a gain of 4-bit extra precision can be obtained at δ=95% by using only the natural mismatch of transistors. As a result, the performance of high precision devices can be greatly improved by utilizing the proposed SR mechanism by utilizing the natural mismatch of transistors.

Moreover, unlike the ADC example, the neurostimulator operation is always governed by an external controller during normal operation. The controller communicates with the neurostimulator regularly to update its parameters and trigger its function when needed. The optimal system settings at each DAC output can then be simply predetermined by foreground calibration and saved on an external memory (i.e., look-up table) that is accessed by the controller at any time. This effectively circumvents the problem of computational difficulties by transferring it to a memory which in some cases may be easier to handle. For example, assuming that a 16-bit target SR is to be achieved with 20 components, storing all optimal configurations per DAC would require 2 ¹⁶×20＝1.3·10⁶ bits or 163KB of memory—which is trivial for off-chip flash.

Referring now to fig. 7A and 6A, DAC channel 700 is shown. DAC channel 700 may include a current DAC circuit 704, and current DAC circuit 704 may include at least a portion of the electrical elements of current DAC circuit 600. The current DAC circuit 704 may include a set of components 706 that includes one or more components, including a first portion 708A, a second component 708B, and a third component 708C. Each of these components may include one or more unit cells. The number of unit cells may be determined using the UN grouping method described in equation (8). For example, current DAC circuit 704 may have an inherent resolution of N ₀ = 8, which results in fifteen components { i ₀,i₁,...,i_n } each having {1,1,1,1,2,2,2,4,4,8,8,15,30,59,117} unit cells. Each unit cell may include a transistor or a transistor pair. For example, first component 708A may include a transistor pair 712. Each component may be coupled to a switch such as a transistor for controlling the current output by each component. For example, first component 708A can be coupled to transistor 716. Each switch may receive a corresponding digital control signal (D ₀,...,D_n) at one of the set of digital control signal networks. For example, transistor 716 may be coupled to a first digital control network included in digital control bus 720. When the digital control signal is activated (i.e., high for an NPN transistor), the corresponding component may provide an output current included in the output current I _DAC generated by the current DAC circuit 704. An external controller (not shown) may be coupled to the current DAC circuit 704 at the digital control bus 720 to control the output of the current DAC circuit 704 and/or the DAC channel 700. The controller may be programmed with a predetermined configuration of components to output a given digital value as an analog signal, as will be described in detail below. Each component configuration may be a grouping of several activated components, for example, components coupled to a switch having an "activated" digital control signal. In some embodiments, a first controller programmed with a predetermined component configuration may be coupled to a second controller configured to generate a digital control signal (D ₀,...,D_n) and an anode output switching signal SW _A and a cathode output switching signal SW _C. The first controller may provide the component configuration to the second controller. The second controller may be used as a timing controller by activating the appropriate digital control signals for a given component configuration and modulating the final output current by activating the anode output switching signal SW _A and the cathode output switching signal SW _C, as will be described below. The current DAC circuit 704 may receive an internal reference current I _ref at an internal reference current network 728.

DAC channel 700 may include a current mirror circuit 732. The current mirror circuit 732 may receive the output current I _DAC from the current DAC circuit 704. The current mirror circuit 732 generates a replica output current I _DAC' of the output current I _DAC and generates positive and negative bias voltages for the output current driver circuit 760, which will be described below. The current mirror circuit 732 may receive a fixed positive bias voltage V _DP, a fixed negative bias voltage V _DN to bias the first n-type operational amplifier 736, the second n-type operational amplifier 740, and the first p-type operational amplifier 744. The fixed positive bias voltage V _DP may be equal to V _DD -0.5 and the fixed negative bias voltage V _DN may be equal to V _SS +0.5. The current mirror circuit 732 may be constructed with a boost cascode architecture to achieve high precision operation.

The current mirror circuit 732 may be coupled to the output current driver circuit 760 to provide a replica output current I _DAC and an output current I _DAC to the output current driver circuit 760. The output current driver circuit 760 multiplies the output current I _DAC by a fixed ratio and drives the electrode output 764 in either the positive (anode) or negative (cathode) direction to generate the final stimulation pulse. Similar to the current mirror circuit 732, the output current driver circuit 760 also utilizes a boost cascode architecture for high precision and ultra high output impedance. The anode output switching signal SW _A and the cathode output switching signal SW _C may be received from a controller, such as a controller coupled to the current DAC circuit 704, which may include a timing controller to activate the anode signal transistor 765 or the cathode signal transistor 767 and thereby control the polarity and pulse width of the final stimulus. The electrode output 764 may be directly connected to a stimulation electrode included in the neurostimulator. The output current driver circuit 760 may include a third n-type operational amplifier 768 and a second p-type operational amplifier 772.

The DAC converter device may comprise several DAC channels. In some embodiments, the DAC device may include sixteen channels. One or more controllers may be coupled to channels included in the DAC device to control the channels as described above.

Referring now to fig. 7B and 7A, an exemplary output current waveform 780 is shown. An output current pulse may be generated by DAC channel 700 and output at electrode output 764. Exemplary output current waveform 780 may include an anodic or positive current pulse 784, a brief delay period 788, and a cathodic or negative current pulse 792.

Referring now to fig. 8A and 7A, a p-type operational amplifier 800 is shown. The p-type operational amplifier 800 may be a first p-type operational amplifier 744 or a second p-type operational amplifier 772. The p-type operational amplifier 800 may receive a positive bias voltage V _biasP from a bias circuit, which will be described below. The p-type operational amplifier 800 may be designed to operate with an input close to the positive supply voltage V _DD.

Referring now to fig. 8B and 7A, an n-type operational amplifier 804 is shown. The n-type operational amplifier 804 may be a first n-type operational amplifier 736, a second n-type operational amplifier 740, or a third n-type operational amplifier 768. The n-type operational amplifier 804 may receive a negative bias voltage V _biasN from a bias circuit, which will be described below. The p-type operational amplifier 800 may be designed to operate with an input near the negative supply voltage V _SS.

Referring now to fig. 8C, and fig. 7A, 8A, and 8B, a bias circuit 808 is shown. The bias circuit 808 may receive the internal reference current I _OTA and generate and output a positive bias voltage V _biasP and a negative bias voltage V _biasN.

Referring now to fig. 9 and fig. 7A and 8C, a voltage-to-current converter circuit 900 is shown. The internal reference current I _ref may be generated for the current DAC circuit 704 using the voltage-to-current converter circuit 900. The voltage-to-current converter circuit 900 may also be used to generate an internal reference current I _OTA for the bias circuit 808. The voltage-to-current converter circuit 900 may use a boost cascode architecture to generate the primary reference current I _ref0. The value of the primary reference current I _ref0 can be determined by the external bias resistance as follows: Where V _CM is the common voltage. The operational amplifier 904 included in the voltage-to-current converter circuit 900 can be designed to operate at a VCM of about (V _DD+V_SS)/2. The operational amplifier may be biased by a self-biasing circuit independent of the power supply and may not require any other reference. The reference currents (I _ref0) are further divided by a factor of 10 and then copied to create I _ref1、I_ref2、…I_refn, each of which flows to the stimulation channel.

Referring now to fig. 10, a voltage level shifter circuit 1000 is shown. The analog front-end circuit requires high voltage power (+ -10V) to adequately drive the output electrodes, while the digital controller is designed with low voltage power (1.8V) to reduce chip area and power consumption. As a result, the voltage level shifter is required to convert the low voltage control signal into a high voltage corresponding signal. The voltage level shifter circuit 1000 may include a low voltage portion 1004 and a high voltage portion 1008. The low voltage portion 1004 may include 5V rated transistors, e.g., transistors 1012 and 1016, configured to boost the input signal from [0,1.8V ] to [ -2.5V, +2.5V ]. The high voltage portion 1012 may include 30V rated transistors, such as transistors 1020 and 1024, configured to boost the signal further from [ -2.5V, +2.5V ] to the desired [ -10V, +10V ] level.

Referring to fig. 11 and 7A, an exemplary process 1100 for calibrating DAC channels to obtain Super Resolution (SR) is shown. The DAC channels may be the DAC channels 700 described above. The process may be implemented as instructions on one or more memories included in one or more controllers coupled to the DAC channels. In general, process 1100 may receive output current measurements configured for each component of a DAC channel. These measurements can then be used to select a component configuration that outputs a current closest to the input digital value. Selecting a particular component configuration may allow the output current to have an improved effective resolution and have a reduced number of unit cells compared to prior art techniques such as binary weighted groupings of components that may require additional unit cells to achieve a given effective resolution. The instructions may be executable by at least one processor included in at least one controller.

At 1104, process 1100 may set a component configuration of the DAC channel. Process 1100 may select component configurations that do not have associated measured anode output currents and measured cathode output currents and traverse each component configuration until each component configuration has associated measured anode and cathode output currents. For example, the controller may provide appropriate digital control signals to output current or voltage from one or more components. For example, a first control switch coupled to a first component and a second control switch coupled to a second component may be turned on, and all control switches coupled to the other components may be turned off. Process 1100 may then proceed to 1108.

At 1108, process 1100 may activate an anode output switching signal (e.g., SW _A) to activate an anode signal transistor (e.g., anode signal transistor 765) included in the DAC channel. The DAC channel may then provide a positive current at the output electrode of the DAC channel. The process may then proceed to 1112.

At 1112, process 1100 may receive an anode output current value. The anode output current value may be received from a human operable bench-top measuring instrument. The anode output current value may correspond to an output amperage that occurs when the selected component configuration is selected. Process 1100 may then proceed to 1116.

At 1116, process 1100 may save the anode output current value in memory. The memory may be included in a controller coupled to the DAC channels and configured to control the DAC channels as described above. As described below, the controller may use this configuration in controlling the DAC channels to output the desired current. Process 1100 may then proceed to 1120.

At 1120, the process 1100 may deactivate the anode output switching signal. Process 1100 may then proceed to 1124.

At 1124, process 1100 may activate a cathode output switching signal (e.g., SW _C) to activate a cathode signal transistor (e.g., cathode signal transistor 767) included in the DAC channel. The DAC channel may then provide a negative current on the output electrode of the DAC channel. The process may then proceed to 1128.

At 1128, process 1100 may receive a cathode output current value. The cathode output current may be received from a human operable bench-top measuring instrument. The cathode output current value may correspond to an output amperage that occurs when the selected component configuration is selected. Process 1100 may then proceed to 1132.

At 1132, the process 1100 may save the cathode output current value in memory. The memory may be included in a controller coupled to the DAC channels and configured to control the DAC channels as described above. As described below, the controller may use this configuration in controlling the DAC channels to output the desired current. Process 1100 may then proceed to 1136.

At 1136, the process 1100 may deactivate the cathode output switching signal. Process 1100 may then proceed to 1140.

At 1140, process 1100 may determine whether one or more component configurations are required to have corresponding anode output currents and cathode output currents measured. Process 1100 may then proceed to 1144.

At 1144, if process 1100 determines that one or more component configurations still require measurement of output current (e.g., yes at 1144), process 1100 may proceed to 1104. If process 1100 determines that one or more component configurations still require measurement of output current (e.g., NO at 1144), process 1100 may end.

Referring now to fig. 12 and to fig. 7A and 11, an exemplary process 1200 for controlling a DAC channel to output a desired current is shown. The DAC channels may be the DAC channels 700 described above. The process may be implemented as instructions on one or more memories included in one or more controllers coupled to the DAC channels. The instructions may be executable by at least one processor included in at least one controller. For example, a portion of process 1200 may be performed on a first controller that includes predetermined anode output currents and cathode output currents associated with a set of component configurations (i.e., output currents measured using process 1100 described above), and another portion of process 1200 may be performed on a second controller (such as a timing controller) that is configured to generate digital control signals (D ₀,...,D_n) for a given component configuration and to generate anode output switch signals SW _A and cathode output switch signals SW _C, as described above. The DAC channels may be included in a medical device such as a neurostimulator.

At 1204, process 1200 may receive a desired output current. The desired current may be received from an external process that implements the DAC channel as part of a medical device, such as a neurostimulator. The desired output current may correspond to a desired stimulation current. Process 1200 may then proceed to 1208.

At 1208, process 1200 may determine an anode component configuration for the desired output current based on the desired output current and a predetermined measure of output current for the set of component configurations. As described above, each component configuration may have an associated anode output current previously measured using, for example, a bench-top measuring instrument. Process 1200 may determine from among the possible component configurations of all DAC channels which component configuration has the associated anode output current closest to the value of the desired output current. For example, for a desired output current of 1.305mA, process 1200 may determine an anode output current of 1.304mA associated with the target component configuration that is closest to the desired output current as compared to all other anode output currents, and select the target component configuration as the anode component configuration. Process 1200 may then proceed to 1212.

At 1212, process 1200 may determine a cathode component configuration for the desired output current based on the desired output current and a predetermined measure of output current for the set of component configurations. As described above, each component configuration may have an associated cathode output current previously measured using, for example, a bench-top measuring instrument. Process 1200 may determine from among the possible component configurations of all DAC channels which component configuration has the associated cathode output current magnitude closest to the value of the desired output current. For example, for a desired output current of 1.305mA, process 1200 may determine a cathode output current of 1.304mA associated with the target component configuration that is closest to the desired output current as compared to all other cathode output currents, and select the target component configuration as the cathode component configuration. Process 1200 may then proceed to 1216.

At 1216, process 1200 may cause current pulses to be output from the DAC channels based on the anode component configuration and/or the cathode component configuration. In some embodiments, process 1200 may activate an appropriate digital control signal (D ₀,...,D_n) for anode component configuration. For example, if the anode component configuration includes a first component and a third component, digital control signals D ₀ and D ₂ may be activated. Process 1200 may then activate anode output switching signal SW _A, causing an anode output current to be output at the output electrode of the DAC channel. The process 1200 may continue to provide the anodic output current for a predetermined pulse width period that may be predetermined or adjusted by an external process to tailor the process 1200 to a particular application (i.e., neural stimulation). Process 1200 may then deactivate digital control signal (D ₀,...,D_n) and anode output switch signal SW _A. After a short delay, such as 1-2 mus, which depends on the structure of the DAC channels (ideally as close to zero as possible), process 1200 may activate the appropriate digital control signal (D ₀,...,D_n) for cathode component configuration. Process 1200 may then activate cathode output switching signal SW _C, causing a cathode output current to be output at the output electrode of the DAC channel. Process 1200 may continue to provide the cathode output current for a predetermined pulse width period. Process 1200 may then deactivate digital control signal (D ₀,...,D_n) and cathode output switch signal SW _C. Process 1200 may then proceed to 1204. In some embodiments, process 1200 may only cause positive or negative current to be output from the DAC channel. In some embodiments, process 1200 may end.

Referring now to fig. 13 as well as fig. 7A, an exemplary process 1300 is provided for determining manufacturing parameters of a DAC with SR in the presence of mismatch errors. In general, process 1300 may be used to increase the actual resolution of a DAC as compared to a typical DAC having the same number of components and having another grouping (such as a binary technique).

At 1304, the process 1300 may determine at least one of the intrinsic resolution N ₀ or the number of unit cells. For example, process 1300 may receive an inherent resolution N ₀ of eight specified by a person, such as an engineer. As another example, process 1300 may receive a number of unit cells, such as 255. The number of parts may be equal toWhere N ₀ is the intrinsic resolution. The process can be performed by setting the intrinsic resolutionThereby normalizing the number of unit cells to the inherent resolution. Process 1300 may then proceed to 1308.

At 1308, process 1300 may determine the inherent resolution N ₀ and/or the number of unit cells to determine the set of components. The set of components may comprise a plurality of components, each component comprising at least one unit cell as described above. Each unit cell may include one transistor or a pair of transistors. In each component, the unit cell(s) may be coupled to a single switch (such as a transistor) to control the current output by the transistor as described above. Process 1300 may determine unit cell to part groupings using the UN grouping method. The unit cells may be grouped according to equation (8) above. Process 1300 may group unit cells into a base arrayAnd a plurality of subarrays. Each of the subarrays may have a different resolution that decreases in a logarithmic scale across the number of subarrays. Each component included in the sub-array has a number of unit cells equal to a power of 2 (e.g., 2j, where j is zero or a positive integer). Base arrayCan be determined using the bottom part of equation (8). Generally, for inclusion in a matrix arrayIf the process 1300 determines that the unit cells are to be included in the corresponding component, then the process 1300 may determine the unit cells for each component, i.e., for all of i e 0, n ₀ -1. For a lower component l of relatively low value (e.g., l < N ₀-N₁), process 1300 may set the number of unit cells equal to 2 ^l. For a relatively high value component 1, process 1300 may be performed by subtracting from 2 ^l for allA kind of electronic deviceAnd to determine the number of unit cells. Thus, the array isOne or more components may be included that include a number of unit cells that are not equal to a power of 2. As will be explained below, each unit cell may be associated with a unit cell size. Process 1300 may then proceed to 1312.

At 1312, process 1300 may determine a target effective resolution value. The target effective resolution value may be used to determine a mismatch error value as will be explained below. The target effective resolution may be specified by an engineer. The target effective resolution value may be greater than the native resolution. For example, if the inherent resolution is 10 (e.g., 10 bits), the value of the target effective resolution may be 14, 18, or more. The target effective resolution value may represent a higher improvement in accuracy of 256-512 times greater than the intrinsic value over 95% of the sampling space of the DAC. Process 1300 may then proceed to 1316.

At 1316, method 1300 may determine a desired mismatch error value for the unit cell based on the target effective resolution value. The required mismatch error value may be a minimum mismatch error ratio (e.g., 10%) required per unit cell in order to achieve an effective resolution of at least the target effective resolution. Process 1300 may estimate the entropy and the number of various mismatch ratios using monte carlo simulations at the target resolution, as described above. Process 1300 may then use an exhaustive search technique to find the optimal setThe optimal setMay be associated with mismatch errors. Process 1300 may determine an optimal setIs the set that achieves the target effective resolution at the lowest mismatch ratio. Process 1300 may then set the desired mismatch error value equal to the optimal setAn associated mismatch error. The process may then proceed to 1320.

At 1320, process 1300 may determine an initial unit cell size based on the desired mismatch error value. Each unit cell included in the component set may be initially set in size to an initial unit cell size. The process 1300 may set the relevant unit cell size associated with each unit cell included in the component set equal to the initial unit cell size. The unit cell size and the initial unit cell size may each include a length value and a width value. For example, if the DAC has an inherent resolution of ten (e.g., N ₀ = 10), the size of all one thousand twenty-four unit cells included in the component set can be set to match the initial unit cell size. The format of the unit cell size may vary depending on the type of the unit cell. For example, the size of a transistor may be determined by dividing the width by the length, which may be referred to as W/L. As another example, the size of the capacitor may be determined by the width multiplied by the length, which may be referred to as w×l. Manufacturers, such as foundry, may provide measurements that may be used to determine the initial unit cell size. For example, the measurement may include an estimated mismatch error ratio of saturated drain currents at different transistor sizes (e.g., length and width). For some unit cell types, smaller unit cell sizes may have a higher mismatch error ratio. Process 1300 may determine a unit cell size having an estimated mismatch error ratio of saturated drain current that is above or closest to the desired mismatch error value. The foundry may not be able to produce unit cells with the desired mismatch error value (e.g., to make unit cells small enough), the process 1300 may determine that the initial unit cell size is the smallest unit cell size that the foundry can make. The unit cell size may indicate that the unit cell is expected to be a nominal size or an expected size. The manufacturing process may introduce defects that cause the size of each unit cell to be different even between unit cells having the same unit cell size. It should be understood that the unit cell size represents the expected size of a unit cell such as a transistor, and that the actual size of unit cells having the same unit cell size may be slightly different due to the differences introduced by the manufacturing process. The unit cell size may be associated with a particular process dimension (such as 10nm, 14nm, etc.) of the unit cell type (e.g., transistor process dimension). While the effect of mismatch errors on transistors may involve factors other than mismatch in saturated drain current, foundry-provided measurements may provide a starting point for determining the overall mismatch error of a unit cell (e.g., transistor). In a unit cell including a pair of transistors, the size of each transistor may be determined according to the size of the unit cell. Process 1300 may then proceed to 1324.

At 1324, process 1300 may determine an effective resolution of the DAC by performing a monte carlo simulation. Monte Carlo simulation may be performed using a statistical model provided by the foundry based on the current unit cell size associated with each unit cell. In embodiments where the unit cell includes a transistor, monte Carlo simulation may be performed at the schematic level using a foundry-provided transistor statistical model (both process and variation). The statistical model may take into account most mismatch errors except for parasitic resistances of metal connections in the schematic layout. Process 1300 may then proceed to 1328.

At 1328, process 1300 may determine whether the effective resolution determined at 1324 is below the target effective resolution. Process 1300 may then proceed to 1332.

At 1332, if the process 1300 determines that the effective resolution is below the target effective resolution (e.g., yes at 1332), the process 1300 may proceed to 1336. If process 1300 determines that the effective resolution is not less than the target effective resolution (e.g., "no" at 1332), process 1300 may proceed to 1340.

At 1336, the process may adjust a unit cell size of one or more unit cells included in the component set. For example, process 1300 may increase the length of transistors included in a component set. In some embodiments, process 1300 may adjust the width of a plurality of transistors included in a component set. The process 1300 may adjust the unit cell size of one or more unit cells by randomly selecting one or more unit cells and adjusting the length and/or width of the selected unit cells by a random or predetermined amount. The process dimensions (e.g., 10nm, 14nm, etc.) may be fixed for each unit cell. In some embodiments, the adjustment amount for each unit cell may be determined by using a Random Number Generator (RNG). For example, a DAC may include an array of 10 unit transistors having a unit cell size of W/l=100/10 nm, which is the smallest dimension for the process dimensions associated with the unit cell. It may be desirable to include additional mismatch to achieve a mismatch ratio of about 10%. RNG with a normal distribution can be used, with an average of 100 and a standard deviation of 10 (10% of the average). The width of each of the 10 unit transistors may be adjusted according to the RNG generated value. For example, one unit transistor may be tuned to 101/10nm, another unit transistor may be tuned to 105/10nm, and another unit transistor may be tuned to 103/10nm by process 1300. The width value may not be adjusted to be less than 100nm because 100nm is already the smallest dimension of the transistor in the process. Adjusting the size of one or more unit cells may increase the mismatch of the DAC. In addition, adjusting the size of one or more randomly selected unit cells can artificially increase the mismatch error of the DAC, which can result in an increase in the effective resolution of the DAC. The process may then proceed to 1324.

At 1340, process 1300 may determine manufacturing parameters for manufacturing a DAC with SR based on the set of components and the unit cell size of each unit cell included in the set of components. Process 1300 may determine a circuit layout that includes a set of manufacturing parameters such as electrical component values and/or models (resistor values, specific models of capacitors, electrical trace materials, etc.) and electrical connections between components. The circuit layout may include a component group and unit cells sized according to unit cell sizes associated with the component group. The circuit layout may then be used to fabricate a DAC with SR. The process may then proceed to 1344.

At 1344, the process 1300 may provide the manufacturing parameters to the manufacturing facility. For example, the process 1344 may provide the circuit layout to a foundry. The foundry may then manufacture a DAC having an SR according to the component set and the unit cell size of each unit cell included in the component set. The foundry may manufacture the DAC with SR to include the grouping indicated by the set of components and the unit cells sized according to the unit cell size associated with the set of components. Process 1300 may then end.

In some embodiments, any suitable computer readable medium may be used to store instructions for performing the functions and/or processes described herein. For example, in some embodiments, the computer readable medium may be transitory or non-transitory. For example, non-transitory computer-readable media may include media such as magnetic media (such as hard disks, floppy disks, etc.), optical media (such as compact disks, digital video disks, blu-ray disks, etc.), semiconductor media (such as RAM, flash memory, electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), etc.), any suitable media that is not transitory or permanent during transmission, and/or any suitable tangible media. As another example, a transitory computer-readable medium may include a signal on a network, a wire, a conductor, an optical fiber, a circuit, or any suitable medium and/or any suitable intangible medium that is transitory and does not have any permanence during transmission.

It should be noted that as used herein, the term "mechanism" may encompass hardware, software, firmware, or any suitable combination thereof.

It should be understood that the steps of the processes of fig. 11, 12 and/or 13 described above may be performed or carried out in other sequences or orders not limited to the sequences and orders shown and described in the figures. Also, some of the above-described steps of the processes of fig. 11, 12, and/or 13 may be performed substantially simultaneously or performed to reduce latency and processing time.

Referring now to fig. 14, an exemplary analog-to-digital converter 1400 is shown. Analog-to-digital converter 1400 may receive analog electrical signals and output fourteen-bit digital electrical signals. Analog to digital converter 1400 may include components that are grouped using UN grouping techniques. More specifically, analog-to-digital converter 1400 may include a set of components 1404 that include a plurality of capacitors. Each component included in the set of components from C ₀ to C _n may include one or more capacitors selected according to equation (8) above based on the inherent resolution of the analog-to-digital converter 1400 and/or the number of capacitors included in the analog of the digital converter 1400. The effective resolution of the device may be four to six bits higher than the inherent resolution of the device. Each component may be coupled to a switch included in the switch set 1408. For example, the first component 1404A can be coupled to a first switch 1408A. Analog-to-digital converter 1400 may also include digital circuitry 1412, where digital circuitry 1412 is configured to selectively activate switch set 1408 to determine a digital value. The digital circuit 1412 may include a controller. The digital circuit 1416 may be coupled to a memory 1416 having stored thereon a set of component configurations, each component configuration being associated with a particular digital value. A digital signal indicative of the digital value may be output at digital output network 1420. Analog-to-digital converter 1400 may include various subcircuits (not shown), clock subcircuits, level shifter subcircuits, and the like, as is known in the art.

The present disclosure proposes a new solution to the RS architecture that allows the quantization or dequantization process to obtain an effective resolution that exceeds the limits that its resource constraints typically allow. Using monte carlo simulations, it can be shown that SR is possible by smartly exploiting the statistical properties called "code diffusion" (properties unique to redundant structures in the presence of random mismatch errors). By applying the UN method on a 10-bit device, a tremendous theoretical increase in effective resolution of 8-9 bits, or a 256-512-fold improvement in accuracy, is demonstrated over 95% of the sample space. The UN grouping method is applicable to various fields of biomedical imaging and data acquisition instruments, especially low power fully integrated sensors and devices that always require higher resolution, as well as other applications of audio and video processing, including wired/wireless data transmission and/or data storage, remote sensing technologies such as radar, sonar, ultrasound and/or infrared sensing, sensors and actuators used in robotics, etc.

Accordingly, the present disclosure provides systems and methods for generating a digital-to-analog converter that provides super resolution without post-processing and in the presence of mismatch errors.

The present invention has been described in terms of one or more preferred embodiments, and it is to be understood that many equivalents, alternatives, modifications, and variations, aside from those expressly stated, are possible and within the scope of the invention.

Claims (7)

1. A digital-to-analog converter apparatus comprising:

A component set, each component included in the component set including a plurality of unit cells, each unit cell being associated with a unit cell size indicating a manufacturing specification of the unit cell;

A plurality of switches, each switch included in the plurality of switches coupled to a component included in the set of components, and

An output electrode coupled to the plurality of switches, the digital-to-analog converter device configured to output an output signal at the output electrode;

Wherein a first unit cell size associated with a first unit cell included in the component set is different from a second unit cell size associated with a second unit cell included in the component set, and wherein the unit cell size of each unit cell is adjustable based on a mismatch error that achieves a target effective resolution value.

2. The apparatus of claim 1, wherein the target effective resolution value is tuned for a particular application.

3. The device of claim 2, wherein the specific application is neuromodulation.

4. The device of claim 3, wherein the specific neuromodulation is neural stimulation.

5. The device of claim 4, wherein the digital-to-analog converter device is a component of a neuromodulation device.

6. The apparatus of claim 5, wherein the output signal is a neural stimulation current.

7. The apparatus of claim 6, wherein the neural stimulation current modulates a particular neural circuit.