CN120568828B

CN120568828B - A 3D-packaged low parasitic inductance SiC power module

Info

Publication number: CN120568828B
Application number: CN202511038710.8A
Authority: CN
Inventors: 吴赞; 王茹; 王异凡; 骆丽; 王尊
Original assignee: Zhejiang University ZJU; Electric Power Research Institute of State Grid Zhejiang Electric Power Co Ltd
Current assignee: Zhejiang University ZJU; Electric Power Research Institute of State Grid Zhejiang Electric Power Co Ltd
Priority date: 2025-07-28
Filing date: 2025-07-28
Publication date: 2025-11-28
Anticipated expiration: 2045-07-28
Also published as: CN120568828A

Abstract

The invention discloses a low parasitic inductance SiC power module of a 3D package, which comprises a substrate layer, a chip layer, a connecting layer, an intermediate layer and a decoupling capacitor, wherein the chip layer is electrically connected with the substrate layer, the intermediate layer is positioned between an upper chip layer and a lower chip layer, the upper connecting layer and the lower connecting layer are windowed copper blocks and are externally connected with DC terminals for connecting the upper substrate layer and the decoupling capacitor, and the decoupling capacitor is two groups of capacitors arranged beside the intermediate layer and electrically connected with the upper connecting layer and the lower connecting layer. The copper material with high conductivity is connected with the lamination and the copper layer in the substrate to form the intermediate layer, so that the inductance of the power electronic system is obviously reduced, the heat dissipation effect is improved, the power electronic system has obvious advantages in high-frequency, high-voltage and high-power application, and the overall performance and reliability of the power electronic system can be effectively improved.

Description

Low parasitic inductance SiC power module of 3D encapsulation

Technical Field

The invention relates to the technical field of power electronics, in particular to a low parasitic inductance SiC power module of a 3D package.

Background

At present, siC power modules are widely used in the field of power electronics, and the system structure thereof generally includes chips, substrates, interconnections, package cases, and the like. The chip is responsible for power conversion, the substrate provides mechanical support and electrical connection, the interconnection realizes the electrical connection of the chip and the substrate, the decoupling capacitor realizes the effect of reducing the overshoot voltage during the switching of the chip, the buffer cushion block realizes the effect of reducing the thermal stress between the connecting surfaces, the service life of the module is prolonged, and the packaging shell plays a role of protection. In the aspect of algorithm, the traditional electromagnetic field simulation algorithm is mainly adopted to predict and optimize the performance of the module.

CN107170714a discloses a low parasitic inductance power module, which comprises an input power terminal, an output power terminal, a top metal insulating substrate, a bottom metal insulating substrate and a plastic package shell, wherein the input power terminal comprises an anode power terminal and a cathode power terminal, the top metal insulating substrate and the bottom metal insulating substrate are arranged in a lamination mode, chips are sintered on the surfaces of the top metal insulating substrate and the bottom metal insulating substrate, which are opposite to each other, the anode power terminal, the cathode power terminal and the output power terminal are electrically connected with the chips, the output power terminal comprises a welding part and a connecting part positioned outside the plastic package shell, and the welding part is positioned between the top metal insulating substrate and the bottom metal insulating substrate. The invention reduces the parasitic inductance of the loop, reduces the volume of the power module, saves the cost, lightens the weight, is particularly suitable for packaging SiC power chips, fully improves the overcurrent capacity and improves the reliability of the module.

CN118431209a discloses a SiC power module with low parasitic inductance and a manufacturing method thereof, comprising a first substrate, a second substrate, power chips, bonding wires, a third substrate, a driving terminal and a power terminal, wherein one side of the first substrate is down, the first substrate, the second substrate and the third substrate are sequentially laminated from bottom to top, a plurality of the power chips and a plurality of the driving terminals are fixedly mounted on the second substrate, the power chips are electrically connected with the second substrate through the bonding wires, a power loop is formed between the power chips, the driving terminals are electrically connected with the power terminals to form the second substrate, an input end and an output end of the second substrate for electrically connecting the power terminals are arranged between the power chips, and the input end and the output end of the second substrate for electrically connecting the power terminals are positioned in the power loop so as to improve the stability of the SiC power module.

The defects of the existing SiC power module products mainly comprise the following categories:

1. the parasitic inductance problem is that the traditional packaging structure causes larger parasitic inductance, so that the problems of limited switching speed, increased electromagnetic interference, voltage spike and the like of the device frequently occur, and the performance and the reliability of the module are seriously weakened. For example, in high frequency applications, voltage spikes due to parasitic inductance can break down the chip, reducing module life.

2. The heat dissipation performance is insufficient, the heat dissipation design of the existing module is not perfect, and a large amount of heat generated by a chip cannot be timely dissipated during high-power operation, so that the temperature of the module is too high, the performance and the stability are affected, and the problem of thermal failure is possibly caused.

3. The traditional package has poor mechanical stress resistance under the working conditions of vibration or bending, so that the chip and the interconnection structure are easily damaged, and the stability and the service life of the module are reduced.

With the development of power electronics technology to high frequency, high power and high integration, higher demands are being placed on the performance of SiC power modules.

Disclosure of Invention

Aiming at the problems that the parasitic inductance is high and the heat dissipation effect is to be improved, the invention provides the 3D packaged low parasitic inductance power module, which is formed by connecting a copper material with high conductivity with a lamination layer and a copper layer in a substrate to form an intermediate layer, thereby obviously reducing the inductance of a machine body, improving the heat dissipation effect, having obvious advantages in high-frequency, high-voltage and high-power application and being capable of effectively improving the overall performance and reliability of a power electronic system.

In order to achieve the above purpose, the invention adopts the following technical scheme:

A low parasitic inductance SiC power module of a 3D package comprises an upper substrate layer, an upper chip layer, an upper connecting layer, an intermediate layer, a decoupling capacitor, a lower connecting layer, a lower chip layer and a lower substrate layer which are stacked in sequence;

the upper chip layer stack is arranged on the inner side of the upper substrate layer, and the lower chip layer stack is arranged on the inner side of the lower substrate layer;

the upper chip layer is arranged on the upper surface of the upper substrate, the lower chip layer is arranged on the lower surface of the lower substrate, the middle layer is arranged between the upper chip layer and the lower chip layer, two sides of the middle layer are respectively and electrically connected with the chip layer through molybdenum copper blocks serving as buffer layers, and an AC connecting terminal is further arranged on the middle layer;

The upper connecting layer and the lower connecting layer are windowed copper blocks and are externally connected with a DC terminal, and the upper connecting layer is positioned between the middle layer and the upper substrate layer and is used for connecting the upper substrate layer and the decoupling capacitor;

The decoupling capacitors are two groups of capacitors arranged beside the middle layer and are electrically connected with the upper connecting layer and the lower connecting layer.

The working principle of the 3D packaging SiC power module is that the tight connection and the high-efficiency electric transmission between the chip and the substrate are realized through an innovative stacking structure and an interconnection technology. In the working process, current enters the module from the DC+ end, reaches the substrate layer through the upper connecting layer and copper cladding inside the upper DBC, passes through the wiring layer and the silver sintering layer on the substrate layer to the upper chip layer, is output from the AC end through the middle layer, or flows out from the DC-end through the lower substrate layer, the connecting copper block and the lower connecting layer and copper cladding inside the lower DBC.

The current path is greatly shortened and the parasitic inductance is obviously reduced due to the stacked structure of the chip layers, and the parasitic inductance of the module is further reduced by utilizing the mutual inductance effect between the upper connecting layer and the lower connecting layer. The decoupling capacitor is integrated in the module, so that the overshoot voltage of the chip is reduced, the circuit space is saved, the electrical property of the chip is improved, and the overall miniaturization of the module is promoted.

Preferably, the chip layer is electrically connected with the substrate layer through silver sintering, the electrical connection between the chip and the substrate is realized through a vertical interconnection technology, silver sintering is usually selected, and the parasitic inductance can be further reduced through the material and structural design of the interconnection layer, so that the signal transmission efficiency is improved. In the invention, the electrical connection between the chip layer and the substrate layer is preferably a silver sintering mode, so that parasitic inductance is reduced.

Preferably, the upper substrate layer and the lower substrate layer include an outer copper layer, a ceramic layer, and an inner copper layer, respectively.

Preferably, the chip layer is connected to the inner copper layer of the substrate layer.

Preferably, the chip layer is any one of a SiC MOSFET, a Si MOSFET and a CoolSiC MOSFET, preferably, the chip layer is a SiC MOSFET, and has the advantages of low on-resistance, high switching speed, high voltage resistance and the like.

Preferably, the ceramic layer is a ceramic material with good insulating property, such as an aluminum nitride ceramic substrate, aluminum oxide or beryllium oxide.

Preferably, the decoupling capacitor is electrically connected with the upper connecting layer and the lower connecting layer through reflow soldering. The decoupling capacitor can be used for absorbing the overshoot voltage generated on the parasitic inductor at the moment of conducting the chip, plays a role in stabilizing the voltages at two ends of the chip, and obviously improves the working stability of the chip.

Preferably, the intermediate layer is composed of copper blocks.

Preferably, the upper connecting layer and the lower connecting layer are externally connected with a direct current terminal, direct current flows in from the upper connecting layer through the terminal and flows out from the lower connecting layer, so as to change a current path, realize mutual inductance cancellation of a current loop and further reduce parasitic inductance. The AC connection terminals are soldered to the intermediate layer by reflow soldering.

Preferably, etched heat dissipation micro-channels are arranged on the outer copper layers of the upper substrate layer and the lower substrate layer. The heat dissipation performance and the reliability of the module can be further improved, the module can still stably run under severe working conditions of higher power and higher frequency, and the service life of the module is prolonged.

Preferably, the inner copper layer is wired using a kelvin wiring method.

Preferably, the molybdenum copper block is an alloy block with 50-80% of molybdenum mass and 20-50% of copper mass. Preferably, the molybdenum-copper pad adopts a combined alloy of 70% of molybdenum and 30% of copper, and combines the stress buffering of the molybdenum and the heat dissipation performance of the copper.

The inner copper layer wiring of the substrate adopts a Kelvin wiring method, so that overshoot voltage generated on the grid electrode is avoided. Meanwhile, the 3D packaged module can realize double-sided heat dissipation, and heat generated by the chip is rapidly conducted to an external radiator through the high-heat-conductivity substrate and the packaging shell, so that the normal working temperature of the module is ensured.

Compared with the traditional SiC power module, the invention adopts a 3D stacked packaging structure, the compact integration of a chip layer, a substrate layer and an interconnection layer and mutual inductance cancellation among the interconnection layers obviously reduce parasitic inductance, an internally integrated decoupling capacitor can reduce the overshoot voltage of the chip and increase the stability of the chip, and an internal copper layer wiring separates a source electrode of a current path between a drain and a source electrode of a current path between a grid and a source electrode by adopting a Kelvin wiring method, so that the overshoot voltage generated on the grid electrode during the switching of the chip is greatly reduced. Meanwhile, the optimized wiring and interconnection technology further improves the electrical performance and the signal transmission efficiency, and the heat dissipation capacity of the module is greatly improved due to the double-sided heat dissipation structure.

The SiC power module is mainly applied to high-frequency, high-voltage and high-power electronic equipment, such as electric automobiles, industrial motor drives, renewable energy systems and the like. In use, the module is mounted on a heat sink and connected to the rest of the system via an external circuit.

Compared with the prior art, the invention has the following beneficial effects:

(1) The SiC power module can obviously reduce parasitic inductance of the SiC power module, improve switching speed and performance, reduce electromagnetic interference and voltage spike, and enhance reliability and stability.

(2) The SiC power module can improve the heat radiation performance of the module, ensure stable operation under high-power and high-frequency conditions, has better electromagnetic compatibility, reduces the influence of electromagnetic interference on a system, improves the reliability and stability of the whole power electronic system, and can also enhance the mechanical stress resistance of the module by the buffer layer, thereby being suitable for different working environments.

Drawings

Fig. 1 is a schematic diagram of a bridge arm circuit of a 3D packaged low parasitic inductance SiC power module half-bridge power module of the present invention.

Fig. 2 is an overall exploded view of the 3D packaged low parasitic inductance SiC power module of example 1.

Fig. 3 is a side cross-sectional view of the lower leg of the 3D packaged low parasitic inductance SiC power module of embodiment 1.

Fig. 4 is a lower leg current path diagram in the low parasitic inductance SiC power module of embodiment 1.

Fig. 5 is a current path diagram under the kelvin wiring method of the inner copper layer in the low parasitic inductance SiC power module of embodiment 1.

Fig. 6 is a simulation result of the non-terminal DC-DC parasitic inductance of the low parasitic inductance SiC power module of example 1.

Fig. 7 is a heat dissipation situation of the SiC power module with low parasitic inductance of embodiment 1.

Fig. 8 is a diagram showing the heat dissipation of the individual chips in the SiC power module with low parasitic inductance in embodiment 1.

Wherein 11 is an upper substrate layer, 12 is a lower substrate layer, 13 is an outer copper layer, 14 is a ceramic layer, 15 is an inner copper layer, 21 is an upper chip layer, 22 is a lower chip layer, 31 is an upper connection layer, 32 is a lower connection layer, 4 is an intermediate layer, 5 is a decoupling capacitor, 6 is a molybdenum copper block, and 7 is an AC connection terminal.

Detailed Description

The present invention will be described in further detail with reference to the following examples in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention. Modifications and equivalents will occur to those skilled in the art upon understanding the present teachings without departing from the spirit and scope of the present teachings.

Example 1

The chip layer is made of Al ₂O₃ ceramic material, has high heat conductivity (170-200W/m K) and good insulating property, copper foils are bonded on two sides of the substrate through a DBC (Direct Bonded Copper) process, an inner copper layer and an outer copper layer are obtained by forming a metal wiring layer, and a bridge arm circuit diagram of the 3D packaged low parasitic inductance SiC half-bridge power module is shown in figure 1.

Fig. 2 is an overall explosion schematic diagram of a 3D packaged SiC power module with low parasitic inductance, which includes an upper substrate layer 11, an upper chip layer 21, an upper connection layer 31, an intermediate layer 4, a decoupling capacitor 5, a lower connection layer 32, a lower chip layer 22 and a lower substrate layer 12 stacked in sequence, where the upper substrate layer 11 and the lower substrate layer 12 include an outer copper layer 13, a ceramic layer 14 and an inner copper layer 15 respectively.

The chip layer and the substrate layer are fixed on the inner copper layer 15 of the substrate by silver paste sintering for electric connection, so that good electric contact and thermal contact are realized. The upper chip layer 21 is stacked and arranged on the inner copper layer 15 of the upper substrate layer 11, the lower chip layer 21 is stacked and arranged on the inner cylinder layer 15 of the lower substrate layer 12, the inner copper layer is wired by a Kelvin wiring method, and etched heat dissipation micro-channels are arranged on the outer copper layer. The heat-conducting structure can be used for realizing the electrical connection between the chip and the external pins, has good heat dissipation performance, and can effectively conduct heat generated by the chip.

The middle layer 4 is positioned between the upper chip layer 21 and the lower chip layer 22, two sides of the middle layer 4 are respectively and electrically connected with the chip layers through molybdenum copper blocks 6 serving as buffer layers, the middle layer 4 is also provided with an AC connecting terminal 7, the chip layers are incompletely covered when the molybdenum copper blocks 6 are connected with the chip layers, and the uncovered parts are used for setting grid electrodes of the chip layers;

The upper connecting layer 31 and the lower connecting layer 32 are windowed copper blocks and are externally connected with a DC terminal, the upper connecting layer 31 is positioned between the middle layer 4 and the upper substrate layer 11 and is used for connecting the upper substrate layer 11 and the decoupling capacitor 5, and the lower connecting layer 32 is positioned between the middle layer 4 and the lower substrate layer 12 and is used for connecting the lower substrate layer 12 and the decoupling capacitor 5;

the decoupling capacitor 5 is two groups of capacitors arranged at the side of the middle layer 4 and electrically connected with the upper connecting layer 31 and the lower connecting layer 32, and the decoupling capacitor 5 is electrically connected with the upper connecting layer 31 and the lower connecting layer 32 through reflow soldering;

Fig. 3 is a side cross-sectional view of the lower leg of the 3D packaged low parasitic inductance SiC power module of embodiment 1. Fig. 4 is a current loop of the lower bridge arm of the module, and the arrow indicates the current flow direction, and the loop fully utilizes the characteristic of mutual inductance cancellation to reduce the inductance, and avoids the conventional flip-chip technology in the 3D module, so that the module is simpler to manufacture.

Fig. 5 also shows the gate kelvin loop of the module. The design separates the gate-source loop from the drain-source loop, prevents large reverse electromotive force generated on the gate-source inductance by large current flowing through the source of the chip from influencing the gate voltage, and accelerates the conduction speed of the chip.

Fig. 6 shows that through Q3D simulation analysis, the parasitic inductance of the module is reduced by about 50% compared with other 3D packaging modules, the EMI interference is reduced, and compared with the traditional module, the parasitic inductance is only 1/5 of that of the traditional SiC power module, the crusting thermal resistance is obviously reduced, and the heat dissipation capacity is improved by about 35%. The technical effects show that the power module has obvious advantages in high-frequency, high-voltage and high-power application, and the overall performance and reliability of a power electronic system can be effectively improved.

Fig. 7 and 8 show heat dissipation data of the module, fig. 7 shows heat dissipation in the case of 5000h convection heat dissipation coefficient and 100W single chip power, and fig. 8 shows heat dissipation in the case of chip, as can be seen from the figure, the thermal resistance of the chip of the module is only 0.15C/W, which is lower than 0.3C/W in industry.

Claims

1. A 3D packaged low parasitic inductance SiC power module, characterized in that it comprises an upper substrate layer, an upper chip layer, an upper interconnect layer, an intermediate layer, a decoupling capacitor, a lower interconnect layer, a lower chip layer, and a lower substrate layer stacked sequentially; wherein the intermediate layer is composed of a copper block;

The upper substrate layer and the lower substrate layer respectively include an outer copper layer, a ceramic layer and an inner copper layer; the chip layer is connected to the inner copper layer of the substrate layer; the chip layer is electrically connected to the substrate layer; the upper chip layer is stacked on the inner side of the upper substrate layer, and the lower chip layer is stacked on the inner side of the lower substrate layer.

The intermediate layer is located between the upper chip layer and the lower chip layer. The two sides of the intermediate layer are electrically connected to the chip layer through molybdenum-copper blocks as buffer layers. The intermediate layer is also provided with AC connection terminals. The AC connection terminals are soldered onto the intermediate layer by reflow soldering. When the molybdenum-copper blocks are connected to the chip layer, they do not completely cover the chip layer. The uncovered part is used to set the gate of the chip layer.

The upper and lower connection layers are windowed copper blocks with external DC terminals. The upper connection layer is located between the middle layer and the upper substrate layer and is used to connect the upper substrate layer and the decoupling capacitor. The lower connection layer is located between the middle layer and the lower substrate layer and is used to connect the lower substrate layer and the decoupling capacitor.

The decoupling capacitors are two sets of capacitors located on the side of the intermediate layer and electrically connected to the upper and lower connection layers.

The outer copper layers of the upper and lower substrate layers are provided with etched heat dissipation microchannels.

2. The 3D packaged low parasitic inductance SiC power module according to claim 1, characterized in that the electrical connection between the chip layer and the substrate layer is achieved through silver sintering.

3. The 3D packaged low parasitic inductance SiC power module according to claim 1, wherein the chip layer is any one of SiC MOSFET, Si MOSFET, and CoolSiC MOSFET; and the ceramic layer is any one of aluminum nitride ceramic substrate, alumina, or beryllium oxide.

4. The 3D packaged low parasitic inductance SiC power module according to claim 1, wherein the decoupling capacitor is electrically connected to the upper connection layer and the lower connection layer by reflow soldering.

5. The 3D packaged low parasitic inductance SiC power module according to claim 1, wherein the molybdenum-copper block is an alloy block with a molybdenum mass percentage of 50-80% and a copper mass percentage of 20-50%.

6. The low parasitic inductance SiC power module with 3D packaging according to claim 1, wherein the inner copper layer is wired using the Kelvin wiring method.