CN120559451A

CN120559451A - An automated testing method, system, device, and computer-readable storage medium for chip particles

Info

Publication number: CN120559451A
Application number: CN202511080255.8A
Authority: CN
Inventors: 请求不公布姓名
Original assignee: Shanghai Qitai Fenghua Semiconductor Technology Co ltd
Current assignee: Shanghai Qitai Fenghua Semiconductor Technology Co ltd
Priority date: 2025-08-04
Filing date: 2025-08-04
Publication date: 2025-08-29
Anticipated expiration: 2045-08-04
Also published as: CN120559451B

Abstract

The invention relates to the technical field of chip detection, and particularly discloses an automatic test method, system and equipment for chip particles and a computer readable storage medium, wherein installation matching parameters (including associated data and contact characteristic parameters) of a chip and test equipment are firstly obtained, an installation matching index is obtained according to the installation matching parameters, whether the installation matching index exceeds a threshold value is judged, physical distribution parameters and electrical characteristic parameters of the chip are obtained if the installation matching index does not exceed the threshold value, and electrical response characteristics such as time sequence delay, current ripple waves, power consumption fluctuation and the like are obtained according to the electrical characteristic parameters, and an electrical performance index is calculated; according to the physical distribution parameters, the surface temperature and humidity distribution field is obtained, the physical energy index and the physical energy index are fused to obtain the comprehensive performance index, whether the preset value is exceeded or not is judged, if the preset value is exceeded, the chip is judged to be defective, the process realizes the automatic comprehensive detection of the chip defect through the fusion of the quantization parameters and the multi-dimension, the unilaterality of single index judgment is avoided, and the reliable result is ensured.

Description

Automatic test method, system and equipment for chip particles and computer readable storage medium

Technical Field

The invention relates to the technical field of chip detection, in particular to an automatic test method, system and equipment for chip particles and a computer readable storage medium.

Background

Chip particles (commonly referred to as "chip bare chips") are the smallest core units with complete circuit functions cut and separated from a wafer in the manufacturing process of integrated circuits (chips), chip detection refers to the process of comprehensively checking and verifying the electrical performance (such as voltage, current, frequency, power consumption and the like), functional integrity (whether preset instructions can be accurately executed), physical structure (such as no manufacturing defects, scratches, impurities, whether packaging is perfect or not) and reliability (such as stability under different temperature and humidity, vibration environments, service life and the like) of the integrated circuits (chips) in the whole life cycle from design, manufacturing and packaging to application through a series of professional technical means, instrument and test flows;

The existing chip detection generally only carries out independent quality judgment on single set attributes (such as electrical performance and physical structure), but cannot correlate and judge comprehensive attributes among several data, so that the judgment of chip particles is unilateral, and an automatic test method of the chip particles is needed to solve the problems.

Disclosure of Invention

The present invention is directed to an automated testing method, system and apparatus for chip particles, and a computer readable storage medium, which solve the technical problems set forth in the background art.

In order to achieve the above purpose, the present invention provides the following technical solutions:

An automatic test method of chip particles, which is applied to automatic test equipment, comprises the following steps:

acquiring installation matching parameters between the chip particles and the automatic test equipment, wherein the installation matching parameters comprise associated data and contact characteristic parameters of the chip particles and the automatic test equipment;

Acquiring an installation matching index according to the associated data and the contact characteristic parameters, and judging whether the installation matching index exceeds a threshold value;

If the installation coordination index does not exceed the threshold value, acquiring physical distribution parameters and electrical characteristic parameters of the chip particles, and acquiring electrical response characteristics according to the electrical characteristic parameters, wherein the electrical response characteristics comprise time sequence delay characteristics, current ripple characteristics and power consumption fluctuation characteristics, and acquiring electrical performance indexes according to the time sequence delay characteristics, the current ripple characteristics and the power consumption fluctuation characteristics;

Acquiring a surface temperature distribution field and a surface humidity distribution field of chip particles according to the physical distribution parameters, and acquiring a physical energy index according to the surface temperature distribution field and the surface humidity distribution field;

Acquiring a chip particle comprehensive performance index according to the physical performance index and the electrical performance index;

judging whether the chip particle comprehensive performance index exceeds a preset chip particle comprehensive performance index;

And if the comprehensive performance index of the chip particles exceeds the preset comprehensive performance index of the chip particles, judging that the chip particles have defects.

Preferably, the step of obtaining the installation matching index according to the association data and the contact characteristic parameter includes:

acquiring point position space offset, attitude angle, standard geometric center offset and height characteristic parameters of chip particles according to the associated data;

Acquiring a mechanical coupling error offset index according to the point position space offset, the attitude angle and the geometric center offset;

acquiring a height difference between a mounting groove reference surface of automatic test equipment and the highest point position of the chip particle surface according to the height characteristic parameters, and acquiring a height adaptation factor according to the height difference and a preset standard limit height;

Acquiring a contact resistance nominal value and a contact force stability coefficient according to the contact characteristic parameter, and acquiring a contact reliability index according to the contact resistance nominal value and the contact force stability coefficient;

And acquiring an installation matching index according to the mechanical coupling error offset index, the height adaptation factor and the contact reliability index.

Preferably, the step of obtaining the physical distribution parameter and the electrical characteristic parameter of the chip particle and obtaining the electrical response characteristic according to the electrical characteristic parameter, wherein the electrical response characteristic includes a time sequence delay characteristic, a current ripple characteristic and a power consumption fluctuation characteristic includes:

acquiring test time sequence data, test current sampling data and test power consumption monitoring data of the chip particles according to the electrical characteristic parameters;

Acquiring a delay time set and a clock jitter sequence within preset test time according to the test time sequence data, wherein the delay time set comprises maximum delay time and average delay time;

Obtaining a jitter standard deviation according to the clock jitter sequence;

Acquiring a time sequence characteristic value according to the maximum delay time, the average delay time and the jitter standard deviation, and taking the time sequence characteristic value as a time sequence delay characteristic;

Obtaining a current waveform according to the test current sampling data, and performing low-pass filtering on the current waveform to obtain a direct current component;

Carrying out high-pass filtering on the current waveform to obtain an alternating current component, and obtaining a crest peak value and a ripple effective value according to the alternating current component;

Calculating a ripple coefficient according to the direct current component and the ripple peak value, acquiring a current ripple characteristic value according to the ripple coefficient and the ripple effective value, and taking the current ripple characteristic value as a current ripple characteristic;

Acquiring a power consumption sequence according to the test power consumption monitoring data, and dividing the power consumption sequence into a plurality of subsequences with equal-length time windows;

Acquiring variances of a plurality of corresponding subsequences according to the subsequences of the long-time window, acquiring variance average values according to the variances of the subsequences, and taking the variance average values as global fluctuation indexes;

Acquiring a plurality of power consumption peaks according to the power consumption sequence, acquiring an average peak according to the plurality of power consumption peaks, acquiring a power consumption fluctuation characteristic value according to the ratio of the average peak to a global fluctuation index, and taking the power consumption fluctuation characteristic value as a power consumption fluctuation characteristic;

and taking the electrical response characteristics including a time sequence delay characteristic, a current ripple characteristic and a power consumption fluctuation characteristic as the electrical response characteristics.

Preferably, the step of obtaining the electrical performance index according to the time sequence delay characteristic, the current ripple characteristic and the power consumption fluctuation characteristic includes:

Mapping the time sequence delay characteristic, the current ripple characteristic and the power consumption fluctuation characteristic into independent components of a three-dimensional vector space respectively, wherein the independent components comprise a time sequence delay characteristic component, a current ripple characteristic component and a power consumption fluctuation characteristic component;

acquiring acquisition time of the electrical characteristic parameters, and equally dividing the acquisition time to obtain a plurality of time nodes;

combining the time sequence delay characteristic component, the current ripple characteristic component and the power consumption fluctuation characteristic component according to a plurality of time nodes to form an initial synergy matrix;

Carrying out standardized treatment on the initial collaboration matrix, and eliminating dimensional differences of different parameters to obtain a multi-modal collaboration matrix;

acquiring a covariance matrix according to the multi-mode cooperative matrix, decomposing eigenvalues of the covariance matrix, and extracting eigenvectors corresponding to the first K maximum eigenvalues;

Acquiring variance contribution rates according to a plurality of feature vectors;

And acquiring the total contribution rate of the feature vectors in the multi-mode cooperative matrix, calculating the contribution rate duty ratio according to the ratio of the variance contribution rate to the total contribution rate, and defining the contribution rate duty ratio as an electrical performance index.

Preferably, the step of obtaining a surface temperature distribution field and a surface humidity distribution field of the chip particles according to the physical distribution parameters, and obtaining a physical energy index according to the surface temperature distribution field and the surface humidity distribution field includes:

Discrete temperature measurement data of different positions of the chip surface are obtained, and a continuous surface temperature distribution field is obtained through an interpolation algorithm;

Identifying the highest temperature region in the temperature distribution field and marking the highest temperature region as a hot spot concentration region;

Acquiring hot spot temperature values of a plurality of continuous sampling moments in the hot spot concentration area, and generating a temperature change gradient of adjacent moments according to the hot spot temperature values of the plurality of continuous sampling moments;

discrete humidity measurement data of different positions of the chip surface are obtained, and a continuous surface humidity distribution field is obtained through an interpolation algorithm;

Identifying the highest humidity area in the humidity distribution field and recording the highest humidity area as a wet point concentrated area;

acquiring hot spot humidity values of a plurality of continuous sampling moments in the hot spot concentration area, and generating humidity change gradients of adjacent moments according to the hot spot humidity values of the plurality of continuous sampling moments;

and carrying out weighted calculation on the humidity change gradient and the temperature change gradient to obtain a surface comprehensive change value, and taking the surface comprehensive change value as a physical energy index.

Preferably, the step of obtaining the chip particle comprehensive performance index according to the physical performance index and the electrical performance index includes:

normalizing the physical energy index to obtain a physical energy normalization value;

Acquiring physical energy normalization value weight according to the physical energy normalization value;

Normalizing the electrical performance index to obtain an electrical performance normalized value;

acquiring an electrical property normalized value weight according to the electrical property normalized value;

And calculating the chip particle comprehensive performance index according to the physical energy normalization value, the physical energy normalization value weight, the electrical property normalization value and the electrical property normalization value weight.

The application also provides an automatic test system for chip particles, which comprises:

The first acquisition module is used for acquiring installation matching parameters between the chip particles and the automatic test equipment, wherein the installation matching parameters comprise associated data and contact characteristic parameters of the chip particles and the automatic test equipment;

The second acquisition module is used for acquiring an installation matching index according to the associated data and the contact characteristic parameters and judging whether the installation matching index exceeds a threshold value or not;

The third acquisition module is used for acquiring a surface temperature distribution field and a surface humidity distribution field of the chip particles according to the physical distribution parameters and acquiring a physical energy index according to the surface temperature distribution field and the surface humidity distribution field;

the fourth acquisition module is used for acquiring the comprehensive performance index of the chip particles according to the physical performance index and the electrical performance index;

the judging module is used for judging whether the chip particle comprehensive performance index exceeds a preset chip particle comprehensive performance index;

Preferably, the second acquisition module includes:

the first acquisition unit is used for acquiring point position space offset, attitude angle, standard geometric center offset and height characteristic parameters of the chip particles according to the associated data;

The second acquisition unit is used for acquiring a mechanical coupling error offset index according to the point position space offset, the attitude angle and the geometric center offset;

The third acquisition unit is used for acquiring the height difference of the highest point position of the mounting groove reference surface of the automatic test equipment and the chip particle surface according to the height characteristic parameters, and acquiring a height adaptation factor according to the height difference and a preset standard limit height;

The third acquisition unit is used for acquiring a contact resistance nominal value and a contact force stability coefficient according to the contact characteristic parameter, and acquiring a contact reliability index according to the contact resistance nominal value and the contact force stability coefficient;

And the fourth acquisition unit is used for acquiring an installation matching index according to the mechanical coupling error offset index, the height adaptation factor and the contact reliability index.

The application also provides automatic test equipment of the chip particles, which comprises a control module and a driving module, wherein the control module is used for controlling parts on the automatic test equipment;

the driving module is used for driving the parts on the automatic test equipment to realize the steps of the method.

The application also provides a computer readable storage medium having stored thereon a computer program which when executed by a processor performs the steps of the above method.

The method has the beneficial effects that firstly, the installation matching parameters (including the associated data and the contact characteristic parameters) of the chip and the test equipment are obtained, the installation matching index is obtained, whether the installation matching index exceeds a threshold value is judged, the physical distribution parameters and the electrical characteristic parameters of the chip are obtained without exceeding the threshold value, the electrical response characteristics such as time sequence delay, current ripple and power consumption fluctuation are obtained through the electrical characteristic parameters, the electrical performance index is calculated, the surface temperature and humidity distribution field is obtained according to the physical distribution parameters, the physical performance index is obtained, the comprehensive performance index is obtained by fusing the physical distribution parameters, whether the preset value is exceeded or not is judged, the defect of the chip is judged if the integrated performance index exceeds the preset value, the process realizes the automatic comprehensive detection of the defect of the chip through the fusion of the quantization parameters and the multidimensional, the one-sided performance of single index judgment is avoided, and the result is reliable.

Drawings

FIG. 1 is a flow chart of a method according to an embodiment of the application.

Fig. 2 is a schematic diagram of a system structure according to an embodiment of the application.

Fig. 3 is a schematic structural diagram of an automated test equipment for chip particles according to an embodiment of the present application.

Fig. 4 is a top view of an automated test equipment for chip particles according to an embodiment of the application.

Fig. 5 is a side view of an automated test equipment for chip particles according to an embodiment of the application.

Fig. 6 is a block diagram of a power and signal board, a pass-through board, a back board, and a mounting platen card for providing chips under test in an automated test equipment for chip particles according to an embodiment of the present application.

Fig. 7 is a diagram illustrating a first board and a first board structure in an automated test equipment for chip particles according to an embodiment of the present application.

The achievement of the objects, functional features and advantages of the present application will be further described with reference to the accompanying drawings, in conjunction with the embodiments.

Detailed Description

It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.

As shown in fig. 1, the present application provides an automated testing method of chip particles, including:

S1, acquiring installation matching parameters between chip particles and automatic test equipment, wherein the installation matching parameters comprise associated data and contact characteristic parameters of the chip particles and the automatic test equipment;

S2, acquiring an installation matching index according to the associated data and the contact characteristic parameter, and judging whether the installation matching index exceeds a threshold value;

S3, acquiring a surface temperature distribution field and a surface humidity distribution field of the chip particles according to the physical distribution parameters, and acquiring a physical energy index according to the surface temperature distribution field and the surface humidity distribution field;

s4, acquiring a chip particle comprehensive performance index according to the physical performance index and the electrical performance index;

s5, judging whether the chip particle comprehensive performance index exceeds a preset chip particle comprehensive performance index;

As described in the above steps S1-S5, since the existing chip detection generally only performs independent quality judgment on a single set attribute (such as electrical performance and physical structure), but cannot correlate and judge comprehensive attributes among several data, so that the judgment of chip particles is unilateral, the invention firstly obtains installation matching parameters between chip particles and automatic test equipment, wherein the installation matching parameters comprise associated data and contact characteristic parameters of the chip particles and the automatic test equipment, so that the installation matching state of the chip particles and the automatic test equipment can be quantified through the associated data and the contact characteristic parameters, and whether the installation matching directly affects the accuracy of subsequent test data or not is good, and the step lays a reliable foundation for subsequent test;

then, acquiring an installation matching index according to the associated data and the contact characteristic parameters, and judging whether the installation matching index exceeds a threshold value;

If the installation matching index does not exceed the threshold value, acquiring physical distribution parameters and electrical characteristic parameters of chip particles, and acquiring electrical response characteristics according to the electrical characteristic parameters, wherein the electrical response characteristics comprise time sequence delay characteristics, current ripple characteristics and power consumption fluctuation characteristics, and acquiring electrical performance indexes according to the time sequence delay characteristics, the current ripple characteristics and the power consumption fluctuation characteristics, so that the installation parameters can be converted into quantifiable installation matching indexes, and the chips suitable for testing are screened out through threshold value judgment (if the indexes are less than or equal to the threshold value and are qualified for installation), and meanwhile, the unqualified chips are prevented from entering a subsequent testing flow, so that resource waste is reduced, the electrical response characteristics reflect the circuit performance of the chips, namely, the excessive time sequence delay can cause data transmission errors, the excessive current ripple can interfere with power supply stability, and the severe power consumption fluctuation can cause circuit overheating, so that the electrical performance of the chips can be quantified comprehensively, and the limitation of single index is avoided;

Secondly, acquiring a surface temperature distribution field and a surface humidity distribution field of chip particles according to the physical distribution parameters, and acquiring physical energy indexes according to the surface temperature distribution field and the surface humidity distribution field, wherein the temperature and humidity distribution reflects the heat dissipation capacity and environmental tolerance of the chip, namely, hot spots are concentrated, the temperature rises rapidly and can cause local burning, the humidity is too high, the electric leakage can be caused due to severe variation, and the defect that only the electrical performance is concerned is overcome by quantifying the physical environmental adaptability of the chip;

And then, acquiring the comprehensive performance index of the chip particles according to the physical performance index and the electrical performance index, and fusing the electrical function and the physical environment adaptability through the comprehensive performance index. For example, if the electrical parameters of a certain chip are qualified, but the temperature of a hot spot is increased sharply, the comprehensive index of the hot spot may exceed the standard, the potential heat dissipation defect is reflected, the multi-dimensional defect judgment can be realized, and the composite defect covered by the qualified single index is avoided;

Finally, judging whether the chip particle comprehensive performance index exceeds a preset chip particle comprehensive performance index;

If the chip particle comprehensive performance index exceeds the preset chip particle comprehensive performance index, judging that the chip particles have defects, so that the installation state, the electrical performance and the physical environment influence are brought into a unified system, and the one-sidedness of the traditional test is solved. Each step ensures that the test process can be interpreted and the result is reliable through the quantitative calculation of specific parameters, realizes the automatic and comprehensive detection of the chip particle defects, and simultaneously can avoid the unilateral detection of the chip particles caused by single independent data judgment.

In one embodiment, the step S2 of obtaining the installation matching index according to the association data and the contact characteristic parameter includes:

S201, acquiring point position space offset, attitude angle, standard geometric center offset and height characteristic parameters of chip particles according to the associated data;

s202, acquiring a mechanical coupling error offset index according to the point position space offset, the attitude angle and the geometric center offset;

S203, acquiring a height difference between a mounting groove reference surface of automatic test equipment and the highest point position of the chip particle surface according to the height characteristic parameters, and acquiring a height adaptation factor according to the height difference and a preset standard limit height;

S204, acquiring a contact resistance nominal value and a contact force stability coefficient according to the contact characteristic parameter, and acquiring a contact reliability index according to the contact resistance nominal value and the contact force stability coefficient;

s205, acquiring an installation matching index according to the mechanical coupling error offset index, the height adaptation factor and the contact reliability index.

According to the method, the point position space offset, the attitude angle, the standard geometric center offset and the height characteristic parameters of the chip particles are firstly obtained according to the related data, wherein the related data are obtained through a vision sensor (such as an industrial camera) and a displacement sensor (such as a laser range finder) of automatic test equipment, the specific process is that 1 the point position space offset is obtained through shooting a preset mark point (such as a pin locating point) on the surface of the chip and comparing with the standard point position of a test probe of the equipment, the position deviation in a three-dimensional space is calculated, 2 the attitude angle is obtained through identifying the edge profile of the chip and comparing with the standard profile of a mounting groove of the equipment, the rotation angle, the inclination angle, 3 the standard geometric center offset of the chip on the horizontal plane are calculated, the distance deviation in the two-dimensional plane is calculated through locating the physical center (such as a diagonal intersection point) of the chip and the geometric center of the mounting groove of the equipment, and 4 the height characteristic parameters are core indexes of the mechanical locating precision of the chip through the laser range finder. For example, an excessive spatial offset of the sites means that the alignment error between the chip pins and the device probes is large, which may cause that part of the pins cannot be contacted; the overlarge attitude angle reflects the inclination of the chip, so that poor contact of local point positions can be aggravated, basic data is provided for subsequent calculation of mechanical positioning related indexes, and the accurate description of the deviation of the mounting position is realized;

And then, acquiring a mechanical coupling error offset index according to the point position space offset, the attitude angle and the geometric center offset, and then sequentially acquiring a maximum allowable offset, a maximum allowable attitude angle and a maximum allowable center offset, wherein the mechanical coupling error offset index= (point position space offset/maximum allowable offset) ×a first weight value (weight value of point position space offset/maximum allowable offset) + (weight value of attitude angle/maximum allowable attitude angle) ×a second weight value (weight value of attitude angle/maximum allowable attitude angle) + (weight value of geometric center offset/maximum allowable center offset) ×a third weight value (weight value of geometric center offset/maximum allowable center offset), and the maximum allowable value is a preset qualification threshold of the device, and the index comprehensively reflects the overall positioning error of the chip in a three-dimensional space. For example, if the chip point position is offset by 0.08mm (reaching 80% of the maximum allowable value), the attitude angle is 0.3 degrees (reaching 60% of the maximum allowable value), the center offset is 0.05mm (reaching 50% of the maximum allowable value), the offset index=0.8×0.4+0.6×0.3+0.5×0.3=0.65, which suggests that a more obvious positioning deviation exists, the point position space offset directly determines the contact dislocation probability of the probe and the pin, the larger the offset, the more difficult the probe to accurately reach the pin is, the most basic "contact precondition", so that the weight is the highest, secondly, the attitude angle influences the uniformity of the contact, the attitude inclination can cause the local pin pressure of the chip to be overlarge and the local poor contact, but can be compensated by micro deformation, the influence the point position offset and the weight times, and finally, the geometric center offset influences the symmetry of the contact, the center offset can cause the uneven distribution of the whole contact pressure, but the contact dislocation risk is slightly weaker than the contact dislocation risk, the damage degree is the lowest, so that a plurality of dispersed mechanical positioning parameters are converted into single mechanical positioning parameters, and the quick positioning index is convenient to evaluate and fast and evaluate the quantization precision;

And then, acquiring the height difference of the highest point position of the mounting groove reference surface of the automatic test equipment and the chip particle surface according to the height characteristic parameters, and acquiring a height adaptation factor according to the height difference and a preset standard limit height, wherein the height adaptation factor=1-height difference/preset standard limit height (the preset standard limit height is the maximum height allowed by the equipment), and simultaneously, the height adaptation factor reflects the suitability of the chip and the equipment in the vertical direction. The factor is closer to 1, which means that the smaller the height difference, the more proper the vertical distance between the chip and the device (neither the contact is caused by too high nor the physical extrusion is caused by too low), and when the factor is negative, the factor indicates that the height exceeds the safety range, so that the mechanical damage is possibly caused, and secondly, the installation rationality in the vertical direction is quantized, so that the physical damage or contact failure caused by the height mismatching is avoided;

and secondly, acquiring a contact resistance nominal value and a contact force stability coefficient according to the contact characteristic parameter, and acquiring a contact reliability index according to the contact resistance nominal value and the contact force stability coefficient, wherein the contact characteristic parameter is obtained by measuring the contact resistance (contact resistance nominal value) of a chip pin and a probe through a resistance tester of equipment, acquiring real-time fluctuation data of the contact force through a pressure sensor (calculating the contact force stability coefficient), and secondly, calculating the contact force stability coefficient by calculating a standard deviation of the contact force sampling data (such as 100 times of sampling) and dividing the standard deviation by an average value to obtain the fluctuation coefficient (the smaller the coefficient is, the higher the stability is), and meanwhile, calculating the contact reliability index by adopting the formula of "(1-contact resistance nominal value/maximum allowable contact resistance) x (1-contact force fluctuation coefficient)", so that the quality of electric contact is reflected through the contact reliability index. The smaller the contact resistance, the smaller the current transmission loss, and the higher the contact force stability, the more stable the contact state (no interruption of contact due to vibration or the like). The closer the index is to 1, the more reliable the electric contact is, and meanwhile, the stability and low loss of the electric contact are comprehensively evaluated, so that the distortion of electric test data caused by the contact problem is avoided;

Finally, a mounting matching index is obtained according to the mechanical coupling error offset index, the height adaptation factor and the contact reliability index, wherein the mounting matching index= (1-mechanical coupling error offset index) ×fourth weight value (weight value of 1-mechanical coupling error offset index) +the height adaptation factor×fifth weight value (weight value of height adaptation factor) +the contact reliability index×sixth weight value (weight value of contact reliability index), weight allocation is based on the influence degree of each factor on mounting quality, and contact reliability has the greatest influence on electrical test, so the weight is the highest, the mechanical positioning is the lowest, the height adaptation weight is the lowest), for example, the mechanical coupling error offset index=0.2 (i.e. 1-0.2=0.8), the height adaptation factor=0.75, the contact reliability index=0.45, then the mounting matching index=0.8×0.3+0.75×0.45×0.5=0.24+0.15+0.225, and the mounting matching index is a quantized value of 1, the mounting quality range is quantized. The lower the index, the worse the installation quality, the invalid subsequent test data can be caused, and the scattered installation parameters are converted into single comparable indexes, so that a clear basis is provided for the subsequent judgment of whether the installation is qualified.

In one embodiment, the step S2 of obtaining the physical distribution parameter and the electrical characteristic parameter of the chip particle, and obtaining the electrical response characteristic according to the electrical characteristic parameter, where the electrical response characteristic includes a time sequence delay characteristic, a current ripple characteristic, and a power consumption fluctuation characteristic includes:

s208, acquiring test time sequence data, test current sampling data and test power consumption monitoring data of the chip particles according to the electrical characteristic parameters;

S209, acquiring a delay time set and a clock jitter sequence within preset test time according to the test time sequence data, wherein the delay time set comprises maximum delay time and average delay time;

S2010, obtaining a jitter standard deviation according to the clock jitter sequence;

S2011, acquiring a time sequence characteristic value according to the maximum delay time, the average delay time and the jitter standard deviation, and taking the time sequence characteristic value as a time sequence delay characteristic;

s2012, acquiring a current waveform according to the test current sampling data, and performing low-pass filtering on the current waveform to obtain a direct current component;

S2013, carrying out high-pass filtering on the current waveform to obtain an alternating current component, and obtaining a crest peak value and a ripple effective value according to the alternating current component;

s2014, calculating a ripple coefficient according to the direct current component and the ripple peak value, obtaining a current ripple characteristic value according to the ripple coefficient and the ripple effective value, and taking the current ripple characteristic value as a current ripple characteristic;

s2015, acquiring a power consumption sequence according to the test power consumption monitoring data, and dividing the power consumption sequence into a plurality of subsequences with equal-length time windows;

s2016, acquiring variances of a plurality of corresponding subsequences according to the subsequences of the long-time window, acquiring variance averages according to the variances of the subsequences, and taking the variance averages as global fluctuation indexes;

s2017, acquiring a plurality of power consumption peaks according to the power consumption sequence, acquiring average peaks according to the power consumption peaks, acquiring a power consumption fluctuation characteristic value according to the ratio of the average peaks to a global fluctuation index, and taking the power consumption fluctuation characteristic value as a power consumption fluctuation characteristic;

and S2018, taking the electrical response characteristics including a time sequence delay characteristic, a current ripple characteristic and a power consumption fluctuation characteristic as electrical response characteristics.

As described in the above steps S208-S2018, because only a single electrical parameter (such as average voltage and current) is tested, the relevance between the parameters (such as the coupling relation between time sequence delay and power consumption fluctuation) is ignored, therefore, the invention firstly obtains the test time sequence data, test current sampling data and test power consumption monitoring data of chip particles according to the electrical characteristic parameter, wherein the test time sequence data is that the transmission time (such as the delay from the rising edge of a clock signal to the output of data) of a key signal path of a chip is collected through an oscilloscope, the sampling frequency is 1GHz, the collection is continuously carried out for 10ms (10000 sampling points altogether), and secondly, the test power consumption monitoring data is that the real-time power consumption of the chip is collected through a power meter, the sampling frequency is 10kHz, the collection is continuously carried out for 1S (10000 sampling points altogether), and the data is a 'time domain image' of the electrical behavior of the chip is that the time sequence data reflects the signal transmission efficiency, the current data represents the energy consumption mode, the whole energy conversion characteristic is revealed by the power consumption data, meanwhile, the original data is provided for the subsequent feature extraction, and the analysis is ensured to cover multiple dimensions of the electrical performance of the chip;

Then, a delay time set and a clock jitter sequence within a preset test time are obtained according to the test time sequence data, wherein the delay time set comprises a maximum delay time and an average delay time, then a jitter standard deviation is obtained according to the clock jitter sequence, then a time sequence characteristic value is obtained according to the maximum delay time, the average delay time and the jitter standard deviation, the time sequence characteristic value is taken as a time sequence delay characteristic, a delay parameter is calculated, namely, the delay time of each sampling point is extracted from the time sequence data, the maximum delay time (Tmax) and the average delay time (Tavg) in the sampling points (such as 10000) within the preset time are counted, the clock jitter is analyzed, namely, a difference sequence of the delay times of adjacent sampling points is calculated, the clock jitter sequence is obtained, and then the standard deviation (CZ) of the sequence is calculated, and the time sequence characteristic value is synthesized, namely, three parameters are fused into a single characteristic value (the larger value, the time sequence performance is worse) through calculation of formula time sequence characteristic value, and the time sequence characteristic value quantifies the instability of signal transmission. For example, if tmax=5 ns (qualification threshold is 4 ns), tavg=3 ns, cz=0.2 ns, then the timing characteristic value= (5+3) ×0.2=1.6, which suggests that there is a serious timing problem (possibly that the signal path is too long due to unreasonable circuit design or manufacturing defect), and complex timing data can be converted into a single index for comparison, so as to facilitate the subsequent collaborative analysis with other electrical characteristics;

Secondly, obtaining a current waveform according to the test current sampling data, carrying out low-pass filtering on the current waveform to obtain a direct current component, simultaneously carrying out high-pass filtering on the current waveform to obtain an alternating current component, obtaining a ripple peak value and a ripple effective value according to the alternating current component, calculating a ripple coefficient according to the direct current component and the ripple peak value, obtaining a current ripple characteristic value according to the ripple coefficient and the ripple effective value, and taking the current ripple characteristic value as a current ripple characteristic, wherein the filtering separates the direct current component and the alternating current component, namely, carrying out low-pass filtering (cut-off frequency 50 Hz) on the current sampling data to obtain a direct current component (IDC), carrying out high-pass filtering (cut-off frequency 1 kHz) to obtain an alternating current component (IAC), and obtaining a plurality of alternating current components (IAC) according to a preset acquisition time, wherein the ripple coefficient = alternating current component peak value/direct current component, and ripple effective value = = N represents the number of ac components, the current ripple characteristic value=ripple coefficient×ripple effective value, and the current ripple characteristic value reflects the "purity" of the power supply. For example, if idc=1a, ac component peak-to-peak value=0.2A (ripple coefficient=0.2), ripple effective value=0.05A, current ripple characteristic value=0.2×0.05=0.01. If the value exceeds a preset threshold (such as 0.005), prompting that the power supply filter circuit is likely to fail, influencing the stability of the chip, quantifying the severity of current fluctuation, and identifying potential power supply design or filter element defects;

Then, according to the test power consumption monitoring data, a power consumption sequence is obtained, the power consumption sequence is divided into a plurality of subsequences with equal length time windows, then, according to the subsequences with equal length time windows, the variances of the corresponding subsequences are obtained, the variance average value is obtained according to the variances of the subsequences, the variance average value is used as a global fluctuation index, next, a plurality of power consumption peak values are obtained according to the power consumption sequence, an average peak value is obtained according to the power consumption peak values, according to the ratio of the average peak value to the global fluctuation index, a power consumption fluctuation characteristic value is obtained, and the power consumption fluctuation characteristic value is used as a power consumption fluctuation characteristic, so that the power consumption fluctuation characteristic value captures the 'dynamic instability' of a chip, meanwhile, the power consumption abnormality of the chip under different working states is identified, the intermittent defect that the traditional average power consumption test cannot detect is found, the value can distinguish the 'high peak value but stable fluctuation' (such as normal program load) from the 'high peak value and intense fluctuation' (such as abnormal short circuit), and the reasonable peak value is avoided;

finally, the electrical response characteristics including time sequence delay characteristics, current ripple characteristics and power consumption fluctuation characteristics are used as electrical response characteristics, so that the three characteristics cover the core dimension of the electrical performance of the chip from time response, current stability and power consumption rationality respectively, the cooperative analysis can capture defects which cannot be reflected by a single characteristic (such as time sequence delay and excessive current ripple possibly caused by internal short circuit), meanwhile, the problem of insufficient one-sided and dynamic characteristic characterization of the traditional electrical test is solved, and a multidimensional and high-precision foundation is laid for the calculation of the subsequent electrical performance index.

In one embodiment, the step S2 of obtaining the electrical performance index according to the timing delay characteristic, the current ripple characteristic, and the power consumption fluctuation characteristic includes:

s2019, mapping the time sequence delay characteristic, the current ripple characteristic and the power consumption fluctuation characteristic into independent components of a three-dimensional vector space respectively, wherein the independent components comprise a time sequence delay characteristic component, a current ripple characteristic component and a power consumption fluctuation characteristic component;

S2020, acquiring acquisition time of the electrical characteristic parameters, and equally dividing the acquisition time to obtain a plurality of time nodes;

s2021, combining the time sequence delay characteristic component, the current ripple characteristic component and the power consumption fluctuation characteristic component according to a plurality of time nodes to form an initial synergy matrix;

S2022, carrying out standardized processing on the initial cooperative matrix, and eliminating dimensional differences of different parameters to obtain a multi-mode cooperative matrix;

S2023, acquiring a covariance matrix according to the multi-mode cooperative matrix, decomposing eigenvalues of the covariance matrix, and extracting eigenvectors corresponding to the first K maximum eigenvalues;

S2024, obtaining variance contribution rates according to a plurality of the feature vectors;

s2025, obtaining the total contribution rate of the feature vectors in the multi-mode collaboration matrix, calculating the contribution rate duty ratio according to the ratio of the variance contribution rate to the total contribution rate, and defining the contribution rate duty ratio as an electrical performance index.

As described in the above steps S2019-S2025, the present invention maps the time delay feature, the current ripple feature and the power consumption fluctuation feature into independent components of a three-dimensional vector space, wherein the independent components include a time delay feature component, a current ripple feature component and a power consumption fluctuation feature component, unifies the dispersed features into the same vector space, lays a foundation for subsequent multi-feature collaborative analysis, and solves the problem of feature dimension isolation;

then, acquiring acquisition time of the electrical characteristic parameters, equally dividing the acquisition time to obtain a plurality of time nodes, and capturing dynamic changes of characteristics along with time (such as gradual increase of time sequence delay in the chip heating process) through time dimension so as to avoid accidental use of data at a single moment;

Then, combining the time sequence delay characteristic component, the current ripple characteristic component and the power consumption fluctuation characteristic component according to a plurality of time nodes to form an initial cooperative matrix, wherein the time sequence delay characteristic component, the current ripple characteristic component and the power consumption fluctuation characteristic component of the corresponding nodes of the plurality of time nodes are respectively identified, and after matrixing, the time relevance of the characteristics is highlighted to provide a structural basis for the subsequent analysis of the characteristic coupling mode;

The initial synergy matrix is subjected to standardization processing, dimensional differences of different parameters are eliminated, a multi-mode synergy matrix is obtained, after standardization, the numerical ranges of three types of features are unified (such as being converted into normal distribution with average value 0 and standard deviation 1), the fact that the time sequence delay increase 1 unit and the current ripple increase 1 unit have the same weight in analysis is ensured, and feature importance misjudgment caused by the dimensional differences is avoided;

Meanwhile, obtaining a covariance matrix according to the multi-mode cooperative matrix, decomposing the characteristic values of the covariance matrix, and extracting characteristic vectors corresponding to the first K maximum characteristic values, so that the characteristic value decomposition compresses the high-dimensional characteristics to main dimensions to enable the high-dimensional characteristics to be compressed;

Secondly, obtaining a variance contribution rate according to a plurality of feature vectors, and secondly, indicating that the higher the contribution rate is, the more the extracted main feature mode can reflect the real state of the electrical performance of the chip, and reducing the interference of noise on an evaluation result, wherein the variance contribution rate is Wherein, the Obtaining a variance contribution rate for the kth feature vector, wherein k=1, 2, 3..k, K is a sequence number of the variance contribution rate obtained for the feature vector;

And finally, acquiring the total contribution rate of the feature vectors in the multi-mode cooperative matrix, calculating the contribution rate duty ratio according to the ratio of the variance contribution rate to the total contribution rate, defining the contribution rate duty ratio as an electrical performance index, converting complex multi-feature and multi-time point data into a single comparable index, realizing the overall quantitative evaluation of the electrical performance of the chip, ensuring that the physical meaning of the index is clear (based on the interpretability of the data variation), avoiding the subjective weighted deviation, and simultaneously, eliminating dimension difference and noise interference, retaining the relevance and time dynamic property among the features and finally obtaining the electrical performance index which can objectively reflect the overall quality of the electrical performance of the chip and providing a reliable electrical dimension basis for the subsequent comprehensive performance evaluation through the cooperative analysis of the multi-dimensional electrical features.

In one embodiment, the step S3 of obtaining a surface temperature distribution field and a surface humidity distribution field of the chip particles according to the physical distribution parameters, and obtaining a physical energy index according to the surface temperature distribution field and the surface humidity distribution field includes:

s301, acquiring discrete temperature measurement data of different positions of the chip surface, and obtaining a continuous surface temperature distribution field through an interpolation algorithm;

s302, identifying a highest temperature region in the temperature distribution field and marking the highest temperature region as a hot spot concentration region;

S303, acquiring hot spot temperature values of a plurality of continuous sampling moments in the hot spot concentrated area, and generating a temperature change gradient of adjacent moments according to the hot spot temperature values of the plurality of continuous sampling moments;

s304, discrete humidity measurement data of different positions of the chip surface are obtained, and a continuous surface humidity distribution field is obtained through an interpolation algorithm;

S305, identifying the highest humidity area in the humidity distribution field, and recording the highest humidity area as a wet point concentrated area;

s306, acquiring hot spot humidity values of a plurality of continuous sampling moments in the hot spot concentrated area, and generating humidity change gradients of adjacent moments according to the hot spot humidity values of the plurality of continuous sampling moments;

s307, carrying out weighted calculation on the humidity change gradient and the temperature change gradient to obtain a surface comprehensive change value, and taking the surface comprehensive change value as a physical energy index.

As described in the above steps S301-S307, the present invention firstly obtains discrete temperature measurement data of different positions on the chip surface, and obtains a continuous surface temperature distribution field through an interpolation algorithm, expands local temperature measurement into global temperature "image", solves the problem that the traditional single-point measurement cannot reflect uneven temperature distribution, and provides a foundation for locating hot spot areas;

Secondly, the highest temperature region in the temperature distribution field is identified and marked as a hot spot concentration region, and the region with the highest focusing temperature and most possibility of causing failure is avoided from indiscriminate analysis on the global temperature, so that the defect positioning efficiency is improved (for example, the hot spot region possibly corresponds to an internal power device dense region, and overheating of the hot spot region possibly is caused by device short circuit);

Then, obtaining hot spot temperature values of a plurality of continuous sampling moments in the hot spot concentrated area, generating a temperature change gradient at adjacent moments according to the hot spot temperature values of the plurality of continuous sampling moments, wherein the temperature change gradient reflects the heating rate of the hot spot, and the larger the gradient is, the worse the heat dissipation capability (such as heat cannot be diffused due to blockage of a heat dissipation channel in a chip) is, and the higher the potential burning risk is;

Meanwhile, discrete humidity measurement data of different positions on the surface of the chip are obtained, a continuous surface humidity distribution field is obtained through an interpolation algorithm, and a local high humidity area (such as corrosion possibly caused by abnormal humidity at an edge pin) possibly caused by poor sealing or environmental exposure is identified through construction of humidity global distribution;

then, identifying the highest humidity area in the humidity distribution field, and recording the highest humidity area as a wet point concentrated area, wherein the area with the highest humidity and most possibility of causing electric leakage or corrosion is positioned, and if the area is overlapped with a pin, the contact resistance is possibly increased;

next, acquiring hot spot humidity values of a plurality of continuous sampling moments in the hot spot concentrated area, generating humidity change gradients of adjacent moments according to the hot spot humidity values of the plurality of continuous sampling moments, wherein the larger the humidity change gradients reflect the wetting rate of wet spots, the worse the moisture resistance (such as rapid invasion of moisture caused by packaging gaps) is indicated, and the higher the potential leakage risk is;

And finally, carrying out weighted calculation on the humidity change gradient and the temperature change gradient to obtain a surface comprehensive change value, taking the surface comprehensive change value as a physical energy index, fusing dynamic change characteristics of temperature and humidity into a single index, comprehensively evaluating the heat radiation capacity and the humidity resistance of the chip, avoiding the limitation of evaluating a single physical parameter (such as that the temperature of a certain chip is normal but the humidity is excessively fast to rise, and the physical energy index of the chip is still out of standard), and carrying out space field reconstruction and dynamic gradient analysis to realize the fine evaluation on the physical characteristics of the chip. The physical energy index obtained by final fusion can comprehensively reflect the physical environment adaptability of the chip from discrete measurement to continuous field construction and from key region identification to change trend quantification, a reliable physical dimension basis is provided for comprehensive performance evaluation, and the defect that only electrical performance is concerned in the prior art is overcome.

In one embodiment, the step S4 of obtaining the chip particle comprehensive performance index according to the physical performance index and the electrical performance index includes:

s401, carrying out normalization processing on the physical energy index to obtain a physical energy normalization value;

s402, acquiring physical energy normalization value weight according to the physical energy normalization value;

s403, carrying out normalization processing on the electrical performance index to obtain an electrical performance normalization value;

s404, acquiring an electrical property normalized value weight according to the electrical property normalized value;

s405, calculating the chip particle comprehensive performance index according to the physical energy normalization value, the physical energy normalization value weight, the electrical property normalization value and the electrical property normalization value weight.

As described in the steps S401-S405, the physical energy indexes are normalized to obtain the physical energy normalized values, and after normalization, the numerical range of the physical energy indexes is unified with the electrical performance indexes (normalized to [0,1 ]), so as to solve the fusion deviation caused by the dimension difference (for example, avoid that the "physical energy index 2.6" and the "electrical performance index 0.8" cannot be directly compared due to different units);

Secondly, the dynamic weight ensures that when the physical performance is imminent to fail, the speaking weight of the physical performance is increased in comprehensive evaluation, so that the risk that the physical performance is about to fail is avoided because the electrical qualification covers (if a certain chip is normal in electricity but the physical energy index is close to a threshold value, the physical defect is focused on);

secondly, carrying out normalization processing on the electrical performance indexes to obtain electrical performance normalization values, and enabling the trend of the electrical performance normalization values to be consistent with that of the physical performance normalization values (the greater the values are, the worse the performance) through reverse normalization, so as to ensure that the electrical performance normalization values and the physical performance normalization values are logically unified in weight distribution (the larger the numerical indexes represent the performance to be close to the defect threshold);

Then, the weight of the electrical performance normalized value is obtained according to the electrical performance normalized value, when the electrical performance is in imminent failure, the weight is automatically improved, and the core problem that the electrical function failure is ignored due to physical qualification (such as that a certain chip is physically stable but the time sequence is seriously delayed, and the electrical defect of the chip needs to be marked with emphasis);

Finally, calculating the comprehensive performance index of the chip particles according to the physical energy normalization value, the physical energy normalization value weight, the electrical performance normalization value and the electrical performance normalization value weight, wherein the defect risk of physical and electrical properties is fused through the comprehensive performance index, the higher the numerical value is, the obvious problem of the chip in at least one dimension (or both) is indicated, secondly, the comprehensive evaluation of defect leading is realized through the dynamic weight, the misjudgment of a single dimension is avoided, the defect type affecting the maximum can be highlighted, meanwhile, the dimension difference is eliminated through normalization, the defect risk of different performance dimensions is reflected through the dynamic weight, and the finally fused comprehensive performance index can comprehensively and objectively reflect the whole quality of the chip. The flow solves the problem of one-sided performance of the traditional independent evaluation, ensures that the synergistic effect of physical and electrical properties is incorporated into a defect judging system, and provides scientific quantitative basis for the automatic test of chip particles.

As shown in fig. 2, the present application further provides an automated testing system for chip particles, including:

In one embodiment, the second acquisition module includes:

As shown in fig. 3-7, an automated testing device for chip particles includes a control module and a driving module, wherein the control module is used for controlling parts on the automated testing device;

the driving module is used for driving parts on the automatic test equipment, and the steps of the method are realized when the computer program is executed.

Wherein, the control module mainly comprises the following:

The driving module mainly comprises a first board card 1, a second board card 2, a shell 3, a display 5, an electric control system 6, a host 7, a tray placement 9, a mouse 10, a power supply button 11 and a three-color lamp 12;

the driving module mainly comprises a testing system 4 and a pressing area 8;

The test system 4 is composed of a power supply and signal board card 44, a through board card 43, a back board card 42 and a tested chip loading platen card 41 in a butt joint mode, wherein the back board card 42, the through board card 43 and the power supply and signal board card 44 in the test equipment are fixedly arranged on a bracket, and the tested chip loading platen card 41 is a moving part.

The present application needs to realize the automatic docking and automatic separation of the first board card 1 and the second board card 2. The second board card 2 is fixed, and the first board card 1 moves along with the automation device.

The second board clamp 2 is provided with 1 coarse positioning pin and 6 fine positioning pins, and the corresponding second board clamp 2 is provided with 1 coarse positioning pin hole and 6 fine positioning pin holes. The second board card 2 is provided with a female connector, and the first board card 1 is provided with a male connector.

Four angles on the supporting plate 100 are provided with 4 guide blocks with slopes, and when the second board card 2 is manually placed on the supporting plate 100, the 4 guide blocks are initially guided. Meanwhile, 4 sensors are arranged on the supporting plate 100 and used for detecting whether the second board card 2 is flatly placed on the supporting plate 100 or not, so that certain angle tilting is avoided. The front end and the rear end of the whole butting device are provided with a pair of full gratings 20 for detecting whether foreign matters enter in the moving process of the second board card 2, and the full gratings are particularly used for safe avoidance.

The motion device is driven by a motor (other power sources such as a cylinder can be used). The servo motor 40 is connected with the screw rod module 50 through a coupler, and the upper end of the screw rod module is provided with a connecting plate 60 which is connected with the supporting plate 100 through a screw. Meanwhile, a sensor blocking piece 90 is arranged on the connecting plate 60 and used for detecting the moving position, and a pull block 80 and a push block 70 are arranged at the front end and the rear end of the supporting plate 100.

When the second board card 2 needs to be in butt joint with the first board card 1, the motor drives the screw rod to amplify power to drive the supporting plate, the pushing block at the tail end of the supporting plate pushes the tail end of the second board card 2 to move towards the direction close to the first board card 1, when the sensor receives a signal (or the encoder reaches a set value), the motor stops moving, the second board card 2 is in butt joint with the first board card 1, and similarly, when the second board card 2 needs to be separated from the first board card 1, the motor reversely runs to drive the pull block 80 to move backwards through the screw rod, the pull block 80 pushes the front end of the second board card 2 to move backwards until the sensor detects that the sensor is in place or the encoder reaches the set value, and the second board card 2 is separated from the first board card 1.

The specific test implementation steps are as follows:

The area button 9, the board 41 which is powered-fully filled with the tested particles is placed on the supporting plate 100, the pressing area 8 is enabled+board insert-the sensor 10 detects that the board 41 is placed in place, the grating 20 detects that the moving area is not blocked, the motor drives the board 41 to move towards the backboard 42, the sensor 90 detects that the motor encoder is in place, and the motor stops moving. boardinsert indicator lights are on, representing that the board is in place by butt joint, pressing the button of the area 8teststart, starting the test, flashing the green lamp of the tri-color lamp 10, ending the test, pressing the area 8enable+board remove, exiting the board 41, ending the whole test, and entering the next cycle;

the above is merely one embodiment of the apparatus of the present application and is not intended to be the only reference herein provided for understanding the operational and functional characteristics of the apparatus.

Those skilled in the art will appreciate that implementing all or part of the above-described methods may be accomplished by hardware associated with a computer program stored on a non-transitory computer readable storage medium, which when executed, may comprise the steps of the above-described method embodiments. Any reference to memory, storage, database, or other medium provided by the present application and used in embodiments may include non-volatile and/or volatile memory. The nonvolatile memory can include Read Only Memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual speed data rate SDRAM (SSRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (SYNCHLINK) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), among others.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, apparatus, article, or method that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, apparatus, article, or method. Without further limitation, an element defined by the phrase "comprising one does not exclude the presence of other like elements in a process, apparatus, article, or method that comprises the element.

The foregoing description is only of the preferred embodiments of the present invention and is not intended to limit the scope of the invention, and all equivalent structures or equivalent processes using the descriptions and drawings of the present invention or directly or indirectly applied to other related technical fields are included in the scope of the invention.

Claims

1. An automated testing method of chip particles, applied to automated testing equipment, is characterized by comprising the following steps:

2. The automated testing method of chip particles of claim 1, wherein the step of obtaining an installation fit index based on the correlation data and the contact characteristic parameter comprises:

3. The automated testing method of chip particles according to claim 1, wherein the steps of obtaining the physical distribution parameter and the electrical characteristic parameter of the chip particles, and obtaining the electrical response characteristic according to the electrical characteristic parameter, wherein the electrical response characteristic includes a time delay characteristic, a current ripple characteristic, and a power consumption fluctuation characteristic, include:

Obtaining a jitter standard deviation according to the clock jitter sequence;

4. The automated testing method of chip particles of claim 1, wherein the step of obtaining an electrical performance index from the timing delay characteristic, the current ripple characteristic, and the power consumption fluctuation characteristic comprises:

5. The automated testing method of chip particles according to claim 1, wherein the step of acquiring a surface temperature distribution field and a surface humidity distribution field of the chip particles according to the physical distribution parameters and acquiring physical energy indexes according to the surface temperature distribution field and the surface humidity distribution field comprises:

6. The automated testing method of chip particles according to claim 1, wherein the step of obtaining a chip particle integrated performance index from the physical performance index and the electrical performance index comprises:

7. An automated testing system for chip particles, comprising:

8. The automated testing system of claim 7, wherein the second acquisition module comprises:

9. The automatic test equipment for the chip particles comprises a control module and a driving module, and is characterized in that the control module is used for controlling parts on the automatic test equipment;

And the driving module is used for driving the parts on the automatic test equipment.

10. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of the method of any of claims 1 to 6.