CN120417435A - NMOS device structure and method for forming NMOS device structure - Google Patents

Abstract

The NMOS device structure comprises an SOI substrate, a first isolation structure, a grid structure and a second isolation structure, wherein the SOI substrate comprises a top silicon layer, a source region, a drain region and a body contact region are distributed in the top silicon layer, the drain region is adjacent to the source region, the body contact region is adjacent to the source region, the drain region and the body contact region are respectively located on different sides of the source region, the first isolation structure is located in the top silicon layer between the adjacent source region and the body contact region, the surface of the first isolation structure is flush with the surface of the top silicon layer, the first isolation structure separates the adjacent source region and the body contact region, the height of the first isolation structure is smaller than the thickness of the top silicon layer, the grid structure is located on the surface of the top silicon layer, and the source region and the drain region are respectively located on two sides of the grid structure. The invention can reduce parasitic devices, improve the inhibition effect of floating body effect and improve the integration level of devices.

Description

NMOS device structure and forming method thereof

Technical Field

The present invention relates to the field of semiconductors, and in particular, to an NMOS device structure and a method for forming the NMOS device structure.

Background

Compared with bulk silicon devices, PD-SOI devices (partially depleted SOI devices) manufactured by SOI substrates are widely applied to the fields of radio frequency, MEMS and the like due to excellent performances such as good device isolation, no latch-up effect, reduced coupling effect between active and passive devices and substrates and the like.

However KINKEFFECT (kink effect) caused by the floating body effect of PD-SOI devices is detrimental in analog circuits. To suppress the floating body effect, the body is usually connected to a fixed potential, thereby controlling the change in the body potential, in a manner known as body contact.

As shown in fig. 1 and 2, the conventional T-type gate structure body contacts, p+ is implanted from the top partial region of the T-type gate 10 to form a p+ implantation region 20, the p+ implantation region 20 is connected with a P-type body region 30 under the T-type gate 10, and when the MOS device is in operation, hole carriers accumulated in the P-type body region 30 are discharged through the p+ implantation region 20, so as to achieve the purpose of reducing the body region potential. However, the additional T-gate extension has a large parasitic capacitance and parasitic resistance between the underlying oxide and the top silicon layer, resulting in device performance delay and reduced circuit performance.

Disclosure of Invention

The invention solves the technical problem of providing an NMOS device structure and a method for forming the NMOS device structure so as to reduce parasitic devices, improve the inhibition effect of floating body effect and improve the integration level of devices.

In order to solve the technical problems, the technical scheme of the invention provides an NMOS device structure, which comprises an SOI substrate, a first isolation structure, a grid structure and a second isolation structure, wherein the SOI substrate comprises a top silicon layer, a source region, a drain region and a body contact region are distributed in the top silicon layer, the drain region is adjacent to the source region, the body contact region is adjacent to the source region, the drain region and the body contact region are respectively located on different sides of the source region, the first isolation structure is located in the top silicon layer between the adjacent source region and the body contact region, the surface of the first isolation structure is flush with the surface of the top silicon layer, the first isolation structure separates the adjacent source region and the body contact region, the height of the first isolation structure is smaller than the thickness of the top silicon layer, the grid structure is located on the surface of the top silicon layer, and the source region and the drain region are respectively located on two sides of the grid structure.

Optionally, the SOI substrate further comprises a bottom silicon layer and an SOI buried oxide layer positioned between the top silicon layer and the bottom silicon layer, the NMOS device structure further comprises a rear buried oxide layer positioned in the top silicon layer, a first interval is arranged between the rear buried oxide layer and the SOI buried oxide layer, and the width of the rear buried oxide layer is larger than that of the first isolation structure, so that the first isolation structure is positioned on the top surface of the rear buried oxide layer.

Optionally, a second isolation structure penetrating through the top silicon layer is further included, wherein the second isolation structure surrounds the source region, the drain region and the body contact region.

Optionally, the source region and the drain region are arranged along a first direction, the body contact region includes a first type body contact region, the first type body contact region and the source region are arranged along a second direction, the first isolation structure includes a first type first isolation structure located between the source region and the first type body contact region, the first type first isolation structure is flush with or exceeds a boundary of the source region in the first direction so as to separate the source region and an adjacent first type body contact region, and the second direction is perpendicular to the first direction.

Optionally, the first type body contact region is further adjacent to the drain region, and the first type first isolation structure is flush with or exceeds the drain region in a first direction.

Optionally, the gate structure includes a first part gate and a second part gate connected to each other and forming an "L" structure, where the first part gate extends along the first direction, the second part gate extends along the second direction, the source region and the drain region are located on two sides of the first part gate, the second part gate is located on a first type of first isolation structure surface adjacent to the drain region, and the second part gate exceeds a boundary of the drain region in the first direction.

Optionally, the number of the first type body contact regions is 2, and along the second direction, the first type body contact regions are respectively located at two sides of the source region.

Optionally, the body contact region includes a second type body contact region, the source region and the drain region are sequentially arranged along a first direction, the first isolation structure includes a second type first isolation structure located between the source region and the second type body contact region, and the second type first isolation structure is flush with or exceeds a boundary of the source region in the second direction so as to separate the source region from an adjacent second type body contact region.

Correspondingly, the technical scheme of the invention also provides a method for forming the NMOS device structure, which comprises the steps of providing an SOI substrate, forming a first isolation structure in the top silicon layer, wherein the surface of the first isolation structure is flush with the surface of the top silicon layer, the height of the first isolation structure is smaller than the thickness of the top silicon layer, after the first isolation structure is formed, forming a source region, a drain region and a body contact region in the SOI substrate, wherein the drain region is adjacent to the source region, the body contact region is adjacent to the source region, the drain region is respectively located on different sides of the source region, the first isolation structure is located between the adjacent source region and the body contact region, the first isolation structure is used for isolating the adjacent source region and the body contact region, and after the source region, the drain region and the body contact region are formed, a grid structure is formed on the surface of the top silicon layer, and the source region and the drain region are respectively located on two sides of the grid structure.

Optionally, the SOI substrate further comprises a bottom silicon layer, and an SOI buried oxide layer located between the top silicon layer and the bottom silicon layer; the method for forming the first isolation structure comprises the steps of forming a patterned first mask structure on the top silicon layer, carrying out ion implantation on the top silicon layer by taking the first mask structure as a mask, carrying out an annealing step after carrying out ion implantation on the top silicon layer, forming a rear buried oxide layer in the top silicon layer, wherein a first interval is formed between the rear buried oxide layer and the SOI buried oxide layer, a second interval is formed between the rear buried oxide layer and the surface of the top silicon layer, forming a patterned second mask structure on the top silicon layer after forming the rear buried oxide layer, etching the top silicon layer until the top surface of the rear buried oxide layer is exposed by taking the second mask structure as a mask, forming a first isolation groove in the top silicon layer, forming the first isolation structure in the first isolation groove, etching the top silicon layer until the top surface of the first isolation groove is exposed by taking the second mask structure as a mask, simultaneously etching the top silicon layer until the top surface of the first isolation groove is exposed by taking the second mask structure as a mask, forming the second isolation groove, and forming a second isolation groove around the top surface of the SOI device structure and the second isolation structure. Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:

according to the NMOS device structure and the forming method of the NMOS device structure, the drain region and the body contact region are respectively located at different sides of the source region, the first isolation structure is located in the top silicon layer between the adjacent source region and the body contact region, the surface of the first isolation structure is flush with the surface of the top silicon layer, the first isolation structure separates the adjacent source region and the body contact region, and the height of the first isolation structure is smaller than the thickness of the top silicon layer, so that on one hand, the first isolation structure separates the adjacent source region and the body contact region, and on the other hand, a sufficient channel is provided for leading out holes between the source region and the body contact region below the first isolation structure, and therefore a good floating body effect inhibition effect can be achieved. On the basis, the floating body effect is restrained by adopting the structure, so that the generation of parasitic devices is reduced and even avoided while the floating body effect is restrained, and especially compared with the structure of the traditional T-shaped grid, the NMOS device structure provided by the technical scheme greatly reduces and even avoids parasitic capacitance and parasitic resistance formed between the grid and top silicon, parasitic MOS tubes formed by the T-shaped grid, an active region and an oxide layer between the T-shaped grid and the active region, parasitic diodes and other parasitic devices existing in the T-shaped grid (the T-shaped grid is subjected to the ion implantation with the reverse direction from top to bottom). Therefore, not only the inhibition effect of the floating body effect is improved, but also the device performance is greatly improved due to the reduction of parasitic devices. In addition, compared with a T-shaped grid needing to be subjected to inversion (N-type and P-type) ion implantation, the first isolation structure is smaller in size, and therefore the integration level is further improved.

Drawings

FIG. 1 is a schematic diagram of a PD-SOI device;

FIG. 2 is a schematic cross-sectional view of FIG. 1 along the direction A1-A2;

fig. 3 to 13 are schematic structural diagrams illustrating steps in a method for forming an NMOS device structure according to an embodiment of the present invention;

Fig. 14 is a schematic top view of an NMOS device structure according to another embodiment of the present invention;

fig. 15 is a schematic top view of an NMOS device structure according to yet another embodiment of the present invention.

The reference numerals:

100-SOI substrate, 101-bottom silicon layer, 102-buried oxide layer, 103-top silicon layer, 104-metal silicide layer, 110-oxidation protection layer, 120-first mask structure, 130-post buried oxide layer, 140-second mask structure, 141-hard mask layer, 142-second photoresist layer, 150-first isolation groove, 151-first isolation structure, 1511-first isolation structure, 1512-second first isolation structure, 160-second isolation groove, 161-second isolation structure, 170, 270-gate structure, 271-first part gate, 272-second part gate, 181-first conductive structure, 182-second conductive structure, 183-third conductive structure, 184-fourth conductive structure, S-source region, D-drain region, B-body contact region, B1-first body contact region, B2-second body contact region, X-first direction, Y-second direction.

Detailed Description

As described in the background art, in the existing PD-SOI device structure, there is a large parasitic capacitance and parasitic resistance between the bulk contact and the bottom silicon of the SOI substrate, which causes delay of the circuit device and degradation of RF performance.

In order to solve the technical problems, the technical scheme of the invention provides an NMOS device structure and a forming method thereof, wherein a drain region and a body contact region are adjacent to a source region, the drain region and the body contact region are respectively positioned at different sides of the source region, a grid structure is positioned on the surface of a top silicon layer, the source region and the drain region are respectively positioned on the two sides of the grid structure, a first isolation structure is arranged in the top silicon layer between the adjacent source region and the body contact region, the surface of the first isolation structure is flush with the surface of the top silicon layer and separates the adjacent source region and the body contact region, and the height of the first isolation structure is smaller than the thickness of the top silicon layer, so that parasitic devices are reduced, the inhibition effect of floating body effect is improved, and the device integration level is improved.

In order to make the above objects, features and advantages of the present invention more comprehensible, the following description of the embodiments of the present invention will be given in connection with the accompanying drawings, and it is apparent that the described embodiments are only some embodiments but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

The terms "first," "second," "third," "fourth" and the like in the description and in the claims and drawings, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus. Furthermore, directional terms, such as above, below, upper, lower, upward, downward, left, right, etc., are used with respect to the exemplary embodiments as they are shown in the drawings, upward or upward toward the top of the corresponding drawing, downward or downward toward the bottom of the corresponding drawing.

Fig. 3 to 13 are schematic structural diagrams illustrating steps in a method for forming an NMOS device structure according to an embodiment of the present invention.

Referring to fig. 3, an SOI substrate 100 is provided.

Wherein the SOI substrate 100 may include a bottom silicon layer 101, a buried oxide layer 102, and a top silicon layer 103 stacked in this order.

Next, a first isolation structure 151 is formed within the top silicon layer 103. Specific steps of forming the first isolation structure 151 are described in detail below with reference to fig. 4 to 9.

Referring to fig. 4, an oxidation protection layer 110 is formed on the surface of the SOI substrate 100.

In the present embodiment, the material of the oxidation protection layer 110 may be silicon oxide.

In other embodiments, the oxidation protection layer 110 may not be formed.

With continued reference to fig. 4, a patterned first mask structure 120 is formed on the surface of the oxidation protection layer 110.

In this embodiment, the material of the first mask structure 120 may include photoresist.

Specifically, the method for forming the first Mask structure 120 includes forming a photoresist material layer of the first Mask structure 120 on the surface of the oxidation protection layer 110, and performing illumination and development on the photoresist material layer of the first Mask structure 120 through a photomask (Photo Mask) to form a patterned first Mask structure 120.

Since the oxidation protection layer 110 is formed on the surface of the SOI substrate 100 before the first mask structure 120 is formed, the oxidation protection layer 110 serves as a protection layer for the surface of the SOI substrate 100 during the formation of the first mask structure 120 on the one hand, and the oxidation protection layer 110 serves as a barrier layer for ion implantation during the subsequent formation of the post-buried oxide layer 130 on the other hand, so as to precisely control the depth of ion implantation, thereby forming the post-buried oxide layer 130 at a desired depth.

Referring to fig. 5, the top silicon layer 103 is ion-implanted using the first mask structure 120 as a mask.

Specifically, in the process of implanting ions into the top silicon layer 103, the implanted ions are oxygen ions, and the implantation depth of the oxygen ions is controlled by adjusting the thickness of the oxidation protection layer 110 and the ion implantation energy, and the ion concentration of the implanted ions is controlled by adjusting the ion implantation dose.

Note that since the post-buried oxide layer 130 to be formed later needs to have a distance from both the surface of the top silicon layer 103 and the SOI buried oxide layer 102, the oxygen ions implanted therein need to have a predetermined depth in the top silicon layer 103 and a distance from the surface of the SOI buried oxide layer 102. In the actual manufacturing process, the thickness of the oxidation protection layer 110 and the implantation energy of the ion implantation process can be controlled, so as to achieve the purpose of ensuring that the implanted oxygen ions are required to have a preset depth in the top silicon layer 103 and a distance from the surface of the SOI buried oxide layer 102.

Referring to fig. 6, after ion implantation is performed on the top silicon layer 103, an annealing step is performed to form a post-buried oxide layer 130 in the top silicon layer 103.

By the annealing step, oxygen ions implanted into the top silicon layer 103 can react with silicon to form the post-buried oxide layer 130. Specifically, the material of the post-buried oxide layer 130 may include silicon oxide.

In this embodiment, there is a spacing of greater than 0nm between the surface of the post buried oxide layer 130 and the top silicon layer 103 and the SOI buried oxide layer 102. The distance between the post-buried oxide layer 130 and the SOI buried oxide layer 102 is a first distance, and the distance between the post-buried oxide layer 130 and the surface of the top silicon layer 103 is a second distance.

Since the rear buried oxide layer 130 having a certain distance from the surface of the top silicon layer 103 and the SOI buried oxide layer 102 is formed in the top silicon layer 103, that is, the rear buried oxide layer 130 has a certain depth in the top silicon layer 103 and a certain distance from the SOI buried oxide layer 102 at the same time, when the top silicon layer 103 is etched by blocking at the rear buried oxide layer 130, a groove stopping at the rear buried oxide layer 130 can be formed, so that the top silicon layer 103 can be etched later by using the same photomask to simultaneously form the first isolation groove 150 and other STI isolation grooves (for example, the second isolation groove 160) having different depths, thereby simplifying the formation process of the first isolation structure 151 and realizing the preparation of the NMOS device structure by simple process steps.

In one embodiment, the first pitch is greater than 1% of the thickness of the top silicon layer 103.

In one embodiment, the annealing temperature of the process of the annealing step is greater than 1000 ℃ and the annealing time period is greater than 0.5 hours.

In this embodiment, the first mask structure 120 is removed and a cleaning step is performed before the annealing step is performed. The process of removing the first mask structure 120 may include an ashing process, etc.

Next, referring to fig. 7, a patterned second mask structure 140 is formed on the top silicon layer 103.

In this embodiment, the second mask structure 140 may include a hard mask layer 141 and a second photoresist layer 142 on a surface of the hard mask layer 141. Because the second Mask structure 140 is a composite layer comprising the Hard Mask layer 141 (Hard Mask) and the second photoresist layer 142, the accuracy of the subsequent pattern transfer is improved, so that the first isolation groove 150 and the second isolation groove 160 with more precise dimensions and better morphology can be formed subsequently.

The hard mask layer 141 may be made of a material having a high hardness such as silicon nitride.

Specifically, the method for forming the second mask structure 140 may include forming a hard mask material layer (not shown) on the surface of the oxidation protection layer 110, forming an initial second photoresist layer (not shown) on the surface of the hard mask material layer, performing illumination and development on the initial second photoresist layer through a photomask to form a patterned second photoresist layer 142, etching the hard mask material layer until the surface of the oxidation protection layer 110 is exposed by using the second photoresist layer 142 as a mask, and transferring the pattern of the second photoresist layer 142 to the hard mask material layer to form the hard mask layer 141.

In other embodiments, the hard mask layer 141 may not be formed.

In this embodiment, since the oxidation protection layer 110 is formed on the surface of the top silicon layer 103 before the patterned second mask structure 140 is formed on the top silicon layer 103, the oxidation protection layer 110 can also play a role in protecting the surface of the SOI substrate 100 when etching the hard mask material layer.

Referring to fig. 8, with the second mask structure 140 as a mask, the top silicon layer 103 is etched until the top surface of the post-buried oxide layer 130 is exposed, and a first isolation trench 150 is formed in the top silicon layer 103.

The first isolation groove 150 is used to provide a space for forming the first isolation structure 151 later.

In the present embodiment, the trench width W2 (as shown in fig. 8) of the first isolation trench 150 is smaller than the width W1 (as shown in fig. 8) of the post buried oxide layer 130, so as to ensure that the first isolation structure 151 formed in the first isolation trench 150 can be accurately located on the top surface of the post buried oxide layer 130. That is, the projection of the first isolation structure 151 on the surface of the SOI substrate 100 is located within the projection of the post-buried oxide layer 130 on the surface of the SOI substrate 100.

In this embodiment, the second mask structure 140 is used as a mask while the first isolation trench 150 is formed, and the top silicon layer 103 except above the buried oxide layer 130 is etched until the top surface of the SOI buried oxide layer 102 is exposed, so as to form the second isolation trench 160.

Wherein, the second isolation groove 160 is used for providing a space for forming the second isolation structure 161 later.

Thus, the first isolation groove 150 and the second isolation groove 160 with different depths can be formed by using the same mask in the same etching process through the post-buried oxide layer 130.

In one embodiment, the process of etching the top silicon layer 103 may include at least one of a dry etching process and a wet etching process using the second mask structure 140 as a mask.

In the present embodiment, after the first and second isolation grooves 150 and 160 are formed, the second photoresist layer 142 is removed.

Next, referring to fig. 9, a first isolation structure 151 is formed in the first isolation groove 150.

Wherein, the height H1 of the first isolation structure 151 is smaller than the thickness H2 of the top silicon layer 103.

In this embodiment, the first isolation structure 151 is formed, and the second isolation structure 161 is formed in the second isolation groove 160, so that the manufacturing process of the NMOS device structure is further simplified.

In this embodiment, the bottom of the second isolation structure 161 is connected to the SOI buried oxide layer 102, and the second isolation structure 161 surrounds the source region S, the drain region D, and the body contact region B. That is, the second isolation structure 161 is used for isolation between devices.

Specifically, the first isolation structure 151 is formed in the first isolation groove 150, and the method of forming the second isolation structure 161 in the second isolation groove 160 may include depositing an isolation material layer (not shown) in the first isolation groove 150, in the second isolation groove 160, and on the surface of the hard mask layer 141, the isolation material layer having a surface higher than the surface of the hard mask layer 141, and polishing the isolation material layer, the hard mask layer 141, and the oxidation protection layer 110 using a Chemical Mechanical Polishing (CMP) process until the surface of the SOI substrate 100 is exposed.

The forming process of the isolation material layer may be a chemical deposition process (CVD) or a physical deposition Process (PVD).

In other embodiments, instead of forming the post-buried oxide layer 130, the first isolation groove 150 and the second isolation groove 160 may be formed, and the first isolation structure 151 and the second isolation structure 161 may be formed, respectively.

In addition, the materials of the first isolation structure 151 and the second isolation structure 161 are both dielectric materials.

Next, referring to fig. 10 to 13, fig. 10 is a schematic top view of fig. 11, 12 and 13, fig. 11 is a schematic cross-sectional structure along a direction A1-A2 in fig. 10, fig. 12 is a schematic cross-sectional structure along a direction A3-A4 in fig. 10, and fig. 3 to 9 are all identical to the view direction of fig. 12, fig. 13 is a schematic cross-sectional structure along a direction A5-A6 in fig. 10, and source region S, drain region D and body contact region B are formed in SOI substrate 100, respectively.

Wherein the drain region D is adjacent to the source region S, the body contact region B is adjacent to the source region S, and the drain region D and the body contact region B are respectively located at different sides of the source region S. In addition, the first isolation structure 151 is located between the adjacent source region S and the body contact region B, and the surface of the first isolation structure 151 is flush with the surface of the top silicon layer 103 and separates the adjacent source region S and the body contact region B.

Specifically, the projected boundary of the first isolation structure 151 on the surface of the top silicon layer 103 exceeds the boundary of the source region S.

In addition, the source region S and the drain region D are heavily doped with N type, and the body contact region B is heavily doped with P type.

With continued reference to fig. 10 to 13, after forming the source region S, the drain region D, and the body contact region B, a gate structure 170 is formed on the surface of the top silicon layer 103, and the source region S and the drain region D are respectively located at both sides of the gate structure 170.

Further, the gate structure 170 may include a gate oxide layer (not shown) and a gate electrode (not shown) on a surface of the gate oxide layer.

In this embodiment, the drain region D and the body contact region B are located on different sides of the source region S respectively, the first isolation structure 151 is located in the top silicon layer 103 between the adjacent source region S and the body contact region B, the surface of the first isolation structure 151 is flush with the surface of the top silicon layer 103, the first isolation structure 151 separates the adjacent source region S and the body contact region B, and the height of the first isolation structure 151 is smaller than the thickness of the top silicon layer 103, so that, on one hand, the first isolation structure 151 separates the adjacent source region S and the body contact region B, and on the other hand, sufficient channels are provided for guiding out holes between the source region S and the body contact region B under the first isolation structure 151, so that a good floating body effect suppression effect can be achieved. On the basis, the floating body effect is restrained by adopting the structure, so that the generation of parasitic devices is reduced and even avoided while the floating body effect is restrained, and especially compared with the structure of the traditional T-shaped grid, the NMOS device structure of the embodiment greatly reduces and even avoids parasitic capacitance and parasitic resistance formed between the grid and the top silicon, parasitic MOS tubes formed by the T-shaped grid, an active region and an oxide layer between the T-shaped grid and the active region, parasitic diodes and other parasitic devices existing in the T-shaped grid (the T-shaped grid is subjected to the ion implantation with the reverse direction from top to bottom). Therefore, not only the inhibition effect of the floating body effect is improved, but also the device performance is greatly improved due to the reduction of parasitic devices.

Furthermore, since the size of the first isolation structure 151 (i.e., the groove width W2 of the first isolation groove 150) is defined by the photolithography step, the occupation of the area in the second direction Y is reduced, thereby also contributing to the improvement of the integration level, compared to the T portion of the T-type gate requiring the inversion (N-type and P-type) ion implantation.

With continued reference to fig. 10-13, after the gate structure 170 is formed, a plurality of first conductive structures 181, a plurality of second conductive structures 182, a plurality of third conductive structures 183, and a plurality of fourth conductive structures 184 are formed.

Wherein the first conductive structure 181 is located on the surface of the body contact region B, the second conductive structure 182 is located on the surface of the source region S, the third conductive structure 183 is located on the surface of the drain region D, and the fourth conductive structure 184 is located on the surface of the gate structure 170.

In one embodiment, before forming the first conductive structure 181, the second conductive structure 182, the third conductive structure 183, and the fourth conductive structure 184, a metal silicide layer 104 is formed on a surface of a portion of the source region S, a surface of a portion of the drain region D, a top surface of the gate structure 170, and a surface of a portion of the body contact region B, so that bottoms of the first conductive structure 181, the second conductive structure 182, the third conductive structure 183, and the fourth conductive structure 184 contact the metal silicide layer 104, thereby further reducing resistance and improving electrical characteristics. The material of the metal silicide layer is, for example, nickel silicide (NiSi), coSi, or the like.

Accordingly, an embodiment of the present invention further provides an NMOS device structure formed by the above method, and please refer to fig. 10 to 13, which may include an SOI substrate 100, a first isolation structure 151 and a gate structure 170.

Wherein the SOI substrate 100 may include a bottom silicon layer 101, a buried oxide layer 102, and a top silicon layer 103 stacked in this order.

In the present embodiment, the active region S, the drain region D, and the body contact region B are distributed in the top silicon layer 103. The source region S and the drain region D are heavily doped with N type, and the body contact region B is heavily doped with P type. Wherein the drain region D is adjacent to the source region S, the body contact region B is adjacent to the source region S, and the drain region D and the body contact region B are respectively located at different sides of the source region S.

In the present embodiment, the first isolation structure 151 is located in the top silicon layer 103 between the adjacent source region S and the body contact region B, the surface of the first isolation structure 151 is flush with the surface of the top silicon layer 103, and the first isolation structure 151 separates the adjacent source region S from the body contact region B, and furthermore, the height H1 of the first isolation structure 151 is smaller than the thickness H2 of the top silicon layer 103.

Specifically, the projected boundary of the first isolation structure 151 on the surface of the top silicon layer 103 exceeds the boundary of the source region S.

In the present embodiment, the gate structure 170 is located on the surface of the top silicon layer 103, and the source region S and the drain region D are located on both sides of the gate structure 170, respectively.

In this embodiment, the drain region D and the body contact region B are located on different sides of the source region S respectively, the first isolation structure 151 is located in the top silicon layer 103 between the adjacent source region S and the body contact region B, the surface of the first isolation structure 151 is flush with the surface of the top silicon layer 103, the first isolation structure 151 separates the adjacent source region S and the body contact region B, and the height of the first isolation structure 151 is smaller than the thickness of the top silicon layer 103, so that, on one hand, the first isolation structure 151 separates the adjacent source region S and the body contact region B, and on the other hand, sufficient channels are provided for guiding out holes between the source region S and the body contact region B under the first isolation structure 151, so that a good floating body effect suppression effect can be achieved. On the basis, the floating body effect is restrained by adopting the structure, so that the generation of parasitic devices is reduced and even avoided while the floating body effect is restrained, and especially compared with the structure of the traditional T-shaped grid, the NMOS device structure of the embodiment greatly reduces and even avoids parasitic capacitance and parasitic resistance formed between the grid and the top silicon, parasitic MOS tubes formed by the T-shaped grid, an active region and an oxide layer between the T-shaped grid and the active region, parasitic diodes and other parasitic devices existing in the T-shaped grid (the T-shaped grid is subjected to the ion implantation with the reverse direction from top to bottom). Therefore, not only the inhibition effect of the floating body effect is improved, but also the device performance is greatly improved due to the reduction of parasitic devices. In addition, the first isolation structure 151 is smaller in size than a T-type gate requiring an inversion (N-type and P-type) ion implantation, and thus, it is also advantageous to improve the integration.

In this embodiment, the NMOS device structure may further include a post buried oxide layer 130.

Wherein the post buried oxide layer 130 is located within the top silicon layer 103. The post buried oxide layer 130 has a first spacing from the SOI buried oxide layer 102. The post buried oxide layer 130 has a second spacing from the surface of the top silicon layer 103. The first pitch and the second pitch are both greater than 0 nanometers.

In one embodiment, the first spacing is greater than 1% of the thickness of the top silicon layer 103.

In addition, the width W1 of the post buried oxide layer 130 is greater than the width of the first isolation structure 151 (i.e., the groove width W2 of the first isolation groove 150 shown in fig. 8) to ensure that the first isolation structure 151 can be located on the top surface of the post buried oxide layer 130.

In this embodiment, the NMOS device structure may further include a second isolation structure 161.

In this embodiment, the second isolation structure 161 penetrates the top silicon layer 103 and the bottom is connected to the SOI buried oxide layer 102, and in addition, the second isolation structure 161 surrounds the source region S, the drain region D, and the body contact region B. I.e. the second isolation structure 161 is used for isolation between devices.

In this embodiment, the NMOS device structure may further include a number of first conductive structures 181, a number of second conductive structures 182, a number of third conductive structures 183, and a number of fourth conductive structures 184.

Wherein the first conductive structure 181 is located on the surface of the body contact region B, the second conductive structure 182 is located on the surface of the source region S, the third conductive structure 183 is located on the surface of the drain region D, and the fourth conductive structure 184 is located on the surface of the gate structure 170.

In one embodiment, a portion of the source region S, a portion of the drain region D, a portion of the gate structure 170 surface, and a portion of the body contact region B surface have a metal silicide layer 104 such that bottoms of the first conductive structure 181, the second conductive structure 182, the third conductive structure 183, and the fourth conductive structure 184 contact the metal silicide layer 104.

In the present embodiment, the source region S and the drain region D are arranged along the first direction X. Also, for ease of understanding, the body contact region B and the first isolation structure 151 located at different sides of the source region S are divided below to be specifically described.

In this embodiment, the body contact region B may include a first type body contact region B1, and the first type body contact region B1 and the source region S are arranged along the second direction Y. Accordingly, the first isolation structure 151 may include a first type first isolation structure 1511, the first type first isolation structure 1511 is located between the source region S and the first type body contact region B1, and the first type first isolation structure 1511 exceeds a boundary of the source region S in the first direction X. Wherein the second direction Y is perpendicular to the first direction X.

In the present embodiment, since the first-type first isolation structure 1511 exceeds the boundary of the source region S in the first direction X, the separation between the source region S and the first-type body contact region B1 is further ensured.

In other embodiments, the first type first isolation structure 1511 is flush with the boundary of the source region S in the first direction X.

Further, the first-type body contact region B1 is also adjacent to the drain region D. Therefore, the area of the body contact region B is enlarged, so that, on one hand, the first conductive structures 181 are more easily aligned to the body contact region B, and the reliability of the device is improved, and on the other hand, positions are provided for forming a greater number of the first conductive structures 181, which is advantageous for improving the electrical performance of the device.

Accordingly, the first type first isolation structures 1511 are also flush with or beyond the drain region D in the first direction X to separate adjacent first type body contact regions B1 from the drain region D. Thereby further reducing parasitic devices.

In the present embodiment, the number of the first-type body contact regions B1 is 1.

In this embodiment, the gate structure 170 may include a gate oxide layer (not shown) and a gate electrode (not shown) on a surface of the gate oxide layer. Wherein the material of the gate electrode comprises N-type heavily doped polysilicon.

In this embodiment, the gate structure 170 is a linear structure extending along the second direction Y. Therefore, no additional T-extension is provided, thereby greatly reducing parasitic capacitance and enhancing the suppression effect of the floating body effect compared to conventional T-gate structure contacts.

Further, one end of the gate structure 170 extends to the surface of the first type first isolation structure 1511, the other end of the gate structure 170 exceeds the boundary of the other side of the source region S and the drain region D opposite to the first type first isolation structure 1511, and the fourth conductive structure 184 is located on the other end surface of the gate structure 170.

In another embodiment, referring to fig. 14, the number of the first type body contact regions B1 and the first type first isolation structures 1511 is 2, and the gate structure 270 is used to replace the gate structure 170.

Specifically, the source region S along the second direction Y has a first type body contact region B1 on both sides thereof, and a first type first isolation structure 1511 is provided between each side of the source region S along the second direction Y and an adjacent first type body contact region B1. Therefore, the area of the body contact region B is further enlarged while the parasitic devices are reduced and the inhibition effect of the floating body effect is improved, so that on one hand, the first conductive structures 181 are more easily aligned to the body contact region B, the reliability of the device is improved, and on the other hand, positions are provided for forming more first conductive structures 181, and the electrical performance of the device is improved.

In addition, the gate structure 270 may include a first partial gate 271 and a second partial gate 272 connected and constituting an "L" type structure. The first partial gate 271 extends in the first direction X, and the second partial gate 272 extends in the second direction Y.

Wherein the source region S and the drain region D are located at both sides of the first partial gate 271, the second partial gate 272 is located at a surface of the first type first isolation structure 1511 adjacent to the drain region D, the second partial gate 272 exceeds a boundary of the drain region D in the first direction X, and the fourth conductive structure 184 is located at a surface of the second partial gate 272 exceeding the boundary of the drain region D. Thus, on the one hand, parasitic devices between the second partial gate 272 and the substrate are avoided by the first type of first isolation structure 1511 under the second partial gate 272, and on the other hand, flexibility in the location of the fourth conductive structure 184 is increased by the different gate structure 270 shape.

In yet another embodiment, referring to fig. 15, compared to the embodiment shown in fig. 14, the body contact region B further includes a second type body contact region B2, and the second type body contact region B2, the source region S, and the drain region D are sequentially arranged along the first direction X. Thus, the area of the body contact region B is further enlarged.

Accordingly, the first isolation structure 151 may further include a second type first isolation structure 1512, the second type first isolation structure 1512 being located between the source region S and the second type contact region B2, and the second type first isolation structure 1512 being flush with or beyond a boundary of the source region S in the second direction Y to separate the source region S from an adjacent second type contact region B2.

In one other embodiment, the body contact region B may also include only the second type body contact region B2. Accordingly, the first isolation structures 151 include only the second type of first isolation structures 1512. Therefore, the body contact area B is flexible in position, and the structural design of the device is facilitated.

For ease of understanding and explanation, fig. 10, 14 and 15 each show an n+ region (N-type heavily doped region) by a blue dotted line, a p+ region (P-type heavily doped region) by a red dotted line, and a position of the buried oxide layer 130 that is blocked by a black dotted line. In addition, the second isolation structure 161 and the metal silicide layer 104 are not illustrated in fig. 10, 14, and 15.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (10)

1. An NMOS device structure, comprising:

the SOI substrate comprises a top silicon layer, a source region, a drain region and a body contact region are distributed in the top silicon layer, the drain region is adjacent to the source region, the body contact region is adjacent to the source region, and the drain region and the body contact region are respectively located on different sides of the source region;

A first isolation structure located in the top silicon layer between adjacent source regions and body contact regions, wherein the surface of the first isolation structure is flush with the surface of the top silicon layer, the first isolation structure separates adjacent source regions from the body contact regions, and the height of the first isolation structure is smaller than the thickness of the top silicon layer;

and the grid structure is positioned on the surface of the top silicon layer, and the source region and the drain region are respectively positioned on two sides of the grid structure.

2. The NMOS device structure of claim 1 wherein said SOI substrate further comprises a bottom silicon layer, and an SOI buried oxide layer located between said top silicon layer and said bottom silicon layer;

the NMOS device structure further comprises a rear buried oxide layer, wherein the rear buried oxide layer is positioned in the top silicon layer, a first interval is reserved between the rear buried oxide layer and the SOI buried oxide layer, and the width of the rear buried oxide layer is larger than that of the first isolation structure, so that the first isolation structure is positioned on the top surface of the rear buried oxide layer.

3. The NMOS device structure of claim 1 further comprising a second isolation structure extending through the top silicon layer, the second isolation structure surrounding the source region, the drain region and the body contact region.

4. The NMOS device structure of claim 1, wherein said source region and said drain region are arranged in a first direction, said body contact region comprises a first type body contact region arranged in a second direction with said source region, said first isolation structure comprises a first type first isolation structure between said source region and said first type body contact region, said first type first isolation structure is flush with or beyond a boundary of said source region in a first direction to separate said source region from an adjacent first type body contact region, said second direction is perpendicular to said first direction.

5. The NMOS device structure of claim 4, wherein said first type body contact region is further adjacent to said drain region, said first type first isolation structure being flush with or beyond said drain region in a first direction.

6. The NMOS device structure of claim 5, wherein said gate structure comprises a first partial gate and a second partial gate connected and forming an "L" structure, said first partial gate extending in said first direction, said second partial gate extending in said second direction, said source region and said drain region being on opposite sides of said first partial gate, said second partial gate being on a first type of first isolation structure surface adjacent said drain region, and said second partial gate exceeding a boundary of said drain region in said first direction.

7. The NMOS device structure of claim 4, wherein said first type body contact regions are 2 in number, said first type body contact regions being located on opposite sides of said source region along said second direction.

8. The NMOS device structure of claim 1 or 4, wherein said body contact region comprises a second type body contact region, said source region, and said drain region being arranged in sequence along a first direction, said first isolation structure comprising a second type first isolation structure between said source region and said second type body contact region, said second type first isolation structure being flush with or beyond a boundary of said source region in a second direction to separate the source region from an adjacent second type body contact region.

9. The method for forming the NMOS device structure is characterized by comprising the following steps:

Providing an SOI substrate, wherein the SOI substrate comprises a top silicon layer;

forming a first isolation structure in the top silicon layer, wherein the surface of the first isolation structure is flush with the surface of the top silicon layer, and the height of the first isolation structure is smaller than the thickness of the top silicon layer;

after the first isolation structures are formed, a source region, a drain region and a body contact region are respectively formed in the SOI substrate, the drain region is adjacent to the source region, the body contact region is adjacent to the source region, the drain region and the body contact region are respectively located on different sides of the source region, the first isolation structures are located between the adjacent source region and the body contact region, and the first isolation structures separate the adjacent source region and the body contact region;

After the source region, the drain region and the body contact region are formed, a gate structure is formed on the surface of the top silicon layer, and the source region and the drain region are respectively located on two sides of the gate structure.

10. The method of forming an NMOS device structure of claim 9, wherein the SOI substrate further comprises a bottom silicon layer, and an SOI buried oxide layer between the top silicon layer and the bottom silicon layer;

The method for forming the first isolation structure comprises the steps of forming a patterned first mask structure on the top silicon layer, carrying out ion implantation on the top silicon layer by taking the first mask structure as a mask, carrying out an annealing step after carrying out ion implantation on the top silicon layer, forming a rear buried oxide layer in the top silicon layer, wherein a first interval is formed between the rear buried oxide layer and the SOI buried oxide layer, a second interval is formed between the rear buried oxide layer and the surface of the top silicon layer, forming a patterned second mask structure on the top silicon layer after forming the rear buried oxide layer, etching the top silicon layer until the top surface of the rear buried oxide layer is exposed by taking the second mask structure as a mask, forming a first isolation groove in the top silicon layer, and forming the first isolation structure in the first isolation groove;

The method for forming the NMOS device structure further comprises the steps of taking the second mask structure as a mask, etching the top silicon layer to form a first isolation groove, and etching the top silicon layer until the top surface of the SOI buried oxide layer is exposed to form a second isolation groove, and forming a second isolation structure in the second isolation groove, wherein the second isolation structure surrounds the source region, the drain region and the body contact region.