CN1202703A - Sensing Circuit for Electrically Erasable Programmable Memory - Google Patents
Sensing Circuit for Electrically Erasable Programmable Memory Download PDFInfo
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- CN1202703A CN1202703A CN 97112323 CN97112323A CN1202703A CN 1202703 A CN1202703 A CN 1202703A CN 97112323 CN97112323 CN 97112323 CN 97112323 A CN97112323 A CN 97112323A CN 1202703 A CN1202703 A CN 1202703A
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Abstract
A sensing circuit of an electrically erasable programmable memory senses information stored in the electrically erasable programmable memory in a current sensing manner. In the circuit structure of the invention, a certain current source generating circuit is provided to provide a certain current source, when the EEPROM unit outputs '0' potential, a load circuit induces a current which is the same as the constant current and is used as the current required for sensing the information of the '0' output of the unit, thereby greatly improving the speed of information reading.
Description
The present invention relates to a kind of sensing circuit of electric erasable programmable memory device,, be meant a kind of current sense formula electric erasable programmable memory device sensing circuit especially in order to the information that stores in the sensing electric erasable programmable memory device.
Electric erasable programmable memory device (to call EEPROM in the following text) is inner has only two kinds of potential states when making information stores, i.e. conducting and not conducting, and this information state can give sensing by outside sensing circuit.
Known EEPROM unit basic structure as shown in Figure 1, its EEPROM unit 1 mainly is made of a MOS switch 11 and an EEMOS storage unit 12.In this circuit, when conducting state, VD is output as electronegative potential, and its VD is output as unsettled (floating) when not on-state.And the information of EEPROM is looked electronegative potential for " 0 ", be " 1 " and look unsettled (floating), wherein whether the conducting of the EEMOS storage unit 12 of EEPROM is decided by the Vt voltage of EEMOS switch, when Vt is conducting state during greater than its grid voltage VG, when Vt then is not conducting (ending) during less than this grid voltage VG.Outside sensing circuit needs only the potential state of sensing VD, can learn the information state of this memory cell.
When reading information " 1 " and reach " 0 ", EEPROM unit each point potential state is as follows:
| Read mode | ????VG | ????VS | ????VD | ???? |
| 1 information | ????0V | ????0V | ????2V | ????5V |
| 0 information | ????0V | ????0V | ????0V | ????5V |
As previously mentioned, information state in the storer can be sensed by a sensing circuit, that is the purpose of sensing circuit is in order to differentiate eeprom memory " 0 " current potential and to be higher than the voltage of " 0 " current potential, it can correctly be read the information in the storer, and export a see-saw circuit to its signal amplification.
The sensing circuit of eeprom circuit commonly used as shown in Figure 2, it mainly includes a PMOS transistor 21, a nmos pass transistor 22, reaches phase inverter 23,24, wherein PMOS transistor 21 is as the circuit component that current potential is drawn high noble potential, the grid of nmos pass transistor 22 is controlled by a bias voltage signal CO, and its source electrode is connected to the information that EEPROM unit (as shown in Figure 1) is sent here, and phase inverter is for differentiating the element of " 0 " and " 1 " information.The current potential of PMOS transistor 21 and nmos pass transistor 22 intermediate node is to utilize voltage to carry out charge and discharge, to reach the information of resolution " 0 " and " 1 ".Because this EEOROM sensing circuit commonly used is to use the mode of the charge and discharge of voltage, so its speed is slower.
Therefore, in view of the shortcoming of common technology, the present invention's fundamental purpose provides the sensing circuit of a kind of improved EEPROM, and the speed that its execution is read is improved.
Another object of the present invention provides a kind of EEPROM sensing circuit of current sense formula, to improve the technology of conventional voltage sensing and detecting type.Because the sensing circuit working voltage came sensing in the past, when sensing " 0 ", the speed of discharge is slower, so the present invention, has used the EEPROM sensing circuit technology of current sense formula for the requirement of raising speed.
In the present invention, its resolution " 0 " is to use the sensing of electric current to finish with the information of " 1 ", rather than adopts voltage sensing formula circuit commonly used, and aspect velocity characteristic, the voltage sensing mode of normal book is a lot of soon.In circuit structure of the present invention, one group of constant current source is provided, when being " 0 " current potential, EEPROM can provide certain electric current, as the required electric current of information of sensing " 0 ".
Principle of the present invention can induce a current source identical with deciding electric current for using one group of current mirror circuit when EEPROM unit (Cell) exports " 0 " current potential, and its voltage can be descended fast, therefore can sense " 0 " current potential fast.
For finishing the foregoing invention purpose, electric erasable programmable memory device sensing circuit of the present invention has an electric current source generating circuit that produces a constant current source, as this sensing circuit required current source when " 0 " of sensing eeprom memory current potential is exported; One on-off circuit opens the beginning one and comes the Control current source generating circuit whether to produce a constant current source under the signal controlling; One load circuit, its signal input part are connected to the EEPROM unit and receive the output information of this EEPROM unit.Decide electric current when this electric current source generating circuit produces, and the eeprom memory unit is when sending " 0 " current potential, the electric current that the load circuit generation is identical with this constant current source; One see-saw circuit, the signal in order to the output terminal that amplifies load circuit is sent into includes a Sheffer stroke gate, and one of them input end is received and is opened the beginning control signal, and the other end is received the output terminal of load circuit; One negative circuit is connected with the output terminal of see-saw circuit, so that the information of being deposited in the output information of this see-saw circuit and the real EEPROM unit conforms to, information is correctly exported.
On-off circuit includes a PMOS transistor, and its source electrode connects noble potential, and its grid is connected to and opens the beginning control signal, opens beginning this transistorized action of control signal control by this.
The electric current source generating circuit includes the nmos pass transistor of a PMOS transistor and several polyphones, the transistorized source electrode of PMOS wherein connects noble potential, the drain electrode that drain electrode links to each other with grid and receives first nmos pass transistor in this polyphone nmos pass transistor, the grid of this first nmos pass transistor connects a bias voltage signal, by this bias voltage signal control, and all the other nmos pass transistor grids are connected to and open the beginning control signal, when opening the beginning control signal when being noble potential, this PMOS transistor and each nmos pass transistor constitute a series connection resistance loop, so that a constant current source to be provided.
Load circuit is made of a PMOS transistor and a nmos pass transistor, wherein this PMOS transistor source is connected to noble potential, its drain electrode is as the output terminal of this load circuit, its grid is received the PMOS transistor drain in the electric current source generating circuit, and constitutes a current mirror circuit structure with this PMOS transistor; Its nmos pass transistor source electrode is received the EEPROM unit, be used for receiving the information that this unit is sent here, its grid is received bias voltage signal, is controlled by this bias voltage input signal, maintains about about 2V so that the source electrode of this nmos pass transistor is received the voltage of EEPROM cell node.
Obviously, compare with the voltage sensing formula circuit of prior art, sensing circuit of the present invention can improve the information reading speed.
Below with conjunction with figs., circuit structure of the present invention and operating principle thereof are further described, wherein:
Fig. 1 is the basic circuit structure of the known EEPROM of expression unit;
Fig. 2 is the sensing circuit figure of the known EEPROM of expression;
Fig. 3 is an expression circuit function block scheme of the present invention;
Fig. 4 is the preferred embodiment circuit diagram of the sensing circuit of expression EEPROM of the present invention;
Fig. 5 is that each interdependent node is being read " 0 " sequential chart when reaching " 1 " in the presentation graphs 4;
Fig. 6 is the connection relationship synoptic diagram of sensing circuit of the present invention and EEPROM unit and interlock circuit.
Shown in Figure 3 is the circuit function block scheme of EEPROM sensing circuit of the present invention.As can be known graphic, sensing circuit 3 of the present invention mainly comprises five parts, i.e. an on-off circuit 31, an electric current source generating circuit 32, a load circuit 33, a see-saw circuit 34, a negative circuit 35.Shown in Figure 4 is the preferred embodiment circuit diagram of the sensing circuit of EEPROM of the present invention.Below will consult Fig. 3 and Fig. 4 simultaneously, circuit structure of the present invention is done an explanation.
On-off circuit 31 mainly is as the control element of opening current source, so that sensing circuit 3 begins action.It mainly includes a PMOS transistor M1, and its source electrode (Source) is connected to noble potential (VDD), and its drain electrode (Drain) is connected to the A point (being the drain electrode of PMOS transistor M2) of electric current source generating circuit 32, and grid (Gate) is to be connected to one to open beginning control signal EN.When sensing circuit 3 was failure to actuate, opening beginning control signal EN was electronegative potential, so PMOS transistor M1 opens (ON), current source is turned off.When opening that the beginning, control signal EN was noble potential, PMOS transistor M1 turns off.
The purpose of electric current source generating circuit 32 provides a constant current source, as current source required when it " 0 " current potential of sensing eeprom memory is exported, it includes a PMOS transistor M2 and five nmos pass transistor M3-M7 finish, its circuit equivalent is in a resistance, so it has the function that produces certain electric current.
The source electrode of PMOS transistor M2 in this electric current source generating circuit 32 is connected to noble potential (VDD), drain and be connected to the drain electrode of nmos pass transistor M3 with grid mutually, also be connected to the grid of the PMOS crystal M8 in the load circuit 33 in addition, M8 constitutes a current mirror structure with this PMOS transistor.
And NMOS crystal M3-M7 forms a string level structure, the grid of nmos pass transistor M3 wherein is to be connected to a bias voltage signal CO, and source electrode is connected to the drain electrode of nmos pass transistor M4, the source electrode of nmos pass transistor M4 is connected to the drain electrode of nmos pass transistor M5, the source electrode of nmos pass transistor M5 is connected to the drain electrode of nmos pass transistor M6, the source electrode of nmos pass transistor M6 is connected to the drain electrode of nmos pass transistor M7, and the source electrode of nmos pass transistor M7 is connected to an electronegative potential.The grid of its nmos pass transistor M4, M5, M6, M7 is connected to jointly and opens beginning control signal EN, and PMOS transistor M2 and five nmos pass transistor M3-M7 constitute a resistance when opening that the beginning, control signal EN was noble potential, so that a constant current source to be provided.
The purpose of load circuit 33 is for producing the required voltage of see-saw circuit 34, and its circuit is made of a PMOS transistor M8 and a nmos pass transistor M9.Wherein PMOS transistor M8 moves the required circuit component of high voltage to as one, its source electrode is to be connected to noble potential (VDD), its drain electrode is connected to one of them input end of the Sheffer stroke gate of see-saw circuit 34, it also is connected to the drain electrode of nmos pass transistor M9 in addition, its grid is connected to the PMOS transistor M2 drain electrode in the electric current source generating circuit 32, and constitute a current mirror circuit structure with this PMOS transistor M2, this current mirror moves when sending " 0 " current potential in the EEPROM unit, pull down with the current potential that B is ordered, export noble potential when the current potential of ordering as B is pulled to the state transition point that is lower than anti-phase multiplying arrangement 34.
When the EEPROM unit is unsettled attitude (floating), then PMOS transistor M8 action, making B point current potential is noble potential, and makes see-saw circuit be output as electronegative potential.
The source electrode of nmos pass transistor M9 is connected to the information that EEPROM unit (as shown in Figure 1) is sent here, its grid is connected to a bias voltage signal CO, CO is controlled by this bias voltage signal, purpose makes the C point voltage about about 2V, that is when the information of reading 1, it can provide the current potential of the voltage of a 2V to EEPROM unit VD.
The purpose of see-saw circuit 34 is for amplifying the signal that load circuit 33 is sent into, and also the voltage amplification that B can be ordered is the level of " 0 " or " 1 ", through the negative circuit of next stage level inversion output is promptly produced the information of outside required " 0 " or " 1 " again.This see-saw circuit 34 is to be made of a Sheffer stroke gate N1 (NAND Gate), one of them input end of its Sheffer stroke gate N1 is connected to and opens beginning control signal EN, the other end then is connected to the output B point (that is drain electrode end of PMOS transistor M8) of load circuit 33, and the output signal of Sheffer stroke gate N1 is then delivered to the input end of phase inverter N2 in the negative circuit 35.
Phase inverter N2 in the negative circuit 35 (NOT Gate) is the usefulness as signal inversion, because the information of being deposited in the output information of see-saw circuit 34 and the real EEPROM unit is opposite, makes the correct output of information energy so need add this phase inverter N2 again.
The explanation of operating principle of the present invention:
When opening that the beginning, control signal EN was noble potential, on-off circuit 31 is opened, and this moment, 32 actions of electric current source generating circuit can produce a constant current source.This moment is when sending " 0 " current potential in the EEPROM unit, load circuit 33 actions, produce an identical electric current of electric current that is produced with electric current source generating circuit 32, therefore B point current potential can be pulled down, when B point current potential is pulled to transfer point less than see-saw circuit 34, then see-saw circuit 34 senses a noble potential, and this noble potential produces an electronegative potential through the negative circuit 35 of next stage again, and " 0 " information that provides the outside to read is provided this current potential.
When sending the current potential of one unsettled (floating) as the EEPROM unit, PMOS transistor M8 action in the load circuit 33 at this moment, B point current potential is pulled to a high voltage, the changing voltage that is higher than see-saw circuit 34 when this voltage, then see-saw circuit 34 senses an electronegative potential, output terminal OUT through the negative circuit 35 of next stage produces a noble potential again, and " 1 " information that provides the outside to read is provided this current potential.
Simultaneously, nmos pass transistor M9 in the load circuit 33, its grid is to be connected to a bias voltage signal CO, thereby makes the C point be limited in the voltage of 2V, and this purpose is for making its VD voltage (as shown in Figure 1) that is added on the EEPROM unit (former because require the integrity problem of EEPROM) about about 2V.
Fig. 6 is the connection relationship block scheme of sensing circuit of the present invention and EEPROM unit and interlock circuit.When wherein VCG and VG voltage generation circuit 4 are used to read information in the EEPROM unit, provide the control circuit of VCG=5V and VG=0V as shown in Figure 1.When one unit switch circuit 5 is used to read the EEPROM unit, this EEPROM unit is opened.
When reading the information of " 0 ", 0V can be sent in the EEPROM unit, and unit switch circuit 5 is opened at this moment, and 0V is delivered to circuits sense circuit 3 sensings one electronegative potential of the present invention, delivers to outside " 0 " information for then output circuit 6.When reading the level information of " 1 ", unsettled (floating) current potential can be sent in the EEPROM unit, unit switch circuit 5 is opened at this moment, but circuit of the present invention can provide the voltage of 2V to EEPROM, so the voltage that EEPROM sends also is 2V, circuit meeting sensing one noble potential simultaneously of the present invention delivers to outside " 1 " information for then output circuit 6.
Claims (4)
1. the sensing circuit of an electric erasable programmable memory device includes:
One electric current source generating circuit is in order to providing a constant current source, as this sensing circuit required current source when " 0 " of sensing eeprom memory current potential is exported;
One on-off circuit opens under the beginning control signal control one, whether produces a constant current source in order to control this electric current source generating circuit;
One load circuit, have an output terminal and and be connected to the signal input part of EEPROM unit, wherein this signal input part is in order to receive the output information of this EEPROM unit, when electric current is decided in this electric current source generating circuit generation, and when " 0 " current potential is sent in this eeprom memory unit, in order to produce an electric current identical with this constant current source;
One see-saw circuit, in order to the information that the output terminal that amplifies load circuit is sent into, it includes a Sheffer stroke gate, and one of them input end of its Sheffer stroke gate is connected to and opens the beginning control signal, and the other end then is connected to the output terminal of load circuit; And
One negative circuit is connected to the output terminal of see-saw circuit, so that the information of being deposited in the output information of this see-saw circuit and the real EEPROM unit conforms to, information is correctly exported.
2. the sensing circuit of electric erasable programmable memory device as claimed in claim 1, it is characterized in that this on-off circuit includes a PMOS transistor, its source electrode is connected to a noble potential, and its grid is to be connected to open the beginning control signal, opens beginning this transistorized action of control signal control by this.
3. the sensing circuit of electric erasable programmable memory device as claimed in claim 1, it is characterized in that, this electric current source generating circuit includes the nmos pass transistor of a PMOS transistor and several polyphones, the source electrode of PMOS transistor wherein is connected to noble potential, drain and be connected to the drain electrode of first nmos pass transistor in this polyphone nmos pass transistor with grid mutually, the grid of this first nmos pass transistor is to be connected to a bias voltage signal, by this bias voltage signal control, and remaining nmos pass transistor grid is connected to and opens the beginning control signal, when opening the beginning control signal when being noble potential, this PMOS transistor and each nmos pass transistor constitute a series connection resistance loop, so that a constant current source to be provided.
4. the sensing circuit of electric erasable programmable memory device as claimed in claim 1, it is characterized in that, this load circuit is made of a PMOS transistor and a nmos pass transistor, wherein the source electrode of this PMOS transistor is to be connected to noble potential, its drain electrode is as the output terminal of this load circuit, its grid is connected to the PMOS transistor drain in the electric current source generating circuit, and constitutes a current mirror circuit structure with this PMOS transistor; The source electrode of this nmos pass transistor is connected to the EEPROM unit, in order to receive the information that this unit is sent here, its grid is connected to bias voltage signal, is controlled by this bias voltage input signal, maintains about about 2V so that the source electrode of this nmos pass transistor is connected in the voltage of this EEPROM cell node.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 97112323 CN1202703A (en) | 1997-06-17 | 1997-06-17 | Sensing Circuit for Electrically Erasable Programmable Memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 97112323 CN1202703A (en) | 1997-06-17 | 1997-06-17 | Sensing Circuit for Electrically Erasable Programmable Memory |
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| CN1202703A true CN1202703A (en) | 1998-12-23 |
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| CN 97112323 Pending CN1202703A (en) | 1997-06-17 | 1997-06-17 | Sensing Circuit for Electrically Erasable Programmable Memory |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100372025C (en) * | 2003-02-18 | 2008-02-27 | 义隆电子股份有限公司 | High-speed sensing circuit and method of memory |
| CN100466108C (en) * | 2003-06-10 | 2009-03-04 | 微米技术有限公司 | Method and apparatus for measuring current as in sensing a memory cell |
| CN101458959B (en) * | 2007-12-12 | 2011-09-21 | 南亚科技股份有限公司 | data programming circuit |
| US8031515B2 (en) | 2007-11-26 | 2011-10-04 | Nanya Technology Corp. | Data programming circuits and memory programming methods |
| CN101465162B (en) * | 2007-12-20 | 2013-06-12 | 世界先进积体电路股份有限公司 | Device and method for automatic sequential programming of memory |
| CN113921048A (en) * | 2021-10-19 | 2022-01-11 | 吉林大学 | Integrated circuit capable of carrying out quaternary logic operation based on two-bit transistor memory |
-
1997
- 1997-06-17 CN CN 97112323 patent/CN1202703A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100372025C (en) * | 2003-02-18 | 2008-02-27 | 义隆电子股份有限公司 | High-speed sensing circuit and method of memory |
| CN100466108C (en) * | 2003-06-10 | 2009-03-04 | 微米技术有限公司 | Method and apparatus for measuring current as in sensing a memory cell |
| US8031515B2 (en) | 2007-11-26 | 2011-10-04 | Nanya Technology Corp. | Data programming circuits and memory programming methods |
| CN101458959B (en) * | 2007-12-12 | 2011-09-21 | 南亚科技股份有限公司 | data programming circuit |
| CN101465162B (en) * | 2007-12-20 | 2013-06-12 | 世界先进积体电路股份有限公司 | Device and method for automatic sequential programming of memory |
| CN113921048A (en) * | 2021-10-19 | 2022-01-11 | 吉林大学 | Integrated circuit capable of carrying out quaternary logic operation based on two-bit transistor memory |
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Address after: No. three, No. two, research road, Hsinchu Science Industrial Park, Taiwan Applicant after: Shengqun Semiconductor Co., Ltd. Address before: No. five, No. two, research road, Hsinchu Science Industrial Park, Taiwan Applicant before: Hetai Semiconductor Co., Ltd. |
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