CN120256359B - Signal processing system, electronic device, storage medium, and program product - Google Patents
Signal processing system, electronic device, storage medium, and program productInfo
- Publication number
- CN120256359B CN120256359B CN202510713315.9A CN202510713315A CN120256359B CN 120256359 B CN120256359 B CN 120256359B CN 202510713315 A CN202510713315 A CN 202510713315A CN 120256359 B CN120256359 B CN 120256359B
- Authority
- CN
- China
- Prior art keywords
- data
- delay
- management controller
- baseboard management
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017509—Interface arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- General Physics & Mathematics (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
本申请公开了一种信号处理系统、电子设备、存储介质及程序产品，涉及计算机技术领域，包括当需要对数据进行延迟接收时，基板管理控制器可以先在第一存储器内确定第一数据，第一数据可以为交替比特序列，按照多个第一延迟，对第一数据进行读取，从而得到多个读取后的第二数据，根据第一数据、多个读取后的第二数据以及多个第一延迟，确定用于数据接收的第二延迟，并在第二存储器中存储第二延迟。这样，通过遍历第一延迟来读取交替比特序列的第一数据，确定用于数据接收的第二延迟，从而降低了基板管理控制器接收信号发生冲突的概率，进而提高基板管理控制器接收信号的成功率。
The present application discloses a signal processing system, electronic device, storage medium and program product, which relate to the field of computer technology. The system includes a baseboard management controller (BMC) that can first determine first data in a first memory when delayed data reception is required. The first data can be an alternating bit sequence. The first data is read according to multiple first delays to obtain multiple read second data. The second delay for data reception is determined based on the first data, the multiple read second data and the multiple first delays, and the second delay is stored in a second memory. In this way, by traversing the first delays to read the first data of the alternating bit sequence and determine the second delay for data reception, the probability of conflict in the BMC receiving signals is reduced, thereby improving the success rate of the BMC receiving signals.
Description
Technical Field
The present application relates to the field of computer technology, and in particular, to a signal processing system, an electronic device, a storage medium, and a program product.
Background
The baseboard management controller can be embedded on the main board of the server, so that a user can conveniently monitor and manage the hardware state remotely.
In complex systems, the baseboard management controller may experience problems of signal interference and collision when receiving data from multiple devices at the same time. In the related art, the received signal may be delayed by controlling the baseboard management controller, thereby reducing signal interference. However, in the above method, the delayed reception period is determined by randomly selecting data, resulting in poor effect of the delayed reception period.
Disclosure of Invention
The application provides a signal processing system, electronic equipment, storage medium and program product, which are used for at least solving the problem of poor effect of delaying a receiving duration.
The present application provides a signal processing system comprising:
The baseboard management controller determines first data and stores the first data in the first memory, wherein the first data is an alternating bit sequence;
The baseboard management controller reads the first data in the first memory according to the first delays to obtain second data;
the baseboard management controller determines a second delay according to the first data, the plurality of second data and the plurality of first delays, wherein the second delay is the delay of the baseboard management controller for data receiving;
The baseboard management controller stores the second delay in the second memory.
The application also provides a data processing device, which comprises a first determining module, a reading module and a second determining module, wherein,
The first determining module is used for determining first data and storing the first data in the first memory, wherein the first data is an alternating bit sequence;
the reading module is used for reading the first data in the first memory according to the first delays to obtain second data;
and the second determining module is used for determining a second delay according to the first data, the plurality of second data and the plurality of first delays, wherein the second delay is the delay of the data receiving of the baseboard management controller, and the baseboard management controller stores the second delay in the second memory.
The application also provides an electronic device comprising a memory for storing a computer program and a processor for implementing any one of the signal processing systems when executing the computer program.
The application also provides a computer readable storage medium having a computer program stored therein, wherein the computer program when executed by a processor implements any of the signal processing systems described above.
The application also provides a computer program product comprising a computer program which when executed by a processor implements any of the signal processing systems described above.
According to the application, when the delay receiving of the data is needed, the baseboard management controller can firstly determine the first data in the first memory, the first data can be an alternating bit sequence, the first data is read according to a plurality of first delays, a plurality of second data after reading is obtained, the second delay for data receiving is determined according to the first data, the plurality of second data after reading and the plurality of first delays, and the second delay is stored in the second memory. In the above procedure, the first data of the alternating bit sequence is read by traversing the first delay, thereby determining an optimal second delay for data reception, because the first data is an alternate bit sequence, the diversity of training samples is improved, and meanwhile, the reliability of the second delay is improved, and the success rate of receiving signals by the substrate management controller is further improved.
Drawings
For a clearer description of embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described, it being apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.
FIG. 1a is a schematic diagram of a system architecture according to an embodiment of the present application;
FIG. 1b is a schematic diagram of a system architecture according to an embodiment of the present application;
Fig. 2 is a schematic flow chart of data processing performed by the signal processing system according to the embodiment of the present application;
FIG. 3 is a schematic diagram of internal clock signals of a baseboard management controller;
fig. 4 is a schematic diagram of a process of performing data reception according to a second delay by the signal processing system according to the embodiment of the present application;
Fig. 5 is a schematic diagram of a first daughter board and a second daughter board according to an embodiment of the present application;
FIG. 6 is a schematic diagram of a data processing apparatus according to an embodiment of the present application;
FIG. 7 is a schematic diagram of another data processing apparatus according to an embodiment of the present application;
Fig. 8 is a schematic structural diagram of an electronic device provided by the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. Based on the embodiments of the present application, all other embodiments obtained by a person of ordinary skill in the art without making any inventive effort are within the scope of the present application.
It should be noted that in the description of the present application, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. The terms "first," "second," and the like in this specification are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order.
First, the terms involved in the present application will be explained:
Baseboard management controller-a type of embedded controller, commonly used in servers and other enterprise-level hardware, provides remote management and monitoring functions for the hardware. The baseboard management controller operates independently of the main operating system, and can still perform management operation under the condition of operating system breakdown or server shutdown. Baseboard management controllers are an important component of modern data centers and enterprise-level servers. The baseboard management controller may be used for remote power control, hardware monitoring, remote console access, firmware update, remote management, and the like.
In complex systems, the baseboard management controller may experience problems of signal interference and collision when receiving data from multiple devices at the same time. In the related art, the received signal may be delayed by controlling the baseboard management controller, thereby reducing signal interference. However, in the above method, the delayed reception period is determined by randomly selecting data, resulting in poor effect of the delayed reception period.
In view of the foregoing, in the embodiment of the present application, when data needs to be processed in the signal processing system, the baseboard management controller may determine first data in the first memory, where the first data may be an alternating bit sequence, read the first data according to a plurality of first delays, thereby obtaining a plurality of second data after reading, determine a second delay for data reception according to the first data, the plurality of second data after reading, and the plurality of first delays, and store the second delay in the second memory. In this way, the first delay is traversed to read the first data of the alternating bit sequence, and the second delay for data reception is determined, so that the probability of collision of signals received by the baseboard management controller is reduced, and the success rate of the signals received by the baseboard management controller is improved.
The present application will be further described in detail below with reference to the drawings and detailed description for the purpose of enabling those skilled in the art to better understand the aspects of the present application.
The specific application environment architecture or specific hardware architecture upon which execution of the signal processing system depends is described herein. Reference is made to fig. 1a and 1b. Fig. 1a is a schematic diagram of a system architecture according to an embodiment of the present application. Referring to fig. 1a, the integrated circuit board includes a board card including a baseboard management controller, a first memory, a second memory, a central processing unit, a multiplexer and a level shifter. The baseboard management controller can be used for receiving the state information sent by the components in the board and remotely monitoring the components in the board. The first memory may be used to store data, e.g., the first memory may be used to store firmware storage, file systems, etc. The second memory may be used to store data, for example, the second memory may be used to store configuration parameters, user settings, etc. that require frequent updating. The first memory may have a larger storage capacity than the second memory. The central processor may be used to execute instructions, process data, and coordinate the operation of other hardware in the system. The multiplexer may be used to route the signals. The level shifter may be used to shift the signal level between different voltage domains, ensuring that devices of different voltages can communicate securely. The central processing unit can be connected with the multiplexer and communicate with the multiplexer, the level shifter can be used for level shifting between the baseboard management controller and the multiplexer, the baseboard management controller can be connected with the second memory, the baseboard management controller can read and receive data of the second memory, and the multiplexer can be connected with the first memory and conduct data transmission.
Fig. 1b is a schematic diagram of another system architecture according to an embodiment of the present application. Referring to fig. 1b, the circuit board comprises a first daughter board, a second daughter board and a baseboard control manager, wherein the first daughter board comprises a second memory and a baseboard control manager, the second daughter board comprises a first memory, a second memory, a central processing unit, a level shifter and a multiplexer, and the first daughter board and the second daughter board are connected through a connector. The baseboard control manager is connected with the second memory of the first daughter board and the second memory of the second daughter board, the baseboard management controller can read and receive data of the second memory, the baseboard control manager is connected with the level shifter of the second daughter board, the level shifter can be used for carrying out level shifting between the baseboard management controller and the multiplexer, the central processing unit can be connected with the multiplexer and communicate with the multiplexer, and the multiplexer can be connected with the first memory and carry out data transmission.
The following describes the technical scheme of the present application and how the technical scheme of the present application solves the above technical problems in detail with specific embodiments. The following embodiments may be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments. Embodiments of the present application will be described below with reference to the accompanying drawings.
Fig. 2 is a schematic flow chart of data processing performed by the signal processing system according to the embodiment of the present application, as shown in fig. 2, as follows:
s201, the baseboard management controller determines first data and stores the first data in a first memory.
The execution body of the embodiment of the application can be a baseboard management controller or a data processing device arranged in the baseboard management controller. The data processing means may be implemented by software or by a combination of software and hardware.
The first data is an alternating bit sequence stored in the first memory corresponding to the board card, that is, the first data is discontinuous binary numbers, which may refer to 0 and 1.
The first data may be 010101010101010, 1010101010, or the like, for example.
The board card may refer to a board card of a server, or may refer to a board card of a computer terminal device. The board card may be provided with a baseboard management controller and a first memory, where the first memory may be used for storing data, and the first memory may be a flash memory module.
The first data may be determined by generating the first data as an alternating bit sequence, where the data size corresponding to the first data is a preset size, and the preset size may be a value preset by a user.
Optionally, the first data may be determined by traversing the data stored in the first memory, determining a plurality of pre-selected data, where the pre-selected data is an alternating bit sequence, determining a data size corresponding to each pre-selected data, determining target data within each pre-selected data, where the data size of the target data is the largest, and determining the target data as the first data.
S202, the baseboard management controller reads the first data in the first memory according to the first delays to obtain second data.
The first delay may refer to a delay duration for delaying the received data, e.g., the first delay may be 30ns, 100ns, etc. The plurality of first delays may be a plurality of delay durations preset by the user, and the plurality of first delays are different from each other.
For any one of the first delays, the baseboard management controller may read the first data from the first memory after delaying the first delay again on the falling edge of the clock signal according to the internal clock signal.
For example, assuming that the first delay is 50ns, the baseboard management controller reads the first data after delaying for 50ns again according to the internal clock signal at the falling edge of the clock signal.
The second data may refer to first data read by the baseboard management controller according to the first delay. One-to-one correspondence is made between the plurality of first delays and the plurality of second data read in accordance with the plurality of first delays.
Next, the first delay will be described in detail by way of a specific example with reference to fig. 3.
Fig. 3 is a schematic diagram of an internal clock signal of the baseboard management controller, please refer to fig. 3, the clock signal may include a plurality of falling edges according to a preset clock period, and the baseboard management controller delays a first delay after the falling edge, and then receives data.
S203, the baseboard management controller determines the second delay according to the first data, the plurality of second data and the plurality of first delays.
The second delay is a delay of the baseboard management controller for data reception.
The second delay may be determined by determining target data from the first data and the plurality of second data, determining a first delay corresponding to the target data, and determining the second delay from the first delay corresponding to the target data.
The similarity between the target data and the first data is greater than or equal to a preset threshold, the target data can be one or more, and the preset threshold can be a numerical value preset in advance by a user.
The target data can be determined by comparing the first data with the plurality of second data, determining the similarity between the first data and the plurality of second data, and determining the target data from the plurality of second data according to the similarity, wherein the similarity of the target data is greater than or equal to a preset threshold.
For example, assuming that there are first data, second data a, second data B, second data C, and second data D, the preset threshold value is 0.8, the similarity between the first data and the second data a is 0.96, the similarity between the first data and the second data B is 0.89, the similarity between the first data and the second data C is 0.58, and the similarity between the first data and the second data D is 0.75, the similarity between the first data and the second data a and the similarity between the first data and the second data B are greater than or equal to the preset threshold value, that is, the target data is the second data a and the second data B.
Alternatively, the second delay may be determined according to the first delays corresponding to the target data by sorting the first delays corresponding to at least one target data in order from large to small among the first delays corresponding to the target data, determining the largest first delay and the smallest first delay according to the sorting, determining a delay section according to the largest first delay and the smallest first delay, the smallest first delay of the delay section being the smallest first delay, and the largest first delay of the delay section being the largest first delay, and determining the second delay according to the delay section, the second delay being the median of the delay section.
For example, assuming that the first delay corresponding to the target data a is 10, the first delay corresponding to the target data B is 38, the first delay corresponding to the target data C is 30, and the first delay corresponding to the target data D is 6, the first delays corresponding to the target data are sorted in order from large to small, the first delays corresponding to the target data B, the first delay corresponding to the target data C, the first delay corresponding to the target data a, the first delay corresponding to the target data D, that is, the largest first delay is 38, and the smallest first delay is 6, so that the delay interval (6,38) can be determined, the median value of the delay interval (6,38) is 22, and the second delay can be determined to be 22.
Optionally, the second delay may be determined according to the first delays corresponding to the target data by sorting the first delays corresponding to at least one target data in order from large to small among the first delays corresponding to the target data, selecting two target data with sorting positions in the middle if the number of the target data is even, averaging the first delays corresponding to the two target data, determining the average value as the second delay, and selecting the target data with sorting positions in the middle if the number of the target data is odd, and determining the target data as the second delay.
For example, assuming that the number of target data is an even number, the first delay corresponding to target data a is 10, the first delay corresponding to target data B is 38, the first delay corresponding to target data C is 30, and the first delay corresponding to target data D is 6, the first delays corresponding to target data are sorted in order from large to small, so that the first delay corresponding to target data B, the first delay corresponding to target data C, the first delay corresponding to target data a, and the first delay corresponding to target data D are sequentially obtained, and the average value of the first delay corresponding to target data a and the first delay corresponding to target data C is 20, that is, the second delay is 20.
Assuming that the number of the target data is an odd number, the first delay corresponding to the target data a is 10, the first delay corresponding to the target data B is 30, and the first delay corresponding to the target data C is 15, the first delays corresponding to the target data C are ordered in the order from large to small, and the order is 30, 15, and 10, and 15.
S204, the baseboard management controller stores the second delay in the second memory.
The board card further includes a second memory, which may be a programmable memory, for storing data.
In the embodiment of the application, when the baseboard management controller needs to delay receiving data, the first data can be determined in the first memory, the first data is an alternating bit sequence, the first data in the first memory is read according to a plurality of first delays, a plurality of second data can be obtained, the plurality of first delays and the plurality of second data read according to the plurality of first delays are in one-to-one correspondence, the second delay can be determined according to the first data, the plurality of second data read and the corresponding plurality of first delays, and the second delay is stored in the second memory. The method may further include determining at least one target data according to the plurality of first delays, determining a section of the first delay corresponding to the at least one target data as a delay section, and determining a second delay as a median of the delay sections. In this way, the first data is read by traversing the first delay, so that the optimal second delay for data reception is determined, the probability of collision of the signals received by the baseboard management controller can be reduced, and the success rate of the signals received by the baseboard management controller is improved.
On the basis of any one of the above embodiments, a process of the signal processing system performing data reception according to the second delay will be described in detail with reference to fig. 4.
Fig. 4 is a schematic diagram of a process of performing data reception according to a second delay by the signal processing system according to the embodiment of the present application. Referring to fig. 4, the method may include:
S401, the baseboard management controller responds to a starting instruction of the baseboard, and obtains baseboard information, second delay and first check codes from the second memory.
The start instruction of the board may refer to an instruction sent to the baseboard management controller when the board receives power supplied by the power supply.
The second memory may refer to a memory of a programmable memory, which may be provided on the board.
The board information may include a serial number of the board. For example, the board information may be AB 123456789.
The first check code may be a check code generated according to the second delay and the board card information after the second delay is determined. The first check code may be used to indicate whether the second delay has been tampered with.
The first check code can be determined by acquiring second delay and board card information, performing check processing on the second delay and the board card information to obtain the first check code, wherein the check processing can refer to hash check processing, and storing the first check code and the second delay into a second memory after the first check code is determined.
Before the board information, the second delay and the first check code are acquired from the second memory, the method further comprises the steps of acquiring target parameters of a target area of the second memory, wherein the target area is an area for storing the second delay, the target parameters are used for indicating whether valid data are stored in the target area, and determining the first data when the target parameters are all preset values. Wherein, the preset value may be 0.
It can be understood that when the target parameters are all preset values, the baseboard management controller is indicated not to generate the second delay, and when any value in the target parameters is not the preset value, the target area is indicated to have written data, namely, the second delay is generated, and then the board card information, the second delay and the first check code are acquired from the second memory.
S402, the baseboard management controller performs verification processing on the board information and the second delay to obtain a second verification code.
And checking the board card information acquired from the second memory and the second delay to obtain a second check code.
The second check code may be used to indicate whether the second delay after storage to the second memory has been tampered with.
S403, the baseboard management controller judges whether the first check code and the second check code are the same.
If yes, then S404 is performed.
If not, then S405 is performed.
S404, the baseboard management controller determines that the second delay is not tampered in the storage process, and receives data according to the second delay.
The second delay not being tampered with during storage may refer to the second delay being retrieved from the second memory being the same as the second delay being stored in the second memory.
S405, the baseboard management controller determines that the second delay has been tampered with during storage.
The second delay having been tampered with during storage may refer to a second delay being retrieved from the second memory and a second delay being stored in the second memory being different.
S406, the baseboard management controller re-reads the first data according to the first delays to obtain third data.
S407, the baseboard management controller redetermines the target data according to the first data and the plurality of third data.
S408, the baseboard management controller redetermines the second delay according to the first delay corresponding to the redetermined target data.
It should be noted that the execution process of the steps S406 to S408 may refer to S202 to S203, and will not be described herein.
And S409, the baseboard management controller receives the data according to the redetermined second delay.
In the embodiment shown in fig. 4, the baseboard management controller may obtain the second delay from the second memory in response to the start instruction of the board card for delaying the received data, in order to prevent the second delay stored in the second memory from being tampered to cause a collision of the received data, may obtain the board card information, the second delay and the first check code from the second memory, then perform check processing according to the board card information and the second delay obtained from the second memory to obtain the second check code, the second check code may be used to indicate whether the second delay stored in the second memory is tampered, determine whether the first check code and the second check code are the same, if so, determine that the second delay is not tampered in the storage process, then perform data reception according to the second delay, if so, determine that the second delay is tampered in the storage process, and need to redetermine the second delay, specifically, re-read the first data according to the plurality of first delays, obtain the plurality of third data, and re-determine the second delay according to the first data and the re-target data, and re-determine the second delay according to the redetermined second delay. In this way, when the second delay is generated for the first time, the first check code is generated, and when the second delay is acquired each time, the second check code is generated according to the acquired second delay, and whether the second delay stored in the second memory is tampered or not can be determined by comparing whether the first check code and the second check code are identical or not, so that the accuracy of the second delay is improved, and the reliability of data reception is improved.
On the basis of any one of the above embodiments, a process of determining the second delay by the signal processing system when the board card includes the first daughter board and the second daughter board, that is, the first memory and the second memory are located in different boards, will be described in detail with reference to fig. 5.
Fig. 5 is a schematic diagram of a first daughter board and a second daughter board provided in an embodiment of the present application, please refer to fig. 5, which includes the first daughter board and the second daughter board. The first daughter board and the second daughter board are connected through a connector. The first daughter board may include a first memory and a second memory, the second daughter board may include a baseboard management controller, wherein the second daughter board may further include a third memory, and the third memory may be a programmable memory corresponding to the second daughter board.
The second memory stores first daughter card information corresponding to the first daughter card and second delay of the first daughter card, and the third memory stores second daughter card information corresponding to the second daughter card and second delay of the second daughter card.
The baseboard management controller can acquire the second delay of the first daughter board card and the second delay of the second daughter board card, judge whether the second delay of the first daughter board card is the same as the second delay of the second daughter board card, read data according to the second delay if the second delay is the same, and re-determine the second delay and receive data according to the re-determined second delay if the second delay is different.
From the description of the above embodiments, it will be clear to a person skilled in the art that the method according to the above embodiments may be implemented by means of software plus the necessary general hardware platform, but of course also by means of hardware, but in many cases the former is a preferred embodiment.
The method of performing data processing by the signal processing system according to any of the above embodiments may also be implemented by a data processing apparatus, and the structure of the data processing apparatus will be described in detail below with reference to fig. 6.
Fig. 6 is a schematic structural diagram of a data processing apparatus according to an embodiment of the present application. As shown in fig. 6, an embodiment of the present application further provides a data processing apparatus 10, comprising a first determining module 11, a reading module 12 and a second determining module 13, wherein,
The first determining module 11 is configured to determine first data, and store the first data in the first memory as an alternating bit sequence stored in the first memory corresponding to the board card;
The reading module 12 is configured to read the first data in the first memory according to a plurality of first delays, so as to obtain a plurality of second data;
The second determining module 13 is configured to determine a second delay according to the first data, the plurality of second data, and the plurality of first delays, and store the second delay in the second memory, where the second delay is a delay of data reception by the board card.
The technical scheme shown in the embodiment of the method can be executed by the data processing device provided by the embodiment of the application, and the implementation principle and the beneficial effects are similar, so that the description is omitted.
In one possible design, the second determination module 13 is used in particular,
Determining target data in the plurality of second data according to the first data and the plurality of second data, wherein the similarity between the target data and the first data is greater than or equal to a preset threshold value;
determining a first delay corresponding to the target data;
And determining the second delay according to the first delay corresponding to the target data.
In one possible design, the second determination module 13 is used in particular,
Determining the maximum first delay and the minimum first delay in the first delays corresponding to the target data;
the second delay is determined based on the maximum first delay and the minimum first delay.
In one possible design, the second determination module 13 is used in particular,
Comparing the first data with the plurality of second data;
determining a similarity between the first data and the plurality of second data;
and determining target data in the plurality of second data according to the similarity, wherein the similarity of the target data is greater than or equal to a preset threshold value.
The technical scheme shown in the embodiment of the method can be executed by the data processing device provided by the embodiment of the application, and the implementation principle and the beneficial effects are similar, so that the description is omitted.
Fig. 7 is a schematic structural diagram of another data processing apparatus according to an embodiment of the present application. On the basis of the embodiment shown in fig. 6, referring to fig. 7, the data processing apparatus 10 further comprises a verification module 14 and a third determination module 15, wherein,
The verification module 14 is configured to determine board information of the board, where the board information includes a serial number of the board;
Performing verification processing on the board card information and the second delay to obtain a first verification code;
And storing the board card information, the second delay and the first check code into a second memory corresponding to the board card.
In one possible design, the verification module 14 is also used to,
Responding to a starting instruction of the board card, and acquiring the board card information, the second delay and the first check code from the second memory;
performing verification processing on the board card information and the second delay to obtain a second verification code;
Determining whether the first check code and the second check code are identical;
When the first check code and the second check code are the same, determining that the second delay is not tampered in the storage process;
receiving data according to the second delay;
determining that the second delay has been tampered with during the storing when the first check code and the second check code are different;
according to the first delays, the first data are read again to obtain third data;
Re-determining target data based on the first data and the plurality of third data;
The second delay is redetermined according to the first delay corresponding to the redetermined target data;
And receiving data according to the redetermined second delay.
The third determining module 15 is configured to obtain a target parameter of a target area of the second memory, where the target area is an area storing the second delay, and the target parameter is used to indicate whether valid data is stored in the target area;
And when the target parameters are all preset values, determining the first data.
The technical scheme shown in the embodiment of the method can be executed by the data processing device provided by the embodiment of the application, and the implementation principle and the beneficial effects are similar, so that the description is omitted.
Fig. 8 is a schematic structural diagram of an electronic device provided by the present application. As shown in fig. 8, the electronic device 50 provided in this embodiment includes at least one processor 501 and a memory 502. Optionally, the electronic device 50 further comprises a communication component 503. The processor 501, the memory 502, and the communication unit 503 are connected via a bus.
In a specific implementation process, at least one processor 501 executes computer-executable instructions stored in a memory 502, so that at least one processor 501 executes the above-described embodiment of a method for managing a server cluster.
The specific implementation process of the processor 501 may refer to the above-mentioned method embodiment, and its implementation principle and technical effects are similar, and this embodiment will not be described herein again.
In the above embodiment, it should be understood that the Processor may be a central processing unit (Central Processing Unit, abbreviated as CPU), other general purpose Processor, digital signal Processor (DIGITAL SIGNAL Processor, abbreviated as DSP), application SPECIFIC INTEGRATED Circuit (ASIC), and the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of a method disclosed in connection with the present application may be embodied directly in a hardware processor for execution, or in a combination of hardware and software modules in a processor for execution.
The Memory may include high-speed Memory (Random Access Memory, RAM) or may further include Non-volatile Memory (NVM), such as at least one disk Memory.
The bus may be an industry standard architecture (Industry Standard Architecture, ISA) bus, an external device interconnect (PERIPHERAL COMPONENT, PCI) bus, or an extended industry standard architecture (Extended Industry Standard Architecture, EISA) bus, among others. The buses may be divided into address buses, data buses, control buses, etc. For ease of illustration, the buses in the drawings of the present application are not limited to only one bus or to one type of bus.
Embodiments of the present application also provide a computer readable storage medium having a computer program stored therein, wherein the computer program is configured to execute the signal processing system when run.
In an exemplary embodiment, the computer readable storage medium may include, but is not limited to, a U disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a removable hard disk, a magnetic disk, or an optical disk, etc. various media in which a computer program may be stored.
Embodiments of the present application also provide a computer program product comprising a computer program which, when executed by a processor, implements the signal processing system described above.
Embodiments of the present application also provide another computer program product comprising a non-volatile computer readable storage medium storing a computer program which, when executed by a processor, implements the signal processing system described above.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative elements and steps are described above generally in terms of functionality in order to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
The above description has been provided for a signal processing system, an electronic device, a storage medium, and a program product. The principles and embodiments of the present application have been described herein with reference to specific examples, the description of which is intended only to facilitate an understanding of the method of the present application and its core ideas. It should be noted that it will be apparent to those skilled in the art that various modifications and adaptations of the application can be made without departing from the principles of the application and these modifications and adaptations are intended to be within the scope of the application as defined in the following claims.
Claims (9)
1. A signal processing system is characterized by comprising a board card, wherein the board card comprises a baseboard management controller, a first memory and a second memory,
The baseboard management controller determines first data and stores the first data in the first memory, wherein the first data is an alternating bit sequence;
the baseboard management controller reads the first data in the first memory according to a plurality of first delays to obtain a plurality of second data;
The baseboard management controller determines a second delay according to the first data, the plurality of second data and the plurality of first delays, wherein the second delay is the delay of the baseboard management controller for data receiving;
the baseboard management controller storing the second delay in the second memory;
the baseboard management controller determining a second delay according to the first data, the plurality of second data, and the plurality of first delays, including:
The baseboard management controller determines target data in the plurality of second data according to the first data and the plurality of second data, wherein the similarity between the target data and the first data is greater than or equal to a preset threshold value;
The baseboard management controller determines first delay corresponding to the target data, determines maximum first delay and minimum first delay in the first delay corresponding to the target data, determines a delay interval according to the maximum first delay and the minimum first delay, and determines second delay which is the median of the delay interval according to the delay interval.
2. The signal processing system of claim 1, wherein the baseboard management controller determining target data among the plurality of second data based on the first data and the plurality of second data, comprises:
The baseboard management controller compares the first data with the plurality of second data and determines the similarity between the first data and the plurality of second data;
And the baseboard management controller determines target data from the plurality of second data according to the similarity, wherein the similarity of the target data is greater than or equal to a preset threshold value.
3. The signal processing system according to any one of claims 1-2, wherein,
The baseboard management controller determines board information of the board, wherein the board information comprises a serial number of the board;
The baseboard management controller performs verification processing on the board information and the second delay to obtain a first verification code;
the baseboard management controller stores the board information, the second delay, and the first check code in the second memory.
4. The signal processing system according to any one of claims 1-2, wherein,
The baseboard management controller responds to a starting instruction of the board card, and acquires the stored board card information, the second delay and the first check code from the second memory;
The baseboard management controller performs verification processing on the board information and the second delay to obtain a second verification code;
The baseboard management controller determines whether the first check code and the second check code are the same;
when the first check code and the second check code are the same, the baseboard management controller determines that the second delay is not tampered in the second memory;
The baseboard management controller receives data according to the second delay;
When the first check code and the second check code are different, the baseboard management controller determines that the second delay has been tampered with in the second memory;
The baseboard management controller reads the first data in the first memory again according to the first delays to obtain third data;
the baseboard management controller redetermines target data according to the first data and the plurality of third data;
the baseboard management controller redetermines the second delay according to the first delay corresponding to the redetermined target data;
The baseboard management controller receives data according to the redetermined second delay.
5. The signal processing system of claim 1, wherein the signal processing system further comprises a processor configured to,
The baseboard management controller obtains target parameters of a target area of the second memory, wherein the target area is an area for storing the second delay, and the target parameters are used for indicating whether valid data are stored in the target area;
The baseboard management controller determines the first data when the target parameter indicates that the target area does not store valid data.
6. The signal processing system of claim 1, wherein the board card comprises a first daughter board and a second daughter board, the first daughter board and the second daughter board being connected by a connector, the first daughter board comprising the baseboard management controller and the second memory, the second daughter board comprising the first memory.
7. An electronic device, comprising:
a memory for storing a computer program;
a processor for implementing a signal processing system as claimed in any one of claims 1 to 6 when executing said computer program.
8. A computer readable storage medium, characterized in that a computer program is stored in the computer readable storage medium, wherein the computer program, when executed by a processor, implements the signal processing system according to any of claims 1 to 6.
9. A computer program product comprising a computer program, characterized in that the computer program, when being executed by a processor, implements the signal processing system of any of the preceding claims 1 to 6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202510713315.9A CN120256359B (en) | 2025-05-29 | 2025-05-29 | Signal processing system, electronic device, storage medium, and program product |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202510713315.9A CN120256359B (en) | 2025-05-29 | 2025-05-29 | Signal processing system, electronic device, storage medium, and program product |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN120256359A CN120256359A (en) | 2025-07-04 |
| CN120256359B true CN120256359B (en) | 2025-08-22 |
Family
ID=96179458
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202510713315.9A Active CN120256359B (en) | 2025-05-29 | 2025-05-29 | Signal processing system, electronic device, storage medium, and program product |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN120256359B (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117370252A (en) * | 2023-09-01 | 2024-01-09 | 联想(北京)有限公司 | Signal processing method, signal processing device, electronic equipment and computer readable storage medium |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7724589B2 (en) * | 2006-07-31 | 2010-05-25 | Google Inc. | System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits |
| WO2021134221A1 (en) * | 2019-12-30 | 2021-07-08 | 成都海光集成电路设计有限公司 | Method for adjusting read speed of memory system, and comparison circuit and memory system |
| CN116225812B (en) * | 2023-05-08 | 2023-08-04 | 山东云海国创云计算装备产业创新中心有限公司 | Baseboard management controller system operation method, device, equipment and storage medium |
| CN118152161A (en) * | 2024-01-30 | 2024-06-07 | 苏州元脑智能科技有限公司 | Server management and control method, system, equipment and computer readable storage medium |
| CN119201814A (en) * | 2024-11-26 | 2024-12-27 | 苏州元脑智能科技有限公司 | Signal transmission system, signal processing method and device, storage medium, electronic device and program product |
| CN119917028A (en) * | 2025-01-24 | 2025-05-02 | 山东云海国创云计算装备产业创新中心有限公司 | Memory data reading method and device, computer equipment, and storage medium |
-
2025
- 2025-05-29 CN CN202510713315.9A patent/CN120256359B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117370252A (en) * | 2023-09-01 | 2024-01-09 | 联想(北京)有限公司 | Signal processing method, signal processing device, electronic equipment and computer readable storage medium |
Also Published As
| Publication number | Publication date |
|---|---|
| CN120256359A (en) | 2025-07-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN112015445B (en) | Firmware updating device and firmware updating method | |
| CN115865866B (en) | Address allocation method and device | |
| US7971114B2 (en) | Method for testing a memory device | |
| CN111988240B (en) | Data transmission method and device, electronic equipment and storage medium | |
| CN110287135B (en) | Bus polling method and device | |
| CN114020681B (en) | Method, device and system for distributing logical drive letter, electronic equipment and storage medium | |
| CN104216740A (en) | Application software management method and device and terminal | |
| CN109254839A (en) | It determines the method in task triggered time, construct the method and system of task timer | |
| CN120256359B (en) | Signal processing system, electronic device, storage medium, and program product | |
| US9786373B2 (en) | EEPROM backup method and device | |
| CN115221092B (en) | Methods, apparatus, devices, and storage media for determining the assignable bus of a PCI-E card. | |
| CN120199314B (en) | System testing method for UFS devices and test host, equipment and media | |
| CN106708569B (en) | Hot loading method and device for VOBC configuration file in over-the-line train | |
| CN107894900B (en) | A method and system for MCU upgrade | |
| CN109087676B (en) | Programming method and device of nonvolatile memory | |
| CN112882727A (en) | Networking module production testing method, production testing tool and computer equipment | |
| CN118484144A (en) | Method, device, equipment and storage medium for reading and writing solid state disk | |
| CN115629663B (en) | Power supply control circuit and server | |
| CN113542398B (en) | Management and control method, device, medium and equipment of distributed cluster system | |
| CN109542726B (en) | Power consumption detection method and device | |
| JP2009187474A (en) | Semiconductor device, portable electronic device, self-diagnosis method, self-diagnosis program | |
| CN113656216A (en) | Method and device for stably operating flash memory | |
| CN115129633B (en) | Method, device, equipment and medium for determining switch downstream port of access SR-IOV equipment | |
| CN111579973A (en) | Chip synchronous testing method, chip, electronic equipment and storage medium | |
| CN113051143A (en) | Detection method, device, equipment and storage medium for service load balancing server |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |