CN120184132A - Packaging substrate and manufacturing method thereof - Google Patents
Packaging substrate and manufacturing method thereof Download PDFInfo
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- CN120184132A CN120184132A CN202510194883.2A CN202510194883A CN120184132A CN 120184132 A CN120184132 A CN 120184132A CN 202510194883 A CN202510194883 A CN 202510194883A CN 120184132 A CN120184132 A CN 120184132A
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- layer
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- H10W70/65—
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- H10W70/05—
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- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
本发明提出一种封装基板及其制法，封装基板包括将布线元件嵌埋于线路结构中，以提升布线密度，使该封装基板可符合细线路/细间距的需求。
The present invention provides a packaging substrate and a manufacturing method thereof. The packaging substrate includes a wiring element embedded in a circuit structure to increase the wiring density so that the packaging substrate can meet the requirements of fine circuits/fine spacing.
Description
Technical Field
The present disclosure relates to semiconductor packaging technology, and more particularly, to a packaging substrate with embedded wiring elements and a method for manufacturing the same.
Background
The technology currently applied to the field of Chip packaging includes, for example, chip size packaging (CHIP SCALE PACKAGE, CSP for short), direct Chip attach packaging (DIRECT CHIP ATTACHED, DCA for short), or Multi-Chip Module (MCM for short) and other types of packaging modules. Typically, the semiconductor chip is disposed on a package substrate.
However, in the conventional package substrate, a build-up process (build-up process) is used to manufacture the circuit layer, which is limited by the miniaturization requirement, so that it is difficult to increase the wiring density, and it is difficult for the conventional package substrate to meet the requirement of fine circuit/fine pitch.
Therefore, how to overcome the above problems of the prior art has been an urgent issue.
Disclosure of Invention
The present invention is directed to a package substrate and a method for manufacturing the same, which solve at least one of the above problems.
In view of the above-mentioned drawbacks of the prior art, the present disclosure provides a package substrate, which includes a core board having a first side and a second side opposite to each other and at least one conductive post connecting the first side and the second side, wherein the first side and the second side are respectively formed with a first circuit structure, the first circuit structure has at least one first dielectric layer and a first circuit layer combined with the first dielectric layer and electrically connected to the conductive post, a wiring element disposed on the first circuit structure of the first side of the core board, and a second circuit structure disposed on the first circuit structure of the first side of the core board and covering the wiring element, such that the wiring element is embedded in the second circuit structure and the second circuit structure is electrically connected to the wiring element and the first circuit layer.
The disclosure also provides a method for manufacturing the package substrate, which comprises providing a core board body with a core layer, defining a first side and a second side opposite to each other and at least one conductive post connecting the first side and the second side, wherein the first side and the second side are respectively provided with a first circuit structure, the first circuit structure is provided with at least one first dielectric layer and a first circuit layer combined with the first dielectric layer and electrically connected with the conductive post, a wiring element is arranged on the first circuit structure of the first side of the core board body, and a second circuit structure is formed on the first circuit structure of the first side of the core board body, so that the second circuit structure covers the wiring element, the wiring element is embedded in the second circuit structure, and the second circuit structure is electrically connected with the wiring element and the first circuit layer.
In an embodiment of the foregoing package substrate and the method for manufacturing the same, an inner circuit layer electrically connected to the conductive pillar is disposed on the first side and the second side of the core layer, respectively.
In an embodiment of the foregoing package substrate and the method for manufacturing the same, the conductive pillars are hollow conductive pillars with two ends flush with the first side and the second side of the core layer, and the inside of the hollow conductive pillars is filled with a plugging material.
In an embodiment of the foregoing package substrate and the method for manufacturing the same, the wiring element is adhered to the first circuit structure by an adhesive layer.
In an embodiment of the foregoing package substrate and the method for manufacturing the same, the adhesive layer is formed on the entire surface of the first circuit structure.
In an embodiment of the foregoing package substrate and the manufacturing method thereof, the second circuit structure is further disposed on the first circuit structure on the second side of the core board.
In an embodiment of the foregoing package substrate and the method for manufacturing the same, the core layer has a plurality of through holes penetrating the first side and the second side, and the first dielectric layer is filled in the plurality of through holes.
In an embodiment of the foregoing package substrate and the method for manufacturing the same, the conductive pillars are formed in the through holes and extend to the surfaces of the first dielectric layers on the first side and the second side.
Therefore, in the package substrate and the manufacturing method thereof of the present disclosure, the design that the wiring element is embedded in the second circuit structure is mainly used to increase the wiring density, so that the package substrate can meet the requirements of fine wires/fine pitches.
In addition, the wiring element is adhered to the first circuit structure, so that when the wiring element is bad, the wiring element can be replaced without scrapping the core plate body, and the manufacturing cost of the packaging substrate can be greatly saved.
In addition, by using glass as the core layer, the core plate body has the characteristics of stable rigidity (high toughness), low thermal expansion coefficient, stable dimensional change and the like, so that the risk of warping or deformation of the core plate body during processing can be reduced.
Further, since glass has stable rigidity (high toughness), low thermal expansion coefficient, stable dimensional change, etc., thinner glass can be used as the core layer to facilitate thinning the total thickness of the package substrate.
Drawings
Fig. 1A to 1G are schematic cross-sectional views illustrating a manufacturing method of a first embodiment of a package substrate of the present disclosure.
Fig. 1H is a schematic cross-sectional view of the subsequent process of fig. 1G.
Fig. 2A to 2C are schematic cross-sectional views illustrating a manufacturing method of a second embodiment of a package substrate of the present disclosure.
The reference numerals are as follows:
1,2 package substrate
1A Wiring block
1B,2b core plate body
10,20 Core layers
10A,20a first side
10B,20b second side
100,201 Conductive post
101. Inner circuit layer
102. Plug hole material
11,21 First circuit structure
110 First dielectric layer
111,211 First line layer
12,22 Second circuit structure
120,220 Second dielectric layer
121,221 Second wiring layer
122,212,222 Electrical contact pad
13. Adhesive layer
14. Wiring element
140. Dielectric body
141. Wiring layer
17. Solder mask layer
170. Perforating the hole
19. Conductive bump
200. Perforation
201A first conical column
201B second conical cylinder
30. Electronic component
8. Support member
80. Board body
81. Copper foil
82. Metal layer
S cutting path.
Detailed Description
Other advantages and effects of the present disclosure will become readily apparent to those skilled in the art from the present disclosure, as the following description proceeds, by way of specific examples.
It should be understood that the structures, proportions, sizes, etc. shown in the drawings attached hereto are merely for the purpose of understanding and reading the disclosure and are not intended to limit the applicable limitations of the disclosure, and that any structural modifications, proportional changes, or dimensional adjustments should be made without affecting the efficacy or achievement of the present disclosure, and are within the scope of the disclosure. Also, the terms "upper", "first", "second", "a" and the like recited in the present specification are also for descriptive purposes only and are not intended to limit the scope of the disclosure to which it may be applied, but rather to modify or adapt its relative relationship without materially altering the technical context to be considered within the scope of the disclosure to which it may be applied.
Fig. 1A to 1H are schematic cross-sectional views illustrating a manufacturing method of a first embodiment of a package substrate 1 of the present disclosure.
As shown in fig. 1A, a support member 8 is provided to form a wiring block 1A on opposite sides of the support member 8, respectively.
In this embodiment, the supporting member 8 is a temporary carrier, which may be a plate having metal layers on opposite sides, such as a copper foil substrate, wherein the surface of the plate body 80 has copper foil 81 thereon, and a metal layer 82, such as a copper layer, is formed on the copper foil 81, so that the wiring block 1a is formed on the metal layer 82.
The wiring block 1a adopts a coreless layer (coreless) wiring specification, which forms a wiring layer 141 in the dielectric 140. For example, the dielectric body 140 is an ABF film (ABF), poly (p-diazole) benzene (Polybenzoxazole, PBO), polyimide (PI), prepreg with glass fiber (Prepreg, PP), or other dielectric materials.
Further, build-up process (build-up process) is used to form the wiring layer 141 by electroplating metal (e.g., copper) or other means. For example, the wiring layer 141 is made of copper, and adopts a wiring redistribution layer (Redistribution layer, abbreviated as RDL) specification, so that the wiring layer 141 has a very small line width/space (L/S), such as L/S less than or equal to 5/5um. It should be appreciated that the wiring layer 141 with the required number of layers can be fabricated by the build-up method.
As shown in fig. 1B, the metal layer 82 is removed after separating the board body 80 of the carrier 8 and the wiring block 1a by the copper foil 81.
In this embodiment, the copper foil 81 is peeled off or otherwise removed to separate the board 80 from the metal layer 82, and then the metal layer 82 on the wiring block 1a is etched away.
As shown in fig. 1C, a singulation process is performed along the dicing path S shown in fig. 1B to obtain a plurality of wiring elements 14. The wiring layer 141 of one side surface of the wiring element 14 is embedded in the dielectric body 140 and is flush with the surface of the wiring element 14, i.e., the side surface of the dielectric body 140 that contacts the metal layer 82, while the wiring layer 141 of the other side surface of the wiring element 14 is formed on the surface of the dielectric body 140.
As shown in fig. 1D to 1E, the wiring element 14 is provided on a core board body 1 b. The core board 1b includes a core layer 10, wherein the core layer 10 defines a first side 10a and a second side 10b opposite to each other, and an inner circuit layer 101 made of copper is disposed on the first side 10a and the second side 10b of the core layer 10, and the core layer 10 has a plurality of conductive pillars 100 connected to the first side 10a and the second side 10b, such that the conductive pillars 100 are electrically connected to the plurality of inner circuit layers 101.
In this embodiment, the core layer 10 is made of a high-hardness dielectric material, such as glass, ceramic, siC, alO 2 or a composite material with high rigidity and a modulus of 50 to 100 Gpa. For example, a plurality of straight cylindrical holes are formed through the first side 10a and the second side 10b of the core layer 10 by using a laser, and then a conductive material is formed on the walls of the holes to form hollow conductive pillars 100, and the hollow portions of the conductive pillars can be filled with the plugging material 102, wherein the plugging material 102 is various, such as conductive adhesive, ink, and the like, and is not particularly limited. The formation of the conductive material may include forming a Barrier layer on the walls of the via and forming a seed layer (SEED LAYER) on the Barrier layer. In addition, the barrier layer and the seed layer may be formed on the surfaces of the first side 10a and the second side 10b of the core layer 10, and then the inner circuit layers 101 may be formed by electroplating copper and patterning. The conductive pillars 100 of the present embodiment are formed by forming a Barrier layer (Barrier layer) on the walls of the through holes and forming a seed layer (SEED LAYER) on the Barrier layer. The barrier layer may be a dielectric barrier layer or a conductive barrier layer, and the material forming the dielectric barrier layer includes, but is not limited to, silicon nitride, silicon oxynitride, silicon carbonitride or Diamond Like Carbon (DLC). The material forming the conductive barrier layer includes, but is not limited to, metal nitride (e.g., ta, tiN, taN or WN). The material forming the seed layer includes copper, manganese doped copper or ruthenium, but is not limited thereto. In addition, in the present embodiment, the conductive pillar 100 is a hollow conductive pillar 100 with two ends flush with the first side 10a and the second side 10b of the core layer 10, and the hollow conductive pillar 100 is filled with the plug hole material 102.
It should be appreciated that in other embodiments, the conductive pillars 100 may be solid metal pillars without filling the plug material 102.
Furthermore, the core board 1b is formed with a first circuit structure 11 on the first side 10a and the second side 10b of the core layer 10, and the first circuit structure 11 is electrically connected to the inner circuit layer 101. For example, the first circuit structure 11 may be formed by a build-up process (build-up process) on the first side 10a and the second side 10b of the core layer 10 to form at least a first dielectric layer 110 and a first circuit layer 111 formed on the first dielectric layer 110 and extending into the first dielectric layer 110 to electrically connect the inner circuit layer 101. The portion of the first circuit layer 111 extending into the first dielectric layer 110 to electrically connect to the inner circuit layer 101 is a conductive via.
In addition, the first dielectric layer 110 is a dielectric material such as ABF film (ABF), poly-p-diazole (Polybenzoxazole, PBO), polyimide (PI), prepreg (Prepreg, PP) or others, and the first circuit layer 111 may be formed by electroplating metal (such as copper) or other methods, such as a circuit redistribution layer (Redistribution layer, RDL) specification. It should be understood that the number of layers of the first circuit layer 111 can be designed according to the requirement, and is not particularly limited.
In addition, the wiring element 14 may be bonded to the first circuit structure 11 of the first side 10a (and/or the second side 10 b) by an adhesive layer 13. For example, an adhesive layer 13 is formed on the entire surface of the first circuit structure 11 to cover the first circuit layer 111, and then the wiring element 14 is adhered to the adhesive layer 13. It should be understood that the number of the wiring elements 14 may be configured as desired, and is not particularly limited.
As shown in fig. 1F, a second circuit structure 12 is formed on the adhesive layer 13 on the first side 10a and the first circuit structure 11 on the second side 10b of the core board body 1b, and the second circuit structure 12 is made to encapsulate the wiring element 14, so that the wiring element 14 is embedded in the second circuit structure 12, and the second circuit structure 12 is electrically connected to the wiring element 14 and the first circuit structure 11.
In this embodiment, the second circuit structure 12 may be formed with a build-up process (build-up process) on the first circuit structure 11 to form at least one second dielectric layer 120 and a second circuit layer 121 (including conductive vias in the second dielectric layer 120 and circuits on the second dielectric layer 120) formed on the second dielectric layer 120 and extending into the second dielectric layer 120 to electrically connect the wiring layer 141 and the first circuit layer 111. For example, the second dielectric layer 120 is a dielectric material such as ABF film (ABF), poly-p-diazole (Polybenzoxazole, PBO), polyimide (PI), prepreg (Prepreg, PP), or others, and the second circuit layer 121 may be formed by electroplating metal (e.g., copper) or other means, such as a circuit redistribution layer (Redistribution layer, RDL) specification. It should be understood that the number of layers of the second circuit layer 121 can be designed according to the requirement, and is not particularly limited.
Furthermore, the dielectric body 140, the first dielectric layer 110 and the second dielectric layer 120 may be formed of the same or different materials.
As shown in fig. 1G, a solder mask layer 17 is formed on each of the second circuit structures 12 to obtain the package substrate 1.
In this embodiment, the second circuit layer 121 is exposed from the solder mask layer 17. For example, the solder mask layer 17 is formed with a plurality of openings 170, so that a portion of the surface of the second circuit layer 121 is exposed out of the plurality of openings 170 for serving as the electrical contact pads 122.
In a subsequent process, as shown in fig. 1H, at least one electronic device 30 may be bonded to a plurality of the electrical contact pads 122 by a plurality of conductive bumps 19, such as solder material, copper bumps, or others.
The electronic device 30 is, for example, an active device, a passive device, a package structure, or a combination thereof, wherein the active device is, for example, a semiconductor chip, and the passive device is, for example, a resistor, a capacitor, or an inductor.
In the present embodiment, the electronic device 30 is a semiconductor chip, which can be flip-chip disposed on the electrical contact pad 122 of the second circuit structure 12 on the first side 10a (and/or the second side 10 b) of the core board body 1b by using the plurality of conductive bumps 19 and electrically connected to the second circuit layer 121, or the electronic device 30 can be electrically connected to the second circuit layer 121 by using a plurality of bonding wires (not shown) in a wire bonding manner, or the electronic device 30 can directly contact the second circuit layer 121. It should be understood that the manner of electrically connecting the electronic device 30 to the second circuit structure 12 is not limited to the above.
Therefore, the manufacturing method of the present embodiment improves the wiring density by embedding the wiring element 14 in the second dielectric layer 120, so that the package substrate 1 meets the requirement of Fine line/Fine pitch (Fine L/S).
Furthermore, by attaching the wiring element 14 to the first circuit structure 11, when the wiring element 14 is defective, the wiring element 14 can be replaced without discarding the core board 1b, so that the manufacturing cost of the package substrate 1 can be greatly reduced.
In addition, by using glass as the core layer 10, for example, since it has stable rigidity (high toughness), low coefficient of thermal expansion (Coefficient of Thermal Expansion, CTE for short), stable dimensional change, and the like, the risk of warpage or deformation of the core plate body 1b during processing can be reduced.
Further, since glass has stable rigidity (high toughness), low coefficient of thermal expansion (Coefficient of Thermal Expansion, CTE for short), stable dimensional change, and the like, thinner glass can be used as the core layer 10 to facilitate thinning of the total thickness of the package substrate 1.
Fig. 2A to 2C are schematic cross-sectional views illustrating a manufacturing method of a second embodiment of the package substrate 2 of the present disclosure. The difference between the present embodiment and the first embodiment is mainly that the design of the core board 2b is substantially the same as other processes, so the following description will not be repeated.
As shown in fig. 2A, a core layer 20 having a plurality of through holes 200 is provided, and the first side 20a and the second side 20b of the core layer 20 are not provided with the inner circuit layer 101.
In the present embodiment, a plurality of straight-cylindrical through holes 200 are formed by laser penetrating the first side 20a and the second side 20b of the core layer 20.
As shown in fig. 2B, a first circuit structure 21 is formed on the first side 20a and the second side 20B of the core layer 20 to form a core board 2B.
In this embodiment, the first circuit structure 21 is formed by a build-up process (build-up process) on the first side 20a and the second side 20b of the core layer 20 respectively to form at least one first dielectric layer 110 and a first circuit layer 211 combined with the first dielectric layer 110, wherein the first dielectric layer 110 is filled into the plurality of through holes 200, and at least one conductive post 201 penetrating through the through holes 200 and extending to the surfaces of the first dielectric layer 110 on the first side 20a and the second side 20b is formed in the first dielectric layer 110 to electrically connect the surfaces of the first circuit layer 211.
The first dielectric layer 110 may be formed on the first side 20a and the second side 20b of the core layer 20 and in the plurality of through holes 200 by lamination. Furthermore, the conductive pillars 201 are funnel-shaped or X-shaped. For example, the process of the conductive pillar 201 may be a two-step opening by laser, and then a plating process is performed to form a first tapered pillar 201a extending into the through hole 200 in the first dielectric layer 110 on the first side 20a of the core layer 20, and a second tapered pillar 201b extending into the through hole 200 in the first dielectric layer 110 on the second side 20b of the core layer 20, such that the taper top of the first tapered pillar 201a is connected to the taper top of the second tapered pillar 201 b. It should be understood that the shape and the manufacturing method of the conductive pillar 201 are not limited to the above. The first circuit layer 211 may also be formed by electroplating and patterning, for example, by laminating a composite material having a first dielectric layer and a metal layer (not shown), so that when at least one first dielectric layer 110 is formed on the first side 20a and the second side 20b of the core layer 20, respectively, the metal layers are formed on both sides of the core plate body 2b, and then the first circuit layer 211 is formed by electroplating and patterning.
As shown in fig. 2C, at least one wiring element 14 is disposed on the first circuit structure 21 on the first side 20a of the core board 2b via the adhesive layer 13, and then a second circuit structure 22 is formed on the adhesive layer 13 and the wiring element 14 on the first circuit structure 21 on the first side 20a of the core board 2 b. Then, a solder mask layer 17 is formed on the first circuit structure 21 on the second side 20b of the core board 2b and the second circuit structure 22 on the first side 20a of the core board 2b, respectively, so as to obtain the package substrate 2.
In the present embodiment, the first circuit layer 211 of the first circuit structure 21 on the second side 20b of the core board 2b is exposed from the solder mask layer 17. For example, the solder mask layer 17 has a plurality of openings 170, so that a portion of the surface of the first circuit layer 211 is exposed out of the plurality of openings 170 for serving as the electrical contact pads 212. It should be understood that, referring to fig. 1F, a build-up process is used to form at least one second dielectric layer 220 on the first circuit structure 21 and a second circuit layer 221 (including conductive vias in the second dielectric layer 220 and lines on the second dielectric layer 220) formed on the second dielectric layer 220 and extending into the second dielectric layer 220 to electrically connect the wiring layer 141 and the first circuit layer 211, respectively. In addition, the second circuit layer 221 is exposed out of the openings 170 of the solder mask layer 17 and serves as an electrical contact pad 222.
Therefore, the method of the present embodiment does not form the second circuit structure 22 on the first circuit structure 21 on the second side 20b of the core board 2b, so that the total thickness of the package substrate 2 of the second embodiment can be greatly reduced, and the total thickness of the package substrate 2 of the second embodiment is smaller than that of the package substrate 1 of the first embodiment.
Furthermore, the manufacturing method of the present embodiment is to manufacture the conductive pillars 201 together when manufacturing the first circuit structure 21, so that the manufacturing of the inner circuit layer 101 and the manufacturing of the plug hole material 102 can be omitted, and the manufacturing of the second circuit structure 12 on the second side 20b of the core board 2b can be omitted, so that the process steps can be greatly reduced, and the manufacturing cost can be effectively reduced.
The present disclosure also provides a package substrate 1,2 comprising a core board 1b,2b, at least one wiring element 14 and a second wiring structure 12,22.
The core board 1b,2b has a core layer 10,20 defining opposite first and second sides 10a,20a, 10b,20b and at least one conductive pillar 100,201 connecting the first and second sides 10a,20a, 10b,20b, and the first and second sides 10a,20 b have a first circuit structure 11,21 respectively formed thereon, wherein the first circuit structure 11,21 has at least one first dielectric layer 110 and a first circuit layer 111,211 combined with the first dielectric layer 110 and electrically connected to the conductive pillar 100, 201.
The wiring elements 14 are provided on the first wiring structures 11,21 of the first sides 10a,20a of the core plate bodies 1b,2 b.
The second circuit structures 12,22 are disposed on the first circuit structures 11,21 on the first sides 10a,20a of the core boards 1b,2b and encapsulate the wiring element 14, so that the wiring element 14 is embedded in the second circuit structures 12,22, and the second circuit structures 12,22 are electrically connected to the wiring element 14 and the first circuit layers 111,211.
In one embodiment, an inner circuit layer 101 electrically connected to the conductive pillar 100 is disposed on the first side 10a and the second side 10b of the core layer 10.
In one embodiment, the conductive pillars 100 are hollow conductive pillars 100 with two ends flush with the first side 10a and the second side 10b of the core layer 10, and the hollow conductive pillars 100 are filled with the plugging material 102.
In one embodiment, the wiring element 14 is adhered to the first circuit structure 11,21 by an adhesive layer 13.
In one embodiment, the adhesion layer 13 is formed on the entire surface of the first circuit structure 11, 21.
In an embodiment, the second circuit structure 12 is further disposed on the first circuit structure 11 on the second side 10b of the core board 1 b.
In one embodiment, the core layer 20 has a plurality of through holes 200 penetrating the first side 20a and the second side 20b, and the first dielectric layer 110 is filled into the plurality of through holes 200.
In one embodiment, the conductive pillars 201 are formed in the through holes 200 and extend to the surface of the first dielectric layer 110 on each of the first side 20a and the second side 20 b.
In summary, the package substrates 1,2 and the manufacturing method thereof of the present disclosure, by embedding the wiring element 14 in the second circuit structure 12,22, the wiring density is improved, so that the package substrates 1,2 meet the requirement of fine wires/fine pitches.
Furthermore, by attaching the wiring element 14 to the first circuit structures 11,21, when the wiring element 14 is defective, the wiring element 14 can be replaced without discarding the core board bodies 1b,2b, so that the manufacturing cost of the package substrate 1,2 can be greatly saved.
In addition, since glass is used as the core layers 10,20, the core plates 1b,2b have stable rigidity (high toughness), low thermal expansion coefficient, stable dimensional change, and the like, so that the risk of warpage or deformation during processing can be reduced.
Further, since glass has stable rigidity (high toughness), low thermal expansion coefficient, stable dimensional change, and the like, thinner glass can be used as the core layers 10,20 to facilitate thinning of the total thickness of the package substrates 1, 2.
The above embodiments are provided to illustrate the principles of the present disclosure and their efficacy, but not to limit the disclosure. Modifications to the above would be obvious to those of ordinary skill in the art, without departing from the spirit and scope of the present disclosure. The scope of the disclosure is therefore intended to be set forth in the following claims.
Claims (16)
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| CN202510194883.2A CN120184132A (en) | 2025-02-21 | 2025-02-21 | Packaging substrate and manufacturing method thereof |
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| CN202510194883.2A CN120184132A (en) | 2025-02-21 | 2025-02-21 | Packaging substrate and manufacturing method thereof |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI855382B (en) * | 2022-09-19 | 2024-09-11 | 大陸商芯愛科技（南京）有限公司 | Packaging substrate and fabrication method thereof |
| CN118658849A (en) * | 2024-08-20 | 2024-09-17 | 芯爱科技(南京)有限公司 | Packaging substrate and manufacturing method thereof |
| CN118676109A (en) * | 2024-08-21 | 2024-09-20 | 芯爱科技(南京)有限公司 | Package substrate and method for fabricating the same |
| CN118888529A (en) * | 2024-03-21 | 2024-11-01 | 芯爱科技(南京)有限公司 | Semiconductor package and method of manufacturing the same |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI855382B (en) * | 2022-09-19 | 2024-09-11 | 大陸商芯愛科技（南京）有限公司 | Packaging substrate and fabrication method thereof |
| CN118888529A (en) * | 2024-03-21 | 2024-11-01 | 芯爱科技(南京)有限公司 | Semiconductor package and method of manufacturing the same |
| CN118658849A (en) * | 2024-08-20 | 2024-09-17 | 芯爱科技(南京)有限公司 | Packaging substrate and manufacturing method thereof |
| CN118676109A (en) * | 2024-08-21 | 2024-09-20 | 芯爱科技(南京)有限公司 | Package substrate and method for fabricating the same |
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