CN120109024A - A three-dimensional integrated chip and its preparation method - Google Patents
A three-dimensional integrated chip and its preparation method Download PDFInfo
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Abstract
本发明公开一种三维集成芯片及其制备方法，涉及半导体封装技术领域。制备方法包括：制备多个第一模块；在多个第一模块的每个凸点上进行倒装处理以进行芯片贴装，以制备多个第二模块；对一个第二模块依次进行塑封处理、晶圆翻转，并对第二模块的玻璃衬底进行半导体工艺处理以及倒装处理，制备获得第三模块；将一个第一模块倒置于第三模块上，依次对第一模块中的玻璃衬底进行半导体工艺处理，以形成基底模块；将多个倒置的第二模块通过倒装处理层叠设置在基底模块上，制备获得三维集成芯片。本发明制备的三维集成芯片制造成本低且工艺简单。
The present invention discloses a three-dimensional integrated chip and a preparation method thereof, and relates to the field of semiconductor packaging technology. The preparation method comprises: preparing a plurality of first modules; performing a flip-chip process on each bump of the plurality of first modules for chip mounting to prepare a plurality of second modules; performing a plastic encapsulation process and a wafer flipping on a second module in sequence, and performing a semiconductor process process and a flip-chip process on the glass substrate of the second module to prepare a third module; placing a first module inverted on the third module, and performing a semiconductor process process on the glass substrate in the first module in sequence to form a base module; stacking a plurality of inverted second modules on the base module through a flip-chip process to prepare a three-dimensional integrated chip. The three-dimensional integrated chip prepared by the present invention has low manufacturing cost and simple process.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a three-dimensional integrated chip and a preparation method thereof.
Background
With the continuous development of semiconductor technology, the packaging requirements of integrated circuits are increasingly complex, especially in the field of three-dimensional integrated chips, where integration level, performance and reliability are required to be improved. The three-dimensional integrated chip can realize higher bandwidth, lower delay and smaller packaging size by vertically stacking a plurality of chips, and is widely applied to the fields of high-performance calculation, memories, radio frequency devices, communication equipment and the like.
In the prior art, through-Silicon Via (TSV) is a vertical interconnection technology penetrating Through a Silicon wafer or a chip, which is a key technology of the existing three-dimensional packaging technology, and has high requirements on etching machines and process capability, high manufacturing cost, and expensive self-price of the TSV equipment, so that large-scale application is limited. In addition, although through-silicon via technology is commonly used to realize the stacking of multi-layer chips, since the thermal expansion coefficient of silicon is about 10x10 -6/°c, and the thermal expansion coefficient of silicon dioxide is about 5x10 -6/°c, that is, the length of silicon is twice as much as that of silicon dioxide under the same temperature change, the thermal stress generated by the through-silicon via is larger, which affects the stacking quality of chips.
Disclosure of Invention
An object of the first aspect of the present invention is to provide a method for manufacturing a three-dimensional integrated chip, which solves the technical problems of high manufacturing cost, complex manufacturing process and low quality of stacked chips in the prior art.
Another object of the first aspect of the invention is to ensure the stability and reliability of the electrical connection between the modules.
The object of the second aspect of the present invention is to provide a three-dimensional integrated chip prepared according to the above-mentioned preparation method.
According to an object of a first aspect of the present invention, the present invention provides a method for manufacturing a three-dimensional integrated chip, including:
Preparing a plurality of first modules, wherein the first modules comprise a glass substrate, an oxide layer and a silicon nitride layer which are sequentially stacked from bottom to top, and each first module is provided with at least one protruding point positioned on the top of the silicon nitride layer;
performing flip-chip processing on each bump of the first modules to perform chip mounting so as to prepare second modules;
Sequentially performing plastic packaging treatment and wafer overturning on one second module, and performing semiconductor process treatment and flip-chip treatment on the glass substrate of the second module to attach chips on the salient points of the glass substrate of the second module so as to prepare a third module;
The first module is arranged on the third module in an inverted mode, so that the convex points of the first module are connected with the chip of the third module, and the semiconductor process treatment is sequentially carried out on the glass substrate in the first module to form a base module;
And laminating at least one inverted second module on the substrate module through flip-chip treatment, so that the chip of the bottommost second module is connected with the convex points of the first module of the substrate module, and when the number of the second modules is multiple, the chips among the adjacent second modules are connected with the convex points, so that the three-dimensional integrated chip is prepared and obtained.
Optionally, the step of disposing the plurality of inverted second modules on the substrate module by flip-chip lamination further comprises:
and carrying out plastic packaging treatment on the substrate module and the at least one inverted second module which are sequentially stacked.
Optionally, the semiconductor processing process includes a substrate opening, an electroplating process, a chemical mechanical polishing process, and a bump process.
Optionally, the step of preparing a plurality of first modules includes:
obtaining a pretreated microstructure comprising at least one first through hole penetrating to the top of the glass substrate;
and sequentially performing the electroplating treatment, the chemical mechanical polishing treatment and the bump treatment on the microstructure to prepare the first module.
Optionally, after the step of sequentially performing plastic packaging processing on the second module, the method further includes:
and bonding the second module subjected to the plastic packaging treatment and the supporting layer.
Optionally, the glass substrate further comprises a second through hole, and the ratio of the intersecting surface of the second through hole and the first through hole is any value of 0.5-0.8.
Optionally, each of the electroplating treatments further comprises, before:
And depositing a blocking layer and a seed layer in the first through hole in sequence.
Optionally, the first through hole is arranged to penetrate through the oxide layer and the silicon nitride layer and has a variable cross section gradually expanding from bottom to top.
Optionally, the way of opening the substrate is to sequentially perform photoetching treatment and etching treatment on the glass substrate.
According to the second aspect of the invention, the invention further provides a three-dimensional integrated chip prepared by the preparation method according to any one of the above.
According to the invention, chip mounting is carried out on the salient points of the first module by using flip-chip processing to form the second module with at least one chip formed on the surface, plastic packaging processing and wafer flip-chip mounting are sequentially carried out on the prepared second module, so that the glass substrate of the second module is turned to the bottom surface upwards, semiconductor process processing and flip-chip mounting are carried out on the glass substrate of the second module to form the third module with chips attached to the surface of the glass substrate and the surface of silicon nitride, one first module is arranged on the third module in an inverted mode, the salient points of the first module are connected with the chips of the third module, semiconductor process processing is sequentially carried out on the glass substrate of the first module to prepare the base module, a plurality of second modules are arranged on the base module in a stacked mode through flip-chip processing, the chips of the second module at the bottommost are connected with the salient points of the first module of the base module, and the chips of the adjacent second modules are connected with the salient points, so that multi-layer chip stacking and electric connection of the three-dimensional integrated chip are realized.
Further, the substrate module and the second module which are sequentially stacked are subjected to one-time plastic packaging treatment, so that the plastic packaging consistency can be ensured, meanwhile, the external mechanical protection is provided for the stacked structure formed by the whole substrate module and at least one second module, the overall structural strength of the three-dimensional integrated chip is improved, the mechanical damage caused by external force in the subsequent treatment or use process is prevented, and the stability and the reliability of the electrical connection between the modules are ensured.
The foregoing description is only an overview of the present invention, and is intended to provide a better understanding of the present invention, as it is embodied in the following description, with reference to the preferred embodiments of the present invention and the accompanying drawings.
Drawings
Some specific embodiments of the invention will be described in detail hereinafter by way of example and not by way of limitation with reference to the accompanying drawings. The same reference numbers will be used throughout the drawings to refer to the same or like parts or portions. It will be appreciated by those skilled in the art that the drawings are not necessarily drawn to scale. In the accompanying drawings:
FIG. 1 is a schematic flow chart of a method of fabricating a three-dimensional integrated chip according to one embodiment of the invention;
FIG. 2 is a schematic block diagram of a three-dimensional integrated chip according to one embodiment of the invention;
FIG. 3 is a schematic block diagram of a third module according to one embodiment of the present invention;
FIG. 4 is a schematic block diagram of a second module according to one embodiment of the invention;
FIG. 5 is a schematic block diagram of a first module according to one embodiment of the present invention;
FIG. 6 is a schematic block diagram of a base module according to one embodiment of the present invention;
Fig. 7 is a schematic structural overall flowchart of a three-dimensional integrated chip manufacturing method according to an embodiment of the present invention.
Reference numerals:
100-three-dimensional integrated chip, 10-first module, 11-glass substrate, 111-second through hole, 12-oxide layer, 13-silicon nitride layer, 14-bump, 21-chip, 20-second module, 30-third module, 40-base module, 15-microstructure, 151-first through hole, 50-support layer.
Detailed Description
The following describes in further detail the embodiments of the present invention with reference to the drawings and examples. The following examples are illustrative of the invention and are not intended to limit the scope of the invention.
In order that the above objects, features and advantages of the application will be readily understood, a more particular description of the application will be rendered by reference to the appended drawings. It is to be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present application are shown in the drawings. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
The terms "comprising" and "having" and any variations thereof herein are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.
Fig. 1 is a schematic flow chart of a method of manufacturing a three-dimensional integrated chip according to an embodiment of the present invention, fig. 2 is a schematic structural diagram of a three-dimensional integrated chip according to an embodiment of the present invention, fig. 3 is a schematic structural diagram of a third module according to an embodiment of the present invention, fig. 4 is a schematic structural diagram of a second module according to an embodiment of the present invention, fig. 5 is a schematic structural diagram of a first module according to an embodiment of the present invention, fig. 6 is a schematic structural diagram of a base module according to an embodiment of the present invention, and fig. 7 is a schematic structural overall flow chart of a method of manufacturing a three-dimensional integrated chip according to an embodiment of the present invention.
As shown in fig. 1, the present invention provides a method for manufacturing a three-dimensional integrated chip 100, including:
Step S100, preparing a plurality of first modules 10, wherein the first modules 10 comprise a glass substrate 11, an oxide layer 12 and a silicon nitride layer 13 which are sequentially stacked from bottom to top, and each first module 10 is provided with at least one salient point 14 positioned on the top of the silicon nitride layer 13;
step S200, performing flip-chip processing on each bump 14 of the plurality of first modules 10 to mount a chip 21 thereon, so as to prepare a plurality of second modules 20;
Step S300, sequentially performing plastic packaging treatment and wafer overturning on one second module 20, and performing semiconductor process treatment and flip-chip treatment on the glass substrate 11 of the second module 20 to attach chips 21 on the bumps 14 of the glass substrate 11 of the second module 20, so as to prepare and obtain a third module 30;
step 400, a first module 10 is placed upside down on a third module 30, so that the bumps 14 of the first module 10 are connected to the chips 21 of the third module 30, and the glass substrate 11 in the first module 10 is sequentially subjected to semiconductor process treatment to form a base module 40;
In step S500, at least one inverted second module 20 is stacked on the base module 40 through flip-chip processing, so that the chips 21 of the bottommost second module 20 are connected with the bumps 14 of the first module 10 of the base module 40, and when the number of the second modules 20 is plural, the chips 21 and the bumps 14 between the adjacent second modules 20 are connected, thereby preparing the three-dimensional integrated chip 100.
As shown in fig. 2, in this embodiment, a plurality of first modules 10 (refer to fig. 5) are first prepared, such that the first modules 10 include a glass substrate 11, an oxide layer 12 and a silicon nitride layer 13 (refer to fig. 3) which are sequentially stacked from bottom to top, and each first module 10 is provided with at least one bump 14 located on top of the silicon nitride layer 13, then flip-chip processing is performed on each bump 14 of the plurality of first modules 10 to attach the chip 21 to the bump 14 of the first module 10, a plurality of second modules 20 (refer to fig. 4) are prepared, plastic package processing is sequentially performed on one second module 20, wafer flipping is performed on the glass substrate 11 of the second module 20, semiconductor process processing and flip-chip processing are performed on the bump 14 of the glass substrate 11 of the second module 20, a third module 30 (refer to fig. 3) is prepared, then one first module 10 is placed on the bump 14 of the third module 30, such that the bump 14 of the first module 10 is connected to the chip 21 of the third module 30, a plurality of second modules 20 are sequentially performed on the second module 20, and the semiconductor process processing is performed on the bump 11 of the second module 20 and the bump 14 of the second module 20 is stacked, such that the semiconductor process is performed on the bump 14 of the second module 20, and the semiconductor process is performed on the bump 14 of the second module 20, and the second module 20 is stacked, and the three-dimensional chip process is stacked between the second module 20 is achieved, and the chip process is finally stacked by the flip-chip process on the bump chip 21 and the chip 21 is connected to the chip module 40 and the chip 21 of the chip 21. Here, the number of bumps 14 of each first module 10 may be one, two or more, and the number of chips 21 of each second module 20 is the same as the number of bumps 14.
In this embodiment, the chip 21 is mounted on the bump 14 of the first module 10 by using flip-chip processing, so as to form the second module 20 with at least one chip 21 formed on the surface, the plastic packaging processing and wafer flip-chip processing are sequentially performed on the prepared second module 20, so as to flip-chip the glass substrate 11 of the second module 20 to the bottom surface, the semiconductor processing and flip-chip processing are performed on the glass substrate 11 of the second module 20, so as to form the third module 30 with the chip 21 mounted on the surface of the glass substrate 11 and the silicon nitride surface, one first module 10 is inverted on the third module 30, so that the bump 14 of the first module 10 is connected to the chip 21 of the third module 30, and the semiconductor processing is sequentially performed on the glass substrate 11 of the first module 10, so as to prepare the base module 40, and the plurality of second modules 20 are stacked on the base module 40 by using flip-chip processing, so that the chip 21 of the bottommost second module 20 is connected with the bump 14 of the first module 10 of the base module 40, the chip 21 of the adjacent second module 20 is connected with the bump 14 of the chip 14, and the chip 21 is stacked with the chip 11 by using the three-dimensional integrated chip, and the three-dimensional integrated chip 11 is manufactured by using the three-dimensional integrated chip 11, and the three-dimensional integrated chip 11 is reduced, and the three-dimensional integrated chip cost is reduced, and the three-dimensional integrated chip 11 is realized.
In this embodiment, silicon oxide and silicon nitride are sequentially deposited on the surface of the glass substrate 11 to form the oxide layer 12 and the silicon nitride layer 13 on the surface of the glass substrate 11, and since the oxide layer 12 and the silicon nitride layer 13 are insulating mediums, leakage and crosstalk between devices can be reduced, that is, when the chips 21 and the conductive layers formed by electroplating are electrically connected, the existence of the oxide layer 12 and the silicon nitride layer 13 can reduce leakage and crosstalk between signals between devices, and ensure the safety and stability of electrical connection between the chips 21, thereby reducing power consumption. Here, the material of the oxide layer 12 may be silicon oxide, aluminum oxide, or titanium oxide.
In a further embodiment, the semiconductor processing includes a substrate opening, a plating process, a chemical mechanical polishing process, and a bump process, i.e., a via is formed in the glass substrate 11 using the substrate opening, a conductive layer is deposited within the via using the plating process, and the conductive layer and the glass substrate 11 are diced using the chemical mechanical polishing process to provide a planar surface for bumps formed by a subsequent bump process.
In this embodiment, the electroplating process is an electrochemical electroplating process, that is, a conductive layer for electrical connection between the chips 21 is deposited in the glass substrate 11 or the oxide layer 12 and the silicon nitride layer 13 by electrochemical deposition, and the conductive layer may be copper or nickel, or may be other conductive metal materials.
In this embodiment, the electrochemical deposited conductive layer is polished to a preset thickness by using chemical mechanical polishing treatment, so as to ensure the flatness of the top surfaces of the conductive layer and the silicon nitride layer 13, ensure the uniformity and precision of the bump 14 prepared by the bump 14 process, improve the reliability of subsequent chip 21 mounting, and prevent the problems of poor contact, signal interference and the like caused by inconsistent height or position deviation of the bump 14. In addition, the flattening of the surface of the silicon nitride layer 13 by the chemical mechanical polishing treatment helps to reduce stress and prevent cracking or failure caused by excessive stress during packaging.
In this embodiment, the second module 20 is subjected to the plastic packaging process to seal the chip 21, the bump 14 and the microstructure 15 in the second module 20 in plastic, so that not only the mechanical strength of the second module 20 can be enhanced, the subsequent processing is facilitated, but also the failure of the solder joint contacting the bump 14 and the chip 21 due to thermal expansion can be prevented, and the structural stability of the three-dimensional integrated chip 100 is further improved.
In this embodiment, the glass material is used as the substrate, and the silicon dioxide is the main component of the glass, and the thermal conductivity coefficient of the silicon dioxide is 0.27W/cm·k, that is, the glass substrate 11 has a strong thermal conductivity, so that the three-dimensional integrated chip 100 prepared by the above process has a better heat dissipation performance.
In a further embodiment, step S500 further includes:
the base module 40 and at least one inverted second module 20, which are sequentially stacked, are subjected to a plastic sealing process.
In this embodiment, by performing one-time plastic packaging treatment on the substrate module 40 and the second module 20 which are sequentially stacked, it is possible to provide external mechanical protection for the stacked structure formed by the whole substrate module 40 and at least one second module 20 while ensuring plastic packaging consistency, which is helpful for improving the overall structural strength of the three-dimensional integrated chip 100 and preventing mechanical damage caused by external force in subsequent processing or use. Meanwhile, the plastic package can fix the relative position between the base module 40 and the second module 20, so that the relative displacement of the base module 40 and the second module 20 can be avoided in the subsequent processing and using processes, and the stability and reliability of the electrical connection between the modules are ensured.
In a further embodiment, the step of preparing a plurality of first modules 10 comprises:
Obtaining a pretreated microstructure 15, the microstructure 15 comprising at least one first through hole 151 penetrating to the top of the glass substrate 11;
The microstructure 15 is sequentially subjected to an electroplating process, a chemical mechanical polishing process, and a bump process to prepare the first module 10.
In this embodiment, the pretreated microstructure 15 is obtained first, and the electroplating treatment is performed in the first through hole 151 of the microstructure 15 to form a conductive layer in the first through hole 151, and then the chemical polishing treatment and the bump treatment are performed on the microstructure 15 after the electroplating treatment to form the bump 14 on the surface of the microstructure 15, so that the bump 14 with the surface formed with the bump 14 corresponding to the first through hole 151 is prepared, so that the second module 20 with the chip 21 attached thereon is formed later.
In this embodiment, the step of preprocessing includes:
sequentially depositing an oxide layer 12 and a silicon nitride layer 13 on a glass substrate 11;
a photolithography process and an etching process are sequentially performed on the surface of the silicon nitride layer 13 to form a first via 151 penetrating the oxide layer 12 and the silicon nitride layer 13 on top of the glass substrate 11.
In this embodiment, after the oxide layer 12 and the silicon nitride layer 13 are formed on the glass substrate 11 through the deposition process, the silicon nitride layer 13 is subjected to a photolithography process, and then the silicon nitride layer 13 and the oxide layer 12 are subjected to an etching process, so that the first through hole 151 is formed in the silicon nitride layer 13 and the oxide layer 12 of the microstructure 15, and through the photolithography process and the etching process, the position and the size of the through hole can be precisely controlled, the selective etching of the silicon nitride layer 13 and the oxide layer 12 is ensured, the subsequent deposition of the conductive layer in the first through hole 151 through the electroplating process is facilitated, and the process is mature and the operation is simple.
In a further embodiment, the step of sequentially performing the plastic packaging treatment on the second module 20 further includes:
the second module 20 after the plastic packaging process is bonded with the supporting layer 50.
In this embodiment, before the second module 20 is subjected to the subsequent substrate opening, electroplating and chemical mechanical polishing, the bonding process is required to be performed on the second module 20 after the plastic packaging process, so as to temporarily fix the second module 20 after the plastic packaging on the supporting layer 50, provide mechanical support while maintaining the flatness of the wafer, ensure the precision of the subsequent process, avoid the breakage, warpage or deformation of the wafer or the chip 21 in the second module 20, and prevent the performance of the final product from being affected.
In this embodiment, the plastic packaging process is an epoxy injection molding process, which can provide external mechanical support, prevent the chip 21 from generating micro cracks, and improve the electrical reliability of the package. In other embodiments, the plastic encapsulation process may also be replaced with a glass encapsulation.
In a further embodiment, the glass substrate 11 further includes a second through hole 111, and the ratio of the intersecting surface of the second through hole 111 and the first through hole 151 is any value from 0.5 to 0.8, that is, the ratio of the intersecting surface of the second through hole 111 in the glass substrate 11 and the first through hole 151 of the silicon nitride layer 13 and the oxide layer 12 may be any value from 0.5, 0.6, 0.7 or 0.8, or may be any value from 0.5 to 0.8. By setting the ratio of the second through hole 111 to the first through hole 151 within the above range, the alignment connection of the first through hole 151 and the second through hole 111 is ensured, thereby ensuring that the conductive layer after the electroplating treatment realizes electrical connection and ensuring that signal transmission is not disturbed.
In a further embodiment, each electroplating process is preceded by:
A barrier layer and a seed layer are sequentially deposited within the first via 151.
In this embodiment, before the electroplating process, a barrier layer and a seed layer are first deposited in the first through hole 151, and then a conductive layer is deposited on the surface of the seed layer, so as to ensure the reliability of the electroplating process, improve the quality of metal deposition, and enhance the electrical performance between the layers of chips 21 in the final three-dimensional integrated chip 100.
In a further embodiment, the first through hole 151 is disposed to penetrate through the oxide layer 12 and the silicon nitride layer 13 and has a variable cross section gradually expanding from bottom to top, and the variable cross section makes the cross section of the upper portion of the first through hole 151 wider, so that metal can more smoothly enter and fill the whole first through hole 151, the filling uniformity is improved, the defect rate is reduced, the situation that the top of the straight cylindrical through hole is sealed prematurely in the electroplating deposition process can be prevented, and the situation that gaps or cracks are generated due to incomplete filling in the through hole is prevented.
In a further embodiment, the way of opening the hole on the substrate is to sequentially perform the photolithography and etching processes on the glass substrate 11, where the photolithography process and the etching process can implement high-precision micro-hole processing, so as to meet the requirement of high-density interconnection, improve the mechanical stability of the glass substrate 11, reduce the cracks and stress concentration, and facilitate the subsequent electroplating process on the first through hole 151 or the second through hole 111, so as to ensure the structural mechanical stability of the three-dimensional integrated chip 100.
As shown in fig. 2, the present invention also provides a three-dimensional integrated chip 100 prepared according to the above-described preparation method. The three-dimensional integrated chip 100 comprises a substrate module 40 and at least one second module 20 which are sequentially stacked from bottom to top, wherein the substrate module 40 is connected with the second module 20 and the plurality of second modules 20 through chips 21 and bumps 14. The method for manufacturing the three-dimensional integrated chip 100 is not described in detail herein.
In this embodiment, the bumps 14 corresponding to the chips 21 in the second module 20 are formed on the surface of the glass substrate 11 on top of the base module 40, so that the second module 20 is connected with the base module 40 through the connection between the chips 21 and the bumps 14, and thus the three-dimensional stacking of the chips 21 is realized by using the semiconductor manufacturing technology, and the manufacturing difficulty and the production cost are reduced.
In this embodiment, the number of the second modules 20 in each three-dimensional integrated chip 100 may be one, two or more, and the number of the second modules 20 may be selected according to the actual requirements of production. When the number of the second modules 20 in each three-dimensional integrated chip 100 is one, stacking of the three-layer chips 21 is realized in the three-dimensional integrated chip 100, that is, in the three-dimensional integrated chip 100 at this time, the three-layer chips 21 are sequentially stacked from bottom to top and electrical connection between the three-layer chips 21 is realized by the plated conductive layers located in the first through holes 151 of the microstructures 15 and the second through holes 111 of the glass substrate 11 in the base module 40, thereby realizing stacking of the three-layer chips 21.
In this embodiment, when the number of the second modules 20 in each three-dimensional integrated chip 100 is two, the two second modules 20 are stacked on the base module 40, and the chip 21 of the second module 20 far from the base module 40 is connected with the bump 14 of the second module 20 near to the base module 40 by flip-chip processing to realize the electrical connection between the two second modules 20, and the chip 21 of the second module 20 near to the base module 40 is connected with the bump 14 on the top of the base module 40 by flip-chip processing to realize the electrical connection between the second module 20 and the base module 40, thereby realizing the stacking of four layers of chips 21.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the invention, which are described in detail and are not to be construed as limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.
Claims (10)
1. The preparation method of the three-dimensional integrated chip is characterized by comprising the following steps of:
Preparing a plurality of first modules, wherein the first modules comprise a glass substrate, an oxide layer and a silicon nitride layer which are sequentially stacked from bottom to top, and each first module is provided with at least one protruding point positioned on the top of the silicon nitride layer;
performing flip-chip processing on each bump of the first modules to perform chip mounting so as to prepare second modules;
Sequentially performing plastic packaging treatment and wafer overturning on one second module, and performing semiconductor process treatment and flip-chip treatment on the glass substrate of the second module to attach chips on the salient points of the glass substrate of the second module, so as to prepare and obtain a third module;
The first module is arranged on the third module in an inverted mode, so that the convex points of the first module are connected with the chip of the third module, and the semiconductor process treatment is sequentially carried out on the glass substrate in the first module to form a base module;
And laminating at least one inverted second module on the substrate module through flip-chip treatment, so that the chip of the bottommost second module is connected with the convex points of the first module of the substrate module, and when the number of the second modules is multiple, the chips among the adjacent second modules are connected with the convex points, so that the three-dimensional integrated chip is prepared and obtained.
2. The method of manufacturing according to claim 1, wherein the step of disposing at least one inverted second module on the base module by flip-chip lamination further comprises:
and carrying out plastic packaging treatment on the substrate module and the at least one inverted second module which are sequentially stacked.
3. The method according to claim 2, wherein,
The semiconductor processing technology comprises substrate opening, electroplating treatment, chemical mechanical polishing treatment and bump treatment.
4. A method of manufacturing as claimed in claim 3, wherein the step of manufacturing a plurality of first modules comprises:
obtaining a pretreated microstructure comprising at least one first through hole penetrating to the top of the glass substrate;
and sequentially performing the electroplating treatment, the chemical mechanical polishing treatment and the bump treatment on the microstructure to prepare the first module.
5. The method according to claim 4, wherein the step of sequentially performing the plastic packaging treatment on the second module further comprises:
and bonding the second module subjected to the plastic packaging treatment and the supporting layer.
6. The method according to claim 5, wherein,
The glass substrate further comprises a second through hole, and the ratio of the intersecting surface of the second through hole and the first through hole is any value of 0.5-0.8.
7. The method of manufacturing according to claim 6, wherein each of the plating treatments is preceded by:
And depositing a blocking layer and a seed layer in the first through hole in sequence.
8. The method of manufacturing according to claim 7, wherein the first through hole is provided penetrating the oxide layer and the silicon nitride layer and has a gradually expanding cross section from bottom to top.
9. The method according to any one of claim 1 to 8, wherein,
The way of opening the substrate is to sequentially carry out photoetching treatment and etching treatment on the glass substrate.
10. A three-dimensional integrated chip prepared according to the preparation method of any one of claims 1 to 9.
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| CN202510160973.XA CN120109024A (en) | 2025-02-13 | 2025-02-13 | A three-dimensional integrated chip and its preparation method |
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| CN202510160973.XA CN120109024A (en) | 2025-02-13 | 2025-02-13 | A three-dimensional integrated chip and its preparation method |
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