CN120070247B

CN120070247B - Sampling point rearrangement method, device, equipment and storage medium

Info

Publication number: CN120070247B
Application number: CN202510532793.XA
Authority: CN
Inventors: 请求不公布姓名
Original assignee: Mole Thread Intelligent Technology Beijing Co ltd
Current assignee: Mole Thread Intelligent Technology Beijing Co ltd
Priority date: 2025-04-25
Filing date: 2025-04-25
Publication date: 2025-09-05
Anticipated expiration: 2045-04-25
Also published as: CN120070247A

Abstract

The application discloses a rearrangement method, a rearrangement device, a rearrangement equipment and a storage medium of sampling points, and belongs to the field of image data processing. The method comprises the steps of reading m sampling points arranged according to a first arrangement mode from a storage unit, wherein the m sampling points are sampling points in at least one pixel point, the first arrangement mode is an arrangement mode based on sampling point index arrangement of the m sampling points, m is a positive integer, rearranging the m sampling points to obtain m sampling points arranged according to a second arrangement mode, the second arrangement mode is an arrangement mode based on position arrangement of the m sampling points in the at least one pixel point, and storing the m sampling points arranged according to the second arrangement mode into the storage unit. For m sampling points stored in the storage unit, the position information of the sampling points is recovered, so that the execution of various algorithms based on the position information of the sampling points is facilitated.

Description

Method, device, equipment and storage medium for rearranging sampling points

Technical Field

The present application relates to the field of image data processing, and in particular, to a method, an apparatus, a device, and a storage medium for rearranging sampling points.

Background

Multisampling antialiasing (Multi-SAMPLING ANTI-Aliasing, MSAA) is an antialiasing method that enables a rendered image edge to be smoother by performing multiple sampling computations on a pixel and eventually aggregating the pixel information for that pixel.

When the MSAA technique is used, the image is stored in the storage unit, and instead of storing the pixel information corresponding to the pixel points in the storage unit, the sampling point information of each sampling point needs to be stored in the storage unit. However, the related art does not adapt the storage manner of the sampling points in the storage unit, which results in that the sampling points can only be stored in the storage unit according to the sampling point index.

But the way in which the sample point index is stored is not friendly to some algorithms that need to be applied to the position information of the sample point.

Disclosure of Invention

The application provides a rearrangement method, a rearrangement device, a rearrangement equipment and a storage medium of sampling points, wherein the technical scheme is as follows:

according to an aspect of the present application, there is provided a sample point rearrangement method, the method including:

Reading m sampling points arranged according to a first arrangement mode from a storage unit, wherein the m sampling points are sampling points in at least one pixel point, the first arrangement mode is an arrangement mode based on sampling point index arrangement of the m sampling points, and m is a positive integer greater than 1;

rearranging the m sampling points to obtain m sampling points which are arranged according to a second arrangement mode, wherein the second arrangement mode is an arrangement mode based on the position arrangement of the m sampling points in the at least one pixel point;

and storing the m sampling points arranged according to the second arrangement mode into the storage unit.

According to an aspect of the present application, there is provided a sample point rearrangement apparatus, the apparatus including:

The acquisition module is used for reading m sampling points which are arranged according to a first arrangement mode from the storage unit, wherein the m sampling points are sampling points in at least one pixel point, the first arrangement mode is an arrangement mode based on sampling point index arrangement of the m sampling points, and m is a positive integer greater than 1;

the rearrangement module is used for rearranging the m sampling points to obtain m sampling points which are arranged according to a second arrangement mode, wherein the second arrangement mode is an arrangement mode based on the position arrangement of the m sampling points in the at least one pixel point;

and the storage module is used for storing the m sampling points which are arranged according to the second arrangement mode into the storage unit.

According to an aspect of the application, a computer device is provided, and the computer device comprises a processor and a memory, wherein at least one section of program is stored in the memory, and the processor is used for executing the at least one section of program in the memory to realize the rearrangement method of the sampling points.

According to an aspect of the present application, there is provided a computer-readable storage medium having stored therein executable instructions that are loaded and executed by a processor to implement the above-described sample point rearrangement method.

According to an aspect of the present application, there is provided a computer program product comprising computer instructions stored in a computer readable storage medium, from which a processor reads and executes the computer instructions to implement the above-described sample point rearrangement method.

The technical scheme provided by the application has the beneficial effects that at least:

M sampling points originally stored in the storage unit according to the first arrangement mode, namely m sampling points stored based on the sampling point index, are rearranged into m sampling points stored in the second arrangement mode, namely m sampling points stored based on the position of each sampling point in the m sampling points in at least one pixel point. For the storage of the sampling points, the position information of the sampling points in at least one pixel point (or called image or image block) is introduced, so that m sampling points arranged according to a second arrangement mode support various algorithms needing to use the position information, such as an image compression algorithm. The method avoids the loss of the position information of the sampling points in the storage process of the m sampling points, and improves the storage flexibility of the m sampling points. And, store based on the second arrangement mode of the position of m sampling points in at least one pixel point, it is more friendly to access the data access mode of the memory cell based on the position information, can improve the access efficiency to m sampling points in the memory cell and improve the inquiry performance.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 shows a schematic diagram of an image compression process;

FIG. 2 is a schematic diagram showing an arrangement of images in a memory cell;

FIG. 3 is a schematic diagram showing another arrangement of images in a memory cell;

FIG. 4 illustrates an architecture diagram of a computer system provided by an exemplary embodiment of the present application;

FIG. 5 is a flow chart illustrating a sample point rearrangement method according to one exemplary embodiment of the present application;

FIG. 6 is a flow chart illustrating a sample point rearrangement method according to another exemplary embodiment of the present application;

FIG. 7 illustrates a schematic diagram of a standard sampling location provided by an exemplary embodiment of the present application;

FIG. 8 is a schematic diagram of a sample point rearrangement method according to an exemplary embodiment of the present application;

FIG. 9 is a diagram illustrating a manner in which pixel index is determined according to an exemplary embodiment of the present application;

FIG. 10 is a schematic diagram of a sample point rearrangement method according to another exemplary embodiment of the present application;

FIG. 11 is a schematic diagram illustrating an arrangement of sampling points according to an exemplary embodiment of the present application;

FIG. 12 is a schematic diagram of a sample point rearrangement method according to still another exemplary embodiment of the present application;

fig. 13 is a schematic diagram illustrating a sample point rearrangement method according to still another exemplary embodiment of the present application;

fig. 14 is a block diagram showing a structure of a sample point rearranging apparatus according to an exemplary embodiment of the present application;

fig. 15 shows a schematic structural diagram of a computer device according to an exemplary embodiment of the present application.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the embodiments of the present application will be described in further detail with reference to the accompanying drawings.

Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the application. Rather, they are merely examples of apparatus and methods consistent with aspects of the application as detailed in the accompanying claims.

The terminology used in the present disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used in this disclosure and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It should be noted that, the user information (including but not limited to user equipment information, user personal information, etc.) and the data (including but not limited to data for analysis, stored data, presented data, etc.) related to the present application are information and data authorized by the user or sufficiently authorized by each party, and the collection, use and processing of the related data need to comply with the related laws and regulations and standards of the related country and region. For example, information such as setting operation involved in the present application is obtained under a sufficient authorization.

It should be understood that, although the terms first, second, etc. may be used in this disclosure to describe various information, these information should not be limited by these terms. These terms are only used to distinguish one type of information from another. For example, a first parameter may also be referred to as a second parameter, and similarly, a second parameter may also be referred to as a first parameter, without departing from the scope of the present disclosure. The term "if" as used herein may be interpreted as "at..once" or "when..once" or "in response to a determination", depending on the context.

First, a description is made of related nouns to which the present application relates.

Image compression Image Compressions is a technique to reduce the size of an image file. Image compression may be achieved by reducing the amount of data in the image while maintaining the visual quality of the image as much as possible. In hardware, particularly in GPUs (Graphics Processing Unit, graphics processors), image compression is a common technique used to reduce bandwidth transmission requirements. In general, image compression requires the use of positional information between pixels (pixels) in order to achieve a higher compression rate. Illustratively, in the image compression technique as shown in fig. 1, for a frame image 10 of a certain frame taken out of video or animation, the compression unit 11 is a hardware or software component for performing data compression and decompression operations in the GPU, the compression unit 11 reads one image block 12 in the frame image 10, and processes the image block 12 within the compression unit 11 using wavelet domain transformation, generating four pieces of information, namely, a portion 13 of upper left low frequency information, a portion 14 of lower left high frequency level information, a portion 15 of upper right high frequency vertical information, and a portion 16 of lower right high frequency diagonal information. After the wavelet domain transformation, each pixel in the four parts of information may be encoded for data compression, for example, for each 2×2 pixel information, for example, 2×2 pixel information is taken from the upper left corner low frequency information part 13, and the pixel information on each pixel point is used to indicate the color information, for example, the gray value, of the pixel point. The extracted 2×2 pixel information, that is, the pixel information 17 of 4 pixels, where the pixel information of each pixel includes 8 bits, the pixel information 17 of 4 pixels includes 32 bits, and for the extracted 4 pixels, performing data compression may be understood as extracting a common portion in the pixel information 17 of 4 pixels, and determining that the pixel information of each pixel in the 4 pixels includes 30 s, so that compression may be performed on the common portion and the non-common portion to obtain compressed pixel information 18, where the compressed pixel information includes 5 portions, where a first portion represents the common portion of the 4 pixels, that is, "011 (i.e., 3)" 0s, and a second portion to a fifth portion represent the non-common portion of the 4 pixels, respectively. Thereby realizing compression of 32-bit pixel information to 23 bits. The above-described image compression method first requires wavelet frequency domain transformation, which essentially performs frequency domain transformation on the original image information, and stores the high-frequency and low-frequency signals respectively. This requires hardware to be able to restore the positional information between pixel information successively stored in the memory to the positional information in the original image.

In GPU, the original image is usually placed in the memory in two modes, linear Layout (Twiddle Layout) and staggered Layout (Linear Layout).

And (3) linearly arranging pixel information of the same row of images or image blocks on continuous addresses in a memory, and arranging pixel information of the next row after each row of pixel information. In other words, the addresses of the same row of adjacent pixel information of the image or the image block are continuous in the memory, as shown in fig. 2, among the pixel information stored in the memory 20 of the image block 19, the pixel information of the 1 st row in the image block 19, that is, the pixel information of the pixel points in coordinates (0, 0) to (0, 3) are stored in the virtual addresses 0x8000 0004 to 0x8000 0007, the pixel information of the 2 nd row in the image block 19, that is, the pixel information of the pixel points in coordinates (1, 0) to (1, 3), the pixel information of the 3 rd row in the image block 19, that is, the pixel information of the pixel points in coordinates (2, 0) to (2, 3) are stored in the virtual addresses 0x8000 0008 to 0x8000 000B, and the pixel information of the 4 th row in the image block 19, that is, the pixel information of the pixel points in coordinates (3, 0) to (3, 0x8000 000F) are stored in the virtual addresses 0x8000 0008 to 0x8000 f.

The staggered arrangement may also be referred to as Tile Layout (Tile Layout). Dividing pixels in an image or an image block to obtain a plurality of groups of pixels, wherein each group of pixels is positioned in a rectangle or a tile, and each group of pixels is stored in a memory according to a fixed sequence. The fixed Order may be a Z-sequence arrangement (Z-Order Curve). As shown in fig. 3, the image block 19 is divided into 4 tiles, each tile includes 2×2 pixels, and the pixels in each tile are stored in the memory 20 in a z-sequence arrangement, and each tile is also stored in the memory 20 in a z-sequence arrangement. The virtual addresses 0x8000 0000 to 0x8000 0003 store pixel information of the first tile, i.e. pixel information of the pixel points in coordinates (0, 0), (1, 0), (0, 1), (1, 1), the virtual addresses 0x8000 0004 to 0x8000 0007 store pixel information of the second tile, i.e. pixel information of the pixel points in coordinates (2, 0), (3, 0), (2, 1), (3, 1), the virtual addresses 0x8000 0008 to 0x8000 000B store pixel information of the pixel points in the third tile, i.e. pixel information of the pixel points in coordinates (0, 2), (1, 2), (0, 3), (1, 3), and the virtual addresses 0x8000 000C to 0x8000 000F store pixel information of the pixel points in the fourth tile, i.e. pixel information of the pixel points in coordinates (2, 2), (3, 000 f).

When the compression unit takes a memory address storing original image information, the relation between the original pixels is restored according to the arrangement mode of the compression unit. As shown in fig. 2, at Linear Layout, the pixel information stored on 0x8000 0000 and 0x8000 0003 is restored to the pixel information of coordinates (0, 0) and (0, 2), and at Twiddle Layout, the pixel information on these two addresses is restored to the pixel information of coordinates (0, 0) and (0, 1) as shown in fig. 3.

MSAA (Multi-SAMPLE ANTI-Alias) is an antialiasing technique, which is to calculate and finally gather the pixel information of a pixel point by sampling multiple times on the pixel point, so that the edge of the drawn image is smoother. That is, one pixel is further subdivided to obtain a plurality of sampling points. Thus, a plurality of sampling points in each pixel point can independently interpolate and independently execute fragment coloring to calculate independent color values and depth values. And then, calculating the arithmetic average value of all sampling points of the same pixel point to obtain the final color of the pixel point. In this way, the drawing of the graphic edges will be finer and smoother. Of course, MSAA4 is a double increase in computational power for 1920×1280 grids, which corresponds to processing 1920×1280×4 grids.

Physical address-an address in the actual physical memory that points directly to a specific location on the memory bank. The physical addresses are hardware-level addresses that are used directly by the CPU (Central Processing Unit ), memory controller, and other hardware to access data in memory. Physical addresses are real, directly accessible memory addresses that are typically translated from virtual addresses by a memory management unit (Memory Management Unit, MMU).

Virtual address is an address in the address space provided by the operating system for each process. It is an address under the view of the process for accessing memory. The virtual address space is created by the operating system for the processes through virtual memory management techniques, which allows each process to have an independent address space, thereby achieving memory protection and isolation. In a virtual memory system, virtual addresses need to be translated to physical addresses by an MMU, a process called address translation (Address Translation).

FIG. 4 illustrates a block diagram of a computer system provided in an exemplary embodiment of the application. The computer system includes a computer device 110.

Alternatively, the computer device 110 may be at least one of a portable computer, a desktop computer, a server cluster, an artificial intelligence (ARTIFICIAL INTELLIGENCE, AI) computing cluster, a cloud computing cluster. The AI computing clusters may also be simply referred to as intelligent computing clusters or intelligent computing clusters.

For images using MSAA technology, multiple sampling points are included in each pixel. The location of the sample points within the pixel points is typically specified by a graphics standard, but also allows the user to customize the location of the sample points using programmable sample location (Programmable Sample Location) techniques. In the related art, the storage manner of the related information of the sampling points is not distinguished according to the above-mentioned 2 sampling point location definition manners, and the related information of the sampling points is sequentially stored in the memory 20 according to the first arrangement manner shown in fig. 4, that is, according to the sampling point index order. That is, for the pixel points 21 of the MSAA8X, the sampling points 0 to 7 (i.e., S0 to S7) are stored in the memory 20 in the order of the sampling point indexes from 0 to 7, although the positional relationship between the sampling point positions varies from top to bottom to left to right. If the compression unit performs the interleaving recovery based on the interleaving arrangement, the compression unit is resolved into the situation shown by the pixel points 22 in fig. 4, and the first arrangement 23 stored in the memory 20 according to the sampling point index order is not beneficial for the compression unit or the GPU to recover the position information of the sampling points inside the pixel points.

According to the method provided by the embodiment of the application, the sampling points in the memory are rearranged so that the position information of the sampling points can be recovered in the compression unit or the GPU. The specific procedure is as follows.

(1) And acquiring m sampling points and m first storage addresses.

Alternatively, the m first storage addresses refer to virtual addresses when m sampling points are stored in the memory 20 according to the sampling point index.

(2) And rearranging the m sampling points to obtain m second storage addresses.

Optionally, the storage address of each of the m sampling points is changed based on the order of the m sampling points indicated by the m first storage addresses, so that the m sampling points stored in the obtained m second storage addresses are arranged according to the positions of the sampling points in the pixel points, such as from left to right and from top to bottom, thereby obtaining m second storage addresses of the m sampling points stored in the order of "s3→s7→s5→s0→s1→s2→s4→s6". The storage sequence relates to an application scene of m sampling points, for example, when the storage sequence is applied to an image compression scene, the storage sequence relates to a mapping rule of a compression unit. The mapping rule of the compression unit refers to a rule that the compression unit reads a plurality of sampling points from the storage unit and then maps each sampling point to a different position of a corresponding pixel point, or the mapping rule of the compression unit refers to a rule that the compression unit reads a plurality of sampling points from the storage unit and then maps each sampling point to a different position of an image or an image block.

That is, for m sampling points corresponding to m second storage addresses, an effect as shown by the pixel points 24 in fig. 4 is obtained after the use of the interlace recovery, and the pixel points 24 arranged according to the second arrangement 25 retain the position information of each sampling point compared with the pixel points 22 arranged according to the first arrangement 23.

(3) Stored back in the memory 20.

Optionally, m sampling points arranged according to the second arrangement 25 are restored back to the memory 20, so that the subsequent other units, such as the compression unit, directly read the relevant information of the sampling points with the position information from the memory 20.

Fig. 5 is a flowchart illustrating a sample point rearrangement method according to an embodiment of the present application. The method is performed by a computer device, which may be a computer device as shown in fig. 4 described above. The method comprises the following steps.

Step 210, reading m sampling points arranged according to a first arrangement mode from a storage unit, wherein the m sampling points are sampling points in at least one pixel point, the first arrangement mode is an arrangement mode based on sampling point index arrangement of the m sampling points, and m is a positive integer greater than 1.

The method comprises the steps of reading m sampling points arranged according to a first arrangement mode from a storage unit, or reading at least one pixel point from the storage unit, wherein the at least one pixel point comprises m sampling points which are arranged according to the first arrangement mode, or reading m sampling points corresponding to the at least one pixel point from the storage unit, and the m sampling points are arranged according to the first arrangement mode.

Optionally, each pixel point in the at least one pixel point comprises m sampling points, and the sampling point indexes of the m sampling points included in each pixel point are different or the sampling point indexes of the m sampling points included in each pixel point are the same.

Illustratively, the sampling point index of the m sampling points included in each pixel point is the same. The sampling point index is used for indicating the index of the sampling point in the pixel points where the sampling point is located, for example, each pixel point comprises 2 sampling points, the sampling point index of the 2 sampling points which are included in the pixel point 0 is respectively 0 and 1, the sampling point index of the 2 sampling points which are included in the pixel point 1 is respectively 0 and 1, the sampling point index of the 2 sampling points which are included in the pixel point 2 is respectively 0 and 1, and the sampling point index of the 2 sampling points which are included in the pixel point 3 is respectively 0 and 1.

Illustratively, the m sampling points included in each pixel point have different sampling point indexes. For example, a sample point index is used to indicate the index of a sample point in an image or image block. If each pixel includes 2 sampling points, the sampling point index of each sampling point is determined based on the index of the sampling point in the pixel point where it is located and the index of the pixel point in the image or image block. The sampling point indexes of 2 sampling points included in the pixel point 0 may be represented as P0S0 and P0S1, wherein P0 represents the index of the pixel point in the image or the image block, S0 and S1 represent the indexes of the sampling points in the pixel point where the sampling point is located, the sampling point indexes of 2 sampling points included in the pixel point 1 may be represented as P1S0 and P1S1, the sampling point indexes of 2 sampling points included in the pixel point 2 may be represented as P2S0 and P2S1, and the sampling point indexes of 2 sampling points included in the pixel point 3 may be represented as P3S0 and P3S1.

It should be noted that, in the embodiment of the present application, the sampling point indexes of the m sampling points included in each pixel point are the same, that is, the sampling point index is used to indicate the index of the sampling point in the pixel point where the sampling point is located, or the sampling point index of the sampling point is used to indicate the index in the pixel point corresponding to the sampling point. The embodiments of the present application are not limited in this regard.

Step 220, rearranging the m sampling points to obtain m sampling points arranged according to a second arrangement mode, wherein the second arrangement mode is an arrangement mode based on the position arrangement of the m sampling points in at least one pixel point.

And rearranging the m sampling points to obtain m sampling points arranged according to a second arrangement mode, or rearranging the m sampling points according to indication information to obtain m sampling points arranged according to the second arrangement mode, wherein the indication information is used for indicating that the rearranged arrangement mode is the second arrangement mode.

Optionally, at least one pixel point is located in the image or the image block, and the second arrangement mode is an arrangement mode based on the position arrangement of m sampling points in the image, or the second arrangement mode is an arrangement mode based on the position arrangement of m sampling points in the image block.

Alternatively, the arrangement may be understood as a storage order in the storage unit, or the arrangement may be understood as a sequence of m sampling points in the storage unit, or the arrangement may be understood as a sequence of storage addresses corresponding to the m sampling points in the storage unit. The storage unit comprises a storage unit, a first arrangement mode and a second arrangement mode, wherein the storage unit is used for storing m sampling points, the first arrangement mode and the second arrangement mode are used for storing m sampling points, or the first arrangement mode and the second arrangement mode are used for storing m sampling points, and the first arrangement mode and the second arrangement mode are used for storing m sampling points.

Optionally, in the field of image compression, the first arrangement is an arrangement that is not related to the mapping rule of the compression unit, and the second arrangement is an arrangement that is related to the mapping rule of the compression unit. Or, the first arrangement mode is an arrangement mode based on the arrangement of the sampling point indexes of the m sampling points, and the sampling point indexes of the m sampling points are irrelevant to the mapping rule of the compression unit. The second arrangement mode is an arrangement mode based on a mapping rule of the compression unit and the position arrangement of m sampling points in at least one pixel point. It can also be said that the first arrangement is not an arrangement arranged in the mapping order of the compression units, and the second arrangement is an arrangement arranged in the mapping order of the compression units. Wherein the compression unit is a unit for performing a compression algorithm on an image or image block. The mapping rule of the compression unit refers to a rule that the compression unit reads a plurality of sampling points from the storage unit and then maps each sampling point to different positions of the corresponding pixel point, or the mapping rule of the compression unit refers to a rule that the compression unit reads a plurality of sampling points from the storage unit and then maps each sampling point to different positions of an image or an image block. The mapping rule of the compression unit is not related to the first arrangement or the sampling point index is not set according to the mapping rule, but is based on other rules, such as the sampling point index is determined based on a standard sampling position formulated by a graphic standard, or the sampling point index is determined based on a programmable sampling position set by a user.

Illustratively, each of the at least one pixel includes 8 sampling points. For the first arrangement, 8 sampling points of each pixel point are sequentially stored in the storage unit according to the sampling point index, but for different pixels in at least one pixel point, each pixel point may be stored in the order of the pixel point index, or may be stored according to the position of the pixel point in the image or the image block. For the second arrangement, m sampling points are taken as independent points in the image or the image block, and the sequence of each pixel point in the m sampling points is determined according to the actual positions of the m sampling points in the image or the image block, that is, the storage positions of the sampling points belonging to the same pixel point at the moment can be adjacent or not adjacent, which depends on the mapping rules of the storage unit or the compression unit for different storage positions. For example, the above-described fig. 2 and 3 illustrate two different mapping rules for pixel points.

And 230, storing the m sampling points arranged according to the second arrangement mode into a storage unit.

And re-storing the m sampling points arranged according to the second arrangement mode into a storage unit to obtain m sampling points stored according to the second arrangement mode.

Alternatively, the above-described m sampling points may also understand the related information of the m sampling points, or the sampling point information of the m sampling points, or the pixel information (color value, depth value, transparency, etc.) of the m sampling points, and so on.

In summary, in the method provided by the embodiment of the present application, m sampling points originally stored in the storage unit according to the first arrangement manner, that is, m sampling points stored based on the sampling point index are rearranged into m sampling points stored in the second arrangement manner, that is, m sampling points stored based on the position of each sampling point in the m sampling points in at least one pixel point. For the storage of the sampling points, the position information of the sampling points in at least one pixel point (or called image or image block) is introduced, so that m sampling points arranged according to a second arrangement mode support various algorithms needing to use the position information, such as an image compression algorithm. The method avoids the loss of the position information of the sampling points in the storage process of the m sampling points, and improves the storage flexibility of the m sampling points. And, store based on the second arrangement mode of the position of m sampling points in at least one pixel point, it is more friendly to access the data access mode of the memory cell based on the position information, can improve the access efficiency to m sampling points in the memory cell and improve the inquiry performance.

The rearrangement method is further described below.

In an alternative embodiment based on fig. 5, as shown in fig. 6, the above-mentioned step 220 may be implemented as steps 221 to 223.

Step 221, obtaining m first storage addresses of m sampling points in a storage unit, wherein the m first storage addresses are in one-to-one correspondence with the m sampling points.

Optionally, the m first storage addresses are virtual addresses, or physical addresses. The embodiment of the application is described by taking the first storage address and the second storage address as virtual addresses as examples, but the protection scope of the embodiment of the application is not limited to this.

Alternatively, the obtaining of m first storage addresses of m sampling points in the storage unit may be understood as obtaining first storage addresses of respective sampling points of the m sampling points in the storage unit. Wherein the first memory address of each sampling point is used for indicating the memory location of each sampling point in the memory cell.

In some embodiments, the step 221 may be performed simultaneously with the step 210 or in a switching sequence, that is, the first storage addresses of the respective sampling points in the storage unit are obtained while the m sampling points are read, or the m sampling points are read after the m first storage addresses of the m sampling points in the storage unit are read, or the m first storage addresses of the m sampling points in the storage unit are read after the m sampling points are read.

Step 222, determining m second storage addresses based on the m first storage addresses, wherein the second storage addresses are in one-to-one correspondence with the m sampling points, and the m second storage addresses are different from the m first storage addresses.

Optionally, the second storage address of each sampling point is determined based on the first storage address of each sampling point in the m sampling points, so as to obtain m second storage addresses. That is, rearrangement of the m sampling points is achieved by a change in the storage address for each of the m sampling points.

Optionally, m second storage addresses are determined based on the mapping rules of the m first storage addresses and the compression unit.

Step 223, determining m sampling points arranged according to the second arrangement mode based on the m second storage addresses.

Optionally, m sampling points arranged according to the second arrangement mode are determined based on m second storage addresses, or storage positions of the m sampling points in the storage unit are determined based on the m second storage addresses, and m sampling points are rearranged based on the storage positions of the m sampling points in the storage unit to obtain m sampling points arranged according to the second arrangement mode.

It should be noted that, the first storage address refers to an original storage address of m sampling points in the storage unit, and the second storage address is a storage address to be stored in the m sampling points determined based on the rearrangement method shown in the embodiment of the present application, but after the m sampling points are stored in the storage unit in the step 230, the m second storage addresses become storage addresses actually corresponding to the m sampling points after being rearranged. That is, the second storage address may be understood as an analog storage address, when m samples are stored in step 230, the samples may be stored according to m second storage addresses, or m samples determined according to the m second storage addresses and arranged according to the second arrangement may be stored in the storage unit instead of the m second storage addresses, that is, the m samples arranged according to the second arrangement correspond to m third storage addresses in the storage unit, where the m third storage addresses are different from the m second storage addresses, and the m samples corresponding to the m third storage addresses and the m second storage addresses are all arranged according to the second arrangement.

Optionally, the sampling point positions of the m sampling points included in each of the at least one pixel point are standard sampling positions, or programmable sampling positions. The standard sampling position refers to a sampling point position determined according to a graph standard. The programmable sampling location refers to a sampling point location set by a user or developer.

The standard sampling position and the programmable sampling position are both sampling modes of a pointer to one pixel point. The standard sampling position means that sampling point positions of a plurality of sampling points within one pixel point are predetermined by a graphic standard. A programmable sampling location refers to a sampling point location of a plurality of sampling points within a pixel point that is set by a user or developer. The standard sampling position is shown in fig. 7, and in the case where one pixel includes 2 sampling points, the standard sampling position is shown in part (1) in fig. 7, which may be referred to as using the MSAA2 technique, in the case where one pixel includes 4 sampling points, the standard sampling position is shown in part (2) in fig. 7, which may be referred to as using the MSAA4 technique, and in the case where one pixel includes 8 sampling points, the standard sampling position is shown in part (3) in fig. 7, which may be referred to as using the MSAA8 technique. For programmable locations, a user or developer is supported to set the number of sampling points and the sampling point locations (or sampling locations) included in a pixel.

Optionally, the mapping rule of the compression unit is set based on a standard sampling position, or the mapping rule of the compression unit is set based on a programmable sampling position.

In summary, the method shown in the embodiment of the present application shows a rearrangement method of m sampling points, where m first storage addresses in a storage unit of m sampling points are changed to obtain m second storage addresses, where the first storage addresses corresponding to each sampling point can represent a sequence of each sampling point in the m sampling points when the sampling points are arranged according to a first arrangement manner, that is, the m first storage addresses can represent a first arrangement manner, and the second storage addresses can represent a second arrangement manner.

In addition, the sampling point position of each sampling point in at least one pixel point supports a standard sampling position and also supports a programmable sampling position, so that the expandability of the sampling point rearrangement method provided by the embodiment of the application is improved. And for the standard sampling position, the method provided by the embodiment of the application can better restore the position information among the sampling points, and reduce the probability of high-frequency signal generation so as to improve the compression rate. For programmable sampling positions, the method provided by the embodiment of the application provides a means for more flexible recovery of the position information of the sampling points for the driver.

The determination manner for the m second storage addresses is as follows.

Determining mode one, address rearrangement (Address Swizzle).

And determining a second mode, namely determining a Look-Up Table (LUT).

Next, an introduction is made to the two determination modes shown above (the introduction order does not represent the merits and merits of the determination modes).

Determining a mode one, namely address rearrangement.

In some embodiments, the step 222 may be implemented by, for the ith first storage address in the m first storage addresses, obtaining the last n bits of the ith first storage address, wherein the last n bits of the last n bits are used for indicating the sampling point index of the sampling point corresponding to the ith first storage address, the first n-1 bits of the last n bits are used for indicating the pixel point index of the pixel point corresponding to the ith first storage address, i and n are positive integers, adjusting the order of bits in the last n bits to determine the second storage address corresponding to the ith first storage address, letting i=i+1, and re-entering the step of obtaining the last n bits of the ith first storage address to start to be performed until the m second storage addresses are determined.

Optionally, n is related to the number of sampling points corresponding to the m sampling points. As an example of the presence of a metal such as,Or, alternatively,。

Optionally, the sampling point index is used to indicate the index of the sampling point in its corresponding pixel point. The pixel point index is used to indicate the index of the pixel point in the image or image block. The sampling point index is irrelevant to the position of the sampling point in the pixel point, or the sampling point index is not strongly related to the position of the sampling point in the pixel point. As shown in fig. 7, the sample point positions and sample point indexes within 3 kinds of pixel points, especially for the case of using MSAA2 technology shown in part (1) of fig. 7 and the case of using MSAA8 shown in part (3) of fig. 7, if the mapping rule of the compression unit is based on the standard sample position map, for the case of part (1) of fig. 7 and the case of shown in part (2) of fig. 7, if arranged in the storage unit according to the sample point indexes, the case of shown in fig. 5 will occur, that is, the compression unit will not be able to correctly restore the sample points in the image or the image block due to the loss of the sample point positions, and thus it is necessary to reorder m sample points already stored in the storage unit.

Alternatively, since the first memory address is more, it is generally greater than or much greater than n. Therefore, only the last n bits of the first storage address are fetched, and since the m first storage addresses can indicate the first arrangement, the first part (i.e. the first n-1 bits) of the last n bits represents the index of each pixel point in the image or the image block, i.e. the pixel point index, and the second part (i.e. the nth bit, or the last bit) of the last n bits represents the index of the sampling point in the pixel point, i.e. the sampling point index.

Optionally, the order of each bit in the n bits after adjustment is used for determining the second storage address corresponding to the ith first storage address, and the method comprises the steps of adjusting the order of each bit in the n bits after adjustment, determining the last n bits of the second storage address corresponding to the ith first storage address, and determining the ith second storage address based on the last n bits of the ith second storage address. Optionally, the second storage address is an analog storage address, that is, the second storage address is mainly used to indicate the position of the corresponding sampling point in the m sampling points, so the address bits of the second storage address may be different from the address bits of the first storage address, if the ith second storage address includes only n bits, the order of each bit in the n bits after adjustment, and the last n bits of the second storage address corresponding to the ith first storage address (that is, the ith second storage address is determined). Or, the second storage address is an actual storage address, that is, the ith sampling point is stored in a storage position corresponding to the second storage address after rearrangement, and then the ith second storage address is determined based on the last n bits of the ith second storage address and the ith first storage address. For example, if the first storage address and the second storage address each include m bits, the first m-n bits of the ith first storage address are spliced with the last n bits of the ith second storage address to obtain the ith second storage address, i.e. the ith second storage address is the first m-n bits of the ith first storage address+the last n bits of the ith second storage address, where "+" is a connector. For example, m is 32, n is 4, the i first memory address is 0x8000, the last 4 bits of the i first memory address is 0x1, that is, 0b0001, and the determined last 4 bits of the i second memory address is 0x0, that is, 0b0000, then the first m-n (that is, 32-4=28) bits of the i first memory address are 0x8000 000, and the i second memory address obtained after concatenation is 0x8000 0000. In this case, m sampling points in a section of continuous storage position in the storage unit are taken out and rearranged and then are stored in the continuous storage position again, but in actual implementation, the m rearranged sampling points can be stored in another section of continuous storage position, and in this case, after the last n bits of the ith second storage address are determined, the ith second storage address is determined based on the storage address corresponding to the storage position to be stored. It should be noted that, in the embodiment of the present application, the m sampling points in a section of continuous storage position in the storage unit are taken out and rearranged and then are stored in the continuous storage position again for illustration, but the protection scope of the embodiment of the present application is not limited to this.

For example, for the ith sample point in the m sample points, it corresponds to the ith first storage address, assuming that the first storage address has 32 bits, for example, the ith first storage address is 0×8000, assuming that n is 4, since 1 hexadecimal bit may be represented as 4 binary bits, the last 4 bits of the ith first storage address are taken out to be 0x1, i.e. 0b0001, where the first 3bits "000" represent that the pixel index of the pixel point corresponding to the ith sample point is "000", i.e. 0b000=0, i.e. the pixel index is 0, and the 4 th bits "1" represent that the sample point index corresponding to the ith sample point is "1", i.e. 0b1=1, i.e. the sample point index is 1. And obtaining an ith second storage address by adjusting the last 4 bits of the ith first storage address, so that the ith second storage address can be mapped to the correct position of the ith sampling point in the image block according to a mapping rule, if the correct position of the ith sampling point in the image block is (0, 0), and if the mapping rule is that the (0, 0) in the image block is mapped to the position of 0b0000 of a storage unit, the last 4 bits of the ith second storage address are 0b0000.

Optionally, the order of each bit in the n bits after the sampling point is adjusted to indicate the position of the sampling point in the image or the image block, or the order of each bit in the n bits after the sampling point is adjusted to indicate the position of the sampling point in the at least one pixel point.

Next, the manner in which each bit of the n bits after adjustment is described.

In some embodiments, the order of each bit in the subsequent n bits is adjusted to determine a second memory address corresponding to the ith first memory address, including inverting the last bit in the subsequent n bits, numbering from the last bit to obtain a plurality of odd bits and a plurality of even bits, exchanging the jth odd bits with the jth even bits, the jth odd bits being the jth odd bits from right to left in the subsequent n bits, the jth even bits being the jth even bits from right to left in the subsequent n bits, j being a positive integer, and determining the second memory address corresponding to the ith first memory address based on the subsequent n bits after the order of exchanging the bits.

Alternatively, the odd and even digits are obtained by numbering from the last digit, and it is understood that the odd and even digits are obtained by numbering from right to left. Alternatively, the numbering starts from 0, or the numbering starts from 1. If the numbering starts from 0, the plurality of even bits may or may not include bits numbered 0.

Optionally, the order of each bit in the n bits after adjustment determines the second storage address corresponding to the ith first storage address, and from the view point of the image block, the m sampling points in the image block are regarded as basic elements, and the m sampling points in the image block are recoded by using Morton coding.

Alternatively, the last bit in the last n bits is inverted, because in the embodiment of the present application, one pixel shown in part (1) in fig. 7 includes 2 sampling points, the sampling point index is also in the manner shown in part (1) in fig. 7, the sampling point index of the sampling point located above is 1, the sampling point index of the sampling point located below is 0, and the sampling point index located below is 1, after the inversion, the sampling point is converted into the sampling point corresponding to 0 located above. Alternatively, the original sample point index is such that the sample point index of the sample point located on the left side is 1, the sample point index of the sample point located on the right side is 0, the sample point index converted into the sample point located on the left side after the inversion is 0, and the sample point index of the sample point located on the right side is 1, as shown in part (1) of fig. 7.

The last 4 bits of the ith first storage address are a first bit, a second bit, a third bit and a fourth bit from right to left, wherein the second bit, the third bit and the fourth bit are used for indicating pixel index of a pixel of a sampling point corresponding to the ith first storage address, the first bit is used for indicating sampling point index of the sampling point corresponding to the ith first storage address, inverting the last one of the last n bits comprises inverting the first bit to obtain the inverted first bit, and exchanging the jth odd bit and the jth even bit comprises exchanging the fourth bit and the third bit and exchanging the second bit and the inverted first bit.

For example, as shown in fig. 8, for the image block 50, 8 pixels are included, 2 sampling points are included in each pixel, and the sampling point index is set based on the standard sampling position shown in fig. 7 described above. The 2 sampling points within one pixel point will be considered as a top-bottom relationship in the image block 50, but these 2 sampling points are still in fact diagonal relationships as shown in fig. 7, which is a simulation made in order to simplify the rearrangement process in fig. 8. In the related art, at least one pixel included in the image block 50 is arranged in a staggered manner, that is, for the pixel in the memory 20, the pixel index is designed according to the staggered arrangement, that is, the pixel index can determine the position information of the pixel in the image block 50 according to the mapping rule, but for 2 sampling points included in the pixel, the sampling points are stored according to the sampling point index, so that the sampling points are arranged according to the first arrangement, as shown by the storage relationship 51 shown in the memory 20 (i.e., the storage unit) in fig. 8, each pixel corresponds to 2 storage positions, 8 pixels are stored according to the manner that the pixel satisfies the mapping rule in the image block 50, and the 2 sampling points included in each pixel are sequentially stored in the 2 storage positions of the corresponding pixel according to the sampling point index of the sampling point. For the pixel, the storage location of the pixel or the pixel index of the pixel is obtained after the morton encoding is performed based on the location of the pixel in the image block 50.

The morton code is a coding method for converting multidimensional data into one-dimensional data. The morton code defines a Z-shaped space filling curve, and is therefore also commonly referred to as a Z-order curve. Having morton codes that are close to each other for coordinates that are close to each other in an N-dimensional space can be applied to generate a unique index for an integer pair. For example, a Morton code generated using Morton encoding for coordinate points in a coordinate system may uniquely index the corresponding points. As shown in fig. 9, for 8 pixels in an image or image block, they are placed in a two-dimensional planar coordinate system, and the row and column numbers are first converted to binary, in fig. 9, to be the converted binary row and column numbers, which are numbered from 0. Here, since the image blocks are arranged in 2×4, 1 bit is required to represent a line number, and 2 bits are required to represent a column number. The row number Y has values of 0 and 1, and the column number X has values of 00, 01, 10, and 11, and for convenience of representation, binary row numbers may be split from right to left, for example, the 1 st row number is denoted as Y0, the 1 st column number is denoted as X0, and the 2 nd column number is denoted as X1. Under the condition that the row and column numbers corresponding to the pixels are known, the indexes of the pixels can be obtained, specifically, the row numbers corresponding to the pixels are staggered according to the sequence of YX, for example, the indexes of the pixels of each pixel are X1Y0X0 in fig. 9, for example, the indexes of the pixels on (0, 0) are X1, X0 and Y0 are 0, so that the indexes of the corresponding sampling points are 0 b000=0, for example, the indexes of the sampling points on (3, 1) are 1, X0 is 1, Y0 is 1, and the indexes of the corresponding sampling points are 0 b111=7.

The adjustment operation for the last n bits of the first storage address shown in the embodiment of the present application is to convert m sampling points arranged according to the first arrangement manner into the arrangement according to the positions of the m sampling points in the image or the image block. For example, the above-described storage relationship 51 in fig. 8 shows a storage relationship in the memory 20 of m sampling points arranged according to the sampling point index in the related art. P0 to P7 denote pixel indices, which are derived based on morton coding, but S0 and S1 denote sampling indices, which are determined in standard sampling locations or programmable sampling locations, and are not derived according to morton coding, i.e. the pixel indices can represent the positions of the pixels in the image or the image block, but the sampling indices cannot represent the positions of the pixels in the pixel or the image block, and in the first storage addresses of the sampling points indicated after splicing the pixel indices and the sampling indices, the positions of the sampling points in the image or the image block cannot be represented, so that it is necessary to re-perform morton coding on the sampling points based on the known first storage addresses (the pixel indices and the sampling indices) of the sampling points to obtain new second storage addresses (the actual indices of the sampling points in the image or the image block) by the method shown in the embodiment of the present application. The recoded second memory address is as shown in fig. 8 for memory relationship 52. For the storage relationship 51 and the storage relationship 52, if the compression unit is used to perform the interleaving recovery on the m sampling points corresponding to the storage relationship 51, the image block 53 is obtained, and it can be known by comparing the image block 50 and the image block 53 that the storage relationship 51 breaks or loses the position information of the m sampling points, and the high frequency information (which generates the severe change of the gray value) is generated in the image block 53 due to the arrangement based on the first arrangement mode and the interleaving recovery, which is unfavorable for the compression unit to perform the image compression. After the address rearrangement shown in the embodiment of the present application is adopted, the image block 54 corresponding to the storage relationship 52 well retains the low-frequency information in the image block 54.

Illustratively, the address rearrangement process is illustrated in fig. 10, and in this example, two sampling points within one pixel point are regarded as an upper-lower relationship. In the case of the first arrangement, the method is equivalent to that after at least one pixel is Morton encoded, a first storage address is obtained according to the pixel index and the sampling point index, and the address rearrangement process is to generate a second storage address of m sampling points, where the second storage address can reflect the position information of the sampling points in the image or the image block, that is, based on the known pixel index and the sampling point index, morton encoding is performed again to obtain the second storage address of the sampling points or the last n bits of the second storage address. Since the sampling points within a pixel are regarded as a top-bottom relationship, that is, for a2×4 pixel, the image block needs to be regarded as a 4×4 sampling point in the morton coding process, in the first arrangement, the first storage Address may be represented as X1Y0X0S0, where X1Y0X0 represents the pixel index, and S0 represents the sampling point index, that is, address_origin [3:0] =x1y0x0s0. Because the sampling points in a pixel point are regarded as the up-down relationship, Y is expanded from one bit to two bits in the Morton coding process, and the expanded line number can be expressed based on the original line number Y0 and the sampling point index S0, and the expanded line number can be expressed as Y0 #S0), wherein%S0) represents the inversion of the sample point index, since the sample point index specified by the standard sample position is that the upper sample point is 1 and the lower sample point is 0, which is not coincident with the actual position of the sample point in the image block. After the line number is expanded, morton encoding can be performed based on the expanded line number and the original column number to obtain a second storage address or the last n bits of the second storage address of each sampling point. Namely, address_ Remap [3:0] =y0x1 ]S0)X0。

The value of n is related to the number of sampling points included in the image block, or the value of n is related to the number of binary digits representing the number of rows and columns of the image block. In addition, the above description is given by taking the sampling points included in one pixel as being arranged up and down and expanding the row number Y as an example, but in actual implementation, the sampling points included in the pixel may be arranged left and right and expanding the column number X. That is, the embodiment of the present application does not limit the manner of determining the second memory address based on the first memory address in the address rearrangement process, but the scope of protection of the embodiment of the present application is not limited thereto.

In addition, the foregoing examples are exemplified by 2×4 pixels, and each pixel includes 2 sampling points, so that the pixel is extended to a 4×4 morton code, but the present application may also be used in scenes such as 1×2 pixels, 2×2 pixels, and 4×4 pixels, which is not limited thereto. For scenes with different numbers of pixels, the main difference is that row numbers and column numbers are staggered when Morton encoding is performed again, and if the row numbers are larger than the column numbers or the column numbers are larger than the column numbers, the row numbers have 1 bit (Y0), and the column numbers have 3 bits (X2X 1X 0), the row numbers are still staggered, and can be expressed as X2X1Y0X0, so that the pixel index is obtained.

In some embodiments, under the condition that sampling points in one pixel point are regarded as being arranged up and down, a plurality of even bits are used for indicating rearranged row numbers, a plurality of odd bits are used for indicating rearranged column numbers, a plurality of even bits comprise last bit bits with the number of 0, the sequence of each bit in the n bits is adjusted, the second storage address corresponding to the ith first storage address is determined, and the sequence of each bit in the n bits is adjusted, so that the last n bits of the second storage address corresponding to the ith first storage address are obtained, and the last n bits of the ith second storage address are Morton codes corresponding to the position information of the ith sampling point in an image block.

In some embodiments, in the case where sampling points in one pixel point are regarded as being arranged left and right, a plurality of even bits are used to indicate the rearranged row number, a plurality of odd bits are used to indicate the rearranged column number, a plurality of even bits do not include the last bit numbered 0, that is, the 1 st odd bit is numbered 1, the 1 st even bit is numbered 2, and so on. The order of each bit in the n bits after adjustment, the second storage address corresponding to the ith first storage address is determined, and the method comprises the steps of adjusting the order of each bit in the n bits after adjustment, obtaining the last n bits of the second storage address corresponding to the ith first storage address, so that the last n bits of the ith second storage address are Morton codes corresponding to the position information of the ith sampling point in the image block.

In summary, the method provided by the embodiment of the present application shows a manner of determining m second storage addresses based on an address rearrangement manner, and after the address rearrangement, the second storage addresses or the last n bits of the second storage addresses, which can represent the positions of m sampling points in an image or an image block, are obtained. So that the position information of m sampling points is restored and saved. In the scene applied to image compression, high-frequency information introduced due to the loss of the position information of the sampling point can be avoided, and the compression rate of image compression is improved.

In addition, a specific process of address rearrangement is shown, based on the pixel point index and the sampling point index in the last n bits in the first storage address, a Morton coding mode is adopted again based on the known pixel point index and the sampling point index, the sampling points are taken as basic elements in the image block as coding conditions, morton codes (namely the second storage address or the last n bits of the second storage address) with the position information hidden in the image block by each sampling point are obtained, and rearrangement of m sampling points is realized. And the address rearrangement process aiming at the condition of 2 multiplied by 4 pixel points is also shown, so that the specific steps of the address rearrangement process are clarified, and the Morton code of each sampling point is obtained based on the known pixel point index and the sampling point index, so that the spatial locality in an image block is maintained, and the efficiency of an application scene needing to process local information in a space, such as a rendering scene aiming at a detail area, can be improved. In addition, the multidimensional information is converted into one-dimensional information, so that the storage of the information is optimized. And a unique index of each sampling point related to the position information is generated, so that the efficiency of searching and reading operations for the unique index is improved.

And determining a second mode, namely looking up a table.

In some embodiments, the step 222 may be implemented by obtaining a lookup table, where the lookup table is used to indicate a mapping relationship between m first storage addresses and m second storage addresses, and searching, based on the lookup table, a second storage address corresponding to each of the m first storage addresses, and determining the m second storage addresses.

Optionally, the look-up table is stored in the terminal device. The look-up table is preset by the user or developer.

Optionally, at least one lookup table is stored in the terminal device, and the mapping relation and the number of mapping relations included in each lookup table are different. For example, for standard sampling positions, there are 3 lookup tables, one lookup table corresponds to 2×4 pixels and each pixel includes an application scene of 2 sampling points, one lookup table corresponds to 1×2 pixels and each pixel includes an application scene of 8 sampling points, one lookup table corresponds to 2×2 pixels and each pixel includes an application scene of 8 sampling points, and so on. For programmable sampling locations, there are 3 look-up tables, one look-up table for programming mode 1, one look-up table for programming mode 2, one look-up table for programming mode 3, etc.

Optionally, the terminal device obtains the lookup table corresponding to the compression unit based on the compression unit.

Optionally, searching the second storage address corresponding to each first storage address in the m first storage addresses based on the lookup table, and determining the m second storage addresses, wherein the method comprises the steps of searching the ith second storage address corresponding to the ith first storage address from the lookup table for the ith first storage address in the m first storage addresses, enabling i=i+1 to reenter the step of searching the ith second storage address corresponding to the ith first storage address from the lookup table, and executing until the m second storage addresses are determined, wherein i is a positive integer.

In some embodiments, the lookup table is used for indicating a mapping relation between the last n bits of the m first storage addresses and the last n bits of the m second storage addresses, and the searching for the second storage address corresponding to each first storage address in the m first storage addresses based on the lookup table, and determining the m second storage addresses comprises obtaining the last n bits of the m first storage addresses, searching for the last n bits of the second storage address corresponding to the m first storage addresses based on the last n bits of the m first storage addresses, and determining the m second storage addresses based on the last n bits of the second storage address corresponding to the m first storage addresses.

Optionally, the last n bits of the first storage address are used to indicate at least one of a sampling point index and a pixel point index of a sampling point corresponding to the first storage address. If the first storage address has the last n bits, the first n-s bits represent the pixel index, the last s bits represent the sampling index, and s is a positive integer.

Optionally, the m second storage addresses are determined based on the last n bits of the second storage addresses corresponding to the m first storage addresses, i.e. the last n bits of the m second storage addresses. Optionally, the second memory address is an analog memory address, that is, the second memory address is mainly used to indicate the position of its corresponding sampling point in the m sampling points, so the address bits of the second memory address may be different from the address bits of the first memory address. Or, the second storage address is an actual storage address, that is, the ith sampling point is stored in a storage position corresponding to the second storage address after rearrangement, and then the ith second storage address is determined based on the last n bits of the ith second storage address and the ith first storage address. For a specific description of the second storage address, reference may be made to the description in "determining mode one: address rearrangement" described above, and details thereof will not be repeated here.

In some embodiments, the sampling point locations of the m sampling points included in each of the at least one pixel point are standard sampling locations, or the sampling point locations of the m sampling points included in each of the at least one pixel point are programmable sampling locations.

Therefore, the determination of the second memory address using the lookup table for the standard sampling position and the programmable sampling position will be described next.

(1) Standard sampling locations.

The standard sampling position is illustrated in fig. 7, and an example in which 8 sampling points are included in one pixel and 1×2 pixels are included in one image block is described below. For 8 sampling points in one pixel, a corresponding second arrangement manner is shown in fig. 11. That is, the storage order of 8 sampling points S0 to S7 in one pixel should be S3→s7→s5→s0→s1→s2→s4→s6 in the storage unit, that is, should be stored in a mapping relationship satisfying the morton encoding process.

For example, as shown in fig. 12, if m sampling points in the image block 60 are arranged in the first arrangement manner, as shown in fig. 12, a storage relationship 61 in the memory 20 is shown in fig. 12, and if the storage relationship 61 is restored by interleaving, an image block 63 is restored, and the image block 63 introduces high-frequency information that is detrimental to image compression compared to the image block 60. If the m sampling points are rearranged to obtain m sampling points arranged according to the second arrangement manner using the lookup table shown in table 1 below, a storage relationship 62 as shown in fig. 12 may be obtained, and the image block 64 retaining the low frequency information in the image block 60 may be recovered by performing the interleaving recovery on the storage relationship 62.

Table 1 look-up table

For example, for m first memory addresses, the last 4 bits of the m first memory addresses are acquired, and then the first 1 bit of the last 4 bits is used to represent the pixel index, and the last 3 bits are used to represent the sampling point index. That is, the last 4 of the first memory Address may be expressed as address_origin [3:0] =x0s2s1s0. In determining the last 4 bits of the m second memory addresses based on the lookup table, the last 4 bits of the second memory addresses may be address_ Remap [3:0] =lut (address_origin [3:0 ]), that is, the last 4 bits of the second memory addresses corresponding to the last 4 bits are queried from the lookup table based on the last 4 bits of the first memory addresses. And the above table 1 is shown by taking 1 hexadecimal bit (equivalent to 4 binary bits) as an example. If the last 4 bits of the first memory address are 0x1, i.e. 0b0001, the last 4 bits of the corresponding second memory address are 0x8, i.e. 0b1000, according to table 1, and the other first memory addresses are determined in a similar manner, which is not exemplified herein.

(2) Programmable sampling locations.

For example, in the case of using a programmable sampling position, if 8 sampling points are included in one pixel, one image block includes 1×2 pixels, and the sampling point position included in the image block can refer to the sampling point position in the image block 70 shown in fig. 13. At this time, the storage order of 8 sampling points S0 to S7 in one pixel point in the storage unit should be s7→s3→s6→s2→s5→s1→s4→s0, that is, should be stored in a mapping relationship satisfying the morton encoding process. For MSAA2X, MSAA, 4, X, MSAA, 8X, the hardware reorders the 16 samples according to the LUT table configured by the Driver.

For example, as shown in fig. 13, if m sampling points in the image block 70 are arranged in the first arrangement manner, as shown in fig. 13, a storage relationship 71 in the memory 20 is shown, and if the storage relationship 71 is recovered by interleaving, the image block 73 is recovered, and the image block 73 introduces high-frequency information that is detrimental to image compression compared to the image block 70. If the m sampling points are rearranged to obtain m sampling points arranged according to the second arrangement manner using the lookup table shown in table 2 below, a storage relationship 72 as shown in fig. 13 may be obtained, and the image block 74 retaining the low frequency information in the image block 70 may be recovered by performing the interleaving recovery on the storage relationship 72.

Table 2 look-up table

For example, for m first memory addresses, the last 4 bits of the m first memory addresses are acquired, and then the first 1 bit of the last 4 bits is used to represent the pixel index, and the last 3 bits are used to represent the sampling point index. That is, the last 4 of the first memory Address may be expressed as address_origin [3:0] =x0s2s1s0. In determining the last 4 bits of the m second memory addresses based on the lookup table, the last 4 bits of the second memory addresses may be represented as address_ Remap [3:0] =lut_prog (address_origin [3:0 ]), that is, the last 4 bits of the second memory addresses corresponding to the last 4 bits are queried from the lookup table based on the last 4 bits of the first memory addresses. And the above table 1 is shown by taking 1 hexadecimal bit (equivalent to 4 binary bits) as an example. If the last 4 bits of the first memory address are 0x1, i.e. 0b0001, the last 4 bits of the corresponding second memory address are 0x8, i.e. 0b1000, according to table 1, and the other first memory addresses are determined in a similar manner, which is not exemplified herein.

In summary, in the method provided by the embodiment of the application, when determining m second storage addresses, the lookup table is directly used for inquiring, and compared with the first determination mode, the determination efficiency of the second storage addresses can be improved. And the applicable scene of the mode of determining the second storage address according to the lookup table is richer, so that the usability of the rearrangement method of the sampling points based on the lookup table is improved.

In addition, the mapping relation between the last n bits of the first storage address and the last n bits of the second storage address is only included in the lookup table, compared with the mapping relation between m first storage addresses and m second storage addresses in the lookup table, the data size of the lookup table is reduced, and therefore the lookup efficiency of searching the second storage address based on the lookup table is improved.

And for the standard sampling position, the method provided by the embodiment of the application can better restore the position information among the sampling points, and reduce the probability of high-frequency signal generation so as to improve the compression rate. For programmable sampling positions, the method provided by the embodiment of the application provides a means for more flexible recovery of the position information of the sampling points for the driver.

It should be noted that, the above-mentioned "determination mode one: address rearrangement" and "determination mode two: lookup table" may be implemented as independent embodiments or may be implemented as a combination embodiment. For example, for a scene where one pixel includes 2 sampling points, rearrangement is performed using the manner shown in the "determination mode one: address rearrangement" described above, and for a scene where one pixel includes more sampling points, such as 4 sampling points, 8 sampling points, etc., if the "determination mode one: address rearrangement" may result in an excessive calculation amount, rearrangement may be performed using the "determination mode two: lookup table", which is not limited in the embodiment of the present application.

In some embodiments, the method further comprises obtaining configuration information of an image block, the image block comprising at least one pixel, the configuration information of the image block being used to indicate a number of sampling points corresponding to each of the at least one pixel.

Optionally, a determination manner (i.e., the determination manner one or the determination manner two described above) of determining m second storage addresses based on m first storage addresses is selected based on the configuration information of the image block.

Optionally, the configuration information is further used to indicate that the sampling point position in each pixel point is a standard sampling position or a programmable sampling position. And acquiring a lookup table corresponding to the sampling point position of each pixel point based on the configuration information.

The configuration information is used for indicating the information such as the number of sampling points in the pixel points, so that the used rearrangement method is determined based on the information such as the number of sampling points, and the diversity and flexibility of the rearrangement method are improved.

Next, a description will be given of a rearrangement method of the above-described sampling points applied in the image compression process, taking an example of applying the above-described rearrangement method to the image compression field.

Step 1, reading m sampling points arranged according to a first arrangement mode from a storage unit based on a compression unit, wherein the m sampling points are sampling points in at least one pixel point in the compression unit, the first arrangement mode is an arrangement mode of sampling point index arrangement based on the m sampling points, and m is a positive integer greater than 1.

Optionally, the first arrangement is not related to a mapping rule of the compression unit. The mapping rule of the compression unit refers to a rule that the compression unit reads a plurality of sampling points from the storage unit and then maps each sampling point to a different position of a corresponding pixel point, or the mapping rule of the compression unit refers to a rule that the compression unit reads a plurality of sampling points from the storage unit and then maps each sampling point to a different position of an image or an image block.

And 2, rearranging the m sampling points to obtain m sampling points which are arranged according to a second arrangement mode, wherein the second arrangement mode is an arrangement mode based on the position arrangement of the m sampling points in at least one pixel point.

Optionally, the second arrangement is related to a mapping rule of the compression unit.

In some embodiments, rearranging m sampling points to obtain m sampling points arranged according to a second arrangement mode, wherein the method comprises the steps of obtaining m first storage addresses of the m sampling points in a storage unit, wherein the m first storage addresses are in one-to-one correspondence with the m sampling points, determining m second storage addresses based on the m first storage addresses, wherein the second storage addresses are in one-to-one correspondence with the m sampling points, the m second storage addresses are different from the m first storage addresses, and determining the m sampling points arranged according to the second arrangement mode based on the m second storage addresses.

In some embodiments, the determining manner of determining the m second storage addresses based on the m first storage addresses may refer to the above-mentioned "determining manner one: address rearrangement" and "determining manner two: lookup table", which are not described herein.

And step 3, storing m sampling points arranged according to a second arrangement mode into a storage unit.

And 4, the compression unit takes out m sampling points which are arranged according to a second arrangement mode from the storage unit, and the image block is recovered based on the m sampling points which are taken out and the mapping rule of the compression unit.

Optionally, the sampling point positions of the sampling points in the image block obtained by the compression unit and the sampling point positions of the sampling points before the image block is stored in the storage unit are the same or similar.

In some embodiments, the method further comprises obtaining configuration information of an image block, the image block comprising at least one pixel, the configuration information of the image block being used to indicate a number of sampling points corresponding to each of the at least one pixel. Optionally, the configuration information of the image block is used to indicate at least one of a size of the compression unit, a mapping rule of the compression unit, and a sampling point position in each pixel point.

In summary, the method provided by the embodiment of the present application shows an example of applying the method shown in the embodiment of the present application to the field of image compression, where m sampling points originally stored in the storage unit according to the first arrangement manner, that is, m sampling points stored based on the sampling point index, are rearranged into m sampling points stored in the second arrangement manner, that is, m sampling points stored based on the position of each sampling point in the m sampling points in at least one pixel point, by a rearrangement manner. For the storage of the sampling points, the position information of the sampling points in at least one pixel point (or called image or image block) is introduced, so that m sampling points arranged according to a second arrangement mode support various algorithms needing to use the position information, such as an image compression algorithm. The method avoids the loss of the position information of the sampling points in the storage process of the m sampling points, and improves the storage flexibility of the m sampling points. And, store based on the second arrangement mode of the position of m sampling points in at least one pixel point, it is more friendly to access the data access mode of the memory cell based on the position information, can improve the access efficiency to m sampling points in the memory cell and improve the inquiry performance. In particular, for an image compression algorithm designed for low frequency information, image compression is performed based on m sampling points arranged in a second arrangement instead of m sampling points arranged in a first arrangement, so that the image compression rate can be improved, for example, the compression rate of the image compression algorithm based on wavelet transform is improved, because the first arrangement may introduce high frequency information which is not present in an original image or an image block, resulting in a reduction in the compression rate.

Referring to fig. 14, a block diagram of a sample point rearrangement apparatus according to an exemplary embodiment of the present application is shown. The device has the function of realizing the example of the rearrangement method of the sampling points, and the function can be realized by hardware or by executing corresponding software by hardware. The apparatus may be the computer device described above or may be provided in a computer device. As shown in fig. 14, the apparatus may include an acquisition module 410, a rearrangement module 420, and a storage module 430.

The obtaining module 410 is configured to read m sampling points arranged according to a first arrangement manner from the storage unit, where the m sampling points are sampling points in at least one pixel point, the first arrangement manner is an arrangement manner based on sampling point index arrangement of the m sampling points, and m is a positive integer greater than 1.

The rearrangement module 420 is configured to rearrange the m sampling points to obtain m sampling points arranged according to a second arrangement mode, where the second arrangement mode is an arrangement mode based on a position arrangement of the m sampling points in the at least one pixel point.

And a storage module 430, configured to store the m sampling points arranged according to the second arrangement manner into the storage unit.

In some embodiments, the rearrangement module 420 is further configured to obtain m first storage addresses of the m sampling points in the storage unit, where the m first storage addresses are in one-to-one correspondence with the m sampling points, determine m second storage addresses based on the m first storage addresses, where the second storage addresses are in one-to-one correspondence with the m sampling points, where the m second storage addresses are different from the m first storage addresses, and determine the m sampling points arranged according to a second arrangement manner based on the m second storage addresses.

In some embodiments, the rearrangement module 420 is further configured to, for an ith first storage address in the m first storage addresses, obtain a last n bits of the ith first storage address, where a last one of the last n bits is used to indicate a sampling point index of a sampling point corresponding to the ith first storage address, a first n-1 bit of the last n bits is used to indicate a pixel point index of a pixel point corresponding to the ith first storage address, i and n are both positive integers, adjust an order of bits in the last n bits, determine a second storage address corresponding to the ith first storage address, and let i=i+1, reenter a step of obtaining the last n bits of the ith first storage address, and start to be executed until the m second storage addresses are determined.

In some embodiments, the rearrangement module 420 is further configured to invert a last bit in the last n bits, number from the last bit to obtain a plurality of odd bits and a plurality of even bits, exchange a j-th odd bit and a j-th even bit, wherein the j-th odd bit is a j-th odd bit from right to left in the last n bits, the j-th even bit is a j-th even bit from right to left in the last n bits, and determine the second storage address corresponding to the i-th first storage address based on the last n bits after the order of exchanging bits.

In some embodiments, n is 4, the last 4 bits of the ith first storage address are a first bit, a second bit, a third bit and a fourth bit from right to left, where the second bit, the third bit and the fourth bit are used to indicate pixel indexes of pixels of a sampling point corresponding to the ith first storage address, the first bit is used to indicate a sampling point index of a sampling point corresponding to the ith first storage address, the rearrangement module 420 is further used to invert the first bit to obtain the inverted first bit, and exchange the fourth bit with the third bit and exchange the second bit with the inverted first bit.

In some embodiments, the rearrangement module 420 is further configured to obtain a lookup table, where the lookup table is used to indicate a mapping relationship between m first storage addresses and the m second storage addresses, and find, based on the lookup table, a second storage address corresponding to each first storage address in the m first storage addresses, and determine the m second storage addresses.

In some embodiments, the lookup table is used for indicating a mapping relationship between the last n bits of the m first storage addresses and the last n bits of the m second storage addresses, the rearrangement module 420 is further used for obtaining the last n bits of the m first storage addresses, searching the last n bits of the second storage addresses corresponding to the m first storage addresses based on the last n bits of the m first storage addresses, and determining the m second storage addresses based on the last n bits of the second storage addresses corresponding to the m first storage addresses.

In some embodiments, the obtaining module 410 is further configured to obtain configuration information of an image block, where the image block includes at least one pixel, and the configuration information of the image block is used to indicate a number of sampling points corresponding to each pixel in the at least one pixel.

In summary, the device provided in the embodiment of the present application shows an example of applying the method shown in the embodiment of the present application to the field of image compression, where m sampling points originally stored in the storage unit according to the first arrangement manner, that is, m sampling points stored based on the sampling point index, are rearranged into m sampling points stored in the second arrangement manner, that is, m sampling points stored based on the position of each sampling point in the m sampling points in at least one pixel point, by a rearrangement manner. For the storage of the sampling points, the position information of the sampling points in at least one pixel point (or called image or image block) is introduced, so that m sampling points arranged according to a second arrangement mode support various algorithms needing to use the position information, such as an image compression algorithm. The method avoids the loss of the position information of the sampling points in the storage process of the m sampling points, and improves the storage flexibility of the m sampling points. And, store based on the second arrangement mode of the position of m sampling points in at least one pixel point, it is more friendly to access the data access mode of the memory cell based on the position information, can improve the access efficiency to m sampling points in the memory cell and improve the inquiry performance.

It should be noted that, when the apparatus provided in the foregoing embodiment performs the functions thereof, only the division of the foregoing functional modules is used as an example, in practical application, the foregoing functional allocation may be performed by different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules, so as to perform all or part of the functions described above. In addition, the apparatus and the method embodiments provided in the foregoing embodiments belong to the same concept, and specific implementation processes of the apparatus and the method embodiments are detailed in the method embodiments and are not repeated herein.

The computer apparatus 800 includes a central processing unit (Central Processing Unit, CPU) 801, a system Memory 804 including a random access Memory (Random Access Memory, RAM) 802 and a Read-Only Memory (ROM) 803, and a system bus 805 connecting the system Memory 804 and the central processing unit 801. The computer device 800 also includes a basic Input/Output system (I/O) 806 for facilitating the transfer of information between the various devices within the computer device, and a mass storage device 807 for storing an operating system 813, application programs 814, and other program modules 815.

The basic input/output system 806 includes a display 808 for displaying information and an input device 809, such as a mouse, keyboard, or the like, for user input of information. Wherein the display 808 and the input device 809 are connected to the central processing unit 801 via an input/output controller 810 connected to a system bus 805. The basic input/output system 806 may also include an input/output controller 810 for receiving and processing input from a number of other devices, such as a keyboard, mouse, or electronic stylus. Similarly, the input/output controller 810 also provides output to a display screen, a printer, or other type of output device.

The mass storage device 807 is connected to the central processing unit 801 through a mass storage controller (not shown) connected to the system bus 805. The mass storage device 807 and its associated computer-readable storage media provide non-volatile storage for the computer device 800. That is, the mass storage device 807 may include a computer readable storage medium (not shown) such as a hard disk or a compact disk-Only (CD-ROM) drive.

The computer-readable storage medium may include computer storage media and communication media without loss of generality. Computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable storage instructions, data structures, program modules or other data. Computer storage media includes RAM, ROM, erasable programmable read-Only register (Erasable Programmable Read Only Memory, EPROM), electrically erasable programmable read-Only Memory (EEPROM), flash Memory or other solid state Memory technology, CD-ROM, digital versatile disks (DIGITAL VERSATILE DISC, DVD) or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices. Of course, those skilled in the art will recognize that the computer storage medium is not limited to the one described above. The system memory 804 and mass storage device 807 described above may be collectively referred to as memory.

The memory stores one or more programs configured to be executed by the one or more central processing units 801, the one or more programs containing instructions for implementing the above-described method embodiments, the central processing unit 801 executing the one or more programs to implement the methods provided by the various method embodiments described above.

According to various embodiments of the application, the computer device 800 may also operate through a network, such as the Internet, to remote computer devices on the network. I.e., the computer device 800 may be connected to a network 812 through a network interface unit 811 connected to the system bus 805, or other types of networks or remote computer device systems (not shown) may be connected using the network interface unit 811.

The memory also includes one or more programs stored in the memory, the one or more programs including steps for performing the methods provided by the embodiments of the present application, as performed by the computer device.

In an exemplary embodiment, a non-transitory computer readable storage medium is also provided, on which a computer program is stored, which when executed by a processor, implements the above-described sample point rearrangement method.

In an exemplary embodiment, a computer program product is also provided, which, when being executed by a processor, is adapted to carry out the above-mentioned sample point rearrangement method.

On the other hand, the embodiment of the application provides a display card, which comprises the compression unit in each embodiment.

It should be understood that references herein to "a plurality" are to two or more. The character "/" generally indicates that the context-dependent object is an "or" relationship. In addition, the step numbers described herein are merely exemplary of one possible execution sequence among steps, and in some other embodiments, the steps may be executed out of the order of numbers, such as two differently numbered steps being executed simultaneously, or two differently numbered steps being executed in an order opposite to that shown, which is not limiting.

The foregoing description of the preferred embodiments of the present application is not intended to limit the application, but rather, the application is to be construed as limited to the appended claims.

Claims

1. A method for reordering sampling points, the method comprising:

Reading m sampling points arranged according to a first arrangement mode from a storage unit, wherein the m sampling points are sampling points in at least one pixel point, the first arrangement mode is an arrangement mode based on sampling point index arrangement of the m sampling points, m is a positive integer greater than 1, sampling point positions of the m sampling points included in each pixel point in the at least one pixel point are standard sampling positions, or sampling point positions of the m sampling points included in each pixel point in the at least one pixel point are programmable sampling positions;

storing the m sampling points arranged according to the second arrangement mode into the storage unit;

the rearranging the m sampling points to obtain m sampling points arranged according to a second arrangement mode, which comprises the following steps:

Obtaining m first storage addresses of the m sampling points in the storage unit, wherein the m first storage addresses are in one-to-one correspondence with the m sampling points;

Determining m second storage addresses based on the m first storage addresses, wherein the second storage addresses are in one-to-one correspondence with the m sampling points, the m second storage addresses are different from the m first storage addresses, the m second storage addresses are obtained based on adjusting the last n bits in the m first storage addresses, and the last n bits of each first storage address in the m first storage addresses are used for indicating at least one of sampling point indexes and pixel point indexes of the sampling points corresponding to the first storage addresses;

and determining the m sampling points arranged according to the second arrangement mode based on the m second storage addresses.

2. The method of claim 1, wherein the determining m second memory addresses based on the m first memory addresses comprises:

For an ith first storage address in the m first storage addresses, acquiring a last n bits of the ith first storage address, wherein a last bit of the last n bits is used for indicating a sampling point index of a sampling point corresponding to the ith first storage address, a first n-1 bit of the last n bits is used for indicating a pixel point index of a pixel point corresponding to the ith first storage address, and both i and n are positive integers;

Adjusting the sequence of each bit in the last n bits, and determining a second storage address corresponding to the ith first storage address;

Let i=i+1, the step of re-entering the last n bits of the i-th first memory address starts to be performed until the m second memory addresses are determined.

3. The method of claim 2, wherein said adjusting the order of bits in the last n bits to determine the second memory address corresponding to the ith first memory address comprises:

Inverting the last bit of the last n bits;

numbering from the last bit to obtain a plurality of odd digits and a plurality of even digits;

Exchanging an jth odd bit and an jth even bit, wherein the jth odd bit is an jth odd bit from right to left in the rear n bits, the jth even bit is an jth even bit from right to left in the rear n bits, and j is a positive integer;

and determining a second storage address corresponding to the ith first storage address based on the last n bits after the sequence of the exchange bits.

4. The method of claim 3, wherein n is 4, and the last 4 bits of the ith first storage address are respectively, from right to left, a first bit, a second bit, a third bit, and a fourth bit, where the second bit, the third bit, and the fourth bit are used to indicate a pixel index of a pixel of the sampling point corresponding to the ith storage address, and the first bit is used to indicate a sampling point index of the sampling point corresponding to the ith first storage address;

the inverting the last bit of the last n bits includes:

Inverting the first bit to obtain the inverted first bit;

the exchanging the jth odd bit and the jth even bit includes:

Exchanging the fourth bit with the third bit, and exchanging the second bit with the inverted first bit.

5. The method of claim 1, wherein the determining m second memory addresses based on the m first memory addresses comprises:

obtaining a lookup table, wherein the lookup table is used for indicating the mapping relation between the m first storage addresses and the m second storage addresses;

and searching a second storage address corresponding to each first storage address in the m first storage addresses based on the lookup table, and determining the m second storage addresses.

6. The method of claim 5, wherein the lookup table is used to indicate a mapping relationship between the last n bits of the m first memory addresses and the last n bits of the m second memory addresses;

the searching the second storage address corresponding to each first storage address in the m first storage addresses based on the lookup table, and determining the m second storage addresses includes:

acquiring the last n bits of the m first storage addresses;

Searching the last n bits of the second storage address corresponding to the m first storage addresses based on the last n bits of the m first storage addresses;

And determining the m second storage addresses based on the last n bits of the second storage addresses corresponding to the m first storage addresses.

7. The method according to any one of claims 1 to 6, further comprising:

the method comprises the steps of obtaining configuration information of an image block, wherein the image block comprises at least one pixel point, and the configuration information of the image block is used for indicating the number of sampling points corresponding to each pixel point in the at least one pixel point.

8. A sample point rearrangement apparatus, the apparatus comprising:

The device comprises an acquisition module, a storage unit and a control module, wherein the acquisition module is used for reading m sampling points which are arranged according to a first arrangement mode from the storage unit, the m sampling points are sampling points in at least one pixel point, the first arrangement mode is an arrangement mode based on sampling point index arrangement of the m sampling points, m is a positive integer greater than 1, sampling point positions of the m sampling points included in each pixel point in the at least one pixel point are standard sampling positions, or sampling point positions of the m sampling points included in each pixel point in the at least one pixel point are programmable sampling positions;

The storage module is used for storing the m sampling points which are arranged according to the second arrangement mode into the storage unit;

the rearrangement module is further configured to obtain m first storage addresses of the m sampling points in the storage unit, where the m first storage addresses are in one-to-one correspondence with the m sampling points, determine m second storage addresses based on the m first storage addresses, where the second storage addresses are in one-to-one correspondence with the m sampling points, where the m second storage addresses are different from the m first storage addresses, where the m second storage addresses are obtained based on adjusting the last n bits in the m first storage addresses, where the last n bits of each first storage address in the m first storage addresses are used to indicate at least one of a sampling point index and a pixel point index of a sampling point corresponding to the first storage address, and determine the m sampling points arranged according to a second arrangement manner based on the m second storage addresses.

9. A computer device, characterized in that it comprises a processor and a memory, said memory having stored therein at least one program, said processor being adapted to execute said at least one program in said memory for implementing a method for reordering sampling points according to any of the preceding claims 1 to 7.

10. A computer readable storage medium having stored therein executable instructions that are loaded and executed by a processor to implement a method of reordering sampling points according to any of the preceding claims 1 to 7.