CN120066579A - RISC-V-based interrupt and exception handling system, method and processor - Google Patents

Abstract

The application provides an interrupt and exception handling system, method and processor based on RISC-V, wherein the system comprises a core local interrupt controller, a platform level interrupt controller and a delivery module, wherein the core local interrupt controller is used for generating software interrupt and timer interrupt, the platform level interrupt controller is used for integrating a plurality of external interrupt sources into an external interrupt signal, the delivery module is arranged in a processor core, and after receiving interrupt signal requests of the core local interrupt controller and the platform level interrupt controller or an exception signal request of an arithmetic logic unit in the processor core, the delivery module sends a pipeline flushing request and a first instruction count value for re-fetching an instruction to a fetching stage, wherein the core local interrupt controller and the platform level interrupt controller are mounted on the processor core. The embedded processor device has the advantages of simple structure, low power consumption and small circuit area, and is suitable for embedded processor devices with low requirements on performance of the processor, but low power consumption design and small area requirements.

Description

RISC-V-based interrupt and exception handling system, method and processor

Technical Field

The present invention relates to the field of interrupt and exception handling systems, methods, and processors based on RISC-V.

Background

In the process of continuous evolution of modern computer architecture, RISC-V is becoming an emerging and very open and scalable instruction set architecture, and is being widely used in a variety of fields, from embedded systems to high performance computing, etc. Under such diversified application scenarios, implementation of a simple and efficient interrupt and exception handling mechanism that is specifically applied in the embedded field plays a vital role in the development of embedded RISC-V processors.

RISC-V processors need to handle interrupt requests from different sources and various exceptions during operation. Conventional interrupt handling designs increasingly expose a number of limitations in facing the nature of RISC-V architecture and complex application requirements. Existing high performance processors divide interrupts and exceptions in detail, and divide different interrupt types and exception types more carefully. The complex and functional interrupt and exception handling system is too high in hardware overhead for processors for applications in the embedded domain, and does not meet the requirements of low power consumption and small area.

Disclosure of Invention

In view of the problems in the prior art, the invention provides an interrupt and exception handling system, a method and a processor based on RISC-V, which mainly solve the problems that the interrupt and exception handling design of the existing processor is complex and the requirements of the embedded field on the ground palace and miniaturization are difficult to meet.

In order to achieve the above and other objects, the present invention adopts the following technical scheme.

The application provides an interrupt and exception handling system based on RISC-V, which comprises a core local interrupt controller, a platform level interrupt controller and a delivery module, wherein the core local interrupt controller is used for generating software interrupt and timer interrupt, the platform level interrupt controller is used for integrating a plurality of external interrupt sources into an external interrupt signal, the delivery module is arranged in a processor core, and after receiving interrupt signal requests of the core local interrupt controller and the platform level interrupt controller or exception signal requests of an arithmetic logic unit in the processor core, a pipeline flushing request and a first instruction count value for re-fetching instructions are sent to an instruction fetching stage, wherein the core local interrupt controller and the platform level interrupt controller are mounted on the processor core.

In one embodiment of the present application, the core local interrupt controller includes msip registers, mtime registers, and mtimecmp registers, generates the software interrupt directly through the msip registers and provides the software interrupt to the processor core, reflects the value of the timer through the mtime, and provides a comparison value to the timer through the mtimecmp registers to generate the timer interrupt when the value of the timer is greater than or equal to the comparison value.

In one embodiment of the application, the msip registers are 32-bit registers, and only the least significant bits are valid bits, which are directly given as software interrupts to the processor core.

In an embodiment of the present application, the external interrupt source includes GPIO, UART, API and I2C, and the platform-level interrupt controller arbitrates the external interrupt signals of the external interrupt sources into a unit and sends the unit to the delivery module for processing.

In one embodiment of the present application, when an asynchronous exception, a synchronous exception, and an interrupt occur simultaneously, the priority of the asynchronous exception is higher than the priority of the interrupt, and the priority of the interrupt is higher than the priority of the synchronous exception.

In an embodiment of the present application, the priority of the external interrupt is higher than the priority of the software interrupt, and the priority of the software interrupt is higher than the priority of the timer interrupt.

The application also provides a method applied to the interrupt and exception handling system based on RISC-V, which comprises the steps of entering an exception program by a processor after receiving an interrupt request or an exception request and stopping executing the current program flow, starting executing the exception program from a second instruction count value defined by a mtvec register, updating the exception type into a mcause register and saving the return address of the exception or the interrupt into a mepc register, updating the memory access address or the instruction code causing the current exception or the interrupt into a mtval register, updating the threshold value in the mstatus register to save the working mode and the interrupt enabling configuration before the exception occurs, exiting the exception handling program, starting executing from the return address in the mepc register and updating the threshold value in the mstatus register again to restore the working mode and the interrupt enabling configuration before the exception occurs.

In one embodiment of the application, the step of saving the return address of the exception or interrupt to the mepc register includes updating the interrupt return address saved in the mepc register to the instruction count value of the next unexecuted instruction when an interrupt occurs, updating the return address saved in the mepc register to the instruction count value of the instruction currently experiencing the exception when an exception occurs, and changing the value in the mepc register to point to the next instruction if an exception occurs at ecall or ebreak.

In an embodiment of the present application, the threshold in the mstatus register includes an MIE threshold for indicating whether to globally enable the interrupt in its mode, a MPIE threshold for storing the MIE threshold before the occurrence of the exception, and an MPP threshold for indicating the operation mode.

The application also provides a processor, which comprises the interrupt and exception handling system based on RISC-V.

As described above, the interrupt and exception handling system, method and processor based on RISC-V have the following beneficial effects.

According to the application, the interrupt and the exception trigger the delivery module to send the pipeline flushing request to the finger fetching stage, the interrupt and the narrowly defined exception are integrated into generalized exception, and the specific exception and the interrupt processing details are distinguished for processing, so that the interrupt and exception processing efficiency can be effectively improved, the complex interrupt processing and exception processing design can be avoided, the resource occupation can be reduced, and the system performance requirements of the embedded field processor with low power consumption and small area can be met.

Drawings

FIG. 1 is a schematic diagram of a RISC-V based interrupt and exception handling system according to one embodiment of the present application.

FIG. 2 illustrates memory mapped addresses of a core local interrupt controller in accordance with one embodiment of the present application.

FIG. 3 is a flow chart of a method applied to the RISC-V based interrupt and exception handling system according to an embodiment of the present application.

FIG. 4 is a table showing the register map required in an exception procedure according to an embodiment of the present application.

FIG. 5 is a detailed diagram of the register used by the exception procedure according to one embodiment of the present application.

FIG. 6 is a flow chart of a method of a RISC-V based interrupt and exception handling system according to another embodiment of the present application.

FIG. 7 is a schematic diagram of a micro-architecture of a processor according to an embodiment of the application.

Detailed Description

Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict.

It should be noted that the illustrations provided in the following embodiments merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.

The inventor researches find that:

In the process of continuous evolution of modern computer architecture, RISC-V is becoming an emerging and very open and scalable instruction set architecture, and is being widely used in a variety of fields, from embedded systems to high performance computing, etc. Under such diversified application scenarios, implementation of a simple and efficient interrupt and exception handling mechanism that is specifically applied in the embedded field plays a vital role in the development of embedded RISC-V processors.

RISC-V processors need to handle interrupt requests from different sources and various exceptions during operation. Conventional interrupt handling designs increasingly expose a number of limitations in facing the nature of RISC-V architecture and complex application requirements. For example, in the aspect of interrupt priority management, some existing general designs are too complex and have too many implementation functions, so that it is difficult to meet the requirements of an embedded RISC-V processor for simple implementation functions, small area and low power consumption, thereby affecting the real-time performance of an embedded processor system.

Existing high performance processors divide interrupts and exceptions in detail, and divide different interrupt types and exception types more carefully. For example, interrupt types are classified into external interrupts, timer interrupts, software interrupts, debug interrupts, exceptions are classified into synchronous exceptions and asynchronous exceptions, and asynchronous exceptions are classified into precise asynchronous exceptions and non-precise asynchronous exceptions. And further detailed processing is carried out on different interruption and abnormality classification according to different production reasons. Such complex and functionally rich interrupt and exception handling systems are too hardware overhead for processors for embedded domain applications, not meeting the requirements of low power consumption and small area.

In addition, in the existing RISC-V processor, the interrupt and exception handling manner is too complex and cumbersome. In terms of interrupt nesting functions, low-priority interrupts may unreasonably preempt the processing resources of high-priority interrupts, resulting in processing delays of high-priority interrupts, severely affecting the real-time response capability of the system and the execution efficiency of critical tasks. Meanwhile, a context saving and restoring mechanism in the interrupt processing process is also to be optimized, the current design often consumes more processor time and memory resources, and the interrupt and exception processing method which occupies a large amount of resources and has complex and complicated functions cannot be better suitable for the requirements of the embedded field on the processor.

Based on the problems existing in the prior art, the present application provides an interrupt and exception handling system, method and processor based on RISC-V, and the technical scheme of the present application is described in detail below with reference to specific embodiments.

Referring to fig. 1, fig. 1 is a schematic diagram illustrating an architecture of a RISC-V based interrupt and exception handling system according to an embodiment of the present application. The system comprises a core local interrupt controller, a platform level interrupt controller and a delivery module, wherein the core local interrupt controller is used for generating software interrupt and timer interrupt, the platform level interrupt controller is used for integrating a plurality of external interrupt sources into an external interrupt signal, the delivery module is arranged in a processor core, and after receiving interrupt signal requests of the core local interrupt controller and the platform level interrupt controller or abnormal signal requests of an arithmetic logic unit in the processor core, the delivery module sends pipeline flushing requests and first instruction count values for re-fetching instructions to a fetching stage, wherein the core local interrupt controller and the platform level interrupt controller are mounted on the processor core. Interrupt and exception handling in embodiments of the present application is primarily focused on the processor execution stage. The CLINT module (Core Local Interrupt Controller) is a processor core local interrupt controller, which is a memory address mapping module, and is mainly used for generating software interrupts and timer interrupts. The PLIC module (Platfrom Level Interrupt Controller) is a platform-level interrupt controller, which is also a memory address mapping module, responsible for aggregating and arbitrating multiple external interrupt sources, and integrating them into a single interrupt signal hull to the delivery module of the processor core. Wherein the external interrupt sources may include GPIO, UART, SPI, I C, etc. The processor of the embodiment of the application is designed based on RV32IM subset in RISC-V instruction set architecture, only supporting machine mode. The application integrates interrupts and exceptions into generalized exception handling. Because both interrupts and exceptions occur, the current pipeline execution program will be suspended for the processor to handle interrupts and exception programs, and finally return to the program suspended before the processor executed the interrupt exception. The system of the embodiment of the application unifies interrupts and exceptions into generalized exception handling, but separate handling of interrupts and exceptions occurs in specific detail. Based on generalized exception, whether an interrupt request or an exception request is received, the current processing program is suspended according to the same flow, the exception program is executed from PC (Program Counter) addresses defined in the base address of the exception entry, and after the exception program is entered, the interrupt and the exception processing mode are distinguished. It should be noted that, the PC address is an instruction count value, and the value may represent an address of an instruction to be executed.

Regfile in FIG. 1 is a register file, which is an array of registers in a processor. RISC-V register files typically have two degree ports and one write port, allowing multiple concurrent accesses to different registers, thereby improving data throughput. OITF (Outstanding Instruction Track FIFO) for detecting RAW and WAW dependencies associated with long instructions. Each time a long instruction is dispatched by the dispatch point, an entry is allocated in the OITF, the entry stores the source operand register index and the result register index of the long instruction, and the entry in the OITF is removed after each sequential write back of a long instruction at the write back point. Pipeline structures typically include three stages, instruction fetch-decode-execute, through which a processor fetches instructions. The Decoder in fig. 1 is a Decoder, and is used in the decoding stage. Pipeline flush requests refer to the fact that in a pipeline processing procedure, when the execution result of a predicted instruction is inconsistent with the actual execution result, the pipeline needs to restart re-execution from the fetch stage, and this procedure is called pipeline flush. Long instructions refer to instructions that typically require multiple clock cycles to complete execution and write back, also known as "post-commit long pipeline instructions.

In one embodiment, the core local interrupt controller includes msip registers, mtime registers, and mtimecmp registers, generates the software interrupt directly through the msip registers and provides the software interrupt to the processor core, reflects the value of the timer through the mtime, and provides a comparison value to the timer through the mtimecmp registers to generate the timer interrupt when the value of the timer is greater than or equal to the comparison value. In particular, referring to FIG. 2, the memory mapped addresses of the core local interrupt controller are shown in FIG. 2. CLINT is used to generate two interrupt types, software interrupt and timer interrupt, respectively. When generating the software interrupt type, a 32-bit msip register is implemented in the CLINT module. Only the least significant bit of the register is the valid bit, which is passed directly to the processor core as a software interrupt signal. When the software write MSIP register triggers a software interrupt, the MSIP field in the CSR register mip generates a1 to indicate the current interrupt waiting state. Software may clear the software interrupt by writing 0 to msip registers. In generating the timer interrupt, a 64-bit register is implemented in the CLINT module. This register reflects the value of the 64-bit timer. The timer counts according to the low-speed input beat signal, and the timer counts always by default. A 64-bit mtimecmp register is also implemented in the CLINT module. This register acts as a comparison value for the timer, and a timer interrupt is generated assuming that the value mtime of the timer is greater than or equal to the value mtimecmp. Software may clear the timer interrupt by overwriting mtimecmp the value (making it greater than mtime).

In one embodiment, the PLIC is a platform-level interrupt controller (Platfrom Level Interrupt Controller) that is also a module for mapping memory addresses, and in the processor SoC of the embodiment of the present application, the PLIC is connected to an external interrupt source such as GIPO, UART, SPI, I C, and the PLIC arbitrates a plurality of external interrupt sources into a unit interrupt signal and sends the unit interrupt signal to the processor core delivery module for processing. The processor interrupt of the embodiment of the application has only the three types, the interrupt priority is external interrupt priority > software interrupt > timer interrupt in sequence, and mcause registers select and update the value of the abnormal number according to the priority sequence. In the interrupt processing according to the embodiment of the present application, the delivery module receives requests of 2 interrupt signals from CLINT and PLIC and an abnormal signal request of ALU (ARITHMETIC AND logic unit), and the delivery module sends a pipeline flush request and a PC for re-fetching an instruction to the fetch stage, so as to start fetching an instruction from a new PC address. When the asynchronous exception and the synchronous exception and the interrupt caused by the ALU occur simultaneously, the asynchronous priority caused by the long instruction is highest, the interrupt priority is second, and the synchronous exception caused by the ALU is lowest.

Referring to fig. 3-5, fig. 3 is a flowchart illustrating a method applied to the RISC-V based interrupt and exception handling system according to an embodiment of the present application. FIG. 4 is a table showing the register map required in an exception procedure according to an embodiment of the present application. FIG. 5 is a detailed diagram of the register used by the exception procedure according to one embodiment of the present application. The method comprises the following steps:

Step S300, after receiving the interrupt request or the exception request, the processor enters an exception program and stops executing the current program flow. Specifically, when the exception request is triggered, the processor immediately enters an exception program, stops the execution flow of the current program, directly stops executing the current flow when the interrupt and the exception are received due to the fact that the interrupt and the exception are integrated into a generalized exception, and enters the exception program.

Step S310, starting to execute the exception program from the second instruction count value defined by mtvec registers. The second instruction count value is the PC address of the exception program. Designation and modification may be made by CSR (Control and status register).

In step S320, the exception type is updated into mcause registers, and the return address of the exception or interrupt is saved into mepc registers.

In step S320, saving the return address of the exception or interrupt to the mepc register includes updating the interrupt return address saved in the mepc register to the instruction count value of the next unexecuted instruction when the interrupt occurs, updating the return address saved in the mepc register to the instruction count value of the instruction where the exception occurs currently when the exception occurs, and changing the value in the mepc register to point to the next instruction if the exception occurs ecall or ebreak. Specifically, after entering the exception program, the registers are first updated mcause to reflect the specific type of the current exception, and the software can read the values of the registers to ascertain the cause of the exception. Next, the return address of the exception is stored in mepc registers, which address is used to return the processor to the PC value of the interrupted program after the exception has ended. In this process, different treatments are performed for the narrow interrupt and exception, if an interrupt occurs, the interrupt return address saved by mepc is updated to the PC value of the next instruction which has not yet been executed, if an exception occurs, the interrupt return address saved by mepc is updated to the PC value of the current exception instruction, and if an exception occurs ecall or ebreak, software sets the value of the mepc register to mepc = mepc +4 in the exception handler to ensure that the program can point to the next instruction, preventing the trap from jumping back to the dead loop of ecall or ebreak instructions again.

Step S330, the memory access address or instruction code that caused the current exception or interrupt is updated into mtval registers.

In one embodiment, the mtval registers are updated to reflect the memory access address or instruction encoding that caused the current exception.

In step S340, the threshold in the mstatus registers is updated to preserve the operating mode and interrupt enable configuration prior to the occurrence of the exception.

In one embodiment, the thresholds in the mstatus registers include a MIE threshold to indicate whether the interrupt is globally enabled in its mode, a MPIE threshold to store the MIE threshold before the exception occurs, and an MPP threshold to indicate the mode of operation. When an abnormality occurs, the value of the MIE domain is updated to 0, the value of the MPIE domain is updated to the value of the MIE domain before the abnormality occurs, the MIE value before the abnormality occurs is recovered by using the value of the MPIE domain after the abnormality is over, and the value of the MPP domain is updated to the mode before the abnormality occurs.

In step S350, the exception handler is exited, and execution is started from the return address in the mepc registers, and the threshold in the mstatus registers is updated again to resume the operating mode and interrupt enable configuration before the exception occurred. Using the mret instruction to exit the exception state, execution of the current instruction stream is stopped, and execution of the program is resumed in accordance with the PC address defined by the mepc register, and at the same time the mstatus register is updated, the MIE field in the register is updated to the current MPIE field value, and the MPIE field value is updated to 1.

Referring to fig. 6, the process of the method may also be implemented by first entering an exception program by the processor after sending an exception request, stopping executing the current program flow by the processor, and starting from the PC address defined by the mtvec register, wherein the mtvec register is a machine mode exception entry base address (MACHINE TRAP-vector base-address), and the CSR designates a readable and writable register, and the software developer changes the value therein by changing the value. The mcause registers are updated to reflect the current exception type, and software can read the register values and query the specific cause of the exception. The return address of the exception is saved in mepc registers for saving the PC value of the interrupted program to be returned by the processor after the exception has ended, and is given in updating mepc registers, embodiments of the present application distinguish between interrupts and exceptions in a narrow sense. When an interrupt occurs, the saved interrupt return address mepc is updated to the PC value of the next instruction that has not yet been executed. When an exception occurs, the mepc saved interrupt return address is updated to the PC of the instruction that is currently in exception, if an exception occurs ecall or ebreak, the value of the mepc register is changed by software in the exception handler, setting it to mepc = mepc +4, pointing it to the next instruction, preventing the occurrence of a jump back to ecall or ebreak instruction again, thus entering a dead loop. The mtval registers are then updated to reflect the memory access address or instruction encoding that caused the current exception. The field value in the mstatus register is updated, where the MIE field indicates whether the interrupt is globally enabled in machine mode. The value of MPIE field is updated to be the value of MIE field before abnormality occurs, the value of MPIE field is used to restore the MIE value before abnormality occurs after abnormality is over, the value of MIE field is updated to be 0, and the value of MPP field is updated to be the mode before abnormality occurs. After the abnormality is ended, the operation mode before the occurrence of the abnormality is restored using the value of the MPP field. The processor core only supports the machine mode, and the MPP threshold value is binary 11. Finally, after the processor completes the exception processing, it exits the exception using mret instructions, halts execution of the current instruction stream, and in turn starts execution from the PC address defined by the mepc register, while updating mstatus register in which the MIE field is updated to the current MPIE field value and the MPIE field value is updated to 1.

In one embodiment, the system of the present application may support 5 exception types, three interrupt types, and simultaneously support 6 interrupt priorities, which may be set according to the type and number of external interrupt sources, without limitation.

Referring to fig. 7, fig. 7 is a schematic diagram of a micro-architecture of a processor according to an embodiment of the application. PLIC and CLINT are mounted on the processor core and external interrupt sources may include UART0, I2C0, GPIO, SPI, UART1, I2C1, and the like. The architecture of the specific processor may be set and adjusted according to actual requirements, and is not limited herein.

Based on the technical scheme provided by the embodiment of the application, the interrupt and abnormal functions of the RV32IM instruction set architecture processor in the machine mode can be simply realized. In addition, the design method has the advantages of simple structure, low power consumption and small circuit area, is suitable for embedded processor equipment with low requirements on performance of the processor, low power consumption design and small area requirements, and has good engineering practicability.

The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (10)

1. A RISC-V based interrupt and exception handling system, comprising:

a core local interrupt controller for generating a software interrupt and a timer interrupt;

a platform-level interrupt controller for integrating a plurality of external interrupt sources into an external interrupt signal;

And the delivery module is arranged in the processor core, and is used for sending a pipeline flushing request and a first instruction count value for re-fetching instructions to the instruction fetching stage after receiving interrupt signal requests of the core local interrupt controller and the platform level interrupt controller or abnormal signal requests of an arithmetic logic unit in the processor core, wherein the core local interrupt controller and the platform level interrupt controller are mounted on the processor core.

2. The RISC-V based interrupt and exception handling system of claim 1, wherein the core local interrupt controller includes msip registers, mtime registers, and mtimecmp registers, the software interrupt is generated directly by the msip registers and provided to the processor core, the value of the timer is reflected by the mtime, and a compare value is provided to the timer by the mtimecmp registers to generate the timer interrupt when the value of the timer is greater than or equal to the compare value.

3. The RISC-V based interrupt and exception handling system of claim 2, wherein the msip registers employ 32-bit registers and only the least significant bits are valid bits, the valid bits being directly provided as software interrupts to the processor core.

4. The RISC-V based interrupt and exception handling system of claim 1, wherein the external interrupt sources include GPIO, UART, API and I2C, and the platform-level interrupt controller arbitrates the external interrupt sources into one unit of the external interrupt signal and feeds the external interrupt signal to the delivery module for processing.

5. The RISC-V based interrupt and exception handling system of claim 1, wherein when an asynchronous exception, a synchronous exception, and an interrupt occur simultaneously, the priority of the asynchronous exception is higher than the priority of the interrupt, and the priority of the interrupt is higher than the priority of the synchronous exception.

6. The RISC-V based interrupt and exception handling system of claim 1, wherein the external interrupt has a higher priority than the software interrupt, and wherein the software interrupt has a higher priority than the timer interrupt.

7. A method for use in a RISC-V based interrupt and exception handling system according to any one of claims 1-6, comprising:

after receiving the interrupt request or the exception request, the processor enters an exception program and stops executing the current program flow;

starting to execute the exception program from a second instruction count value defined by mtvec registers;

Updating the exception type into mcause registers and saving the return address of the exception or interrupt into mepc registers;

updating a memory access address or instruction code that caused the current exception or interrupt into a mtval register;

Updating mstatus the thresholds in the registers to preserve the operating mode and interrupt enable configuration prior to the occurrence of the exception;

The exception handler is exited, execution is started from the return address in the mepc registers, and the threshold in the mstatus registers is updated again to resume the operating mode and interrupt enable configuration prior to the exception.

8. The method of claim 7, wherein the step of saving the return address of the exception or interrupt to the mepc registers comprises:

when an interrupt occurs, the interrupt return address stored in the mepc register is updated to the instruction count value of the next unexecuted instruction, when an exception occurs, the return address stored in the mepc register is updated to the instruction count value of the instruction that is currently experiencing the exception, and if an exception occurs ecall or ebreak, the value in the mepc register is changed to point to the next instruction.

9. The method of claim 7, wherein the threshold in the mstatus registers comprises:

MIE threshold value, is used for showing whether the overall situation enables the interrupt in its mode;

MPIE threshold, which is used for saving MIE threshold before abnormality occurs;

the MPP threshold is used to represent the mode of operation.

10. A processor comprising a RISC-V based interrupt and exception handling system as claimed in any one of claims 1to 6.