CN1200512C - Multi-stage modulator - Google Patents
Multi-stage modulator Download PDFInfo
- Publication number
- CN1200512C CN1200512C CN 01129562 CN01129562A CN1200512C CN 1200512 C CN1200512 C CN 1200512C CN 01129562 CN01129562 CN 01129562 CN 01129562 A CN01129562 A CN 01129562A CN 1200512 C CN1200512 C CN 1200512C
- Authority
- CN
- China
- Prior art keywords
- output
- signal
- buffer
- order
- output buffer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Analogue/Digital Conversion (AREA)
Abstract
The present invention relates to a multi-stage modulation device. A converting device which can output m-step analog signals is used for converting n-m maximal bit numerical values in n bit PCM numerical values into PWM waveforms to output first input signals and second input signals. 2<m1> first output damping devices are used for receiving the first input signals and each first output damping device has an output current value. 2<m2> second output damping devices are used for receiving the second input signals and each second output damping device has an output current value. A control device is used for controlling the on-off states of the first output damping devices and the second output damping devices.
Description
The invention relates to a kind of multi-stage modulator, and particularly relevant for a kind of modulating device of multistage pulses width of digital to analogy.
(Pulse Width Modulation is that (Pulse Code Modulation, PCM) conversion of signals one-tenth was represented with the different work period (dutycycle) with the digital pulse coding modulation PWM) in pulse width modulation.Convert PCM to PWM and can directly promote the output of loudspeaker generation analog signal afterwards, become PWM digital analog converter (PWM DAC).The resolution of PWM DAC, sampling rate and input clock pulse frequency have following relation:
A. single-ended PWM DAC: resolution * sampling rate=input clock pulse frequency
B. both-end PWM DAC: resolution * sampling rate=2 * input clock pulse frequency
From the above, when the input clock pulse fixed-frequency of system, resolution and sampling rate are inverse relations.That is to say,, then certainly will will reduce sampling rate if want PWM DAC to have high-res.Otherwise,, then must sacrifice resolution if will improve sampling rate.
Please refer to Fig. 1, what it illustrated is the calcspar of traditional a kind of PWM DAC, wherein the PCM change-over circuit receives after the PCM signal, export P+12 and P-14 signal immediately to buffer 16/18, and via output buffer 16/18 output drive signal to output device 20, make the signal of output device 20 output PWM.
Please refer to Fig. 2, what it illustrated is the schematic diagram of traditional a kind of PWM DAC.
Conventional P WM DAC mainly is made up of output buffer (output driver) 22 and output buffer 24.The input of output buffer 22 receives an input signal P+, and its output is connected to a loud speaker (speaker) 26, an input.And the input of output buffer 24 receives an input signal P-, and its output is connected to another input of loud speaker 26.Loud speaker 26 is by from two input signals of output buffer 22 with output buffer 24, and is extremely outside to export a voice signal.Above-mentioned input signal P+ and P-are from order to the maximum bit value of the n-m in the n bit PCM numerical value is converted to the change-over circuit of PWM waveform, and wherein, n and m are positive count, and n＞m.
In view of this, the present invention proposes a kind of multi-stage modulator, comprises that device has: change-over circuit, 2
mIndividual first output buffer, 2
mIndividual second output buffer, control device and output device.Above-mentioned m rank change-over circuit is in order to convert the n-m in the n bit PCM numerical value maximum bit value to the PWM waveform, to export first input signal and second input signal.First output buffer is in order to receiving first input signal, and each first output buffer has each output current value.Second output buffer is in order to receiving second input signal, and each second output buffer has each output current value.
And control device is in order to control the on off state of first output buffer and second output buffer.Wherein, control device can in a certain interval of each sampling period, be transformed into the high output impedance state with several first output buffers and several second output buffers according to m the minimum bit of PCM.In addition, the number of first output buffer and second output buffer can be different, that is, can have 2
M1Individual first output buffer and 2
M2Individual second output buffer, wherein, m1 and m2 are respectively the positive number less than n.The multi-standard-bit pulse width modulation digital analog converter that the present invention proposes not only can improve resolution, and also can keep original sampling rate.
For above-mentioned and other purposes of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below:
Graphic simple declaration:
What Fig. 1 illustrated is the calcspar of traditional a kind of PWM DAC;
What Fig. 2 illustrated is the schematic representation of apparatus of traditional a kind of PWM DAC;
Fig. 3 illustrates is calcspar according to MPWM DAC of the present invention;
Fig. 4 illustrates is schematic representation of apparatus according to a kind of both-end quadravalence MPWM DAC of a preferred embodiment of the present invention;
Fig. 5 illustrates is control device schematic diagram according to a kind of MPWM DAC of a preferred embodiment of the present invention;
What Fig. 6 illustrated is the output waveform of conventional P WM DAC; And
What Fig. 7 illustrated is the output waveform of MPWM DAC of the present invention.
As discussed previously, the output waveform of conventional P WM has only the digital waveform of 0 and 1 liang of accurate position, yet the present invention changes to analog output with the PWM output waveform, this claim for multi-standard-bit pulse width modulate (Multi-level PWM, MPWM).Adopt the method for the MPWMDAC of the present invention's proposition, not only can improve resolution, and also can keep original sampling rate.Below, will be example with quadravalence MPWM DAC, implementation method of the present invention is described in detail in detail.
Please refer to Fig. 3, it is drawn is calcspar according to a kind of MPWMDAC of a preferred embodiment of the present invention, after wherein PCM change-over circuit 28 receives the signal of PCM, each exports an input signal MP+30, input signal MP-32, export buffer unit 38/40 and control device 34 respectively to enabling signal 33, and receive in the enabling signal 33 at control device 34, then export control signal 36 to first output buffers 38 and second output buffer 40, and first output buffer 38 and second output buffer 40 respectively receive input signal MP+30, input signal MP-32, with control signal 36, each output drive signal of now is to output device 42, in order to output pwm signal.
Please refer to Fig. 4, it illustrates is calcspar and schematic diagram according to a kind of MPWMDAC of a preferred embodiment of the present invention.
MPWM DAC of the present invention is that the output buffer 22 and 24 with Fig. 2 conventional P WM DAC respectively is divided into four little output buffer 52a-52d and output buffer 54a-54d respectively, makes the summation of the output current of each output buffer 52a-52d or output buffer 54a-54d respectively be the output buffer 12 of conventional P WM DAC or 14 output current value.Wherein, removing 52a and 54a can be general output buffer or tristate buffer (Tri-State Buffer), and other output buffer 52bn-52d and 54b-54d realize with tristate buffer, illustrate and the following stated all is example with the tristate buffer.
The input of each tristate buffer 52a-52d all receives an input signal MP+, and its output E, F, G and H are connected to an input of loud speaker 56.Each tristate buffer 53a-52d has a control end respectively, and these control ends receive control signal A, B, C and D respectively, in order to the on off state of control tristate buffer 52a-52d, wherein control signal A, B, C and D are that control device 34 by Fig. 3 is produced.Similarly, the input of each tristate buffer 54a-54d all receives an input signal MP., and its output I, J, K and L are connected to another input of loud speaker 56.Each tristate buffer 54a-54d has a control end respectively, and these control ends receive above-mentioned control signal A, B, C and D respectively, in order to the on off state of control tristate buffer 54a-54d.Above-mentioned input signal MP+ and MP-are from order to the maximum bit value of the n-m in the n bit PCM numerical value is converted to the m rank PCM change-over circuit of PWM waveform, and wherein, n and m are positive count, and n＞m.
Though the summation of each the output buffer 52a-52d of MPWM DAC or the maximum output current of output buffer 54a-54d is only the current value of conventional P WM DAC, but owing to the action of four output buffer 52a-52d or output buffer 54a-54d is identical, so its result and conventional P WM DAC equivalence.
If the PCM value that will further represent X+ (Q/P) then conventional P WM DAC can't be finished, wherein P represents the summation of the maximum output current of output buffer 52a-52d or output buffer 54a-54d, each electric current total value of the tristate buffer that Q then represents control device and started, because conventional P WM DAC is digital output, least unit is 1, so can only represent X and X+1, integer values such as X+2, and since each output buffer 52a-52d of quadravalence MPWM DAC of the present invention and output buffer 54a-54d its maximum output current all arranged, ingenious collocation by these four output buffer 52a-52d or output buffer 54a-54d, least unit can be reduced into Q/P, and then the PCM value of expression X+ (Q/P).
Please be simultaneously with reference to Fig. 4 and Fig. 7.Figure 7 shows that the output waveform of MPWM DAC of the present invention.
Between time X and X+1, each keeps the output buffer representative of electronegative potential that output valve is added the maximum current of its output, and during this section, is not that the output buffer of electronegative potential must become the high output impedance state.Till finishing to this after time X+1, all output buffers are all exported high potential sampling period.
For instance, during first sampling period, in the time of at the beginning, input signal MP+ and the MP. of output buffer 52a-52d and output buffer 54a-54d are respectively high levle and low level, just become the high levle state and input signal MP. can keep the low level state behind time X+1.In addition, control signal A, B, C and D are high levle, and this moment, output signal B, F, G and H and 1, J, K and the L of output buffer 52a-52d and output buffer 54a-54d were in high levle and low level respectively.
After time X, control signal B, C and D can become low level, make output signal F, G and H to descend from the high levle state and one fix the position, and output signal J, K can fix the position from low level state rising one with L.Now, after time X+1, control signal B, C and D can become high levle again, make output signal F, G and H become the high levle state again, and output signal J, K and L can rise to the high levle state fully, and output signal J, K and L can maintain the high levle state just become the low level state after this first sampling period finishes.
During second sampling period, the accurate position state variation of the input signal MP+ of output buffer 52a-52d and 54a-54d and MP-is as described in previous first sampling period.And control signal A, B, C and D are high levle, and this moment, output signal E, F, G and H and I, J, K and the L of output buffer 52a-52d and output buffer 54a-54d were in high levle and low level respectively.
After time X, control signal C and D can become low level, make output signal G and H to descend from the high levle state and one fix the position, and output signal K can fix the position from low level state rising one with L.Now, after time X+1, control signal C and D can become high levle again, make output signal G and H become the high levle state again, and output signal K and L can rise to the high levle state fully, and output signal I and J can become high levle and output signal K and L can maintain the high levle state, finishes back output signal I, J, K and L up to this second sampling period and just all becomes the low level state.
During the 3rd sampling period, the accurate position state variation of the input signal MP+ of output buffer 52a-52d and output buffer 54a-54d and MP-is as described in previous first sampling period.And control signal A, B, C and D are high levle, and this moment, output signal B, F, G and H and 1, J, K and the L of output buffer 52a-52d and output buffer 54a-54d were in high levle and low level respectively.
After time X, control signal D can become low level, make output signal H to fix the position from high levle state decline one, and output signal L can fix the position from low level state rising one.Now, after time X+1, control signal D can become high levle again, make output signal H become the high levle state again, and output signal L can rise to the high levle state fully, and output signal I, J and K can become high levle, finish back output signal I, J, K and L up to this 3rd sampling period and just all become the low level state.
Now, the waveform of sampling period returned shown in first sampling period, and cycling in regular turn.
Wherein, the MPWM DAC that loud speaker 56 is exported can be changed according to output buffer 52a-52d is different with the output current of output buffer 54a-54d, for instance, the output current of output buffer 52a-52d and output buffer 54a-54d respectively is MP+ and MP, 1/8,1/8,1/4,1/2, and via above-mentioned How It Works, and by the 34 control device selection output buffer 52a-52d of Fig. 3 and the output situation of output buffer 54a-54d, thus, in order to control the output situation of loud speaker 56.
Please refer to Fig. 5, it illustrates is schematic diagram according to a kind of MPWMDAC control device of a preferred embodiment of the present invention, wherein B1 and B0 are the minimum bit of PCM, in order to the startup of operation control 58/60/62 whether its input, and, by A, B, C, with D output control signal, the state of exporting in order to the output buffer 52a-52d and the output buffer 54a-54d of control chart 4.
Herein, present embodiment is to be example with quadravalence MPWM DAC, can certainly eight rank MPWM DAC or more, and for example 2
n, wherein n can be the positive count value.For instance, if n=1, then resolution can have more 1 bit, if n=2, then resolution can have more 2 bits, if n=3, then resolution can have more 3 bits.
In addition, must be noted that the number of first output buffer and second output buffer can be different.Just, can have 2
M1Individual first output buffer and 2
M2Individual second output buffer, and wherein m1 and m2 are respectively positive number less than n.
In sum,, not only resolution can be improved, also original sampling rate can be kept simultaneously according to MPWM DAC of the present invention.Though wherein present embodiment is an example with MPWM DAD, however know this operator as can be known the present invention also can be used in the digital to analogy modulation.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; anyly have the knack of this skill person; without departing from the spirit and scope of the present invention; when can being used for a variety of modifications and variations, so protection scope of the present invention is as the criterion when looking accompanying the claim person of defining.
Claims (14)
1. multi-stage modulator in order to receiving a digital pulse coding modulation signal, and is exported a pulse width modulating signal, it is characterized in that, comprising:
One digital pulse coding modulation conversion circuit, in order to receive this digital pulse coding modulation signal of n bit, convert the bit value of n-m to pulse width modulated waveform, wherein m is the number for the minimum bit signal in this digital pulse coding modulation signal, and n＞m, now, this digital pulse coding modulation conversion circuit is exported one first output signal, one second output signal is with an enabling signal;
One control device in order to receiving this enabling signal, and produces a control signal;
One first output buffer has 2
M1Individual output buffer, wherein, m1＜n in order to receiving this first output signal and this control signal, and exports one first drive signal;
One second output buffer has 2
M2Individual output buffer, wherein, m2＜n in order to receiving this second output signal and this control signal, and exports one second drive signal; And
One output device receives this first drive signal and this second drive signal, and exports this pwm signal;
Wherein this control device can be according to the minimum bit signal of PCM, in a certain interval of each sampling period, select and close to make these output buffers of this first output buffer and these output buffers of this second output buffer form the high output impedance state, in order to control the output situation of this first output buffer and this second output buffer.
2. multi-stage modulator according to claim 1 is characterized in that, wherein these output buffers of this first output buffer are meant tristate buffer.
3. multi-stage modulator according to claim 1 is characterized in that, wherein these output buffers of this second output buffer are meant tristate buffer.
4. multi-stage modulator according to claim 1 is characterized in that, these output buffers of this first output buffer wherein, and wherein these output buffers are output buffer.
5. multi-stage modulator according to claim 1 is characterized in that, these output buffers of this second output buffer wherein, and wherein these output buffers are output buffer.
6. multi-stage modulator according to claim 1, it is characterized in that, wherein this control device has a plurality of controllers, these controllers are in order to receive this enabling signal of this change-over circuit, this enabling signal is these the minimum bit signals for this digital pulse coding modulation signal, differentiate these output buffers of this first output buffer and this second output buffer these output buffers startup whether.
7. multi-stage modulator according to claim 1 is characterized in that, wherein this output device is to be a loud speaker.
8. multi-stage modulator, in order to receive a digital signal, this digital signal has the accurate bit of at least one modulation bit and at least one position, and exports a modulated-analog signal, it is characterized in that this digital simulation modulating device with multidigit standard comprises:
One change-over circuit, in order to receiving this digital signal, and, convert this modulation bit of this digital signal to one first output signal and one second output signal, then, this change-over circuit is exported this first output signal, this second output signal, and this accurate bit of this digital signal;
One control device in order to receiving this accurate bit of this digital signal, and produces a control signal;
A plurality of first output buffers in order to receiving this first output signal and this control signal, and are exported one first drive signal;
A plurality of second output buffers in order to receiving this second output signal and this control signal, and are exported one second drive signal; And
One output device receives this first drive signal and this second drive signal, in order to export this modulated-analog signal;
Wherein this control device can be according to this accurate bit, in a certain interval of each sampling period, select and close to make some first output buffers and some second output buffers form the high output impedance state, in order to control the output situation of some first output buffers and some second output buffers.
9. multi-stage modulator according to claim 8 is characterized in that, wherein these first output buffers are meant tristate buffer.
10. multi-stage modulator according to claim 8 is characterized in that, wherein these second output buffers are meant tristate buffer.
11. multi-stage modulator according to claim 8 is characterized in that, wherein these first output buffers one of them be output buffer.
12. multi-stage modulator according to claim 8 is characterized in that, wherein these second output buffers one of them be output buffer.
13. multi-stage modulator according to claim 8, it is characterized in that, in order to the startup of differentiating these first output buffers and these second output buffers whether wherein this control device has a plurality of controllers, and these controllers are in order to receiving this accurate bit of this change-over circuit.
14. multi-stage modulator according to claim 8 is characterized in that, wherein this output device is to be a loud speaker.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01129562 CN1200512C (en) | 2001-06-27 | 2001-06-27 | Multi-stage modulator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01129562 CN1200512C (en) | 2001-06-27 | 2001-06-27 | Multi-stage modulator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1393994A CN1393994A (en) | 2003-01-29 |
| CN1200512C true CN1200512C (en) | 2005-05-04 |
Family
ID=4669275
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 01129562 Expired - Fee Related CN1200512C (en) | 2001-06-27 | 2001-06-27 | Multi-stage modulator |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1200512C (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105553915B (en) * | 2015-12-10 | 2020-07-03 | 中国人民解放军32181部队 | Demodulation method for transient modulation parameters of intermittent radiation signals |
-
2001
- 2001-06-27 CN CN 01129562 patent/CN1200512C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN1393994A (en) | 2003-01-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5337338A (en) | Pulse density modulation circuit (parallel to serial) comparing in a nonsequential bit order | |
| EP1122973B1 (en) | Digital pulse-width-modulation generator | |
| US4621254A (en) | Apparatus and methods for analogue-to-digital conversion | |
| EP2432124B1 (en) | Pulse width modulator | |
| JP3090200B2 (en) | Pulse width modulator | |
| JPH07193509A (en) | Thermometer binary encoding method | |
| CN1571274A (en) | Multi level class-D amplifier by means of 2 physical layers | |
| JP2001522572A (en) | Class D amplifier with reduced clock requirements and related methods | |
| CN1841937A (en) | Voltage hold circuit and clock synchronization circuit | |
| CN1829085A (en) | Tri-state pulse density modulator | |
| CN1650525A (en) | Sigma-delta analog-to-digital converter and method | |
| JP2004032501A (en) | Apparatus and method for digital signal conversion | |
| CN1269641A (en) | Circuit for attenuating noise in data converter and method thereof | |
| US6927715B2 (en) | Device and control structure of multi-level pulse width modulation | |
| CN1200512C (en) | Multi-stage modulator | |
| EP0836769A1 (en) | Rotated-bit pulse width modulated digital-to-analog converter | |
| CN1156974C (en) | Pulse width modulation control system | |
| JPH0783267B2 (en) | Device for converting a binary signal into a DC signal proportional thereto | |
| US4685114A (en) | Waveform modulation system | |
| EP1014552B1 (en) | Conversion of a numeric command value in a constant frequency PWM drive signal for an electromagnetic load | |
| CA2499981A1 (en) | Digital-to-analog conversion with an interleaved, pulse-width modulated signal | |
| US6281827B1 (en) | Method of converting digital signal to analog signal | |
| US7215272B2 (en) | Schemes to implement multi-level PWM in digital system | |
| CN1112777C (en) | Signal processing method and device | |
| GB2177565A (en) | Digital signal processing device working with continuous bit streams |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20050504 |