CN119947110A - A memory and a method for preparing the same - Google Patents
A memory and a method for preparing the same Download PDFInfo
- Publication number
- CN119947110A CN119947110A CN202311459829.3A CN202311459829A CN119947110A CN 119947110 A CN119947110 A CN 119947110A CN 202311459829 A CN202311459829 A CN 202311459829A CN 119947110 A CN119947110 A CN 119947110A
- Authority
- CN
- China
- Prior art keywords
- region
- doping
- doping type
- transfer transistor
- vertical transfer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Semiconductor Memories (AREA)
Abstract
The embodiment of the invention discloses a memory and a preparation method thereof, wherein the memory comprises a plurality of memory cells, each memory cell comprises a charge storage area and a vertical transfer transistor positioned on the charge storage area, the doping concentration of a source end, a drain end and a channel area of the vertical transfer transistor is controlled, so that band tunneling is easy to occur at an interface of the source end and the channel area to realize lower subthreshold swing and larger on-state current, the read-write speed is improved, and further, a lightly doped concentration area which comprises light doping and has opposite doping types with the drain end is controlled between the drain end and the channel area, so that the leakage current is reduced, the refreshing times are reduced, and the power consumption is reduced. The preparation method of the memory can be completed by only simple doping concentration control, can be compatible with the manufacture of the CMOS image sensor, and can reduce the process manufacture difficulty.
Description
Technical Field
The present invention relates to the field of storage processing of image sensors, and more particularly, to a memory and a method for manufacturing the same
Background
With the increase of the pixel array density in the image sensor, the storage requirement on the image signal is also increasing, which makes the buffer memory occupy a very large area in the image sensor chip and consumes a large amount of energy in the fast reading and writing process. In order to further improve the energy consumption ratio of the cache system, a process method for preparing the high-density multi-value cache by using etching and epitaxy processes is provided in the earlier stage, so that the storage density of signals is effectively improved, and the cache area is reduced. However, under the conventional transistor design, the read-write of the large data signal still needs to consume a lot of energy.
As shown in fig. 1, which is a schematic example of the conventional memory design, the conventional vertical transfer transistor Tx is designed to have a small doping concentration of the source S, the channel CL and the drain D, and sometimes only the drain is heavily doped to reduce the leakage current, but the performance improvement of the memory is very limited. The conventional memories, which use conventional transistor designs, consume a lot of energy, and in the conventional designs, charge transfer is accomplished by thermionic emission in the conventional MOSFET, so that the minimum value of the subthreshold swing (subthreshold swing is a performance index for measuring the mutual conversion rate between the on and off states of the transistor and represents the amount of change of gate voltage required by ten times of change of leakage current) is not lower than the lower limit value of 60mV/dec, in which case the switching ratio (I on/Ioff) of the transistor at a lower operation voltage is difficult to increase, so that the reading speed of the memory charge is difficult to further increase, and due to the influence of short channel effect, as the memory density increases, the capacitance leakage is increasingly obvious, the memory time is limited, and the refresh frequency is forced to increase, resulting in difficulty in reducing the power consumption.
Disclosure of Invention
Based on the above problems, the invention aims to provide a memory and a preparation method thereof, wherein the memory utilizes the technological process of the pixel region of the existing CMOS image sensor, only a transfer transistor with tunneling is prepared by changing doping distribution to be used as a switch of the memory, and the doping concentration distribution design of the source end and the channel region realizes lower subthreshold swing and larger on-state current, thereby improving the reading and writing speed. Further, a light doping concentration region which is lightly doped and has the doping type opposite to that of the drain terminal is formed between the drain terminal and the channel region, so that leakage current is reduced, refreshing times are reduced, and power consumption is reduced. The preparation method of the memory can be completed by only simple doping concentration control, can be compatible with the manufacture of the CMOS image sensor, and can reduce the process manufacture difficulty.
The invention provides a preparation method of a memory, which comprises a plurality of memory cells, wherein each memory cell comprises a charge storage region and a vertical transfer transistor positioned on the charge storage region, and is characterized in that the preparation method comprises the steps of providing a substrate, preparing the charge storage region on the substrate, and preparing the vertical transfer transistor on the charge storage region, wherein the doping concentration of a source end, a drain end and a channel region of the vertical transfer transistor is controlled so that band-to-band tunneling is easy to occur at an interface of the source end and the channel region.
In some embodiments, the source terminal of the vertical transfer transistor includes a heavily doped first doping type region, the drain terminal includes a heavily doped second doping type region, the channel region includes an intrinsic doping region, or a first lightly doping region, wherein the first doping type is opposite to the second doping type.
In some embodiments, the first doping type region is formed by self-aligned implantation after the vertical transfer transistor is etched, or the first doping type region including a ring-shaped region, or the first doping type region including a U-shaped region, or the first doping type region including the first sub-region and the second sub-region which are independently spaced.
In some embodiments, the first doping type region is formed by well implantation.
In some embodiments, the gate of the vertical transfer transistor is in a flat loop shape surrounding the channel region in a plane perpendicular to the length direction of the channel.
In some embodiments, the gate includes a ring shape or a U shape on a peripheral side of the channel region or includes first and second sub-gates on both sides of the channel region in a plane perpendicular to a length direction of the channel.
In some embodiments, a second lightly doped region is further included between the drain and the channel region, the second lightly doped region having a doping type opposite to the doping type of the second doping type region.
In some embodiments, both sides of the channel region further comprise heavily doped sub-regions of the second doping type contiguous therewith.
In some embodiments, the cross-sectional width of the second doping type sub-region is smaller than the width of the channel region.
In some embodiments, one end of the second doping type subregion adjoins the second lightly doped region, and the other end adjoins the first doping type region.
In some embodiments, the doping concentration of the second lightly doped region is greater than the doping concentration of the channel region.
In some embodiments, the depth dimension of the second lightly doped region is less than the depth dimension of the channel region.
In some embodiments, the width dimension of the first doping type region is greater than the width dimension of the second doping type region.
In some embodiments, the charge storage region has a charge type that is the same as the doping type of the source terminal and opposite the doping type of the drain terminal.
In some embodiments, the substrate includes a first sub-substrate of a first doping type and a second sub-substrate of a second doping type located on the first sub-substrate, and a third sub-substrate of the first doping type located on the second sub-substrate.
In some embodiments, preparing a charge storage region on the substrate includes the steps of:
S1, etching the substrate to form a plurality of first grooves;
s2, forming a first dielectric layer in the groove;
and S3, filling a first polysilicon material on the surface of the first dielectric layer, and forming a lateral PN junction with the first polysilicon material by a second sub-substrate part between the adjacent first trenches to serve as the charge storage region.
In some embodiments, preparing the vertical transfer transistor on the charge storage region includes the steps of:
s4, carrying out heavy doping injection of the first doping type, wherein the injection depth is lower than the bottom of the vertical transfer transistor so as to form a source end of the vertical transfer transistor;
s5, etching the third sub-substrate of the substrate to form a plurality of second grooves;
S6, forming a second dielectric layer in the second groove;
And S7, filling a second polysilicon material on the surface of the second dielectric layer.
In some embodiments, preparing the vertical transfer transistor on the charge storage region further comprises the step of heavily doping the drain terminal of the vertical transfer transistor with a second doping type.
In some embodiments, fabricating the vertical transfer transistor on the charge storage region includes planarizing a second polysilicon material remaining above a silicon surface using chemical mechanical polishing and then etching the second polysilicon material below the silicon surface using an etching process such that gates of the plurality of transfer transistors are separated from one another.
In some embodiments, the process step of etching the second polysilicon material below the silicon surface is performed in synchronization with the etching back step of the transistors of the pixel region.
In some embodiments, the preparing the vertical transfer transistor on the charge storage region includes the step of doping a gate of the vertical transfer transistor.
In some embodiments, the process step of doping the gate of the vertical transfer transistor is performed in synchronization with the process step of doping the gate of the transistor of the pixel region.
In some embodiments, the vertical transfer transistor is located in a region between adjacent ones of the two first trenches.
In some embodiments, preparing the vertical transfer transistor on the charge storage region further comprises the step of doping the channel region, the doping type comprising a first doping type or a second doping type.
In some embodiments, the first doping type comprises a P-type or an N-type, and the second doping type comprises an N-type or a P-type.
The invention also provides a memory prepared by the method according to any of the previous embodiments.
Compared with the prior art, the invention has the following beneficial effects:
(1) By controlling the doping concentration of the source end, the drain end and the channel region of the vertical transfer transistor, the interface between the source end and the channel region is easy to carry out band tunneling so as to realize lower subthreshold swing and larger on-state current, thereby improving the reading and writing speed. The source end is controlled to comprise a heavily doped region, the channel region is an intrinsic region or a lightly doped region, under the condition that the transistor is in a closed state, the channel is low in doping concentration and is depleted under the action of a grid work function, and a long and narrow depletion channel presents larger resistance, so that leakage of charges in the capacitor to the drain end is inhibited, and enough memory time is still ensured under the condition that negative operation voltage is not needed. When the transistor is in an open state, gate voltage is applied to the gate of the transistor, when a reverse PN junction is formed between the channel and the source end, the interface energy band of the channel and the source end is bent greatly, and band tunneling occurs at the interface of the channel and the source end. When the channel and the source end form a forward PN junction, the whole channel section is utilized for carrying out charge transmission, the charge transmission section in the state is obviously larger than the starting state corresponding to a conventional transfer transistor, the conventional MOSFET reads and writes by a channel inversion layer, the inversion layer is only formed on the surface, the sectional area is small, and the channel resistance is large, so that the tunneling transistor in the state still has more excellent writing performance. In summary, the present invention can realize high-speed storage of the multi-value memory, thereby reducing storage power consumption.
(2) Furthermore, the control drain terminal forms a second doping type region comprising heavy doping, and a second light doping type region is arranged between the channel region and the drain terminal, wherein the concentration of the second light doping type region is larger than that of the channel region, so that the leakage current of the depletion region during turn-off can be further reduced, the refresh frequency is reduced, and the storage power consumption is reduced.
(3) Further, a heavily doped region opposite to the source terminal doping type is formed on the side surface of the channel region and the surface of the first doping type region to connect the source terminal and the second lightly doping type region, so that power consumption can be further reduced.
(4) The preparation method of the memory can be completed by only simple concentration setting, can be compatible with the manufacture of the CMOS image sensor, and can reduce the manufacture process difficulty.
Drawings
The invention will be further described by way of exemplary embodiments, which will be described in detail with reference to the accompanying drawings. The embodiments are not limiting, in which like numerals represent like structures, wherein:
Fig. 1 is a schematic partial cross-sectional view of a prior art memory.
FIG. 2 is a schematic cross-sectional view of a memory according to an embodiment.
FIG. 3 is a schematic cross-sectional view of a memory of another embodiment.
Fig. 4 is a schematic cross-sectional view of a memory of yet another embodiment.
Fig. 5 is a schematic cross-sectional view of a memory of yet another embodiment.
Fig. 6-1 to 6-5 are schematic views showing an embodiment of the process of the method for manufacturing a memory according to the present invention.
Fig. 7 is a schematic illustration of a further embodiment of the process of the method for manufacturing a memory according to the invention.
FIG. 8 is a schematic cross-sectional view of a memory including specific doping types, according to an embodiment.
Fig. 9 is a schematic diagram of XZ cross-sectional shape of a gate, channel region of a vertical transfer transistor.
Detailed Description
In order to more clearly illustrate the technical solution of the embodiments of the present invention, the drawings that are required to be used in the description of the embodiments will be briefly described below. It is apparent that the drawings in the following description are only some examples or embodiments of the present invention, and it is apparent to those of ordinary skill in the art that the present invention may be applied to other similar situations according to the drawings without inventive effort. Unless otherwise apparent from the context of the language or otherwise specified, like reference numerals in the figures refer to like structures or operations.
The problems mentioned in the background art are explained below in connection with specific embodiments.
Fig. 2 is a schematic cross-sectional view of a memory according to an embodiment, the memory 1 includes a plurality of memory cells Cs formed on a substrate 100, each memory cell Cs including a charge storage region and a vertical transfer transistor Tx located on the charge storage region Cs, the vertical transfer transistor Tx including a drain terminal D, a source terminal S, and a channel region CL, wherein the drain terminal D, the channel region CL, and the source terminal S are sequentially arranged in a Y direction. The charge storage region Cs has the same charge type as the doping type of the source terminal S and has the opposite doping type as the drain terminal D.
Wherein the doping concentration of the source S, the drain D, and the channel region CL of the vertical transfer transistor is controlled, the source S is set to include a heavily doped first doping type region 106, and the drain D includes a heavily doped second doping type region 109 of a doping type opposite to that of the first doping type region. The channel region CL is provided as an intrinsic doped region or as a first lightly doped type region, and the doping type of the first lightly doped type region may be the first doping type or the second doping type. By setting the source terminal S to include the heavily doped first doping type region 106 and the channel region CL to be intrinsic doping or lightly doping (i.e., the doping concentration of the first doping type region is far greater than that of the channel region CL), after the gate is pressurized, the interface energy band between the first doping type region 106 and the channel region CL is bent greatly, and band tunneling occurs at the interface between the first doping type region 106 and the channel region CL.
In a preferred embodiment, as shown in fig. 3, a second lightly doped region 111 is further disposed between the heavily doped second doping type region 109 and the channel region CL, the doping concentration of the second lightly doped region 111 is greater than the doping concentration of the channel region CL but less than the doping concentration of the second doping type region 109, and the doping type of the second lightly doped region 111 is opposite to the doping type of the second doping type region 109. The channel region CL may include intrinsic doping or light doping, and if the doping type of the channel region CL is the same as that of the second light doping region, the doping concentration of the channel region CL is required to be smaller than that of the second light doping region 111, otherwise the channel region is set to be intrinsic doping or a light doping region opposite to that of the second light doping region 111. In addition, the depth dimension (i.e., the dimension in the Y direction) of the second lightly doped region 111 is smaller than the depth dimension of the channel region CL. Controlling the drain and channel regions to form regions with decreasing doping concentrations can reduce leakage current, reduce refresh times, and further reduce power consumption. And the doping concentrations of the source end S and the channel region CL are controlled so that the band-to-band tunneling probability at the interface is increased, and the drain end D and the channel region CL are controlled in a matched mode to form a region with decreasing doping concentration, so that the on-state current of the transistor is increased, the leakage current is reduced, and the on-off ratio is further improved.
As shown in fig. 2 or 3, the first doping type region 106 may be formed by a well implant, or a remote implant, including a width dimension that is greater than the width dimension of the second doping type region 109. As shown in fig. 2, the width of the first doping type region 106 in the X direction is substantially equal to the sum of the width of the channel region CL and the width of the gate G on both sides, i.e., the first doping type region 106 not only has the width of the second doping type region 109, but also extends to both sides. The shape of the first doping type region 106 in the XZ cross-section may be formed to include one or a combination of shapes including a block shape, a circular shape, an oblate circular shape, a U-shape, and the like. The first doping type region 106 may further have a shape of XZ cross section to form a first sub-region and a second sub-region, which are independent and include blocks, and are symmetrically formed at two sides of the channel region CL with respect to the channel region CL, and the first sub-region and the second sub-region form contact interfaces with the channel region CL. The first doping type region 106 may be formed in a shape substantially identical to the shape of the gate electrode G in the XZ cross section, as shown in fig. 9, and may be formed in one or more shapes including a block shape ((a), a ring shape ((c) - (e), a ring shape ((e), a doughnut shape ((d), a U shape ((b)) and the like, as shown in fig. 9), or may be formed in a gate electrode G including separate first and second blocks, that is, a double gate transistor, as shown in (a) in fig. 9. Preferably, the gate G is formed in an XZ cross-section to include a doughnut shape ((d) to ensure that the channel is fully depleted when the transistor is turned on, to enhance gate-to-channel control, and to provide a smaller doughnut area to ensure a certain separation distance from surrounding regions.
In a preferred embodiment, the first doping type region 106 is preferably formed by a vertical transfer transistor Tx self-aligned implant to facilitate process compatibility with CMOS image sensors and to simplify the fabrication process. As shown in fig. 4, which is a cross-sectional example of an embodiment of the memory of the present disclosure, the first doping type region 106 is formed based on the vertical transfer transistor Tx self-aligned implantation, and two discrete regions can be seen in the XY cross-section, but the first doping type region 106 in the XZ cross-section may be formed based on the vertical transfer transistor Tx self-aligned implantation to include a circular ring shape, an oblate ring shape, a U shape, and the like of the doped regions, or may be formed to include a block-shaped independent first sub-region and second sub-region. The self-aligned ion implantation of the transfer transistor may specifically be performed after the formation of the transfer transistor shape Tx and before the filling of the gate polysilicon material G, so as to form the heavily doped first doping type region 106 based on the self-aligned doping implantation of the transfer transistor shape Tx.
In a preferred embodiment, when forming the heavily doped first doping type region 106 based on the self-aligned implantation of the vertical transfer transistor Tx, in order to further reduce the threshold voltage and thus the operating voltage, which is advantageous for reducing the power consumption, a heavily doped second doping type sub-region 112 may be formed at the side interface of the channel region CL and the upper interface of the first doping type region 106, as shown in fig. 5. The cross-sectional width of the second doping type sub-region 112 (the cross-sectional width, specifically, the width in the X direction of a portion located on one side of the portion located on both sides of the channel region CL, the width in the Y direction of a portion located on the upper interface of the first doping type region 106) is smaller than the width of the channel region CL, and one end of the second doping type sub-region 112 adjoins the second lightly doped region 111 to form an interface, and the other end adjoins the first doping type region 106 to form an interface. As shown in fig. 5, the second doping type sub-region 112 forms a positive and negative "L" shape in the XY section, and the bottom side of the "L" forms a contact interface with the upper surface of the first doping type region 106.
In any embodiment of the disclosure, the first doping type may include a P-type or an N-type, and the second doping type may include an N-type or a P-type, and specifically, when the first doping type is a P-type, the second doping type includes a type, and when the first doping type is an N-type, the second doping type is a P-type. The first lightly doped region may be lightly doped N-type or lightly doped P-type.
Taking an N-type tunneling transistor as an example, as shown in fig. 8, during the process, the drain D and the floating diffusion FD of the pixel region of the CMOS image sensor are formed to include a heavily doped n+ region, the control source S is a heavily doped p+ region, the second lightly doped region 111 is a lightly doped P-region, the channel CL of the transfer transistor is an N- (N-type lightly doped) region (or an intrinsic doped or P-type region (P-type refers to a P-type lightly doped region having a lower doping concentration than the second lightly doped region 111 is a P-type region), and the gate G of the vertical transfer transistor Tx and the gate G of the pixel region transistor are formed to be N-type doped together according to a required threshold voltage, so as to form an N-type tunneling transistor. When the gate G is positively pressurized during read-write operation, the channel region CL is N-type, the drain end D is pressurized (write 1), the N-type of the channel region CL and the P+ type of the source end S form a reverse bias PN junction, the carrier concentration of the P+ region of the source end S and the N-region of the channel region CL is controlled, the probability of carrying tunneling at the interface between the first doping type region 106 (or the source end S) and the channel region CL is increased, and the tunneling transistor does not depend on carrier thermal diffusion for charge transport, so that the subthreshold swing of the vertical transfer transistor Tx can break through thermodynamic limit. Higher on-state currents are achieved at lower operating voltages and the writing (write 1) speed is faster. On the other hand, when the drain terminal D is low-voltage (written 0), the N-type of the channel region CL and the p+ type of the source terminal S form a forward-biased PN junction, and the forward-biased PN junction can transfer charges by using the entire channel cross section, and the transfer current cross section in this state is significantly larger than that of the corresponding on state of the conventional transfer transistor. Compared with the traditional field effect transistor which is used for writing '0', the channel inversion layer is formed only on the surface of a channel, the sectional area is small, and the channel resistance is large, and the tunneling transistor has more excellent writing performance under the same state. When the tunneling transistor is turned off, the tunneling transistor is depleted under the action of the work function of the grid electrode due to the fact that the doping concentration of the channel region CL is low, and a long and narrow depletion channel presents larger resistance, so that leakage of charges in the capacitor to the drain end D is restrained, and enough memory time can be ensured under the state that negative operation voltage is not needed. Therefore, the memory of the present disclosure can reduce memory power consumption while high-speed storage of a multi-value memory can be realized. In addition, a second lightly doped region 111 is added near the drain, that is, a second lightly doped region 111 is disposed between the drain and the channel region, and the concentration of the second lightly doped region 111 is greater than the concentration of the channel region CL and less than the doping concentration of the drain. The interface between the source terminal S and the channel region CL is easy to carry out band-tunneling during the on-state, and the channel depletion region has a larger resistance due to the existence of the second lightly doped region 111 during the off-state, so that the off-state current is lower, and a higher on-off ratio can be achieved.
The present disclosure also provides a method for manufacturing a memory according to any one of the foregoing embodiments, where the structure of the memory disclosed by the present disclosure may be compatible with an existing CMOS image sensor process, and only the doping concentration of the source end and the etching depth of the vertical transfer transistor need to be controlled to form a tunneling transistor, and band tunneling is easy to occur by using the interface between the source end and the channel region, so as to improve the performance of the memory.
The memory comprises a plurality of memory cells, each memory cell comprises a charge storage region and a vertical transfer transistor positioned on the charge storage region, and the preparation method comprises the steps of providing a substrate, preparing the charge storage region on the substrate and preparing the vertical transfer transistor on the charge storage region, wherein the process flow of the preparation method of the memory is described below with reference to specific embodiments.
As shown in the flow (a) of fig. 6-1, a semiconductor substrate 100 is provided, and materials containing silicon may be used as materials for manufacturing the semiconductor substrate, such as silicon, single crystal or polycrystalline silicon, amorphous silicon, carbon doped silicon, or a combination thereof or a plurality of layers of two or more thereof, and the semiconductor substrate 100 may be germanium, silicon germanium, or silicon on insulator. The substrate 100 is provided comprising a first sub-substrate 101 of a first doping type and a second sub-substrate 102 of a second doping type located on the first sub-substrate, and a third sub-substrate 103 of the first doping type located on the second sub-substrate. For example, the first sub-substrate 101 at the lowermost layer may include a P-type substrate, the second sub-substrate 102 in the middle may include an N-type region as a charge storage region (or photodiode region), and the third sub-substrate 103 at the uppermost layer may include a P-type epitaxial layer for use as a functional pipe (e.g., vertical transfer transistor, etc.) substrate. The steps of preparing the charge storage region Cs on the substrate 100, and preparing the vertical transfer transistor Tx on the charge storage region Cs are described in detail below.
Wherein the preparation of the charge storage region Cs on the substrate 100 comprises the steps of:
S1, etching the substrate 100 to form a plurality of first grooves 104, as shown in a flow (b) of FIG. 6-1. The vertical transfer transistor Tx prepared later is located in the region between the two adjacent first trenches 104.
S2, a buffer layer and a first dielectric layer (the buffer layer and the dielectric layer are not shown) are formed in the groove 104, and the dielectric layer can be made of silicon oxide.
And S3, filling a first polysilicon material 105 on the surface of the first dielectric layer, and forming a lateral PN junction between the remaining second sub-substrate (for example, N-type) area part between the adjacent first trenches 104 and the first polysilicon material 105 to serve as a charge storage area Cs, wherein the process (c) is shown in the figure 6-2. Here, after the isolation trench 104 is formed by etching the substrate 100, a portion of the substrate that is not etched with a smaller size remains, and after the isolation trench 104 is filled with the buffer layer, the dielectric layer, and the polysilicon material, the portion of the substrate that is left is compensated by the P-type buffer layer, so that the portion of the substrate that is not etched finally presents a P-type region (i.e., a P-type lightly doped region (P-)). As shown in fig. 8.
The preparation of the vertical transfer transistor Tx on the charge storage region Cs includes the steps of:
and S4, carrying out heavy doping injection of the first doping type, wherein the injection depth is lower than the bottom of the vertical transfer transistor so as to form a source end S comprising the first doping type region 106, and carrying out a process (d) shown in fig. 6-2. For example, a remote P-type heavy doping implantation is performed to a depth lower than the bottom of the vertical transfer transistor, so that a block-shaped first doping type region 106 having a larger width than that of the second doping type region 109 is formed (the first doping type at this step may be doped by EPI growth, and the first doping type region 106 having the shape shown in the flow (d) shown in fig. 6-2 may be easily formed). The doping concentration of the first doping type (e.g., P-type) region 106 of the source terminal S and the etching depth of the vertical transistor Tx are required to meet the requirement that the band bending of the depletion region after the reverse bias of the PN junction at the interface of the source terminal S and the channel region CL is sufficiently large when the transistor is turned on, which is more favorable for band tunneling. For example, the band gap width of the source terminal S can be reduced by injecting a semiconductor element (such as Ge) with a narrower band gap, so that the occurrence probability of band-gap tunneling (BTBT) is enhanced, and the switching ratio of the device is further improved.
S5, etching the third sub-substrate 103 of the substrate 100 to form a plurality of second trenches 110, as shown in the flow (e) of FIGS. 6-3.
S6, forming a second dielectric layer (not shown) in the second groove 110;
and S7, filling a second polysilicon material 108 on the surface of the second dielectric layer, and performing a process (f) shown in the figure 6-3.
And S8, flattening the second polysilicon material 108 remained above the surface of the third sub-substrate 103 by using chemical mechanical polishing, wherein the process (g) is shown in the process of fig. 6-4.
The drain terminal of the vertical transfer transistor Tx is heavily doped with the second doping type to form a second doping type region 109, and the second doping type region 109 may be completed together with the second doping type doping implantation of the floating diffusion region of the pixel region. As shown in flow (h) of fig. 6-4.
And S10, etching the second polysilicon material 108 below the silicon surface by using an etching process, wherein the process (i) shown in the fig. 6-4 ensures that the grid electrodes G of the plurality of transfer transistors are mutually separated. The gate G may be formed in a circular ring shape, an oblate circular ring shape, or a U-shape at the peripheral side of the channel region on a plane perpendicular to the length direction of the channel CL, or the gate G may be formed to include first and second sub-gates located at both sides of the channel CL to form a double gate transistor. Preferably, on a plane perpendicular to the length direction of the channel CL, the gate of the vertical transfer transistor surrounds the channel region in a flat ring shape, so that the channel can be fully depleted when the transistor is turned on, the control capability of the gate to the channel is enhanced, and meanwhile, the flat ring shape is smaller in area, and a certain isolation distance from the surrounding region is ensured.
In addition, the method for preparing the vertical transfer transistor Tx may further include a step of gate doping, and the gate back etching and the gate doping of the vertical transfer transistor Tx may be performed together with the gate back etching and the doping of the pixel region, so as to reduce the process steps. The method of manufacturing may further include the step of doping the channel region, and the doping type of the channel region may include light doping of the first doping type or the second doping type.
In a preferred embodiment, the steps of the processes of the steps (d) - (e) may be replaced by steps (d ') - (e '), as shown in fig. 7, etching the third sub-substrate 103 to form the trench 110 of the vertical transfer transistor, and performing the doping implantation of the first doping type (e.g., P-type) by using the self-alignment of the vertical transfer transistor 107 to form the heavily doped first doping type region 106, as shown in the step (d '), so that the implantation depth is naturally lower than the bottom of the vertical transfer transistor to form the source terminal S of the vertical transfer transistor, thereby greatly simplifying the process and improving the implantation accuracy. The first doping type region formed in this manner may form a first doping type region including a ring-shaped region, or a first doping type region including a U-shaped region, or a first doping type region including independently spaced first and second sub-regions, and further preferably, the first doping type region 106 may form a first doping type region including a flat ring shape.
In a preferred embodiment, the method for manufacturing the vertical transfer transistor Tx may further include a step of disposing the second lightly doped region 111, and controlling the doping concentration of the second lightly doped region 111 to be greater than the doping concentration of the channel region CL and less than the doping concentration of the second doping type region 109. The doping implant involved in this step may be accomplished with a well implant after formation of trench 110 as illustrated in flow (e) (or as illustrated in flow (d '), (e')), and prior to filling with the second polysilicon material 108.
In a preferred embodiment, the method for fabricating the vertical transfer transistor Tx may further include an implantation step of forming the heavily doped second doping type sub-region 112 on the side of the channel region CL and on the upper surface of the first doping type region 106, and the doping implantation involved in the step may be completed by well implantation and self-aligned implantation after the formation of the trench 110 illustrated in the process (e) (or illustrated in the process (d '), (e')) and before the filling of the second polysilicon material 108.
In a preferred embodiment, the portion of the first polysilicon material 105 filled in the first trench 104 located in the vertical transfer transistor Tx is etched back to a depth (not shown in the drawings) in the subsequent process, and the etched back depth may be slightly higher than the bottom of the vertical transfer transistor Tx or slightly lower than the bottom of the vertical transfer transistor Tx, and the dielectric layer is filled for isolation after the etched back.
While the basic concepts have been described above, it will be apparent to those skilled in the art that the foregoing detailed disclosure is by way of example only and is not intended to be limiting. Although not explicitly described herein, various modifications, improvements and adaptations of the invention may occur to one skilled in the art. Such modifications, improvements, and modifications are intended to be suggested within the present disclosure, and therefore, such modifications, improvements, and adaptations are intended to be within the spirit and scope of the exemplary embodiments of the present disclosure.
It should be understood that the embodiments described herein are merely illustrative of the principles of the embodiments of the present invention. Other variations are also possible within the scope of the invention. Thus, by way of example, and not limitation, alternative configurations of embodiments of the invention may be considered in keeping with the teachings of the invention. Accordingly, the embodiments of the present invention are not limited to the embodiments explicitly described and depicted herein.
Claims (26)
1. A method of manufacturing a memory comprising a plurality of memory cells, each of the memory cells comprising a charge storage region and a vertical transfer transistor located on the charge storage region, the method comprising,
Providing a substrate, preparing a charge storage region on the substrate, and preparing a vertical transfer transistor on the charge storage region;
And the doping concentration of the source end, the drain end and the channel region of the vertical transfer transistor is controlled, so that band-to-band tunneling is easy to occur at the interface of the source end and the channel region.
2. The method of claim 1, wherein a source terminal of the vertical transfer transistor comprises a heavily doped first doping type region, a drain terminal comprises a heavily doped second doping type region, and a channel region comprises an intrinsic doping region, or a first lightly doping region, wherein the first doping type is opposite the second doping type.
3. The method of claim 2, wherein the first doping type region is formed by self-aligned implantation after the vertical transfer transistor is etched to form the first doping type region comprising a ring-shaped region, or to form the first doping type region comprising a U-shaped region, or to form the first doping type region comprising a first sub-region and a second sub-region that are independently spaced.
4. The method of claim 2, wherein the first doping type region is formed by well implantation.
5. The method of claim 1, wherein the gate of the vertical transfer transistor is in a flat loop shape surrounding the channel region in a plane perpendicular to the length direction of the channel.
6. The method of claim 1, wherein the gate comprises a ring shape or a U-shape on a peripheral side of the channel region or comprises a first sub-gate and a second sub-gate on both sides of the channel region in a plane perpendicular to a length direction of the channel.
7. The method of claim 2, further comprising a second lightly doped region between the drain and the channel region, the second lightly doped region having a doping type opposite to a doping type of the second doping type region.
8. The method of claim 7, wherein the front side of the channel region and the front side of the first doping type region further form a second doping type sub-region comprising heavy doping.
9. The method of claim 8, wherein a cross-sectional width of the second doping type sub-region is less than a width of the channel region.
10. The method of claim 8, wherein one end of the second doping type sub-region adjoins the second lightly doped region and the other end adjoins the first doping type region.
11. The method of claim 7, wherein a doping concentration of the second lightly doped region is greater than a doping concentration of the channel region.
12. The method of claim 2, wherein a depth dimension of the second lightly doped region is less than a depth dimension of the channel region.
13. The method of claim 2, wherein a width dimension of the first doping type region is greater than a width dimension of the second doping type region.
14. The method of any of claims 1-13, wherein the charge storage region has a charge type that is the same as a doping type of the source terminal and opposite to a doping type of the drain terminal.
15. The method of any of claims 1-14, wherein the substrate comprises a first sub-substrate of a first doping type, a second sub-substrate of a second doping type on the first sub-substrate, and a third sub-substrate of the first doping type on the second sub-substrate.
16. The method of claim 15, wherein preparing a charge storage region on the substrate comprises the steps of:
S1, etching the substrate to form a plurality of first grooves;
s2, forming a first dielectric layer in the groove;
And S3, filling a first polysilicon material on the surface of the first dielectric layer, and forming a lateral PN junction with the first polysilicon material by the second substrate region part between the adjacent first trenches to serve as the charge storage region.
17. The method of claim 15 or 16, wherein preparing the vertical transfer transistor on the charge storage region comprises the steps of:
s4, carrying out heavy doping injection of the first doping type, wherein the injection depth is lower than the bottom of the vertical transfer transistor so as to form a source end of the vertical transfer transistor;
s5, etching the third sub-substrate of the substrate to form a plurality of second grooves;
S6, forming a second dielectric layer in the second groove;
And S7, filling a second polysilicon material on the surface of the second dielectric layer.
18. The method of claim 17, wherein fabricating the vertical transfer transistor on the charge storage region further comprises heavily doping a drain terminal of the vertical transfer transistor with a second doping type.
19. The method of claim 17 wherein fabricating the vertical transfer transistor on the charge storage region comprises planarizing a second polysilicon material remaining above a silicon surface using chemical mechanical polishing and then etching the second polysilicon material below the silicon surface using an etching process such that the gates of the plurality of transfer transistors are separated from one another.
20. The method of claim 19, wherein the step of etching the second polysilicon material below the silicon surface is performed simultaneously with the step of etching back the transistors of the pixel region.
21. The method of claim 17, wherein said fabricating said vertical transfer transistor on said charge storage region comprises doping a gate of a vertical transfer transistor.
22. The method of claim 21, wherein the process step of doping the gate of the vertical transfer transistor is performed simultaneously with the process step of doping the gate of the transistor of the pixel region.
23. The method of claim 17 wherein the vertical transfer transistor is located in a region between adjacent ones of the two first trenches.
24. The method of claim 16, wherein fabricating the vertical transfer transistor on the charge storage region further comprises doping the channel region, the doping type comprising a first doping type or a second doping type.
25. The method of any one of claims 1-24, wherein the first doping type comprises a P-type or an N-type and the second doping type comprises an N-type or a P-type.
26. A memory prepared according to the method of any one of claims 1-25.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311459829.3A CN119947110A (en) | 2023-11-03 | 2023-11-03 | A memory and a method for preparing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311459829.3A CN119947110A (en) | 2023-11-03 | 2023-11-03 | A memory and a method for preparing the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN119947110A true CN119947110A (en) | 2025-05-06 |
Family
ID=95537287
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311459829.3A Pending CN119947110A (en) | 2023-11-03 | 2023-11-03 | A memory and a method for preparing the same |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN119947110A (en) |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050167756A1 (en) * | 2004-01-29 | 2005-08-04 | Enpirion, Incorporated | Laterally diffused metal oxide semiconductor device and method of forming the same |
| US7067879B1 (en) * | 2004-05-28 | 2006-06-27 | National Semiconductor Corporation | Integration of trench power transistors into a 1.5 μm BCD process |
| CN102354694A (en) * | 2011-08-25 | 2012-02-15 | 复旦大学 | Self-aligned vertical non-volatile semiconductor memory device |
| CN102403352A (en) * | 2010-09-14 | 2012-04-04 | 无锡华润上华半导体有限公司 | A MOS transistor |
| US20130341702A1 (en) * | 2011-01-24 | 2013-12-26 | Imec | Vertical Memory Device and Method for Making Thereof |
| CN105633147A (en) * | 2014-10-27 | 2016-06-01 | 中国科学院微电子研究所 | Tunneling field effect transistor and manufacturing method thereof |
| CN108538918A (en) * | 2018-04-27 | 2018-09-14 | 电子科技大学 | A kind of depletion type super-junction MOSFET device and its manufacturing method |
| US20220149198A1 (en) * | 2020-11-10 | 2022-05-12 | University Of Electronic Science And Technology Of China | Nano-wall Integrated Circuit Structure with High Integrated Density |
-
2023
- 2023-11-03 CN CN202311459829.3A patent/CN119947110A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050167756A1 (en) * | 2004-01-29 | 2005-08-04 | Enpirion, Incorporated | Laterally diffused metal oxide semiconductor device and method of forming the same |
| US7067879B1 (en) * | 2004-05-28 | 2006-06-27 | National Semiconductor Corporation | Integration of trench power transistors into a 1.5 μm BCD process |
| CN102403352A (en) * | 2010-09-14 | 2012-04-04 | 无锡华润上华半导体有限公司 | A MOS transistor |
| US20130341702A1 (en) * | 2011-01-24 | 2013-12-26 | Imec | Vertical Memory Device and Method for Making Thereof |
| CN102354694A (en) * | 2011-08-25 | 2012-02-15 | 复旦大学 | Self-aligned vertical non-volatile semiconductor memory device |
| CN105633147A (en) * | 2014-10-27 | 2016-06-01 | 中国科学院微电子研究所 | Tunneling field effect transistor and manufacturing method thereof |
| CN108538918A (en) * | 2018-04-27 | 2018-09-14 | 电子科技大学 | A kind of depletion type super-junction MOSFET device and its manufacturing method |
| US20220149198A1 (en) * | 2020-11-10 | 2022-05-12 | University Of Electronic Science And Technology Of China | Nano-wall Integrated Circuit Structure with High Integrated Density |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6617643B1 (en) | Low power tunneling metal-oxide-semiconductor (MOS) device | |
| US20070228491A1 (en) | Tunneling transistor with sublithographic channel | |
| KR101286707B1 (en) | Tunneling field effect transistor having finfet structure of independent dual gates and fabrication method thereof | |
| SG172643A1 (en) | Etched nanofin transistors | |
| WO2015131527A1 (en) | Semi-floating gate device and preparation method therefor | |
| US7432560B2 (en) | Body-tied-to-source MOSFETs with asymmetrical source and drain regions and methods of fabricating the same | |
| CN107527917A (en) | 1.5T depletion type SONOS non-volatility memorizers and its manufacture method | |
| US12279411B2 (en) | Memory device using semiconductor device | |
| WO2021232806A1 (en) | Trench gate metal oxide semiconductor field effect transistor and manufacturing method therefor | |
| US20070231980A1 (en) | Etched nanofin transistors | |
| CN115084267A (en) | SOI LDMOS device and manufacturing method thereof | |
| CN114121993B (en) | Mirror image bit SONOS flash memory unit | |
| KR20150092003A (en) | Semiconductor memory device and method of manufacturing the same | |
| CN103972238A (en) | Memory unit structure | |
| KR20170055031A (en) | Capacitorless 1t dram cell device using tunneling field effect transistor, fabrication method thereof and memory array using the same | |
| US20070001165A1 (en) | Memory cell comprising one MOS transistor with an isolated body having a prolonged memory effect | |
| CN114121994A (en) | Mirror image position SONOS flash memory unit and manufacturing method thereof | |
| CN106098765B (en) | A Tunneling Field Effect Transistor with Increased Current Switching Ratio | |
| CN119947110A (en) | A memory and a method for preparing the same | |
| US8525248B2 (en) | Memory cell comprising a floating body, a channel region, and a diode | |
| US20150117110A1 (en) | Connecting storage gate memory | |
| JP2003060095A (en) | Integrated semiconductor memory device and manufacturing method | |
| WO2023056798A1 (en) | Back gate modulation device and preparation method therefor, memory, and logic device | |
| CN102637730B (en) | Heterojunction 1T-DRAM (dynamic random access memory) structure on basis of buried-layer N-type trap and forming method of 1T-DRAM structure | |
| CN105633155A (en) | Structure and fabrication method of metal-oxide-semiconductor field-effect transistor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |