CN119908011A - Semiconductor devices - Google Patents

Abstract

A novel semiconductor device is provided. The semiconductor device includes a trigger group having n triggers and a plurality of storage cells. The trigger group has a function of holding n-bit data. One of the plurality of storage cells has a function of holding n-bit data. Another of the plurality of storage cells has a function of holding p-bit data. When the data held in the trigger group is n-bit, the n-bit data held in the trigger group is written to one of the storage cells in a first operation. When the data held in the trigger group is p-bit, the p-bit data is written to another of the storage cells in a second operation. n is any integer greater than 2, and p is any integer greater than 1 and less than n.

Description

Semiconductor device with a semiconductor device having a plurality of semiconductor chips

Technical Field

One embodiment of the present invention relates to a semiconductor device and the like.

Note that one embodiment of the present invention is not limited to the above-described technical field. The technical field of the invention disclosed in the specification and the like relates to an object, a method or a manufacturing method. In addition, one embodiment of the present invention relates to a process, machine, product, or composition (composition of matter). Specifically, examples of the technical field of one embodiment of the present invention disclosed in the present specification include a semiconductor device, a display device, a light-emitting device, a power storage device, a driving method of these devices, and a manufacturing method of these devices.

In this specification and the like, a semiconductor device refers to a device using semiconductor characteristics, and refers to a circuit including semiconductor elements (transistors, diodes, photodiodes, and the like), a device having the circuit, and the like. The semiconductor device refers to all devices that can operate using semiconductor characteristics. Examples of the semiconductor device include an integrated circuit, a chip including the integrated circuit, and an electronic component in which the chip is housed in a package. In addition, a memory device, a display device, a light-emitting device, a lighting device, an electronic device, or the like may be a semiconductor device itself or may include a semiconductor device.

Background

Technology development of a semiconductor device in which an oxide semiconductor is used for a semiconductor layer forming a channel (also referred to as an "OS transistor") and a transistor in which silicon is used for a semiconductor layer forming a channel (also referred to as an "Si transistor") are combined to be able to hold electric charges corresponding to data is increasingly hot.

By providing the semiconductor device with a structure in which programs or data held in a flip-flop or the like are stored (also referred to as "reserved", "stored" or "backed up") or loaded (also referred to as "regenerated", "restored" or "rebuilt"), low power consumption can be achieved by power gating or the like. Therefore, the present invention has been applied to a semiconductor device such as a CPU (central processing unit) (for example, refer to patent document 1).

[ Prior Art literature ]

[ Patent literature ]

[ Patent document 1] Japanese patent application laid-open No. 2013-9297

Disclosure of Invention

Technical problem to be solved by the invention

In a semiconductor device such as a CPU, when an exception process (also referred to as "interrupt process") request occurs, the exception process is performed after data held in a register is backed up (written) to an external memory. Further, after the exception processing ends, the data backed up in the external memory needs to be written back to the register. For example, when an exception processing request such as an emergency stop occurs, if the backup time of data is long, a serious problem may occur. In addition, when the occurrence frequency of the exception processing request is high, the time required for data backup and the time required for write-back cannot be ignored. Therefore, it is necessary to shorten the time required for data backup and write-back. In addition, when the occurrence frequency of the exception processing request is high, much energy is consumed when data is backed up and written back between the external memory and the register, and power consumption increases.

An object of one embodiment of the present invention is to provide a novel semiconductor device and the like. Another object of one embodiment of the present invention is to provide a semiconductor device or the like having a reduced occupied area. Further, an object of one embodiment of the present invention is to provide a semiconductor device or the like with reduced power consumption. Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device or the like. Another object of one embodiment of the present invention is to provide a semiconductor device and the like having excellent arithmetic performance.

Note that the object of one embodiment of the present invention is not limited to the above object. The above listed objects do not prevent the existence of other objects. Further, other objects are not mentioned above but will be described in the following description. The objects other than the above can be appropriately extracted from the description of the specification, drawings, and the like by those skilled in the art. Note that one embodiment of the present invention achieves at least one of the above objects and/or other objects.

Means for solving the technical problems

A semiconductor device includes a flip-flop group including n (n is any one of integers of 2 or more) flip-flops, a first memory cell including n memory circuits provided on the flip-flop group, and a second memory cell including p (p is an integer of 1 or more and less than n) memory circuits provided on the first memory cell, wherein the flip-flop includes a first transistor including silicon in a semiconductor layer forming a channel, the n memory circuits and the p memory circuits each include a second transistor including an oxide semiconductor in the semiconductor layer forming the channel, and the semiconductor device has a function of holding the first data in the first memory cell in a first operation when data held by the flip-flop group is n-bit first data, and holding the second data in the second memory cell in a second operation when the data held by the flip-flop group is p-bit second data.

For example, each of the n memory circuits and the p memory circuits includes two second transistors and one capacitor. Both second transistors preferably have a region overlapping the capacitor. As the second transistor, a vertical channel transistor is preferably used. The flip-flop group has a function of holding data of 1 bit or more and n bits or less.

The first operation is, for example, an operation accompanied by power gating. The second job is, for example, a job accompanied by interrupt processing.

Effects of the invention

According to one embodiment of the present invention, a novel semiconductor device or the like can be provided. Further, according to an embodiment of the present invention, a semiconductor device or the like having a reduced occupied area can be provided. Further, according to an embodiment of the present invention, a semiconductor device or the like with reduced power consumption can be provided. Further, according to one embodiment of the present invention, a highly reliable semiconductor device or the like can be provided. Further, according to one embodiment of the present invention, a semiconductor device or the like having excellent arithmetic performance can be provided.

Note that the description of these effects does not prevent the existence of other effects. Note that one mode of the present invention is not required to have all of the above effects. Note that effects other than the above can be obtained and extracted from the description of the specification, drawings, claims, and the like.

Brief description of the drawings

Fig. 1A and 1B are diagrams illustrating a structural example of a semiconductor device.

Fig. 2A and 2B are diagrams illustrating a structural example of the semiconductor device.

Fig. 3A and 3B are diagrams illustrating a structural example of the semiconductor device.

Fig. 4A is a diagram illustrating a structural example of the semiconductor device. Fig. 4B is a timing chart illustrating an operation example of the semiconductor device.

Fig. 5A to 5E are diagrams illustrating an operation example of the semiconductor device.

Fig. 6 is a diagram illustrating an operation example of the semiconductor device.

Fig. 7A and 7B are diagrams illustrating a structural example of the semiconductor device.

Fig. 8A and 8B are diagrams illustrating a structural example of the semiconductor device.

Fig. 9 is a diagram illustrating a structural example of the semiconductor device.

Fig. 10 is a diagram illustrating a structural example of the semiconductor device.

Fig. 11 is a diagram illustrating an operation example of the semiconductor device.

Fig. 12 is a diagram illustrating an operation example of the semiconductor device.

Fig. 13A to 13C are diagrams showing structural examples of the semiconductor device.

Fig. 14A to 14E are diagrams showing structural examples of the semiconductor device.

Fig. 15A and 15B are diagrams showing a configuration example of the semiconductor device.

Fig. 16A and 16B are diagrams showing a configuration example of the semiconductor device.

Fig. 17A to 17D are diagrams showing structural examples of the semiconductor device.

Fig. 18 is a diagram showing a structural example of the semiconductor device.

Fig. 19 is a diagram showing a structural example of the semiconductor device.

Fig. 20A and 20B are diagrams showing a configuration example of the semiconductor device.

Fig. 21A and 21B are diagrams showing a configuration example of the semiconductor device.

Fig. 22A and 22B are diagrams showing a configuration example of the semiconductor device.

Fig. 23A and 23B are diagrams showing a configuration example of the semiconductor device.

Fig. 24A and 24B are diagrams showing a configuration example of the semiconductor device.

Fig. 25 is a diagram illustrating a configuration example of the semiconductor device.

Fig. 26 is a diagram illustrating a configuration example of the semiconductor device.

Fig. 27A to 27J are diagrams illustrating an example of an electronic device.

Fig. 28A to 28C are diagrams illustrating an example of the electronic apparatus.

Fig. 29 is a diagram showing an example of the space equipment.

Modes for carrying out the invention

The embodiments will be described below with reference to the drawings. It is noted that one of ordinary skill in the art can easily understand the fact that the embodiments may be implemented in a plurality of different ways, and that the manner and details thereof may be changed into various forms without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the following embodiments.

In the drawings, the size, thickness of layers, or regions are sometimes exaggerated for clarity of illustration. Accordingly, the present invention is not limited to the dimensions in the drawings. In addition, in the drawings, ideal examples are schematically shown, and therefore the present invention is not limited to the shapes, numerical values, and the like shown in the drawings.

In particular, in plan views (also referred to as top views) and perspective views, the description of some components may be omitted for the convenience of understanding the present invention. In addition, a description of a partially hidden line or the like may be omitted.

Unless otherwise specified, the transistor shown in this specification and the like is an enhancement (normally-off) field effect transistor. In addition, when the transistor shown in this specification or the like is an n-channel transistor and is not particularly described, the threshold voltage (also referred to as "Vth") of the transistor is larger than 0V. In addition, when the transistor shown in this specification or the like is a p-channel transistor and is not particularly described, the threshold voltage (also referred to as "Vth") of the transistor is 0V or less. When not specifically described, vth of each of the plurality of transistors of the same conductivity type is equal.

In this specification and the like, unless otherwise specified, the on-state current refers to a drain current (also referred to as "Id") when the transistor is in an on state (also referred to as "on state"). Unless otherwise specified, the on state in an n-channel transistor means a state in which the voltage between the gate and the source (also referred to as "Vg" or "Vgs") is Vth or more, and the on state in a p-channel transistor means a state in which Vg is Vth or less. For example, the on-state current of an n-channel transistor may be the drain current when Vg is Vth or more.

In this specification and the like, unless otherwise specified, an off-state current (Id) refers to an Id when a transistor is in an off state (also referred to as a non-conducting state or an off state). In the case where it is not specifically described, the off state refers to a state in which Vg is lower than Vth (higher than Vth in the p-channel transistor) in the n-channel transistor. In this specification and the like, the off-state current may be referred to as a leakage current.

In the present specification and the like, metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), and oxide semiconductors (Oxide Semiconductor, which may also be simply referred to as OS), and the like. For example, in the case where a metal oxide is used for a semiconductor layer of a transistor, the metal oxide is sometimes referred to as an oxide semiconductor. In other words, the OS transistor may be referred to as a transistor including an oxide or an oxide semiconductor.

The ordinal numbers such as "first" and "second" in the present specification are added to avoid confusion of the constituent elements, and do not indicate any order or sequence such as a process sequence or a lamination sequence. In addition, in order to avoid confusion of constituent elements, ordinal words may be added to the terms such as the present specification. Note that ordinal words attached in the present specification and the like are sometimes different from ordinal words attached in the claims. Note that, in terms of terms such as this specification and the like to which ordinal words are attached, the ordinal words may be omitted in the claims and the like.

In the present specification and the like, the "electrode", "wiring" and "terminal" do not limit the functions of the constituent elements. For example, an "electrode" is sometimes used as part of a "wiring" and vice versa. The term "electrode" and "wiring" also includes a case where a plurality of "electrodes" and "wirings" are integrally provided. Further, for example, a "terminal" is sometimes used as a part of a "wiring" or an "electrode", and vice versa. The term "terminal" includes a case where a plurality of "electrodes", "wirings", "terminals", and the like are integrally formed. Thus, for example, an "electrode" may be part of a "wiring" or "terminal", e.g., a "terminal" may be part of a "wiring" or "electrode". In addition, "electrode", "wiring", and "terminal" may be replaced with "region" or the like.

In this specification and the like, the supply of a signal refers to a case where a predetermined potential is supplied to a wiring or the like. Therefore, the "signal" may be sometimes referred to as "potential" or the like. In addition, the "potential" or the like may be sometimes referred to as a "signal". The "signal" may be a varying potential or a fixed potential. For example, the potential of the power supply may be used.

In addition, the "film" and the "layer" may be exchanged with each other according to the situation or state. For example, the "conductive layer" may be sometimes converted into the "conductive film". In addition, the "insulating film" may be converted into an "insulating layer" in some cases.

In this specification and the like, the "capacitor" may be, for example, a circuit element having a capacitance value higher than 0F, a region of a wiring having a capacitance value higher than 0F, a parasitic capacitance, or a gate capacitance of a transistor. In addition, the "capacitor", "parasitic capacitance", or "gate capacitance" may be sometimes referred to as "capacitance". In contrast, the "capacitance" may be replaced by "capacitor", "parasitic capacitance" or "gate capacitance". Further, the "capacitor" (including a three-terminal or more "capacitor") has a structure including an insulator and a pair of conductors sandwiching the insulator. Accordingly, a "pair of conductors" of a "capacitor" may be referred to interchangeably as a "pair of electrodes", "a pair of conductive regions", "a pair of regions", or a "pair of terminals". Further, "one of a pair of terminals" is sometimes referred to as "one terminal" or "first terminal". Further, "the other of the pair of terminals" is sometimes referred to as "the other terminal" or "the second terminal". The capacitance value may be, for example, 0.05fF or more and 10pF or less. For example, the temperature may be 1pF or more and 10. Mu.F or less.

In the case of using transistors having different polarities, the current direction of the circuit operation, or the like, the functions of the "source" and the "drain" of the transistors may be interchanged. Therefore, in this specification and the like, "source" and "drain" may be used interchangeably.

In this specification and the like, "gate" means a part or all of a gate electrode and a gate wiring. The gate wiring refers to a wiring for electrically connecting a gate electrode of at least one transistor with other electrodes or other wirings.

In this specification and the like, "source" means a part or all of a source region, a source electrode, and a source wiring. The source region is a region in the semiconductor layer having a specific resistance of a predetermined value or less. The source electrode refers to a conductive layer including a portion connected to the source region. The source wiring means a wiring for electrically connecting a source electrode of at least one transistor with another electrode or another wiring.

In this specification and the like, "drain" means a part or all of a drain region, a drain electrode, and a drain wiring. The drain region is a region in the semiconductor layer having a specific resistance of a certain value or less. The drain electrode refers to a conductive layer including a portion connected to the drain region. The drain wiring means a wiring for electrically connecting a drain electrode of at least one transistor with other electrodes or other wirings.

In this specification and the like, for convenience, terms such as "upper", "lower", "upper" or "lower" are sometimes used to indicate arrangement so as to describe positional relationships of constituent elements with reference to the drawings. In addition, the positional relationship of the constituent elements is appropriately changed according to the direction in which the respective structures are described. Therefore, the words and phrases described in the specification and the like are not limited, and words and phrases may be appropriately replaced according to circumstances. For example, if the expression "insulator located on top of the conductor" is used, the direction of the drawing is rotated 180 degrees, and this expression may be referred to as "insulator located under the conductor".

The terms "upper" and "lower" are not limited to the case where the positional relationship of the constituent elements is "directly above" or "directly below" and are in direct contact. For example, in the expression "electrode B on insulating layer a", electrode B is not necessarily formed in direct contact with insulating layer a, and other components may be included between insulating layer a and electrode B.

In the present specification and the like, terms such as "overlap" and the like do not limit the state of the stacking order of the constituent elements and the like. For example, the "electrode B overlapping with the insulating layer a" is not limited to a state in which the electrode B is formed on the insulating layer a, but includes a state in which the electrode B is formed under the insulating layer a, a state in which the electrode B is formed on the right (or left) side of the insulating layer a, and the like.

In the present specification and the like, terms such as "adjacent" and "close" do not limit a state in which constituent elements are in direct contact. For example, if the expression "electrode B adjacent to insulating layer a" is used, it is not necessarily the case where insulating layer a is in direct contact with electrode B, but may include the case where other components are included between insulating layer a and electrode B.

In the present specification and the like, "parallel" means a state in which an angle formed by two straight lines is-10 ° or more and 10 ° or less. Therefore, the state in which the angle is-5 ° or more and 5 ° or less is also included. "substantially parallel" means a state in which two straight lines form an angle of-30 DEG or more and 30 DEG or less. The term "vertical" refers to a state in which an angle formed by two straight lines is 80 ° or more and 100 ° or less. Therefore, the state in which the angle is 85 ° or more and 95 ° or less is also included. The term "substantially perpendicular" refers to a state in which an angle formed by two straight lines is 60 ° or more and 120 ° or less.

In this specification and the like, unless specifically stated otherwise, cases of count values or measurement values of "same", "equal", or "uniform" (including synonyms for these words) and the like include variations of ±20% as errors.

Arrows indicating the X direction, the Y direction, and the Z direction may be attached to drawings and the like according to the present specification. In the present specification and the like, the "X direction" means a direction along the X axis, and unless specifically described otherwise, the forward direction and the reverse direction are sometimes indistinguishable. The "Y direction" and the "Z direction" are also the same as the "X direction". The X direction, the Y direction, and the Z direction are directions intersecting each other. More specifically, the X direction, the Y direction, and the Z direction are directions orthogonal to each other. In this specification and the like, one of the X direction, the Y direction, and the Z direction is sometimes referred to as "first direction". In addition, the other is sometimes referred to as a "second direction". In addition, the remaining one is sometimes referred to as "third direction".

In this specification and the like, when the same symbol is used for a plurality of constituent elements and it is necessary to distinguish them, a symbol for identification such as "a", "b", "1", "n", or "[ m, n" may be added to the symbol. For example, in order to clearly indicate a specific memory cell 255 among the plurality of memory cells 255, the memory cells 255[1], 255[2], 255[3], and the like are sometimes referred to.

(Embodiment 1)

In this embodiment mode, a configuration example of a semiconductor device according to an embodiment of the present invention will be described. Fig. 1A is a block diagram showing a structural example of a semiconductor device 100.

The semiconductor device 100 shown in fig. 1A includes a CPU core 110, a bus 120, a PMU (Power Management Unit (power management unit)) 130, an input/output IF140, a cache memory 150, and a state control section 160. The CPU core 110 includes an arithmetic unit 111 and a register group 200.

Note that the constituent elements of the semiconductor device 100 are not limited to those shown in fig. 1A, and may include other constituent elements. In addition, a part of the constituent elements shown in fig. 1A may be removed. In addition, one component may have the functions of other components.

The register group 200 has a function of temporarily storing data used by the CPU core 110. The CPU core 110 has a function of performing arithmetic processing in the arithmetic unit 111 based on the data held in the register group 200. The arithmetic unit 111 can perform various arithmetic operations such as four arithmetic operations and logical operations. The operation unit 111 is also called an ALU (ARITHMETIC LOGIC UNIT: arithmetic logic unit). CPU core 110 is sometimes referred to as a processor core. The CPU core 110 may be provided in one semiconductor device 100 (single core) or two or more cores (multi-cores such as dual core and many cores).

The register group 200 includes a plurality of registers 201 (registers 201[1], 201[2], 201[3], 201[4], 201[5], and 201[6 ]). Note that the register 201 is one type of memory device and also one type of semiconductor device.

The register 201[1] is used as a program counter, for example. The program counter has a function of storing a memory address indicating a next instruction. The register 201[2] is used as an instruction register, for example. The instruction register has a function of storing instructions read out from the memory. The register 201[3] is used as a base address register, for example. The base address register has a function of a header address of a program and data stored in the memory. The register 201[4] is used as an index register, for example. The index register has a function of storing the size of data. Register 201[5] is used, for example, as an accumulator. The accumulator has a function of temporarily storing the operation result by the operation unit 111. The register 201[6] is used as a general-purpose register, for example. The general purpose registers are not limited to a specific use but are used for various purposes. For example, register 201[6] may be used as an accumulator.

Note that the registers 201 included in the register group 200 may not include all of the above-described registers 201, but may include other registers 201. Further, some or all of the plurality of these registers 201 may be included. For example, a plurality of registers 201[6] serving as general-purpose registers may also be included.

Bus 120 has functions to control the transmission and reception of data among CPU core 110, PMU130, input output IF140, cache memory 150, and state control circuit 160.

PMU130 includes control circuitry 131 and registers 201[7], and has the function of controlling the performance and stopping of power gating. In addition, the register 201[7] is also one of the registers 201. The register 201[7] is used as a setting register, for example. The setting register has a function of temporarily storing data used by the control circuit 131.

The input/output IF140 has a function of controlling transmission and reception of data between an external device such as a main memory (not shown) and the semiconductor device 100. Data output from the external device is input to the semiconductor device 100 through the input-output IF 140. In addition, data output from the semiconductor device 100 is input to an external device through the input/output IF 140. The cache memory 150 has a function of storing instructions, data, and the like with a high frequency of use, and reducing the frequency of access to the main memory to increase the operation speed of the semiconductor device 100.

Fig. 1B is a block diagram showing a structural example of the register 201. The register 201 includes n (n is any one of integers of 2 or more) OSFF pieces 210. In FIG. 1B, the first OSFF is denoted OSFF210[1], and the nth OSFF210 is denoted OSFF210[ n ]. OSFF210,210 has the function of holding 1 bit of data. Therefore, n corresponds to the data length that the register 201 can store at a time. For example, in the register 201 capable of storing 64 bits of data at a time, n is 64. Note that one OSFF210,210 may also be referred to as a register 201 capable of storing 1 bit of data.

Fig. 2A shows a perspective block diagram of OSFF a 210. Fig. 2B shows a circuit configuration example of OSFF a 210. OSFF210 include a data retention circuit 230 on a scan flip-flop 220 (volatile register). The data holding circuit 230 includes a plurality of memory circuits 231. In this embodiment, three memory circuits 231 (memory circuits 231[1] to 231[3 ]) are shown superimposed, but the number of memory circuits 231 is not limited to three. Note that all scan flip-flops 220 included in the register 201 are collectively referred to as a flip-flop group 250 (see fig. 1B). In addition, all the data holding circuits 230 included in the register 201 are collectively referred to as a bank memory 260. Thus, the bank memory 260 includes a plurality of memory circuits 231.

The scan flip-flop 220 includes a selector 221 and a flip-flop 222. The data holding circuit 230 includes a memory circuit 231. Further OSFF includes a transistor 232.

The state control unit 160 is a circuit that outputs a control signal for switching between interrupt processing (also referred to as "exception processing") and power gating, based on an interrupt signal input from the outside, a sleep signal generated by the CPU core 110, and the like. The state control unit 160 generates, for example, a clock signal CLK and various signals (signal BK, signal RE, signal SE). The clock signal CLK and various signals are input to the CPU core 110.

The signal BK is a signal for controlling the saving of data held in the flip-flop 222 in the scan flip-flop 220. By storing data, the data held by the flip-flop 222 is held in any one of the plurality of memory circuits 231 in the data holding circuit 230. Note that in fig. 2B, the signal BK supplied to the memory circuit 231[1] is denoted as a signal BK [1], the signal BK supplied to the memory circuit 231[2] is denoted as a signal BK [2], and the signal BK supplied to the memory circuit 231[3] is denoted as a signal BK [3].

The signal RE is a signal for controlling loading of data held in any one of the plurality of memory circuits 231 in the data holding circuit 230. By loading data, the data held by any one of the plurality of memory circuits 231 in the data holding circuit 230 is held in the flip-flop 222 in the scan flip-flop 220. Note that in fig. 2B, the signal RE supplied to the memory circuit 231[1] is denoted as a signal RE [1], the signal RE supplied to the memory circuit 231[2] is denoted as a signal RE [2], and the signal RE supplied to the memory circuit 231[3] is denoted as a signal RE [3].

The signal SE is a switching signal of the selector 221. The clock signal CLK is a signal determining the operation timing of the flip-flop 222.

OSFF210 to 210 has a function of holding data input from the terminal D or data input from the terminal SD of the scan flip-flop 220 in the scan flip-flop 220 and outputting the data from the terminal Q according to the clock signal CLK. The data of the scan flip-flop 220 output from the terminal Q is held by any one of the plurality of memory circuits 231 included in the data holding circuit 230 according to the signal BK. Data of any one of the plurality of memory circuits 231 included in the data holding circuit 230 is loaded from the terminal SD of the scan flip-flop 220 to the scan flip-flop 220 according to the signal RE.

The selector 221 has a function of transmitting one of the signals input to the terminal D or the terminal SD to the flip-flop 222 according to the signal SE. Terminal D is inputted with data supplied from outside OSFF to 210. The terminal SD is inputted with data inputted from the data holding circuit 230 or data for scan test supplied through the terminal sd_in. The scan test data supplied through the terminal sd_in is input to the terminal SD through the transistor 232. The conductive or nonconductive state of transistor 232 is controlled by signal BK [0 ].

In fig. 2B, a D flip-flop is shown as flip-flop 222, but is not limited thereto. As the flip-flop 222, a flip-flop in a standard circuit library can be used. The transistors included in the flip-flop 222 are Si transistors that can constitute a CMOS circuit, and one data can be held by a circuit including an inversion loop or the like. The flip-flop 222 holds the data of the input terminal D _F according to the clock signal CLK, and outputs the held data from the output terminal Q _F to the terminal Q.

The plurality of memory circuits 231 are connected to the terminal Q and the terminal SD, respectively. In each of the plurality of memory circuits 231, a terminal electrically connected to the terminal Q is referred to as an input terminal, and a terminal electrically connected to the terminal SD is referred to as an output terminal. The output terminal Q _F of the flip-flop 222 is electrically connected to the input terminal of the data holding circuit 230 (the memory circuit 231), and the input terminal D _F of the flip-flop 222 is electrically connected to the output terminal of the data holding circuit 230 (the memory circuit 231) through the terminal SD and the selector 221.

Each of the plurality of memory circuits 231 includes a transistor 233, a transistor 234, and a capacitor 235. The transistor 233 is provided between one electrode of the capacitor 235 and the terminal Q. The transistor 234 is provided between one electrode of the capacitor 235 and the terminal SD. The other electrode of the capacitor 235 is connected to the wiring CL. In each of the plurality of memory circuits 231, one electrode of the capacitor 235 is represented as a node SN.

The transistor 233 and the transistor 234 are preferably OS transistors. Since the off-state current of the OS transistor is extremely small, the charge held in the node SN is not easily reduced, and thus the voltage drop of the node SN can be suppressed for a long period. Further, power to hold data (charge) written to the node SN is hardly required. Thus, the memory circuit 231 included in the data holding circuit 230 can be also referred to as a nonvolatile memory. Since the memory circuit 231 rewrites data by charging and discharging the capacitor 235, the number of rewrites is not limited in principle. In addition, data can be written and read at high speed and with low energy.

The memory circuit configured using the OS transistor is also referred to as an "OS memory". Thus, the memory circuit 231 is an OS memory.

Further, a transistor including a back gate can be used for the transistor 233 and the transistor 234. By supplying a constant voltage to the back gate, the Vth of the transistor can be controlled.

In the memory circuit 231, an OS transistor is used as a switch. In an OS transistor which is an n-channel transistor, a signal supplied to a gate electrode is set to a high level (hereinafter, also referred to as "H") to bring a source electrode and a drain electrode into a conductive state (on state), and a signal supplied to a gate electrode is set to a low level (hereinafter, also referred to as "L") to bring a source electrode and a drain electrode into a non-conductive state (off state). Further, in the selector 221, the signal of the terminal SD is selected by setting the signal SE to a high level, and the signal of the terminal D can be selected by setting the signal SE to a low level.

For example, in the memory circuit 231[1], by setting the signal BK [1] to H, the data held by the flip-flop 222 can be written to the node SN of the memory circuit 231[1 ]. Similarly, by setting BK 2 to H and BK 3 to H, the data of flip-flop 222 can be written to node SN of memory circuit 231[2] and node SN of memory circuit 231[3 ]. Further, by setting RE [1] to H and SE to H, the data of node SN of memory circuit 231[2] can be written back to flip-flop 222. Similarly, by setting RE [2] to H and SE to H, the data of node SN of memory circuit 231[2] can be written back to flip-flop 222. Similarly, by setting RE [3] to H and SE to H, the data of node SN of memory circuit 231[3] can be written back to flip-flop 222.

All the transistors of the memory circuit 231 included in the data holding circuit 230 are preferably OS transistors. The OS transistor is one type of thin film transistor, and can be formed by stacking using an existing thin film formation technique. By configuring the memory circuit 231 using OS transistors, the data holding circuit 230 can be stacked on the scan flip-flop 220 configured by a CMOS circuit using Si transistors.

For example, as in OSFF210 shown in fig. 3A, a plurality of memory circuits 231 may be stacked as different layers on the scan flip-flop 220 configured by a CMOS circuit using Si transistors. Note that fig. 3A shows the memory circuit 231[1], the memory circuit 231[2] to the memory circuit 231[ k ] (k is any one of integers of 2 or more).

For example, as shown in fig. 3A and 3B, a scan flip-flop 220 may be formed in the layer 10 including the Si transistor, and a data holding circuit 230 may be formed in the layer 20 including the OS transistor. That is, trigger clusters 250 may be formed in layer 10 and group memories 260 may be formed in layer 20. In addition, the layer 20 may be formed in a plurality of layers. FIGS. 3A and 3B show examples in which the memory circuit 231[1] is formed in the layer 20[1], the memory circuit 231[2] is formed in the layer 20[2], and the memory circuit 231[ k ] is formed in the layer 20[ k ]. Further, the signal BK supplied to the memory circuit 231[ k ] is represented as a signal BK [ k ], and the signal RE supplied to the memory circuit 231[ k ] is represented as a signal RE [ k ].

By adopting this structure, a plurality of memory circuits 231 can be provided in a region where the scan flip-flop 220 is formed, one by one overlapping. Therefore, even if a plurality of memory circuits 231 are mounted, the area overhead of OSFF can be made substantially 0. Therefore, a semiconductor device having a reduced occupied area can be realized.

To explain the operation of OSFF210, fig. 4A shows a structure when the number of memory circuits 231 included in the data holding circuit 230 is four (k=4). In fig. 4A, nodes SN [1] to SN [4] which are nodes SN holding data in the memory circuits 231 (memory circuits 231[1] to 231[4 ]) included in the data holding circuit 230 are shown. Further, in fig. 4A, signals BK [1] to BK [4] and signals RE [1] to RE [4] that control the memory circuit 231[1] to the memory circuit 231[4] are shown.

Fig. 4B shows an example of a timing chart illustrating the operation of OSFF210 shown in fig. 4A. Further, in fig. 4B, T0 to T7 represent time. In fig. 4B, a clock signal CLK, a terminal D, a terminal Q, a signal BK [1], a signal BK [2], a signal RE [1], a signal RE [2], a node SN [1], a node SN [2], and a signal SE supplied to the selector 221 are shown. The flip-flop 222 stores data of the input terminal D in synchronization with the rising edge of the clock signal CLK (waveform in which the clock signal CLK is switched from the L level to the H level) and outputs the stored data from the output terminal Q.

Further, fig. 5A to 5E show schematic diagrams of OSFF210 for explaining the operation in the timing chart of fig. 4B. Fig. 5A shows the memory circuits 231[1] to 231[4] included in the scan flip-flop 220 and the data holding circuit 230. Fig. 5B, 5C, 5D, and 5E show data input and output from the scan flip-flop 220 and the data holding circuit 230 from 131[1] to the memory circuit 231[4] at time T1, time T3, time T5, and time T7 in fig. 4B.

At time T0, in synchronization with the rising edge of the clock signal CLK, the scan flip-flop 220 holds the data D0 and outputs it from the output terminal Q. Terminal D is supplied with data D1.

At time T1, in synchronization with the rising edge of the clock signal CLK, the scan flip-flop 220 holds the data D1 supplied to the terminal D, and outputs the data D1 from the output terminal Q. At time T1, by setting the signal BK [1] to H, the signal RE [1] to L, and the signal SE to L, the data D1 output from the output terminal Q of the scan flip-flop 220 is held in the memory circuit 231[1] (see fig. 5B). Terminal D is supplied with data D2.

At time T1, signals BK [2] through BK [4] and signals RE [2] through RE [4] are L.

At time T2, in synchronization with the rising edge of the clock signal CLK, the scan flip-flop 220 holds the data D2 supplied to the terminal D, and outputs the data D2 from the output terminal Q. Terminal D is supplied with data D3.

At time T3, in synchronization with the rising edge of the clock signal CLK, the scan flip-flop 220 holds the data D3 supplied to the terminal D, and outputs the data D3 from the output terminal Q. At time T3, by setting the signal BK [2] to H, the signal RE [2] to L, and the signal SE to L, the data D3 of the scan flip-flop 220 is held in the memory circuit 231[2] (see fig. 5C). Terminal D is supplied with data D4.

At time T3, signal BK [1], signal BK [3], signal BK [4], signal RE [1], signal RE [3], and signal RE [4] are L.

At time T4, in synchronization with the rising edge of the clock signal CLK, the scan flip-flop 220 holds the data D4 supplied to the terminal D, and outputs the data D4 from the output terminal Q. Terminal D is supplied with data D5.

At time T5, by setting BK [1] to L, RE [1] to H, and SE to H, the data D1 held in the memory circuit 231[1] can be written back to the scan flip-flop 220 (see fig. 5D). Terminal D is supplied with data D6.

At time T5, signals BK 2 through BK 4 and signals RE 2 through RE 4 are L.

At time T6, in synchronization with the rising edge of the clock signal CLK, the scan flip-flop 220 holds the data D6 supplied to the terminal D, and outputs the data D6 from the output terminal Q. Terminal D is supplied with data D7.

At time T7, by setting BK [2] to L, RE [2] to H, and SE to H, the data D3 held by the memory circuit 231[2] can be written back to the scan flip-flop 220 (see fig. 5E). Terminal D is supplied with data D8.

At time T7, signal BK [1], signal BK [3], signal BK [4], signal RE [1], signal RE [3], and signal RE [4] are L.

As illustrated in fig. 4B and 5B to 5E, OSFF210 may save the data of the ongoing process before the interrupt process and load the data of the restart process after the interrupt process is completed. In one embodiment of the present invention, data stored in accordance with switching of interrupt processing may be held in a plurality of memory circuits included in the data holding circuit. With this configuration, data is stored and loaded in response to switching of a plurality of interrupt processes at the timing of inputting an interrupt signal. Therefore, a plurality of interrupt processes can be sequentially performed. Therefore, data processing can be performed more efficiently.

Fig. 6 is a timing chart of switching operation of interrupt processing of the semiconductor device 100 using the operations OSFF and OSFF210 shown in fig. 4A and described in fig. 4B, and the horizontal axis represents Time elapsed (Time).

At time Ta, the data of the scan flip-flop 220 is stored in the memory circuit 231[1] (saved to 231[1 ]) in a state where the semiconductor device 100 performs the first process (Ope 1), and then the data of the memory circuit 231[2] is written back to the scan flip-flop 220 (loaded from 231[2 ]). In this manner, the semiconductor device 100 may interrupt the first process to perform the second process (Ope 2).

At time Tb, the data of the scan flip-flop 220 is stored in the memory circuit 231[2] (saved to 231[2 ]) in a state where the semiconductor device 100 performs the second process, and then the data of the memory circuit 231[3] is written back to the scan flip-flop 220 (loaded from 231[3 ]). In this manner, the semiconductor device 100 may interrupt the second process to perform the third process (Ope).

At time Tc, the data of the scan flip-flop 220 is stored in the memory circuit 231[3] (to 231[3 ]) in a state where the semiconductor device 100 performs the third process, and then the data of the memory circuit 231[1] is written back to the scan flip-flop 220 (loaded from 231[1 ]). Here, the data written back from the memory circuit 231[1] to the scan flip-flop 220 is the data stored in the memory circuit 231[1] from the scan flip-flop 220 at time Ta. That is, the above data is data necessary for starting (resume) the first processing at the time Ta interruption again. In this way, the state of the third process can be stored, and the semiconductor device 100 can start the interrupted first process again.

By using OSFF to 210 according to one embodiment of the present invention, a semiconductor device that can interrupt an ongoing process to perform an interrupt process with a high priority and then start the interrupt process again can be realized. Therefore, a semiconductor device with improved arithmetic performance can be provided.

By including a plurality OSFF of 210, the register 201 capable of temporarily backing up a plurality of multi-valued data can be realized. Fig. 7A is a perspective block diagram of a register 201A including three OSFF210,210, the OSFF including three memory circuits 231 shown in fig. 2A. Fig. 7B is a diagram showing a circuit configuration example of the register 201A shown in fig. 7A.

The register 201A shown in fig. 7A and 7B is a register 201 in which n is 3, and is used as the register 201 capable of storing 3 bits of data at a time. Thus, register 201A includes flip-flop group 250 having three scan flip-flops 220 (scan flip-flop 220[1], scan flip-flop 220[2] and scan flip-flop 220[3 ]). In fig. 7A, the data holding circuit 230 provided above the scan flip-flop 220[1] is represented as a data holding circuit 230[1].

In fig. 7B, a terminal D included in the scan flip-flop 220[1] is denoted as a terminal D [1], and a terminal SD is denoted as a terminal SD [1]. The scan flip-flop 220[2] includes a terminal D [2] (not shown) as a terminal D, and a terminal SD [2] (not shown) as a terminal SD. Similarly, the scan flip-flop 220[3] includes a terminal D [3] (not shown) as a terminal D, and a terminal SD [3] (not shown) as a terminal SD.

Further, terminal Q of scan flip-flop 220[1] is denoted as terminal Q [1], terminal Q of scan flip-flop 220[2] is denoted as terminal Q [2], and terminal Q of scan flip-flop 220[3] is denoted as terminal Q [3].

In the memory circuits 231[1,1], the memory circuits 231[1,2], and the memory circuits 231[1,3] each include the gate supplied signal BK [1] of the transistor 233 and the gate supplied signal RE [1] of the transistor 234 each included in the first layer (for example, layer 20[1]. Refer to fig. 3A and 3B) provided on the flip-flop group 250. The memory circuits 231[1,1], the memory circuits 231[1,2], and the memory circuits 231[1,3] are used as one memory circuit capable of storing 3-bit data.

In addition, in the memory circuits 231[2,1], the memory circuits 231[2,2], and the memory circuits 231[2,3] each include the gate supplied signal BK [2] of the transistor 233 and the gate supplied signal RE [2] of the transistor 234 each included in the second layer (for example, layer 20[2]. Refer to fig. 3A and 3B) provided on the flip-flop group 250. The memory circuits 231[2,1], the memory circuits 231[2,2], and the memory circuits 231[2,3] are used as one memory circuit capable of storing 3-bit data.

In addition, the signal BK [3] is supplied to the gate of the transistor 233 included in each of the memory circuits 231[3,1], 231[3,2] and 231[3,3] in the third layer provided on the flip-flop group 250, and the signal RE [3] is supplied to the gate of the transistor 234 included in each. The memory circuits 231[3,1], the memory circuits 231[3,2], and the memory circuits 231[3,3] are used as one memory circuit capable of storing 3-bit data. A circuit that includes a plurality of memory circuits 231 and is used as one memory circuit is sometimes referred to as a "memory cell".

Therefore, the group memory 260 of the register 201A shown in fig. 7A and 7B includes three memory cells capable of storing 3 bits of data. The register 201A shown in fig. 7A and 7B may back up data held in the flip-flop group 250 before power gating in any one of the memory cells. In addition, even if the interrupt processing is continued three times, each data can be backed up in a different storage unit in turn. Further, each time the interrupt processing ends, the backed up data may be restored to the trigger cluster 250.

The register 201B shown in fig. 8A and the register 201C shown in fig. 8B are registers 201 in the case where n is 9 or more, and are used as registers 201 capable of storing n-bit data at a time.

Therefore, the registers 201B and 201C include n scan flip-flops 220 (scan flip-flop 220[1] to scan flip-flop 220[ n ]) as the flip-flop group 250.

Further, on the flip-flop group 250, the first layer includes n memory circuits 231 (memory circuits 231[1,1] to 231[1, n ]), the second layer includes n memory circuits 231 (memory circuits 231[2,1] to 231[2, n ]), and the third layer includes n memory circuits 231 (memory circuits 231[3,1] to 231[3, n ]).

Fig. 9 shows a block diagram of the register 201B as seen from the X direction. Fig. 10 shows a block diagram of the register 201C as seen from the X direction. The signal SE is input to all the scan flip-flops 220 included in the register 201B at the same time or substantially the same time, and the clock signal CLK is input at the same time or substantially the same time. The register 201C also has the same structure. Both the register 201B and the register 201C are used as registers capable of storing n-bit data in the flip-flop group 250 at a time.

The register 201C is a modified example of the register 201B. To reduce duplicate description, the descriptions for registers 201B and 201C may be interchanged unless specifically stated otherwise.

The group memory 260 includes a plurality of memory cells 255 formed of a plurality of memory circuits 231. The storage capacities of the plurality of storage units 255 may be the same or different.

The register 201B includes a memory cell 255[1] having n memory circuits 231 (memory circuits 231[1,1] to 231[1, n ]) formed in the first layer on the flip-flop group 250. The signal BK [1] and the signal RE [1] are supplied to all the memory circuits 231 included in the memory cell 255[1]. The memory cell 255[1] is used as a memory circuit that stores n bits of capacity. Note that the storage unit 255 having a storage capacity of n bits is sometimes referred to as "n-bit storage unit 255".

Further, the register 201B includes, as the memory unit 255, a memory unit 255[2] having p memory circuits 231 formed in the second layer on the flip-flop group 250. p is an integer of 1 or more and less than n. In the memory cell 255[2] shown in fig. 8A and 9, p, which is the number of memory circuits 231, is 8. Therefore, the memory cell 255[2] is used as a memory circuit having a memory capacity of 8 bits. For example, in the case where n is 64 and p is 8, eight memory cells 255[2] having a memory capacity of 8 bits may be formed in the second layer on the flip-flop group 250.

In FIGS. 8A and 9, the first memory cell 255[2] is represented as memory cell 255[ 2a ]. The signal BK [2]a ] and the signal RE [2]a ] are supplied to all the memory circuits 231 included in the memory cell 255[1] a. The memory cell 255[2] a is used as a memory circuit having a memory capacity of 8 bits.

The register 201B includes, as the memory cell 255, a memory cell 255[3] having p memory circuits 231 formed in the third layer on the flip-flop group 250. In the memory cell 255[3] shown in fig. 8A and 9, p, which is the number of memory circuits 231, is 4. Therefore, the memory cell 255[3] is used as a memory circuit storing 4 bits of capacity. For example, in the case where n is 64 and p is 4, sixteen memory cells 255[3] with a storage capacity of 4 bits may be formed in the third layer on the flip-flop group 250.

In fig. 9, a first memory cell 255[3] including memory circuits 231[3,1] to 231[3,4] (refer to fig. 8A) is denoted as a memory cell 255[ 3a ], and a second memory cell 255[3] including memory circuits 231[3,5] to 231[3,8] (refer to fig. 8A) is denoted as a memory cell 255[ 3b ] all memory circuits 231 included in the memory cell 255[ 3a ] are supplied with a signal BK [3]a ] and a signal RE [3]a. All memory circuits 231 included in memory cell 255[3] b are supplied with signal BK [3]b ] and signal RE [3]b ]. Both memory cell 255[2] a and memory cell 255[2] b are used as a memory circuit for storing 4 bits of capacity.

In addition, as in the register 201C shown in fig. 8B and 10, a plurality of memory cells 255[2] (memory cells 255[2] a and 255[2] B) each having p as 4 as the number of memory circuits 231 and serving as a 4-bit memory circuit may be included in the second layer on the flip-flop group 250. Further, a memory cell 255[3] having two memory circuits 231 may be included in the 3 rd layer on the flip-flop group 250.

In the register 201C shown in fig. 8B and 10, the number p of memory circuits 231 included in the memory unit 255[3] is 2. Therefore, the memory cell 255[3] is used as a memory circuit storing 2 bits of capacity. For example, in the case where n is 64 and p is 2, thirty-two memory cells 255[3] having a memory capacity of 2 bits may be formed in the third layer on the flip-flop group 250.

In fig. 10, a first memory cell 255[3] including memory circuits 231[3,1] and 231[3,2] (see fig. 8B) is denoted as a memory cell 255[ 3a ], a second memory cell 255[3] including memory circuits 231[3,3] and 231[3,4] (see fig. 8B) is denoted as a memory cell 255[ 3B ], a second memory cell 255[3] including memory circuits 231[3,5] and 231[3,6] (see fig. 8B) is denoted as a memory cell 255[ 3c ], and a second memory cell 255[3] including memory circuits 231[3,7] and 231[3,8] (see fig. 8B) is denoted as a memory cell 255[ 3d ].

The signal BK [3]a ] and the signal RE [3]a ] are supplied to all the memory circuits 231 included in the memory cell 255[3] a, the signal BK [3]b ] and the signal RE [3]b ] are supplied to all the memory circuits 231 included in the memory cell 255[3] b, the signal BK [3]c ] and the signal RE [3]c ] are supplied to all the memory circuits 231 included in the memory cell 255[3] c, and the signal BK [3] d and the signal RE [3] d are supplied to all the memory circuits 231 included in the memory cell 255[3] d. All of the memory cells 255[3] a to 255[ 3d ] are used as a memory circuit for storing 2 bits in capacity.

The storage capacity of the storage unit 255 is not limited to the above-described storage capacity. The storage capacity of the storage unit 255 may be 32 bits or 16 bits. Further, 9 bits or 17 bits may be used depending on the purpose or the like.

In the present embodiment, the n-bit memory cell 255 is provided in the first layer (for example, layer 20[1]. Refer to fig. 3A and 3B) on the flip-flop group 250, but may be provided outside the first layer. For example, it may be provided in the layer 20[2] or the layer 20[ k ].

The number of bits of data represented in binary is sometimes referred to as the "bit length" or "data length". The storage units 255 having different storage capacities may be provided in the same layer. For example, a 32-bit memory cell 255 having p of 32, a 16-bit memory cell 255 having p of 16, an 8-bit memory cell 255, and the like may be provided in the same layer. That is, a plurality of memory cells 255 having different bit lengths of data that can be stored may be provided in the same layer.

Since the size (bit length) of data held by the register 201 may be different depending on the processing performed, the same size is not always necessary. For example, when 32 bits of data are stored in the 64-bit storage unit 255, unnecessary storage work is performed in the remaining 32 bits. Thus, unnecessary power consumption occurs. By providing the group memory 260 with the storage unit 255 having various storage capacities, data having different sizes can be efficiently stored. Accordingly, the power consumption of the register 201 can be reduced.

Further, by combining the storage units 255 having different storage capacities, data of various sizes can be efficiently stored. For example, 12 bits of data can be saved by combining a 4-bit memory cell 255 with p being 4 and an 8-bit memory cell 255 with p being 4.

When power gating is performed, all data (n-bit data) of the scan flip-flops 220 needs to be backed up. In this case, the n-bit data stored in the scan flip-flop 220 may be divided into a plurality of data pieces and stored in the plurality of storage units 255.

On the other hand, in order to divide n-bit data into a plurality of pieces for storage, there are a step of finding a plurality of available storage units 255, a step of confirming a storage capacity of each of the plurality of available storage units 255, a step of determining a division position of the stored n-bit data, a step of actually performing storage, and the like. This results in the onset and resumption of power gating requiring a longer time without the occurrence of power consumption.

Therefore, at least one of the plurality of memory cells 255 is preferably a memory cell 255 having a memory capacity of n bits. That is, at least one of the plurality of storage units 255 preferably includes a storage unit 255 having the same storage capacity as the register 201B.

As described above, the semiconductor device according to the present embodiment can restart the original process based on the data immediately before the interrupt process even when the interrupt process occurs and another interrupt process occurs during the program process. The data used to restart the processing of the interrupt is held by the register group 200 within the CPU core 110. Thus, there is no need to access external memory such as SRAM or DRAM to save or load data. Therefore, the execution of the interrupt processing and the data saving or loading accompanying the restoration of the processing of the interrupt can be efficiently performed without generating a time lag.

The structure shown in this embodiment mode can be implemented in appropriate combination with the structure shown in other embodiment modes.

(Embodiment 2)

In this embodiment, an operation example of the semiconductor device 100 according to one embodiment of the present invention will be described. As described above, the semiconductor device 100 includes the register 201 (see fig. 1) according to one embodiment of the present invention. The register 201 illustrated in this embodiment is a register capable of storing 64-bit data in the flip-flop group 250. Fig. 11 is a timing chart illustrating the operation states of the semiconductor device 100 and the register 201, and the horizontal axis represents Time elapsed (Time).

[ Time Ta ]

In a state where the semiconductor device 100 performs the first process (Ope 1), a signal for performing Power Gating (Power Gating) is supplied from the CPU core 110 or the input/output IF140 to the state control unit 160 at time Ta.

The state control unit 160 backs up (saves) 64-bit data held by the flip-flop group 250 of the register 201 to a storage unit 255 having a storage capacity of 64 bits included in the register 201. For example, to a storage unit 255[1] having a storage capacity of 64 bits (to 255[1 ]).

In the register 201 according to one embodiment of the present invention, by setting the signal BK [1] to L, all 64 bits of data can be stored in the memory cell 255[1] (see fig. 2B and 9). That is, since data backup can be performed at 1 clock operation, data backup can be performed promptly.

The state control unit 160 supplies a signal for stopping power supply to the PMU 130. The power supply may be stopped for the entire CPU core 110 or for a part of the CPU core 110. For example, the supply of power to all the registers 201 included in the register group 200 may be stopped, or the supply of power to the registers 201 included in a part of the register group 200 may be stopped.

In this manner, the semiconductor device 100 transitions to the power-gating state. Note that in the power supply gating state, the supply of electric power to a circuit or the like required for starting the electric power supply again later is not stopped.

[ Time Tb ]

At time Tb, a signal of the end of power supply gating is supplied from the CPU core 110 or through the input/output IF140 to the state control section 160. The state control section 160 supplies a signal to the PMU130 to restart the power supply.

After the power supply is restarted, the state control section 160 causes the data held by the storage unit 255[1] of the register 201 to be read to the flip-flop group 250 (loaded from 255[1 ]) of the register 201. Then, the semiconductor device 100 starts the first process interrupted at time Ta again. In this manner, the semiconductor device 100 transitions from the power-gating state to the normal Active state (Active).

In addition, in the register 201 according to one embodiment of the present invention, by setting the signal RE [1] to H when the signal BK [1] is held to L, and then setting the signal SE to H, all 64-bit data held in the memory cell 255[1] can be restored from the memory cell 255[1] to the flip-flop group 250. That is, since data can be recovered at 2 clock work, data can be recovered promptly.

[ Time Tc ]

When the semiconductor device 100 performs the first process (Ope 1), a signal for preparing to perform the second process (Ope 2) as the interrupt process is supplied from the CPU core 110 or the input/output IF140 to the state control unit 160 at time Tc.

The state control unit 160 determines the memory cell 255 to be stored with the data based on the bit length of the data held by the flip-flop group 250 of the register 201. For example, in the case where the bit length of the data is 8 bits, the data is stored in the memory cell 255[ 2a ] having a storage capacity of 8 bits (to 255[ 2a ]).

Note that when there is no space in the memory cell 255 whose bit length is the same as that of the stored data, the data may be stored in the memory cell 255 whose bit length is larger than that of the data. Alternatively, the data may be divided and stored in a plurality of memory cells 255 each having a bit length smaller than the data.

Next, data necessary for performing the second processing is read out from the storage unit 255[3] a (loaded from 255[3] a). In addition, data necessary for performing the second processing may be read out from the cache memory 150 or may be supplied from the outside through the input/output IF 140. The semiconductor device 100 performs the second process after reading the data necessary for performing the second process.

[ Time Td ]

When the semiconductor device 100 performs the second process, a signal for preparing to perform the third process (Ope) as the interrupt process is supplied from the CPU core 110 or through the input/output IF140 to the state control section 160 at time Td.

The state control unit 160 determines the memory cell 255 to be stored with the data based on the bit length of the data held by the flip-flop group 250 of the register 201. For example, in the case where the bit length of the data is 4 bits, the data is stored in a storage unit 255[ 3a ] having a storage capacity of 4 bits (to 255[ 3a ]).

Next, data necessary for performing the third process is read out from the storage unit 255[3] b (loaded from 255[3] b). In addition, data necessary for performing the third processing may be read out from the cache memory 150 or may be supplied from the outside through the input/output IF 140. The semiconductor device 100 performs the third process after reading the data necessary for performing the third process.

[ Time Te ]

At time Te, the third process ends. After the third processing is completed, the data held by the flip-flop group 250 of the register 201 may be stored in the storage unit 255 (to 255[3 b ]).

After the third process is completed, the saved data (loaded from 255 < 3 > a) is read to the storage unit 255 < 3 > a in order to restart the interrupted second process. The semiconductor device 100 starts the interrupted second process again after reading the data necessary for the second process.

[ Time Tf ]

At time Tf, the second process ends. After the second process is completed, the data held by the flip-flop group 250 of the register 201 may be stored in the storage unit 255 (to 255 < 3 > a).

After the second process is finished, the saved data (loaded from 255 < 2 > a) is read to the storage unit 255 < 2 > a in order to restart the interrupted first process. The semiconductor device 100 starts the interrupted first process again after reading the data necessary for the first process.

The registers 201[1], 201[2], 201[3], 201[4], 201[5] and 201[6] included in the CPU core 110 may be processed differently. For example, as shown in the timing chart of fig. 12, only the register 201[1] and the register 201[2] may be in the power-gating state during the period from time Ta to time Tb. In addition, data for performing the second processing may be held in the register 201[1] and the register 201[2] during the period from the time Tb to the time Tc, and data for performing the first processing may be held in the register 201[5] and the register 201[6 ].

Since the storage unit 255 is configured of an OS memory, data can be written and read at high speed and with low energy. Accordingly, the data held by the flip-flop group 250 immediately before the transition to the power-gating state can be backed up in the storage unit 255 included in the group memory 260 in a short time. In addition, the data backed up in the storage unit 255 may also be maintained during the power gating state. Further, when the power gating state is restored to the active state, the data of the memory cell 255 can be written back to the flip-flop group 250 in a short time, and thus the process can be immediately restarted.

In addition, even when the interrupt processing occurs, backup (writing) and restoration (reading) of data can be performed at high speed and low energy. By including the group memory 260 with the plurality of storage units 255 having different storage capacities, data having different bit lengths can be efficiently backed up. That is, the use efficiency of the bank memory 260 can be improved.

The structure shown in this embodiment mode can be implemented in appropriate combination with the structure shown in other embodiment modes.

Embodiment 3

In this embodiment mode, a stacked structure example of a semiconductor device according to an embodiment of the present invention will be described.

Fig. 13A is a plan view of the memory circuit 231 of one of the semiconductor devices as seen from the Z direction. Fig. 13B is a sectional view of a portion shown by a chain line of A1-A2 in fig. 13A viewed from the Y direction. Fig. 13C is a sectional view of a portion shown by a chain line of A3 to A4 in fig. 13A seen from the X direction. For clarity, some constituent elements are omitted in the plan view of fig. 13A. Note that in this embodiment mode and the like, the lamination direction of layers constituting the semiconductor device is set to the Z direction.

The memory circuit 231 of one of the semiconductor devices includes an insulating layer 353, a conductive layer 351 formed so as to be embedded in the insulating layer 353, and a conductive layer 352. The conductive layer 351 and the conductive layer 352 can be formed simultaneously by the same manufacturing process using the same material. Further, the positions of the top surfaces (positions in the Z direction) of the insulating layer 353, the conductive layer 351, and the conductive layer 352 are preferably made uniform or substantially uniform by a chemical mechanical Polishing (CMP: CHEMICAL MECHANICAL Polishing) method or the like. By performing the CMP treatment, irregularities on the surface of the sample can be reduced, and thus the coverage of the insulating layer and the conductive layer formed later can be improved.

Further, an insulating layer 354 is provided over the insulating layer 353, the conductive layer 351, and the conductive layer 352, and a conductive layer 355 is provided over the insulating layer 354. The conductive layer 351 and the conductive layer 355 have regions overlapping each other with the insulating layer 354 interposed therebetween.

In addition, a region including the conductive layer 351, the conductive layer 355, and the insulating layer 354, in which the conductive layer 351 and the conductive layer 355 overlap with each other with the insulating layer 354 interposed therebetween, is used as the capacitor 235. Thus, the conductive layer 355 is used as one electrode of the capacitor 235. The conductive layer 351 is used as the other electrode of the capacitor 235.

As the insulating layer 354 which is used as a dielectric of the capacitor 235, a material having a high relative permittivity (also referred to as a "high-k material") can be used. By using a high-k material for the insulating layer 354, the capacitance required for the capacitor 235 can be ensured and the insulating layer 354 can be thickened. By thickening the insulating layer 354, the insulating withstand voltage between the conductive layer 351 and the conductive layer 355 is improved and electrostatic breakdown is suppressed. Thus, the reliability of the capacitor 235 is improved. Thereby, the reliability of the semiconductor device using the capacitor 235 is improved.

Ferroelectric may also be used for the insulating layer 354 which serves as a dielectric of the capacitor 235. The ferroelectric has a property that an electric field is applied from the outside to generate polarization inside and that polarization is maintained even when the electric field is 0. Therefore, by using a capacitor (also referred to as a ferroelectric capacitor) using this material as a dielectric, a nonvolatile memory element can be formed.

In addition, the memory circuit 231 illustrated in fig. 13A to 13C includes an insulating layer 357 over the insulating layer 354 and the conductive layer 355, an insulating layer 358 over the insulating layer 357, and an insulating layer 359 over the insulating layer 358. Insulating layer 357, insulating layer 358, and insulating layer 359 are sometimes collectively referred to as insulating layer 356 or a spacer layer. In addition, a conductive layer 361 is included over the insulating layer 359.

In a region overlapping with a part of the conductive layer 355, an opening 362 is provided in each of the conductive layer 361, the insulating layer 359, the insulating layer 358, and the insulating layer 357. The memory circuit 231 shown in fig. 13A to 13C includes a semiconductor layer 363 covering the opening 362. The semiconductor layer 363 has a region overlapping with the bottom of the opening 362 and a region overlapping with the side surface of the opening 362. That is, the semiconductor layer 363 has a region in contact with the insulating layer 356. In fig. 13B and 13C, the semiconductor layer 363 has a region in contact with the side surface of the insulating layer 357, a region in contact with the side surface of the insulating layer 358, and a region in contact with the side surface of the insulating layer 359.

In addition, the semiconductor layer 363 has a region in contact with the conductive layer 355 and a region in contact with the conductive layer 361. That is, a part of the semiconductor layer 363 is electrically connected to the conductive layer 355, and the other part of the semiconductor layer 363 is electrically connected to the conductive layer 361. The semiconductor layer 363 may have a region extending beyond an end portion of the conductive layer 361 (see fig. 13A and 14A).

An insulating layer 364 is included over the insulating layer 359, the conductive layer 361, and the semiconductor layer 363. Further, a conductive layer 365 is included over the insulating layer 364. In fig. 13A, the conductive layer 365 extends in the Y direction.

Both insulating layer 364 and conductive layer 365 have regions that overlap openings 362. In the opening 362, the insulating layer 364 has a region overlapping with a side surface of the conductive layer 361 through the semiconductor layer 363 and a region overlapping with a side surface of the insulating layer 356 (the insulating layer 359, the insulating layer 358, and the insulating layer 357). In addition, in the opening 362, the conductive layer 365 has a region overlapping with a side surface of the opening 362 (a side surface of the insulating layer 356) through the insulating layer 364 and the semiconductor layer 363.

The thickness of the semiconductor layer 363 is preferably 1nm or more, 3nm or more, or 5nm or more and 20nm or less, 15nm or less, 12nm or less, or 10nm or less. The thickness of the insulating layer 364 is preferably 0.5nm to 15nm, more preferably 0.5nm to 12nm, still more preferably 0.5nm to 10 nm. At least a part of the insulating layer 364 may be a region having the above thickness.

An insulating layer 366 is included over the insulating layer 364 (see fig. 13B). It is preferable that top surfaces of the conductive layer 365 and the insulating layer 366 be positioned at the same or substantially the same position (in the Z direction). For example, the top surfaces of the conductive layer 365 and the insulating layer 366 are preferably aligned or substantially aligned by performing CMP treatment or the like. By making the top surfaces of the conductive layer 365 and the insulating layer 366 uniform or substantially uniform, coverage of the insulating layer and the conductive layer formed later can be improved.

Insulating layer 367 is included over conductive layer 365 and insulating layer 366. Further, in a region overlapping with the conductive layer 352, a conductive layer 368 embedded in the insulating layer 367, the insulating layer 366, the insulating layer 364, the conductive layer 361, the insulating layer 359, the insulating layer 358, the insulating layer 357, and a part of the insulating layer 354 is included. Conductive layer 368 is electrically connected to conductive layer 361 and conductive layer 352. Conductive layer 368 and conductive layer 352 are used as contact plugs. In addition, the conductive layer 368 formed through the plurality of layers is also referred to as a "through electrode" or a "VIA".

The conductive layer 361 is used as one of a source electrode and a drain electrode of the transistor 234. Further, the conductive layer 355 is used as the other of the source electrode and the drain electrode of the transistor 234. For example, when the conductive layer 361 is used as a drain electrode of the transistor 234, the conductive layer 355 is used as a source electrode of the transistor 234. The transistor 234 is formed in a region overlapping with the conductive layer 355. Transistor 234 and capacitor 235 have regions that overlap each other.

The semiconductor layer 363 is used as a semiconductor layer forming a channel of the transistor 234 (a semiconductor layer including a channel formation region), the insulating layer 364 is used as a gate insulating layer, and the conductive layer 365 is used as a gate electrode. Thus, it can be said that the transistor 234 is provided in a region including the opening 362.

In addition, the transistor 233 is formed in a region which does not overlap with the transistor 234 and overlaps with the conductive layer 355. The transistor 233 and the capacitor 235 have regions overlapping each other. The transistor 233 has the same structure as the transistor 234 and is formed simultaneously with the transistor 234. Accordingly, the transistor 233 can be described instead of the transistor 233 with respect to the transistor 234.

In the transistor 234, a source electrode and a drain electrode are arranged in the Z direction. That is, the source and drain of the transistor 234 are disposed at different heights. In other words, the source and drain of the transistor 234 are disposed at different positions in the Z direction. Such a Transistor is also referred to as a "vertical channel Transistor", "vertical Transistor" or "VFET (VERTICAL FIELD EFFECT Transistor)".

In the vertical channel transistor according to one embodiment of the present invention, the source electrode and the drain electrode are arranged in the Z direction. That is, the channel formation region, the source region, and the drain region are arranged in the Z direction. In comparison with a conventional transistor in which a channel formation region, a source region, and a drain region are provided on an XY plane, the occupied area can be reduced when a vertical transistor is used.

Therefore, by using a vertical channel transistor for a semiconductor device, the occupied area of the semiconductor device can be reduced. Further, by using a vertical channel transistor for a semiconductor device, high integration of the semiconductor device can be achieved. In addition, the memory capacity per unit area of the memory device using the semiconductor device can be increased.

In addition, the conventional transistor sets the channel length according to the exposure limit of the photolithography. The vertical channel type transistor according to an embodiment of the present invention may set a channel length according to a thickness of the insulating layer 356 or the insulating layer 358. Accordingly, the channel length of the transistor 234 can be set to a very fine structure (for example, 60nm or less, 50nm or less, 40nm or less, 30nm or less, 20nm or less, or 10nm or less, and 1nm or more, or 5nm or more) which is less than or equal to the exposure limit of the photolithography. This increases the on-state current of the transistor 234, and thus improves the frequency characteristics. By using a vertical channel type transistor, a semiconductor device with high operation speed can be provided.

< Constituent Material of semiconductor device >

An example of a material that can be used for a semiconductor device according to one embodiment of the present invention is described.

[ Substrate ]

When the semiconductor device is provided over a substrate, a material for the substrate is not particularly limited. It can be determined by considering whether or not light transmittance is required and heat resistance to withstand the degree of heat treatment is required depending on the purpose. As the substrate, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate can be used. Examples of the insulator substrate include glass substrates such as barium borosilicate glass and aluminoborosilicate glass, ceramic substrates, quartz substrates, sapphire substrates, and stabilized zirconia substrates (yttria-stabilized zirconia substrates, etc.). In addition, a semiconductor substrate, a flexible substrate, a resin substrate, or the like can also be used.

For example, a semiconductor substrate made of silicon, germanium, or the like, a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, or the like is used as a material of the semiconductor substrate. Further, a semiconductor substrate having an insulator region inside the semiconductor substrate may be exemplified by an SOI (Silicon On Insulator; silicon on insulator) substrate or the like. In addition, the semiconductor substrate may be a single crystal semiconductor or a polycrystalline semiconductor.

Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate. Or a substrate containing a metal nitride, a substrate containing a metal oxide, or the like can be given. Further, an insulator substrate provided with a conductor or a semiconductor, a semiconductor substrate provided with a conductor or an insulator, a conductor substrate provided with a semiconductor or an insulator, or the like can be given.

Examples of the material of the flexible substrate or the substrate include polyesters such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), polyacrylonitrile, acrylic resin, polyimide, polymethyl methacrylate, polycarbonate (PC), polyether sulfone (PES), polyamide (nylon, aramid, etc.), polysiloxane, cycloolefin resin, polystyrene, polyamide-imide, polyurethane, polyvinyl chloride, polyvinylidene chloride, polypropylene, polytetrafluoroethylene (PTFE), ABS resin, cellulose nanofibers, and the like.

By using the above material as a substrate, a lightweight semiconductor device including the transistor 234 can be provided. Further, by using the above material as a substrate, a semiconductor device having high impact resistance can be provided. Further, by using the above material as a substrate, a semiconductor device which is not easily broken can be provided.

Alternatively, a substrate having elements provided over these substrates may be used. Examples of the element provided over the substrate include a capacitor, a resistor, a switching element, a light-emitting element, and a memory element.

[ Insulating layer ]

As the insulating layer, an oxide, nitride, oxynitride, metal oxide, metal oxynitride, or the like having insulating property can be used. For example, a single layer or a stacked layer of an insulating material selected from aluminum nitride, aluminum oxide, aluminum oxynitride, aluminum oxide, magnesium oxide, silicon nitride, silicon oxide, silicon oxynitride, silicon nitride oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, aluminosilicate, or the like is used as the insulating layer. In addition, a material in which a plurality of oxide materials, nitride materials, oxynitride materials, or oxynitride materials are mixed may be used.

In the present specification and the like, nitrogen oxides refer to materials having a nitrogen content greater than the oxygen content. In addition, oxynitride refers to a material having an oxygen content greater than the nitrogen content. In addition, the content of each element can be measured using, for example, rutherford backscattering spectrometry (RBS: rutherford Backscattering Spectrometry) or the like.

When miniaturization and high integration of transistors are performed, problems such as leakage current may occur due to thinning of the gate insulating layer. By using a high-k material (high dielectric constant material, material having a high relative dielectric constant) as an insulating layer serving as a gate insulating layer, the gate potential when the transistor operates can be reduced while maintaining the physical thickness. In addition, a substance having a high dielectric constant such as lead zirconate titanate (PZT) or strontium titanate (SrTiO ₃)、(Ba,Sr)TiO₃ (BST)) may be used as the insulating layer, by using a material having a low relative dielectric constant for the insulating layer used for the interlayer film, parasitic capacitance generated between wirings can be reduced.

Examples of the material having a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

Examples of the material having a low relative dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide containing fluorine, silicon oxide containing carbon and nitrogen, silicon oxide containing voids, and resin.

The method for forming the insulating material is not particularly limited, and various forming methods such as an evaporation method, an ALD (Atomic Layer Deposition: atomic layer deposition) method, a CVD (Chemical Vapor Deposition: chemical vapor deposition) method, a sputtering method, and a spin coating method can be used.

In particular, the insulating layers 353 and 367 are preferably formed using an insulating material which is not easily permeable to impurities. For example, a single layer or a stacked layer of an insulating material containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used. Examples of the insulating material which is less permeable to impurities include aluminum oxide, aluminum nitride, aluminum oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, silicon nitride, and the like.

By using an insulating material which is less likely to transmit impurities as the insulating layer 353, diffusion of impurities from below the insulating layer 353 can be suppressed, and reliability of the transistor 234 can be improved. That is, the reliability of the semiconductor device including the transistor 234 can be improved. By using an insulating material which is not easily permeable to impurities as the insulating layer 367, diffusion of impurities from above the insulating layer 367 can be suppressed, and reliability of the transistor 234 can be improved. That is, the reliability of the semiconductor device including the transistor 234 can be improved.

Further, an insulating layer used as a planarizing layer can be used as the insulating layer. Examples of the material used for the planarizing layer include acrylic resin, polyimide, epoxy resin, polyamide, polyimide amide, silicone resin, benzocyclobutene resin, phenol resin, and a precursor of these resins. In addition to the above organic materials, low-k materials (low dielectric constant materials, materials having a small relative dielectric constant), silicone resins, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), and the like may be used. In addition, a plurality of insulating layers made of these materials may be stacked.

The siloxane resin corresponds to a resin containing si—o—si bonds, which is formed using a siloxane-based material as a starting material. The siloxane resin may also use an organic group (e.g., an alkyl group or an aryl group) or a fluoro group as a substituent. The organic group may have a fluoro group.

As the insulating layer 354 which serves as a dielectric of the capacitor 235, a three-layer insulating layer (also referred to as "ZAZ") in which aluminum oxide is sandwiched between two layers of zirconium oxide can be used. ZAZ is a material having a high relative permittivity, and by using ZAZ as a dielectric of the capacitor 235, the occupied area of the capacitor 235 can be reduced.

As described above, a material which can have ferroelectric properties can be used for the insulating layer 354, so that the capacitor 235 can be used as a ferroelectric capacitor.

As a material which can have ferroelectricity, for example, hafnium oxide is preferably used. As a material capable of having ferroelectricity, a metal oxide such as zirconia or HfZrO _X (X is a real number greater than 0, hereinafter also referred to as "HfZrOx") may be used. Or as a material which can have ferroelectricity, a material in which an element J1 is added to hafnium oxide (here, the element J1 is one or more selected from zirconium (Zr), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), and the like) can be used.

Here, the atomic number ratio of hafnium atoms to the element J1 can be appropriately set. For example, the atomic numbers of the hafnium atoms and the zirconium atoms may be set to 1:1 or the vicinity thereof. As a material capable of having ferroelectricity, a material or the like in which element J2 is added to zirconia (here, element J2 is one or more selected from hafnium (Hf), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), and the like) can be used. The atomic number ratio of the zirconium atom to the element J2 may be set appropriately, and for example, the atomic number ratio of the zirconium atom to the element J2 may be set to 1:1 or the vicinity thereof. As the material capable of having ferroelectricity, piezoelectric ceramics having a perovskite structure such as lead titanate (PbTiO _X), barium Strontium Titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium Bismuth Tantalate (SBT), bismuth Ferrite (BFO), and barium titanate may be used.

As a material which can have ferroelectricity, aluminum scandium nitride (Al _1-aSc_aN_b (a is a real number of more than 0 and less than 0.5, and b is a value of 1 or the vicinity thereof, hereinafter abbreviated as AlScN)), al—ga-Sc nitride, ga-Sc nitride, or the like can be used.

[ Conductive layer ]

As a conductive material used for a conductive layer of various wirings, electrodes, and the like of a semiconductor device, a metal element selected from aluminum (Al), chromium (Cr), copper (Cu), silver (Ag), gold (Au), platinum (Pt), tantalum (Ta), nickel (Ni), titanium (Ti), molybdenum (Mo), tungsten (W), hafnium (Hf), vanadium (V), niobium (Nb), manganese (Mn), magnesium (Mg), zirconium (Zr), beryllium (Be), an alloy containing the above metal element as a component, an alloy combining the above metal elements, or the like can Be used.

For example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, or the like is preferably used. Further, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel are conductive materials which are not easily oxidized or materials which absorb oxygen and maintain conductivity are preferable. Further, a semiconductor having high conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, and a silicide such as nickel silicide may be used. The method for forming the conductive material is not particularly limited, and various forming methods such as a vapor deposition method, an ALD method, a CVD method, a sputtering method, a spin coating method, and the like can be used.

In addition, as the conductive material, a cu—x alloy (X is Mn, ni, cr, fe, co, mo, ta or Ti) may be used. The layer formed using the cu—x alloy can be processed in a wet etching process, and thus the manufacturing cost can be suppressed. Further, as the conductive material, an aluminum alloy containing one or more elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium may be used.

As a conductive material which can be used for the conductive layer, a conductive material containing oxygen such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide to which silicon oxide is added, or the like can also be used. In addition, a conductive material containing nitrogen such as titanium nitride, tantalum nitride, tungsten nitride, or the like can also be used. The conductive layer may have a stacked-layer structure in which a conductive material containing oxygen, a conductive material containing nitrogen, and a material containing the above metal element are appropriately combined.

For example, the conductive layer may have a single-layer structure including an aluminum layer of silicon, a two-layer structure including a titanium layer stacked on the aluminum layer, a two-layer structure including a titanium layer stacked on a titanium nitride layer, a two-layer structure including a tungsten layer stacked on a tantalum nitride layer, and a three-layer structure including a titanium layer, an aluminum layer, and a titanium layer stacked in this order.

In addition, a plurality of conductive layers formed of the conductive material may be stacked. For example, a stacked-layer structure of a material containing the above metal element and a conductive material containing oxygen may be used as the conductive layer. For example, a stacked-layer structure of a material containing the above metal element and a conductive material containing oxygen may be used as the conductive layer. For example, a stacked structure of a material containing the above metal element, a conductive material containing oxygen, and a conductive material containing nitrogen may be used for the conductive layer.

For example, the conductive layer may have a three-layer structure in which a conductive layer containing oxygen and at least one of indium and zinc, a conductive layer containing copper, and a conductive layer containing oxygen and at least one of indium and zinc are stacked in this order. In this case, the side surface of the conductive layer containing copper is preferably also covered with a conductive layer containing oxygen and at least one of indium and zinc. For example, a plurality of conductive layers including oxygen and at least one of indium and zinc may be stacked as the conductive layer.

In the case where the capacitor 235 is used as a ferroelectric capacitor, a material which easily polarizes the insulating layer 354 is preferably used as the conductive layer 351 and the conductive layer 355 which are in contact with the insulating layer 354 of the ferroelectric. For example, titanium nitride is preferably used for the conductive layer 351 and the conductive layer 355.

[ Semiconductor layer ]

As the semiconductor layer 363, a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like can be used singly or in combination. As the semiconductor material, silicon, germanium, or the like can be used, for example. Further, compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, and nitride semiconductors may be used. As the compound semiconductor, an organic substance having semiconductor characteristics or a metal oxide having semiconductor characteristics (also referred to as an oxide semiconductor) can be used. Note that these semiconductor materials may also contain impurities as dopants.

For example, single crystal silicon, polycrystalline silicon, microcrystalline silicon, or amorphous silicon can be used for the semiconductor layer 363. As the polysilicon, for example, low temperature polysilicon (LTPS: low Temperature Poly Silicon) can be used.

A transistor using amorphous silicon for the semiconductor layer 363 can be formed over a large-sized glass substrate, and can be manufactured at low cost. A transistor using polysilicon as the semiconductor layer 363 has high field effect mobility and can operate at high speed. Further, a transistor using microcrystalline silicon as the semiconductor layer 363 has higher field-effect mobility than a transistor using amorphous silicon, and can operate at a high speed.

The semiconductor layer 363 may also contain a layered substance serving as a semiconductor. The lamellar substance is a generic term for a group of materials having a lamellar crystal structure. The layered crystal structure is a structure in which layers formed of covalent bonds or ionic bonds are laminated by bonding weaker than covalent bonds and ionic bonds, such as van der waals forces. The layered substance has high conductivity in the unit layer, that is, has high two-dimensional conductivity. By using a material which serves as a semiconductor and has high two-dimensional conductivity for the channel formation region, a transistor with a large on-state current can be provided.

Examples of the layered substance include graphene, silylene, and chalcogenides. Chalcogenides are compounds that contain an oxygen group element (an element belonging to group 16). Examples of the chalcogenides include transition metal chalcogenides and group 13 chalcogenides. As a transition metal chalcogenide that can be used as a semiconductor layer of the transistor, molybdenum sulfide (typically MoS ₂), molybdenum selenide (typically MoSe ₂), molybdenum telluride (typically MoTe ₂), tungsten sulfide (typically WS ₂), tungsten selenide (typically WSe ₂), tungsten telluride (typically WTe ₂), hafnium sulfide (typically HfS ₂), hafnium selenide (typically HfSe ₂), zirconium sulfide (typically ZrS ₂), zirconium selenide (typically ZrSe ₂), and the like can be specifically mentioned.

Further, since the band gap of an oxide semiconductor is 2eV or more, an off-state current of a transistor (also referred to as an "OS transistor") using an oxide semiconductor which is one of metal oxides for a semiconductor layer in which a channel is formed is extremely small. Thereby, power consumption of the semiconductor device including the OS transistor can be reduced. Further, the OS transistor stably operates even in a high-temperature environment, and the characteristic variation is small. For example, the off-state current hardly increases even in a high-temperature environment. Specifically, the off-state current hardly increases even at an ambient temperature of not less than room temperature and not more than 200 ℃. In addition, the on-state current is not easily lowered even in a high temperature environment. Therefore, the semiconductor device including the OS transistor stably operates even under a high-temperature environment and has high reliability.

In this embodiment mode or the like, an OS transistor is preferably used for the transistor 233 and the transistor 234. Since the source and drain of the OS transistor have high dielectric breakdown voltages, the channel length can be reduced. Thus, the on-state current can be increased. The OS transistor is suitable for a vertical channel transistor.

Examples of the metal oxide that can be used for the semiconductor layer of the OS transistor include indium oxide, gallium oxide, and zinc oxide. The metal oxide preferably contains at least indium (In) or zinc (Zn). In addition, the metal oxide preferably contains two or three selected from indium, element M, and zinc. Note that the element M is a metal element or a semi-metal element having a high bonding energy with oxygen, for example, a metal element or a semi-metal element having a higher bonding energy with oxygen than indium.

The element M includes, specifically, aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, antimony, and the like. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and further preferably gallium. Note that in this specification and the like, a metal element and a semimetal element may be collectively referred to as a "metal element", and the "metal element" described in this specification and the like may include a semimetal element.

For example, indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga-Zn oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide), gallium zinc oxide (Ga-Zn oxide, also denoted as "GZO"), aluminum zinc oxide (Al-Zn oxide, also denoted as "AZO"), indium aluminum zinc oxide (In-Al-Zn oxide, also denoted as "IAZO"), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also denoted as "IGZO"), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also denoted as "IGZTO"), indium gallium aluminum zinc oxide (In-Ga-Zn oxide, also denoted as "IGAZO" or "IAGZO"), and the like can be used. Alternatively, indium tin oxide containing silicon, gallium tin oxide (ga—sn oxide), aluminum tin oxide (al—sn oxide), or the like may be used.

By increasing the ratio of the atomic number of indium relative to the sum of the atomic numbers of all metal elements contained in the metal oxide, the field effect mobility of the transistor can be improved.

Note that the metal oxide may contain one or more metal elements having a large number of cycles instead of or in addition to indium. Alternatively, the metal oxide may contain one or more metal elements having a large number of cycles instead of or in addition to indium. The metal oxide tends to have a greater carrier conduction in the metal oxide as the overlap of the orbitals of the metal elements is greater. Therefore, by including a metal element having a large number of periods, field-effect mobility of the transistor can be improved in some cases. Examples of the metal element having a large cycle number include a metal element belonging to the 5 th cycle and a metal element belonging to the 6 th cycle. Specific examples of the metal element include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, europium, and the like. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are referred to as light rare earth elements.

The metal oxide may also contain one or more of nonmetallic elements. The field effect mobility of the transistor can sometimes be improved by the metal oxide containing a nonmetallic element. Examples of the nonmetallic element include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

By increasing the ratio of the atomic number of zinc to the total atomic number of the metal elements among the main component elements included in the metal oxide, the metal oxide having high crystallinity can be formed, and thus diffusion of impurities in the metal oxide can be suppressed. Therefore, variations in the electrical characteristics of the transistor are suppressed, and reliability can be improved.

By increasing the ratio of the atomic number of the element M relative to the sum of the atomic numbers of the metal elements among the main constituent elements contained in the metal oxide, formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, generation of carriers due to oxygen vacancies is suppressed, whereby a transistor with a small off-state current can be realized. Further, variations in the electrical characteristics of the transistor are suppressed, whereby the reliability can be improved.

The electrical characteristics and reliability of the transistor differ according to the composition of the metal oxide used for the semiconductor layer. Therefore, by making the composition of the metal oxide different depending on the electric characteristics and reliability required for the transistor, a semiconductor device having both excellent electric characteristics and high reliability can be realized.

In the case of using an in—zn oxide as a semiconductor layer of an OS transistor, a metal oxide having an atomic ratio of indium of zinc or more may be used. For example, a metal oxide having an atomic number ratio of in:zn=1:1, in:zn=2:1, in:zn=3:1, in:zn=4:1, in:zn=5:1, in:zn=7:1, in:zn=10:1, or a vicinity thereof may be used.

In the case of using an in—sn oxide as a semiconductor layer of an OS transistor, a metal oxide having an atomic ratio of indium of at least an atomic ratio of tin may be used. For example, a metal oxide having an atomic number ratio of In: sn=1:1, in: sn=2:1, in: sn=3:1, in: sn=4:1, in: sn=5:1, in: sn=7:1, in: sn=10:1, or the vicinity thereof may be used.

In the case of using an in—sn—zn oxide as a semiconductor layer of an OS transistor, a metal oxide having an atomic ratio of indium higher than that of tin may be used. Further, a metal oxide having an atomic ratio of zinc higher than that of tin is preferably used. For example, a metal oxide having an atomic ratio of metal elements of In：Sn：Zn＝2：1：3、In：Sn：Zn＝3：1：2、In：Sn：Zn＝4：2：3、In：Sn：Zn＝4：2：4.1、In：Sn：Zn＝5：1：3、In：Sn：Zn＝5：1：6、In：Sn：Zn＝5：1：7、In：Sn：Zn＝5：1：8、In：Sn：Zn＝6：1：6、In：Sn：Zn＝10：1：3、In：Sn：Zn＝10：1：6、In：Sn：Zn＝10：1：7、In：Sn：Zn＝10：1：8、In：Sn：Zn＝5：2：5、In：Sn：Zn＝10：1：10、In：Sn：Zn＝20：1：10、In：Sn：Zn＝40：1：10 or the vicinity thereof can be used.

In the case of using an in—al—zn oxide as a semiconductor layer of an OS transistor, a metal oxide having an atomic ratio of indium higher than that of aluminum may be used. Further, a metal oxide having an atomic ratio of zinc higher than that of aluminum is preferably used. For example, a metal oxide having an atomic number ratio of metal elements of In：Al：Zn＝2：1：3、In：Al：Zn＝3：1：2、In：Al：Zn＝4：2：3、In：Al：Zn＝4：2：4.1、In：Al：Zn＝5：1：3、In：Al：Zn＝5：1：6、In：Al：Zn＝5：1：7、In：Al：Zn＝5：1：8、In：Al：Zn＝6：1：6、In：Al：Zn＝10：1：3、In：Al：Zn＝10：1：6、In：Al：Zn＝10：1：7、In：Al：Zn＝10：1：8、In：Al：Zn＝5：2：5、In：Al：Zn＝10：1：10、In：Al：Zn＝20：1：10、In：Al：Zn＝40：1：10 or the vicinity thereof may be used.

In the case of using an In-Ga-Zn oxide as a semiconductor layer of an OS transistor, a metal oxide In which the atomic ratio of indium to the sum of the atomic ratios of metal elements In the In-Ga-Zn oxide is higher than the atomic ratio of gallium may be used. Further, a metal oxide having an atomic ratio of zinc higher than that of gallium is preferably used. For example, a metal oxide having an atomic ratio of metal elements of In：Ga：Zn＝2：1：3、In：Ga：Zn＝3：1：2、In：Ga：Zn＝4：2：3、In：Ga：Zn＝4：2：4.1、In：Ga：Zn＝5：1：3、In：Ga：Zn＝5：1：6、In：Ga：Zn＝5：1：7、In：Ga：Zn＝5：1：8、In：Ga：Zn＝6：1：6、In：Ga：Zn＝10：1：3、In：Ga：Zn＝10：1：6、In：Ga：Zn＝10：1：7、In：Ga：Zn＝10：1：8、In：Ga：Zn＝5：2：5、In：Ga：Zn＝10：1：10、In：Ga：Zn＝20：1：10、In：Ga：Zn＝40：1：10 or the vicinity thereof may be used for the semiconductor layer.

In the case of using an In-M-Zn oxide as a semiconductor layer of an OS transistor, a metal oxide In which the atomic ratio of indium to the sum of the atomic ratios of metal elements In the In-M-Zn oxide is higher than the atomic ratio of element M may be used. Further, a metal oxide having an atomic ratio of zinc higher than that of the element M is preferably used. For example, a metal oxide having an atomic ratio of metal elements of In：M：Zn＝2：1：3、In：M：Zn＝3：1：2、In：M：Zn＝4：2：3、In：M：Zn＝4：2：4.1、In：M：Zn＝5：1：3、In：M：Zn＝5：1：6、In：M：Zn＝5：1：7、In：M：Zn＝5：1：8、In：M：Zn＝6：1：6、In：M：Zn＝10：1：3、In：M：Zn＝10：1：6、In：M：Zn＝10：1：7、In：M：Zn＝10：1：8、In：M：Zn＝5：2：5、In：M：Zn＝10：1：10、In：M：Zn＝20：1：10、In：M：Zn＝40：1：10 or the vicinity thereof may be used for the semiconductor layer.

When an In-M-Zn oxide is used as the semiconductor layer, a metal oxide In which the atomic ratio of metal elements is In: M: zn=1:3:2 [ atomic ratio ] or a composition In the vicinity thereof, in: M: zn=1:3:4 [ atomic ratio ] or a composition In the vicinity thereof, in: M: zn=1:1:0.5 [ atomic ratio ] or a composition In the vicinity thereof, in: M: zn=1:1:1.2 [ atomic ratio ] or a composition In the vicinity thereof, in: M: zn=1:1:2 [ atomic ratio ] or a composition In the vicinity thereof, or In: M: zn=4:2:3 [ atomic ratio ] or a composition In the vicinity thereof may be used. Note that the nearby composition includes a range of ±30% of the desired atomic number ratio. Further, gallium is preferably used as the element M.

Note that when a plurality of metal elements are included as the element M, the total of the atomic number ratios of the metal elements may be the atomic number ratio of the element M. For example, when an in—ga—al—zn oxide containing gallium and aluminum is used as the element M, the total of the atomic ratio of gallium and the atomic ratio of aluminum may be the atomic ratio of the element M. The atomic ratio of indium, the element M, and zinc is preferably in the above range.

The metal oxide is preferably used such that the ratio of the atomic number of indium to the total of the atomic numbers of the metal elements in the main component elements included in the metal oxide is 30 atomic% or more and 100 atomic% or less, preferably 30 atomic% or more and 95 atomic% or less, more preferably 35 atomic% or more and 90 atomic% or less, more preferably 40 atomic% or more and 90 atomic% or less, more preferably 45 atomic% or more and 90 atomic% or less, more preferably 50 atomic% or more and 80 atomic% or less, more preferably 60 atomic% or more and 80 atomic% or less, and more preferably 70 atomic% or more and 80 atomic% or less. For example, when an in—m—zn oxide is used as the semiconductor layer, the ratio of the atomic number of indium to the total atomic number of indium, element M, and zinc is preferably within the above-described range.

As described above, when the ratio of the atomic number of indium relative to the total of the atomic numbers of the metal elements in the main component element contained in the metal oxide is increased, the field effect mobility of the transistor can be increased. By using this transistor, a circuit capable of high-speed operation can be manufactured. Furthermore, the occupied area of the circuit can be reduced.

For analysis of the composition of the metal oxide, for example, energy dispersive X-ray spectrometry (EDX: ENERGY DISPERSIVE X-ray spectroscopy), X-ray photoelectron spectroscopy (XPS: X-ray Photoelectron Spectroscopy), inductively coupled plasma mass spectrometry (ICP-MS: inductively Coupled Plasma-Mass Spectrometry), or inductively coupled plasma atomic emission spectrometry (ICP-AES: inductively Coupled Plasma-Atomic Emission Spectrometry) can be used. Or may be analyzed in combination with a plurality of the above methods. Note that, when the element having a low content is affected by the analysis accuracy, the actual content may be different from the content obtained by the analysis. For example, when the content of the element M is low, the content of the element M obtained by analysis may be lower than the actual content.

The metal oxide may be formed by a sputtering method or an ALD method as appropriate. Note that when a metal oxide is formed by a sputtering method, the atomic ratio of a target may be different from the atomic ratio of the metal oxide. In particular, the atomic ratio of zinc in the metal oxide is sometimes smaller than the atomic ratio of zinc in the target. Specifically, the atomic ratio of zinc may be about 40% to 90% of the atomic ratio of zinc in the target.

In the case of depositing a metal oxide by a sputtering method, the atomic ratio is not limited to the atomic ratio of the deposited metal oxide, and may be an atomic ratio of a sputtering target used for the deposition of the metal oxide.

Further, when a metal oxide is formed by an ALD method, atoms can be deposited in layers, and therefore, there are effects that deposition can be performed by a method with few defects such as pinholes, deposition with excellent coverage can be performed, deposition can be performed at a low temperature, and the like. Further, it is preferable that an impurity removal treatment is performed after the metal oxide is formed to remove impurities (here, impurities such as water, hydrogen, carbon, and nitrogen) from the film of the metal oxide. Examples of the impurity treatment include plasma treatment, microwave treatment, and heat treatment.

Here, the reliability of the transistor is described. As one of indexes for evaluating reliability of a transistor, GBT (Gate Bias Temperature) stress test for maintaining a state in which an electric field is applied to a gate electrode is known. Among them, the test to be held at a high temperature in a state where a positive potential (positive bias) is applied to the gate with respect to the source potential and the drain potential is referred to as PBTS (Positive Bias Temperature Stress) test, and the test to be held at a high temperature in a state where a negative potential (negative bias) is applied to the gate is referred to as NBTS (Negative Bias Temperature Stress) test. The PBTS test and the NBTS test performed in the state of being irradiated with light are referred to as PBTIS (Positive Bias Temperature Illumination Stress) test and NBTIS (Negative Bias Temperature Illumination Stress) test, respectively.

In an n-channel transistor, since a positive potential is applied to the gate when the transistor is turned on, the variation in threshold voltage in the PBTS test is one of important factors to be considered as an indicator of the reliability of the transistor.

By using a metal oxide containing no gallium or a low content of gallium in the semiconductor layer, a transistor with high reliability against forward bias application can be realized. That is, a transistor with a small fluctuation of the threshold voltage in the PBTS test can be realized. In the case of using a gallium-containing metal oxide, the content of gallium is preferably lower than that of indium. Thus, a highly reliable transistor can be realized.

One of the causes of the threshold voltage fluctuation in the PBTS test is a defect state at or near the interface between the semiconductor layer and the gate insulating layer. The greater the defect state density, the more significant the degradation in the PBTS test. The generation of the defect state can be suppressed by reducing the gallium content of the region of the semiconductor layer in contact with the gate insulating layer.

The reason why the variation in threshold voltage in the PBTS test can be suppressed by using a metal oxide containing no gallium or a low gallium content for the semiconductor layer is as follows, for example. Gallium contained in a metal oxide is more likely to absorb oxygen than other metal elements (e.g., indium or zinc). Therefore, it is presumed that carrier (electron) trap sites (trap sites) are easily generated by bonding gallium to excess oxygen in the gate insulating layer at the interface between the gate insulating layer and the metal oxide containing more gallium. Therefore, when a positive potential is applied to the gate electrode, carriers are trapped at the interface between the semiconductor layer and the gate insulating layer, and the threshold voltage varies.

More specifically, in the case of using an in—ga—zn oxide as the semiconductor layer, a metal oxide having an atomic ratio of indium higher than that of gallium may be used for the semiconductor layer. More preferably, a metal oxide having an atomic ratio of zinc greater than that of gallium is used. In other words, a metal oxide In which the atomic number ratio of the metal element satisfies In > Ga and Zn > Ga is used for the semiconductor layer.

For example, a metal oxide having an atomic ratio of metal elements of In：Ga：Zn＝2：1：3、In：Ga：Zn＝3：1：2、In：Ga：Zn＝4：2：3、In：Ga：Zn＝4：2：4.1、In：Ga：Zn＝5：1：3、In：Ga：Zn＝5：1：6、In：Ga：Zn＝5：1：7、In：Ga：Zn＝5：1：8、In：Ga：Zn＝6：1：6、In：Ga：Zn＝10：1：3、In：Ga：Zn＝10：1：6、In：Ga：Zn＝10：1：7、In：Ga：Zn＝10：1：8、In：Ga：Zn＝5：2：5、In：Ga：Zn＝10：1：10、In：Ga：Zn＝20：1：10、In：Ga：Zn＝40：1：10 or the vicinity thereof can be used for the semiconductor layer of the OS transistor.

The semiconductor layer of the OS transistor preferably uses a metal oxide in which the ratio of the atomic number of gallium to the atomic number of the metal element included is higher than 0 atomic% and 50 atomic% or less, preferably 0.1 atomic% or more and 40 atomic% or less, more preferably 0.1 atomic% or more and 35 atomic% or less, more preferably 0.1 atomic% or more and 30 atomic% or less, more preferably 0.1 atomic% or more and 25 atomic% or less, more preferably 0.1 atomic% or more and 20 atomic% or less, more preferably 0.1 atomic% or more and 15 atomic% or less, and more preferably 0.1 atomic% or more and 10 atomic% or less. By reducing the content of gallium in the semiconductor layer, a transistor having high resistance to the PBTS test can be realized. Note that, by containing gallium in the metal oxide, there is an effect that Oxygen vacancies (V _O: oxygen vacancies) are not easily generated in the metal oxide.

As the semiconductor layer of the OS transistor, a metal oxide containing no gallium may be used. For example, in—zn oxide may be used for the semiconductor layer. At this time, when the atomic number ratio of indium with respect to the atomic number of the metal element contained in the metal oxide is increased, the field effect mobility of the transistor can be increased. On the other hand, when the atomic number ratio of zinc to the atomic number of the metal element contained in the metal oxide is increased, the metal oxide has high crystallinity, and thus variations in the electrical characteristics of the transistor are suppressed, and the reliability can be improved. Further, a metal oxide such as indium oxide that does not include gallium or zinc may be used as the semiconductor layer. By using a metal oxide containing no gallium, in particular, the variation of the threshold voltage in the PBTS test can be made extremely small.

For example, an oxide containing indium and zinc can be used as the semiconductor layer. In this case, for example, a metal oxide having an atomic number ratio of metal elements of in:zn=2:3, in:zn=4:1, or the vicinity thereof can be used.

Note that gallium is taken as an example for explanation, but it is also applicable to a case where the element M is used instead of gallium. A metal oxide having an atomic ratio of indium higher than that of the element M is preferably used for the semiconductor layer. In addition, a metal oxide having an atomic ratio of zinc higher than that of the element M is preferably used.

By using a metal oxide having a low content of the element M as the semiconductor layer, a transistor having high reliability against forward bias application can be realized. By using this transistor as a transistor which needs to have high reliability for forward bias application, a semiconductor device having high reliability can be realized.

The semiconductor layer may have a stacked-layer structure including two or more metal oxide layers. The composition of two or more metal oxide layers included in the semiconductor layer may be the same or substantially the same as each other. By adopting a stacked structure of metal oxide layers having the same composition, for example, the same sputtering target material can be used, and thus manufacturing cost can be reduced.

The composition of two or more metal oxide layers included in the semiconductor layer may be different from each other. For example, a stacked structure of a first metal oxide layer having a composition of In: M: zn=1:3:4 [ atomic number ratio ] or the vicinity thereof and a second metal oxide layer having a composition of In: M: zn=1:1:1 [ atomic number ratio ] or the vicinity thereof provided on the first metal oxide layer can be suitably used. In addition, gallium or aluminum is particularly preferably used as the element M. For example, a stacked structure of any one selected from indium oxide, indium gallium oxide, and IGZO and any one selected from IAZO, IAGZO, and ITZO (registered trademark) or the like may be used.

In addition, for example, a stacked structure of a first metal oxide layer having a composition of In: M: zn=1:1:1 [ atomic ratio ] or the vicinity thereof and a second metal oxide layer having a composition of In: zn=4:1 [ atomic ratio ] or the vicinity thereof provided on the first metal oxide layer can be suitably used.

As the semiconductor layer, a metal oxide layer having crystallinity is preferably used. For example, a metal oxide layer having a CAAC (c-axis ALIGNED CRYSTAL) structure, a polycrystalline structure, a microcrystalline (nc) structure, or the like, which will be described later, may be used. By using a metal oxide layer having crystallinity for a semiconductor layer, the defect state density in the semiconductor layer can be reduced, whereby a display device with high reliability can be realized.

The higher the crystallinity of the metal oxide layer used for the semiconductor layer, the lower the defect state density in the semiconductor layer can be. On the other hand, by using a metal oxide layer having low crystallinity, a transistor capable of flowing a large current can be realized.

When a metal oxide layer is formed by a sputtering method, the higher the substrate temperature (stage temperature) at the time of formation, the more a metal oxide layer having high crystallinity can be formed. In addition, the higher the flow rate ratio of the oxygen gas (hereinafter, also referred to as oxygen flow rate ratio) with respect to the entire deposition gas used at the time of formation, the more crystalline the metal oxide layer can be formed.

The semiconductor layer of the OS transistor may have a stacked structure of two or more metal oxide layers having different crystallinity. For example, the semiconductor device may have a stacked structure of a first metal oxide layer and a second metal oxide layer provided on the first metal oxide layer, and the second metal oxide layer may have a region having higher crystallinity than the first metal oxide layer. Or the second metal oxide layer may have a region whose crystallinity is lower than that of the first metal oxide layer. The composition of two or more metal oxide layers included in the semiconductor layer may be the same or substantially the same as each other. By adopting a stacked structure of metal oxide layers having the same composition, for example, the same sputtering target material can be used, and thus manufacturing cost can be reduced. For example, by using the same sputtering target material and varying the oxygen flow rate ratio, a stacked structure of two or more metal oxide layers having different crystallinity can be formed. Note that the composition of two or more metal oxide layers included in the semiconductor layer may also be different from each other.

When an oxide semiconductor is used for the semiconductor layer 363, a material containing hydrogen is preferably used for the insulating layer 357 and the insulating layer 359. When an insulating layer containing hydrogen is in contact with an oxide semiconductor, the oxide semiconductor in a region where the insulating layer is in contact is n-type, and can be used as a source region or a drain region. As the insulating layer, for example, a material containing silicon, nitrogen, and hydrogen can be used. Specifically, silicon nitride containing hydrogen, silicon oxynitride containing hydrogen, or the like can be used.

The thickness of each of insulating layer 357 and insulating layer 359 is preferably 1nm to 15nm, more preferably 2nm to 10nm, still more preferably 3nm to 7nm, still more preferably 3nm to 5 nm. When an oxide semiconductor is used for the semiconductor layer 363, a region of the semiconductor layer 363 which contacts the insulating layer 357 containing hydrogen and a region of the semiconductor layer 359 containing hydrogen function as a source region or a drain region. By adjusting the thicknesses of the insulating layer 357 and the insulating layer 359, the sizes of the source region and the drain region formed in the semiconductor layer 363 can be controlled.

The thickness of the insulating layer 358 is preferably 1nm to 50nm, more preferably 2nm to 30nm, still more preferably 3nm to 20 nm. By adjusting the thickness of the insulating layer 358, the size of the channel formation region of the semiconductor layer 363 can be controlled.

The thickness of insulating layer 357, insulating layer 358, and insulating layer 359 can be appropriately set according to the characteristics required for transistor 234.

The deposition of insulating layer 357, insulating layer 358, and insulating layer 359 is preferably performed continuously so as not to be exposed to the atmosphere in the middle. By continuously depositing insulating layer 357, insulating layer 358, and insulating layer 359 so as not to be exposed to the atmosphere in the middle, impurities or moisture can be prevented from adhering to the interface between insulating layer 357 and insulating layer 358 and the vicinity thereof, and the interface between insulating layer 358 and insulating layer 359 and the vicinity thereof from the atmosphere.

In addition, when an oxide semiconductor is used for the semiconductor layer 363, a conductive material for n-type the oxide semiconductor is preferably used for the conductive layer 355 which is in contact with the semiconductor layer 363 and the conductive layer 361 which is in contact with the semiconductor layer 363. For example, a conductive material containing nitrogen may be used. For example, a conductive material containing titanium or tantalum or nitrogen may be used. In addition, another conductive material may be provided so as to overlap with the nitrogen-containing conductive material.

On the other hand, a material which has reduced hydrogen and contains oxygen is preferably used for the insulating layer 358. For example, a material containing silicon and oxygen may be used. Specifically, silicon oxide, silicon oxynitride, or the like is used. Since hydrogen is an impurity element in the oxide semiconductor, when the semiconductor layer 363 of the oxide semiconductor is in contact with the insulating layer 358 which reduces hydrogen, the semiconductor layer 363 is not easily n-type. In addition, when the semiconductor layer 363 of the oxide semiconductor is in contact with the insulating layer 358 containing oxygen, oxygen vacancies of the semiconductor layer 363 are reduced, characteristics of the transistor 234 become stable, and reliability is improved.

In addition, when an oxide semiconductor is used for the semiconductor layer 363, the insulating layer 358 preferably contains excess oxygen. In the present specification and the like, the excess oxygen means oxygen desorbed by heating. When a material containing excess oxygen is used for insulating layer 358, a material which is not easily permeable to oxygen is preferably used for insulating layer 357 and insulating layer 359. As the material which is not easily permeable to oxygen, for example, an oxide containing one or both of aluminum and hafnium, a nitride of silicon, or the like can be used. The insulating layers 357 and 359 are made of a material which is not easily permeable to oxygen, so that excess oxygen contained in the insulating layer 358 is not easily removed from the lower layer or the upper layer. Therefore, sufficient oxygen can be supplied to the oxide semiconductor. For example, an insulating layer containing silicon and oxygen (insulating layer 358) may be provided between two insulating layers containing silicon and nitrogen (insulating layer 357 and insulating layer 359).

In addition, by using an oxide semiconductor for the semiconductor layer 363 and using a material containing hydrogen for the insulating layer 357 and the insulating layer 359, a region of the semiconductor layer 363 in contact with the insulating layer 357 and a region of the semiconductor layer 363 in contact with the insulating layer 359 are supplied with hydrogen, and each region in the semiconductor layer 363 is n-type. Therefore, a region of the semiconductor layer 363 in contact with the conductive layer 361 and a region of the semiconductor layer 363 in contact with the insulating layer 359 are used as one of a source (source region) and a drain (drain region). Further, a region of the semiconductor layer 363 in contact with the conductive layer 355 and a region of the semiconductor layer 363 in contact with the insulating layer 357 are used as the other of the source electrode (source region) and the drain electrode (drain region).

Fig. 14A shows an enlarged view of a cross section of the transistor 234 shown in fig. 13B. In the above-described structure, in the transistor 234 of the VFET, the length of the insulating layer 358 side surface viewed from the X direction or the Y direction is the channel length L (channel length L1) (see fig. 14A). Accordingly, the channel length L of the transistor 234 is determined according to the thickness t1 of the insulating layer 358.

In addition, materials containing no hydrogen or little hydrogen may be used for insulating layer 357 and insulating layer 359. For example, silicon nitride with little hydrogen or silicon oxynitride with little hydrogen may be used. At this time, the region where semiconductor layer 363 contacts insulating layer 357 and the region where semiconductor layer 363 contacts insulating layer 359 are not n-typed. Accordingly, a region of the semiconductor layer 363 in contact with the conductive layer 361 is used as one of a source (source region) and a drain (drain region). In addition, a region of the semiconductor layer 363 in contact with the conductive layer 355 is used as the other of the source (source region) and the drain (drain region). In addition, a region of the semiconductor layer 363 in contact with the insulating layer 358 is used as a channel formation region.

In this case, the total length of each side surface of insulating layer 357, insulating layer 358, and insulating layer 359 when viewed from the X direction or the Y direction is the channel length L (channel length L2). Accordingly, the channel length L of the transistor 234 is determined by the total thickness t2 of the insulating layer 357, the insulating layer 358, and the insulating layer 359.

Fig. 15A and 15B show a modified example of fig. 14A. For example, insulating layer 358 alone may be provided without insulating layer 357 and insulating layer 359 so that insulating layer 358 is in contact with conductive layer 355 and conductive layer 361 (see fig. 15A). In this case, the length of the side surface of the insulating layer 358 when viewed from the X direction or the Y direction is the channel length L. Accordingly, the channel length L of the transistor 234 is determined according to the thickness t of the insulating layer 358. In addition, when the structure shown in fig. 15A is employed, the insulating layer 358 is sometimes referred to as an insulating layer 356. Note that the channel length L shown in fig. 15A is synonymous with the channel length L2 shown in fig. 14A, and the thickness t2 shown in fig. 15A is synonymous with the thickness t2 shown in fig. 14A.

When an oxide semiconductor is used for the semiconductor layer 363, a material containing hydrogen is used for the insulating layer 357 and the insulating layer 359, and a material containing excess oxygen is used for the insulating layer 358, hydrogen in the insulating layer 357 and the insulating layer 359 is bonded to the excess oxygen in the insulating layer 358, and a region of the semiconductor layer 363 in contact with the insulating layer 357 and a region of the semiconductor layer 363 in contact with the insulating layer 359 are not sufficiently supplied with hydrogen, so that n-type is not easily performed. Likewise, a region of the semiconductor layer 363 in contact with the insulating layer 358 is not supplied with sufficient oxygen.

In order to solve the above problem, an insulating layer 371 which is not easily permeable to oxygen and nitrogen may be provided between the insulating layer 357 and the insulating layer 358, and an insulating layer 372 which is not easily permeable to oxygen and nitrogen may be provided between the insulating layer 359 and the insulating layer 358 (see fig. 15B). For example, a material that is not easily permeable to oxygen and nitrogen can be realized using silicon nitride or the like. Note that when the structure shown in fig. 15B is used, insulating layers 357, 371, 358, 372, and 359 may be collectively referred to as an insulating layer 356.

When a material which is not easily permeable to oxygen is used for the insulating layer 371 and the insulating layer 372, bonding between hydrogen in the insulating layer 357 and the insulating layer 359 and excess oxygen in the insulating layer 358 is blocked. Therefore, a region of the semiconductor layer 363 in contact with the insulating layer 357 and a region of the semiconductor layer 363 in contact with the insulating layer 359 are supplied with sufficient hydrogen. Similarly, a region of the semiconductor layer 363 in contact with the insulating layer 358 is supplied with sufficient oxygen.

In this case, the total length of the side surfaces of the insulating layer 371, the insulating layer 358, and the insulating layer 372 when viewed from the X direction or the Y direction is the channel length L3. Accordingly, the channel length L of the transistor 234 is determined by the total thickness t3 of the insulating layer 371, the insulating layer 358, and the insulating layer 372.

The transistor 234 according to the present embodiment determines the channel length L according to the thickness of the insulating layer provided between the conductive layer 361 and the conductive layer 355. Therefore, a transistor having a short channel length L can be manufactured with high accuracy. Further, characteristic unevenness among the plurality of transistors 234 can be reduced. Accordingly, the semiconductor device including the transistor 234 operates stably, and reliability can be improved. In addition, when the characteristic unevenness is reduced, the degree of freedom of circuit design of the semiconductor device is improved, and the operating voltage can also be reduced. Therefore, power consumption of the semiconductor device can be reduced.

In this embodiment, three insulating layers (an insulating layer 357, an insulating layer 358, and an insulating layer 359) or five insulating layers (an insulating layer 357, an insulating layer 358, an insulating layer 359, an insulating layer 371, and an insulating layer 372) are provided between the conductive layer 355 and the conductive layer 361, but the number of layers of the insulating layers between the conductive layer 355 and the conductive layer 361 is not limited thereto. The insulating layer between the conductive layer 355 and the conductive layer 361 may be one layer, two layers, four layers, or more than six layers.

In order to improve the coverage of the semiconductor layer 363, the insulating layer 364, and the conductive layer 365 formed in the opening 362, the taper angle θ of the side surface of the opening 362, that is, the taper angle θ of the side surface of each of the insulating layer 357, the insulating layer 358, and the insulating layer 359 may be set to 45 degrees or more and 90 degrees or less, preferably 50 degrees or more and 75 degrees or less. The taper angle θ of the side surface of a layer (insulating layer, conductive layer, or semiconductor layer) refers to the angle formed between the bottom surface and the side surface of the layer (see fig. 14A).

Fig. 16A and 16B show a modified example of fig. 14A. As shown in fig. 16A, by reducing the area of the bottom of the opening 362, the taper angle θ of the side surface of the opening 362 can be increased without increasing the occupied area of the transistor 234. By increasing the taper angle θ of the side surface of the opening 362, coverage of the semiconductor layer 363, the insulating layer 364, and the conductive layer 365 can be improved.

In addition, when the area of the bottom of the opening 362 is reduced, the conductive layer 365 sometimes becomes thinner toward the bottom of the opening 362 in the opening 362. The shape of the conductive layer 365 is sometimes referred to as a "needle shape" or a "cone shape".

As shown in fig. 16B, the side surfaces of the opening 362 can be made vertical or substantially vertical without causing any problem in coverage of the semiconductor layer 363, the insulating layer 364, and the conductive layer 365. In other words, the taper angle θ of the side surface of the opening 362 may be 90 degrees or substantially 90 degrees. By making the sides of the opening 362 vertical or substantially vertical, the occupied area of the transistor 234 can be reduced. Accordingly, the occupied area of the semiconductor device including the transistor 234 can be reduced.

By making the side surfaces of the opening 362 perpendicular, the channel length L1 is equal to the thickness t1 of the insulating layer 358. Further, by making the side surfaces of the opening 362 perpendicular, the channel length L2 is equal to the thickness t2 of the insulating layer 356.

Since the semiconductor layer 363 is provided in the opening 362, a perimeter of the opening 362 when viewed from the Z direction is a channel width W of the transistor 234 (see fig. 14B). As the circumferential length, for example, a circumferential length at a position half of the thickness t1 or a position half of the thickness t2 of the insulating layer 358 may be obtained. Note that the perimeter of any position of the opening 362 may be set to the channel width W as necessary. For example, the circumference of the lowermost portion of the opening 362 may be set to the channel width W or the circumference of the uppermost portion of the opening 362 may be set to the channel width W.

In the memory device according to one embodiment of the present invention, the channel length L is preferably at least smaller than the channel width W. The channel length L of one embodiment of the present invention is preferably 0.1 to 0.99 times, preferably 0.5 to 0.8 times, the channel width W.

In fig. 14B, the outline (planar shape) of the opening 362 when viewed from the Z direction is shown in a circular shape, but is not limited thereto. For example, the outline of the opening 362 as viewed from the Z direction may be elliptical (see fig. 14C) or rectangular (see fig. 14D). Note that fig. 14D shows a rectangle with corners curved. For example, the outline of the opening 362 as viewed from the Z direction may have a shape including one or both of a straight line portion and a curved line portion (see fig. 14E).

In addition, the opening 362 is preferably minute. For example, the maximum width of the opening 362 (maximum diameter when the opening 362 is circular) is preferably 60nm or less, more preferably 50nm or less, further preferably 40nm or less, and particularly preferably 30nm or less when viewed from the Z direction. The maximum width of the opening 362 as viewed in the Z direction may be 20nm or less. The minimum width of the opening 362 (i.e., the minimum diameter when the opening 362 is circular) is preferably 1nm or more, more preferably 5nm or more, when viewed from the Z direction. In order to form the minute openings 362, photolithography using a short wavelength light such as EUV light or an electron beam is preferably used.

In the transistor 234 according to one embodiment of the present invention, a capacitance value of a parasitic capacitance generated between the gate and the source is different from a capacitance value of a parasitic capacitance generated between the gate and the drain. Specifically, in the capacitor C1 generated between the conductive layer 365 and the conductive layer 361 and the capacitor C2 generated between the conductive layer 365 and the conductive layer 355, the capacitance value of the capacitor C1 is larger than that of the capacitor C2.

Fig. 17A and 17B show plan views of the transistor 234, and fig. 17C shows a cross-sectional view of the transistor 234. Note that in fig. 17A and 17B, a part of the constituent elements is omitted. In addition, fig. 17D shows an equivalent circuit diagram of the transistor 234.

When the transistor 234 according to one embodiment of the present invention is seen in the Z direction, the conductive layer 365 overlaps the conductive layer 361 at the peripheral portion of the opening 362, and overlaps the conductive layer 355 at the bottom portion of the opening 362. In fig. 17A, a region serving as the capacitor C1 when viewed from the Z direction is hatched. A region where the conductive layer 365 and the conductive layer 361 overlap with each other through the semiconductor layer 363 and the insulating layer 364 is used as the capacitor C1.

In fig. 17B, a region serving as the capacitor C2 when viewed from the Z direction is hatched. At the bottom of the opening 362, a region where the conductive layer 365 and the conductive layer 355 overlap with each other through the semiconductor layer 363 and the insulating layer 364 is used as the capacitor C2.

As is clear from fig. 17A and 17B, the area of the region serving as the capacitor C2 is larger than the area of the region serving as the capacitor C1. When the area of the region serving as the capacitor C2 is larger than the area of the region serving as the capacitor C1, the capacitance value of the capacitor C1 is larger than the capacitor C2.

By utilizing this phenomenon, the capacitor C1 and the capacitor C2, which are parasitic capacitances, can be intentionally used as capacitors. When the overlapping area of the conductive layer 365 and the conductive layer 355 is changed in order to change the capacitance value of the capacitor C2, the shape of the opening 362 is changed, whereby the circumference of the opening 362 is changed. The perimeter of opening 362 is the channel width W of transistor 234. Therefore, since the change in the circumferential length p directly affects the change in the electrical characteristics of the transistor 234, the adjustment of the capacitance value of the capacitor C2 is difficult.

On the other hand, the overlapping area of the conductive layer 365 and the conductive layer 361 is easily adjusted, and the electric characteristics of the transistor 234 are not easily affected. For example, by increasing the overlapping area of the conductive layer 365 and the conductive layer 361, the capacitance value of the capacitor C1 can be increased.

Fig. 18 shows a circuit diagram of the memory circuit 231. When VFET is used as the transistor 233 and the transistor 234 constituting the memory circuit 231, the capacitor C2 is preferably formed between the gate of the transistor and the capacitor 235. In addition, in the transistor 233, a capacitor C1 is preferably formed between the gate and the terminal Q. In addition, in the transistor 234, a capacitor C1 is preferably formed between the gate and the terminal SD.

When the capacitance value between the gate of the transistor 233 and the capacitor 235 is large, the node SN is easily affected by the potential variation of the signal BK. In addition, when the capacitance value between the gate of the transistor 234 and the capacitor 235 is large, the node SN is easily affected by the potential variation of the signal RE. In order to suppress the potential variation of the node SN and to operate the memory circuit 231 more stably, it is preferable that the capacitors C2 of the transistors 233 and 234 be formed between the node SD and the gate.

That is, in the transistor 233, the conductive layer 361 is preferably electrically connected to the terminal Q, and the conductive layer 355 is preferably electrically connected to one electrode (node SN) of the capacitor 235. In addition, in the transistor 234, the conductive layer 361 is preferably electrically connected to the terminal SD, and the conductive layer 355 is preferably electrically connected to one electrode (node SN) of the capacitor 235.

Fig. 19 shows an example of a stacked structure of OSFF to 210 of one of the semiconductor devices. OSFF210, shown in fig. 19, includes a layer 20 of k layers with memory circuits 231 over layer 10 including scan flip-flops 220. In fig. 19, the memory circuits 231 included in each of the layers 20 as the k layers exemplify the structure shown in fig. 13. In order to reduce the repetition of the description, the description of the memory circuit 231 is omitted here.

In addition, fig. 19 illustrates a transistor 400 included in the scan flip-flop 220. The transistor 400 is provided over a semiconductor substrate 311, and includes a conductive layer 316 serving as a gate, an insulating layer 315 serving as a gate insulator, a semiconductor region 313 constituted by a portion of the substrate 311, and a low-resistance region 314a and a low-resistance region 314b serving as source regions or drain regions. Transistor 400 may be a p-channel type transistor or an n-channel type transistor. As the substrate 311, a single crystal silicon substrate can be used, for example.

Here, in the transistor 400 shown in fig. 19, the semiconductor region 313 (a portion of the substrate 311) forming the channel has a convex shape. In addition, the conductive layer 316 covers the side surface and the top surface of the semiconductor region 313 via the insulating layer 315. In addition, a material for adjusting the work function can be used for the conductive layer 316. Such a transistor 400 is also referred to as a FIN-type transistor because of the use of a convex portion of a semiconductor substrate. Further, an insulator having a mask for forming the convex portion may be provided so as to be in contact with the top portion of the convex portion. Although the case where a portion of the semiconductor substrate is processed to form the convex portion is described here, the SOI (Silicon on Insulator) substrate may be processed to form a semiconductor film having a convex shape.

Note that the structure of the transistor 400 shown in fig. 19 is only an example, and the transistor is not limited to the above-described structure, and an appropriate transistor may be used according to a circuit structure or a driving method.

Wiring layers including interlayer films, wirings, plugs, and the like may be provided between the respective structures. Further, the wiring layer may be provided as a plurality of layers according to design. In this specification, the wiring and the plug electrically connected to the wiring may be one component. That is, a part of the electric conductor is sometimes used as a wiring, and a part of the electric conductor is sometimes used as a plug.

For example, an insulating layer 320, an insulating layer 322, an insulating layer 324, and an insulating layer 326 are stacked in this order as interlayer films over the transistor 400. Further, the insulating layer 320, the insulating layer 322, the insulating layer 324, the insulating layer 326 are embedded with a conductive layer 328, a conductive layer 330, and the like which are electrically connected to the conductive layer 352. In addition, the conductive layer 328 and the conductive layer 330 are used as contact plugs or wirings.

Further, an insulator which serves as an interlayer film may be used as a planarizing film which covers the concave-convex shape thereunder. For example, CMP treatment or the like may be performed to improve the flatness of the top surface of the insulating layer 322.

Further, a wiring layer may be provided over the insulating layer 326 and the conductive layer 330. For example, in fig. 19, an insulating layer 350, an insulating layer 382, and an insulating layer 384 are sequentially stacked over the insulating layer 326 and the conductive layer 330. The insulating layer 350, the insulating layer 382, and the insulating layer 384 have a conductive layer 386 formed therein. The conductive layer 386 is used as a contact plug or wire. Conductive layer 386 is electrically connected to conductive layer 352.

The structure shown in this embodiment mode can be implemented in appropriate combination with the structure shown in other embodiment modes.

Embodiment 4

In this embodiment, a configuration example in which a plurality of memory circuits 231 are arranged in one OSFF to overlap with the scan flip-flop 220 is described. Note that in order to reduce repetitive description, in this embodiment, a description will be mainly given of a portion different from other embodiments. Therefore, for the content not described in the present embodiment, reference may be made to other embodiments.

In the above embodiment, a configuration example in which a plurality of memory circuits 231 are stacked in the Z direction in one OSFF is described. When the area of the memory circuit 231 is sufficiently small relative to the area of the scan flip-flop 220, j (j is any one of integers of 2 or more) memory circuits 231 may be arranged in the X-Y plane on the same layer overlapping with the scan flip-flop 220.

In order to reduce the area of the memory circuit 231, VFET is preferably used for a transistor constituting the memory circuit 231. By setting the area of the memory circuit 231 to 1/2 or less, preferably 1/5 or less, more preferably 1/8 or less of the area of the scan flip-flop 220, it is easy to arrange a plurality of memory circuits 231 in a row on the same layer overlapping with the scan flip-flop 220.

Fig. 20A shows a perspective block diagram of OSFF a in which a plurality of memory circuits 231 are arranged in parallel on the same layer overlapping with the scan flip-flop 220. Fig. 21A shows an example of a circuit configuration of this OSFF. As an example, fig. 20A shows an example of four memory circuits 231 (memory circuits 231[1] to 231[4 ]) when j is 4 in parallel arrangement on the scan flip-flop 220. The scan flip-flop 220 is formed in the layer 10, and four memory circuits 231 are formed in the layer 20[1 ].

As shown in fig. 20B, the memory circuit 231 may be stacked. Fig. 20B is a perspective block diagram showing an example in which four memory circuits 231 are arranged in parallel in each of the layers 20[1] to 20[4 ]. Therefore, OSFF shown in FIG. 20B includes 16 storage circuits 231 (storage circuit 231[1] to storage circuit 231[16 ]). OSFF210 shown in fig. 20B is OSFF210 when k is 4 and j is 4.

By providing a plurality of memory circuits 231 in one layer 20, a larger number of memory circuits 231 can be provided with a smaller number of layers. In addition, by reducing the number of stacked layers 20, the productivity of OSFF a 210 can be improved. Further, the productivity of the semiconductor device including OSFF to 210 is improved.

The transistor 232 may be provided in the layer 10 or the layer 20 (see fig. 21A and 21B). In other words, the transistor 232 may be a Si transistor or an OS transistor.

As described above, by using VFET as a transistor constituting the memory circuit 231, the area of the memory circuit 231 can be reduced. In addition, if the areas of the memory circuits 231 are equal, the number of transistors for the memory circuits 231 can be increased. For example, by connecting a plurality of VFETs in parallel, the plurality of VFETs can be used as one transistor with a larger channel width W. In addition, a photomask for forming the VFET may be used to form the capacitor 235 overlapping the VFET when viewed from the Z direction.

Fig. 22A shows a schematic perspective view of a structural example of the memory circuit 231. Fig. 22B is a circuit diagram of the memory circuit 231 shown in fig. 22A. The memory circuit 231 shown in fig. 22A and 22B includes eight transistors (a transistor 233a, a transistor 233B, a transistor 233c, a transistor 233d, a transistor 234a, a transistor 234B, a transistor 234c, and a transistor 234 d). The memory circuit 231 shown in fig. 22A and 22B includes eight capacitors (a capacitor 235a, a capacitor 235B, a capacitor 235c, a capacitor 235d, a capacitor 235e, a capacitor 235f, a capacitor 235g, and a capacitor 235 h).

The transistor 233a, the transistor 233b, the transistor 233c, and the transistor 233d are connected in parallel and are used as one transistor 233. The sources of the transistors 233a, 233b, 233c, and 233d are electrically connected to each other, the drains thereof are electrically connected to each other, and the gates thereof are electrically connected to each other.

The transistor 234a, the transistor 234b, the transistor 234c, and the transistor 234d are connected in parallel, and are used as one transistor 234. The sources of the transistors 234a, 234b, 234c, and 234d are electrically connected to each other, the drains thereof are electrically connected to each other, and the gates thereof are electrically connected to each other.

The capacitor 235a, the capacitor 235b, the capacitor 235c, the capacitor 235d, the capacitor 235e, the capacitor 235f, the capacitor 235g, and the capacitor 235h are connected in parallel, and are used as one capacitor 235. One electrode of each of the capacitors 235a to 235h is electrically connected to each other, and the other electrode is electrically connected to each other.

As described above, by connecting a plurality of transistors in parallel, the plurality of transistors are used as one transistor whose channel width W is large. By increasing the channel width W of the transistor 233, the speed of writing data to the node SN can be increased. By increasing the channel width W of the transistor 234, the speed of reading data from the node SN can be increased. In addition, by connecting a plurality of capacitors in parallel, the capacitance value of the capacitor 235 increases, whereby the data holding capability of the node SN can be improved.

Fig. 23A shows a plan view of the OSFF when the memory circuit 231 shown in fig. 22A is used for the OSFF a to 210 shown in fig. 20A. Fig. 23B shows a plan view of the amplification memory circuit 231[1 ]. Fig. 24A shows a schematic perspective view of an area including the memory circuit 231[1] and the memory circuit 231[2] of OSFF a shown in fig. 23A. Fig. 24B is a schematic perspective view showing a region including the memory circuit 231[1] and the conductive layer 369SD of OSFF a shown in fig. 23A.

In fig. 23A, the conductive layer 361Q is electrically connected to the terminal Q of OSFF through the conductive layer 369Q. In addition, the conductive layer 361Q and the conductive layer 369Q can be used as the terminal Q. The conductive layer 361SD is electrically connected to the terminal SD of OSFF through the conductive layer 369 SD. In addition, the conductive layers 361SD and 369SD can be used as the terminals Q.

The conductive layer 361Q and the conductive layer 361SD both extend in the X direction. In addition, the conductive layers 347 (conductive layers 347 1a, 347 2a, 347 3a, 347 4 a) to which the signal RE is supplied and the conductive layers 347 (conductive layers 347 1b, 347 2b, 347 3 b, 347 4 b) to which the signal BK is supplied extend in the Y direction. That is, the conductive layer 347 extends in a direction intersecting the conductive layers 361 (the conductive layer 361Q and the conductive layer 361 SD).

In addition, each of the conductive layer 369Q and the conductive layer 369SD extends in the Z direction (see fig. 24B). That is, the conductive layers 369 (the conductive layers 369Q and 369 SD) extend in a direction intersecting each of the conductive layers 347 and 361.

The conductive layer 369 is used as a contact plug, a through electrode (VIA), or a wiring. By extending the conductive layer 369Q in the Z direction, the conductive layer 361Q included in each of the stacked memory circuits 231 (see fig. 20B) can be electrically connected to the terminal Q of the OSFF through one conductive layer 369Q. In addition, by extending the conductive layer 369SD in the Z direction, the conductive layer 361SD included in each of the stacked memory circuits 231 can be electrically connected to the terminal SD of OSFF210 through one conductive layer 369 SD.

For example, the signal RE [1] is supplied to the memory circuit 231[1] through the conductive layer 347[ 1a ], and the signal BK [1] is supplied to the memory circuit 231[1] through the conductive layer 347[ 1b ]. In addition, the signal RE 2 is supplied to the memory circuit 231 2 through the conductive layer 347 2 a, and the signal BK 2 is supplied to the memory circuit 231 2 through the conductive layer 347 2 b. In addition, the signal RE [3] is supplied to the memory circuit 231[3] through the conductive layer 347[ 3a ], and the signal BK [3] is supplied to the memory circuit 231[3] through the conductive layer 347[ 3b ]. In addition, the signal RE [4] is supplied to the memory circuit 231[4] through the conductive layer 347[ 4a ], and the signal BK [4] is supplied to the memory circuit 231[4] through the conductive layer 347[ 4b ].

Next, a stacked structure example of a semiconductor device according to an embodiment of the present invention shown in fig. 23A will be described. Fig. 25 is a sectional view of a portion along the chain line A1-A2 in fig. 23A. Further, fig. 26 is a sectional view of a portion along the dash-dot line of A3-A4 in fig. 23A. In this embodiment, an example of a stacked structure of the portions shown by the alternate long and short dash lines A1 to A2 in fig. 23A and the portions shown by the alternate long and short dash lines A3 to A4 in fig. 23A will be described.

Fig. 25 is a diagram of a cross-sectional structure including the memory circuit 231[1], and fig. 26 is a diagram of a cross-sectional structure including the memory circuit 231[1] and the memory circuit 231[2 ]. The semiconductor device includes an insulating layer 353 (not shown in fig. 26) and a conductive layer 351 formed so as to be embedded in the insulating layer 353 on the scan flip-flop 220 provided in the layer 10. The conductive layer 351 is used as a wiring CL. Further, the top surface positions (positions in the Z direction) of the insulating layer 353 and the conductive layer 351 are preferably made uniform or substantially uniform by a CMP method or the like.

The semiconductor device includes an insulating layer 341 over the insulating layer 353 and the conductive layer 351. The insulating layer 353 is provided with openings 342 (openings 342a to 342 h) in a region overlapping with a part of the conductive layer 351. Note that in fig. 25 and 26, the opening 342c, the opening 342d, and the opening 342g are not illustrated.

In addition, the semiconductor device includes a conductive layer 343 over the insulating layer 341. The insulating layer 341 includes a region overlapping with the openings 342 (the openings 342a to 342 h). In each of the openings 342a to 342h, the conductive layer 343 has a region overlapping the bottom of the opening and a region overlapping the side surface of the opening (the side surface of the insulating layer 341). At the bottom of each of the openings 342a to 342h, a conductive layer 343 is electrically connected to the conductive layer 351.

In addition, the semiconductor device includes an insulating layer 344 covering the conductive layer 343 over the conductive layer 343. The insulating layer 344 has a region overlapping the side surface of the opening 342 with the conductive layer 343 interposed therebetween, and a region overlapping the bottom surface of the opening 342 with the conductive layer 343 interposed therebetween. In addition, the semiconductor device includes a plurality of conductive layers 355 over the insulating layer 344. The conductive layer 355 has a region overlapping the side surface of the opening 342 with the insulating layer 344 and the conductive layer 343 interposed therebetween, and a region overlapping the bottom surface of the opening 342 with the insulating layer 344 and the conductive layer 343 interposed therebetween.

In the opening 342a, a region where the conductive layer 343 and the conductive layer 355 (the conductive layer 355[1] or the conductive layer 355[2 ]) overlap with each other through the insulating layer 344 is used as the capacitor 235a. In the opening 342b, a region where the conductive layer 343 and the conductive layer 355 overlap with each other through the insulating layer 344 is used as the capacitor 235b. In the opening 342c, a region where the conductive layer 343 and the conductive layer 355 overlap with each other through the insulating layer 344 is used as the capacitor 235c. In the opening 342d, a region where the conductive layer 343 and the conductive layer 355 overlap with each other through the insulating layer 344 is used as the capacitor 235d. In the opening 342e, a region where the conductive layer 343 and the conductive layer 355 overlap with each other through the insulating layer 344 is used as the capacitor 235e. In the opening 342f, a region where the conductive layer 343 and the conductive layer 355 overlap with each other through the insulating layer 344 is used as the capacitor 235f. In the opening 342g, a region where the conductive layer 343 and the conductive layer 355 overlap with each other through the insulating layer 344 is used as the capacitor 235g. In the opening 342h, a region where the conductive layer 343 and the conductive layer 355 overlap with each other through the insulating layer 344 is used as the capacitor 235h.

The capacitors 235a to 235h are connected in parallel to each other and are used as one capacitor 235. The insulating layer 344 used as the dielectric of the capacitor 235 may be made of a material having a high relative permittivity (also referred to as a high-k material). In addition, a ferroelectric may be used for the insulating layer 344 that serves as a dielectric of the capacitor 235.

Conductive layer 355 is used as node SN. In addition, the conductive layer 355 is provided independently in each memory circuit 231. For example, the conductive layer 355[1] included in the memory circuit 231[1] is used as the node SN for holding data written to the memory circuit 231[1], and the conductive layer 355[2] included in the memory circuit 231[2] is used as the node SN for holding data written to the memory circuit 231[2 ].

The semiconductor device includes an insulating layer 357 over the insulating layer 341 and the conductive layer 355, an insulating layer 358 over the insulating layer 357, and an insulating layer 359 over the insulating layer 358. Insulating layer 357, insulating layer 358, and insulating layer 359 are sometimes collectively referred to as insulating layer 356 or a spacer layer. Further, a conductive layer 361 (a conductive layer 361SD and a conductive layer 361Q) is included over the insulating layer 359.

In a region overlapping with a part of the conductive layer 355, openings 362 (openings 362a to 362 h) are provided in the conductive layer 361, the insulating layer 359, the insulating layer 358, and the insulating layer 357. Note that, in fig. 25 and 26, the opening 362c, the opening 362d, and the opening 362g are not illustrated.

In FIG. 25, the semiconductor device includes a semiconductor layer 363[1] a covering an opening 362a, an opening 362b, an opening 362c (not shown), and an opening 362d (not shown). The semiconductor layer 363[1] a has a region overlapping with the bottoms of the openings 362a, 362b, 362c, and 362d and a region overlapping with each side surface.

In addition, in fig. 25 and 26, the semiconductor device includes a semiconductor layer 363[1] b covering the opening 362e, the opening 362f, the opening 362g (not shown), and the opening 362 h. The semiconductor layer 363[1] b includes a region overlapping with the bottoms of the openings 362e, 362f, 362g, and 362h and a region overlapping with each side surface.

The semiconductor device includes an insulating layer 364 over an insulating layer 359, a conductive layer 361, and a semiconductor layer 363 (a semiconductor layer 3631 a, a semiconductor layer 3631 b, a semiconductor layer 3632 a (not shown), and a semiconductor layer 3632 b), and includes a conductive layer 365 (a conductive layer 365 1 a, a conductive layer 365 1b, a conductive layer 365 2a (not shown), and a conductive layer 365 2 b) over the insulating layer 364. In addition, the semiconductor device includes an insulating layer 366 over the insulating layer 364. The top surfaces of the conductive layer 365 and the insulating layer 366 are aligned or substantially aligned (i.e., aligned in the Z direction).

The region including the opening 362a is used as the transistor 234a, and the region including the opening 362b is used as the transistor 234b. In addition, a region including the opening 362c is used as the transistor 234c (not shown), and a region including the opening 362d is used as the transistor 234d (not shown). The transistor 234a, the transistor 234b, the transistor 234c, and the transistor 234d are connected in parallel, and are used as one transistor 234 having a large channel width W.

In addition, a region including the opening 362e is used as the transistor 233a, and a region including the opening 362f is used as the transistor 233b. In addition, a region including the opening 362g is used as the transistor 233c (not shown), and a region including the opening 362h is used as the transistor 233d (not shown). The transistor 233a, the transistor 233b, the transistor 233c, and the transistor 233d are connected in parallel, and are used as one transistor 233 having a large channel width W.

Note that the description of the transistor 233 and the transistor 234 can be given with reference to the above embodiment. Therefore, in this embodiment, description of the transistor 233 and the transistor 234 is omitted.

In addition, the semiconductor device includes a conductive layer 345 over the conductive layer 365. FIG. 25 shows conductive layer 345[1] a on conductive layer 365[1] a, and FIG. 26 shows conductive layer 345[1] b on conductive layer 365[1] b and conductive layer 345[2] b on conductive layer 365[2] b. In addition, the semiconductor device includes an insulating layer 346 over the insulating layer 366 and the conductive layer 365. It is preferable that top surfaces of the conductive layer 345 and the insulating layer 346 be positioned at the same or substantially the same position (position in the Z direction).

In addition, the semiconductor device includes a plurality of conductive layers 347 over the conductive layer 345 and the insulating layer 346. In fig. 25 and 26, a conductive layer 347 1a, a conductive layer 347 1b, a conductive layer 347 2a, and a conductive layer 347 2b are illustrated as a plurality of conductive layers 347. Conductive layer 347[1] a is electrically connected to conductive layer 365[1] a through conductive layer 345[1] a. Conductive layer 347[1] b is electrically connected to conductive layer 365[1] b through conductive layer 345[1] b. Conductive layer 347[2] a is electrically connected to conductive layer 365[2] a (not shown) through conductive layer 345[2] a (not shown). Conductive layer 347[2] b is electrically connected to conductive layer 365[2] b through conductive layer 345[2] b.

In addition, the semiconductor device includes an insulating layer 348 over the insulating layer 346. The top surfaces of the conductive layer 347 and the insulating layer 348 are preferably aligned or substantially aligned (i.e., aligned in the Z direction). In addition, the semiconductor device includes an insulating layer 349 over the conductive layer 347 and the insulating layer 348.

As described above, the conductive layer 361SD is used as the terminal SD, and the conductive layer 361Q is used as the terminal Q. In addition, the signal RE [1] is supplied to the memory circuit 231[1] through the conductive layer 347[1 a ], and the signal BK [1] is supplied to the memory circuit 231[1] through the conductive layer 347[ 1b ]. In addition, the signal RE 2 is supplied to the memory circuit 231 2 through the conductive layer 347 2a, and the signal BK 2 is supplied to the memory circuit 231 2 through the conductive layer 347 2 b.

The structure shown in this embodiment mode can be implemented in appropriate combination with the structure shown in other embodiment modes.

Embodiment 5

An application example of the semiconductor device according to one embodiment of the present invention will be described in this embodiment.

The semiconductor device according to one embodiment of the present invention can be applied to various electronic components in addition to a CPU. For example, the method can be applied to registers of microprocessors such as a DSP (DIGITAL SIGNAL Processor: digital signal Processor) and a GPU (Graphics Processing Unit: graphics Processor). The microprocessor may also be implemented by PLDs (Programmable Logic Device: programmable logic devices) such as FPGAs (Field Programmable GATE ARRAY: field programmable gate arrays), FPAA (Field Programmable Analog Array: field programmable analog arrays), and the like.

Accordingly, the semiconductor device according to one embodiment of the present invention can be applied to various electronic devices (for example, an information terminal, a computer, a smart phone, an electronic book reader terminal, a digital still camera, a video recording and reproducing device, a navigation system, a game machine, and the like). In addition, the method can also be applied to image sensors, ioT (Internet of Things: internet of things), medical equipment and the like. Here, the computer includes a tablet computer, a notebook computer, a desktop computer, and a mainframe computer such as a server system.

An example of an electronic device including a semiconductor device according to an embodiment of the present invention will be described. Fig. 27A to 27J show a case where an electronic component 700 having the semiconductor device is included in each electronic apparatus.

Mobile telephone set

The information terminal 5500 shown in fig. 27A is a mobile phone (smart phone) which is one of information terminals. The information terminal 5500 includes a housing 5510 and a display portion 5511, and the display portion 5511 includes a touch panel as an input interface and buttons are provided on the housing 5510.

By applying the semiconductor device according to one embodiment of the present invention to the information terminal 5500, interrupt processing or the like occurring when a program is executed can be promptly handled.

Wearable terminal

Fig. 27B shows an information terminal 5900 which is an example of a wearable terminal. The information terminal 5900 includes a housing 5901, a display portion 5902, an operation switch 5903, an operation switch 5904, a wristband 5905, and the like.

As in the case of the information terminal 5500, by applying the semiconductor device according to one embodiment of the present invention to a wearable terminal, interrupt processing or the like occurring when a program is executed can be promptly handled.

[ Information terminal ]

Fig. 27C shows a station information terminal 5300. The desktop information terminal 5300 includes an information terminal main body 5301, a display portion 5302, and a keyboard 5303.

As in the case of the information terminal 5500, by applying the semiconductor device according to one embodiment of the present invention to the desk type information terminal 5300, interrupt processing or the like occurring when a program is executed can be promptly handled.

Note that in the above description, fig. 27A to 27C show a smart phone, a wearable terminal, and a desk-top information terminal as examples of the electronic device, respectively, but information terminals other than the smart phone, the wearable terminal, and the desk-top information terminal may be applied. Examples of information terminals other than smart phones, wearable terminals, and desktop information terminals include PDAs (Personal DIGITAL ASSISTANT: personal digital assistants), notebook information terminals, and workstations.

[ Electrical products ]

Fig. 27D shows an electric refrigerator-freezer 5800 which is an example of an electric product. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like. For example, the electric refrigerator-freezer 5800 is an electric refrigerator-freezer corresponding to IoT (Internet of Things: internet of things).

The semiconductor device according to one embodiment of the present invention can be applied to the electric refrigerator-freezer 5800. By using the internet or the like, the electric refrigerator-freezer 5800 can be caused to transmit information such as food stored in the electric refrigerator-freezer 5800, or a consumption period of the food, to an information terminal or the like.

As in the case of the information terminal 5500, by applying the semiconductor device according to one embodiment of the present invention to the electric refrigerator/freezer 5800, it is possible to promptly cope with an interruption process or the like occurring when a program is executed.

In the above examples, the electric refrigerator-freezer is described as an electric appliance, but examples of other electric appliances include a vacuum cleaner, a microwave oven, an electric rice cooker, a water heater, an IH cooker, a water dispenser, a cooling and heating air conditioner including an air conditioner, a washing machine, a clothes dryer, and an audio-visual appliance.

[ Game machine ]

Further, fig. 27E shows a portable game machine 5200 which is an example of a game machine. The portable game machine 5200 includes a housing 5201, a display portion 5202, a button 5203, and the like.

Fig. 27F shows a stationary game machine 7500 as an example of a game machine. The stationary game machine 7500 includes a main body 7520 and a controller 7522. The main body 7520 may be connected to the controller 7522 in a wireless manner or a wired manner. Although not shown in fig. 27F, the controller 7522 may include a display unit for displaying an image of a game, a touch panel and a lever as an input interface other than buttons, a rotary gripper, a slide gripper, or the like. The shape of the controller 7522 is not limited to the shape shown in fig. 27F, and the shape of the controller 7522 may be changed according to the type of game. For example, in a shooting game such as FPS (First Person Shooter, first person shooting game), a controller that mimics the shape of a gun may be used as a trigger use button. Further, for example, in a music game or the like, a controller that mimics the shape of a musical instrument, a musical device or the like may be used. Further, the stationary game machine may be provided with a camera, a depth sensor, a microphone, and the like, and may be operated by a gesture or sound of a game player, instead of the controller.

The video of the game machine may be outputted from a display device such as a television device, a personal computer display, a game display, or a head mounted display.

By using the semiconductor device described in the above embodiment modes for the portable game machine 5200 or the stationary game machine 7500, the portable game machine 5200 or the stationary game machine 7500 with low power consumption can be realized. Further, by virtue of low power consumption, heat generation from the circuit can be reduced, whereby adverse effects on the circuit itself, peripheral circuits, and modules due to heat generation can be reduced.

Further, by using the semiconductor device described in the above embodiment for the portable game machine 5200 or the stationary game machine 7500, it is possible to quickly cope with an interruption process or the like occurring when a game is played.

In fig. 27E, a portable game machine is shown as an example of the game machine. In addition, fig. 27F shows a home stationary game machine. The electronic device according to one embodiment of the present invention is not limited to this. Examples of the electronic device according to one embodiment of the present invention include a arcade game machine installed in an amusement facility (a game center, an amusement park, etc.), a ball pitching machine for ball hitting practice installed in a sports facility, and the like.

[ Moving object ]

The semiconductor device described in the above embodiment mode can be applied to an automobile as a moving body and the vicinity of a driver's seat of the automobile.

Fig. 27G shows an automobile 5700 as an example of a moving body.

An instrument panel capable of displaying a speedometer, a tachometer, a travel distance, an amount of fuel charged, a gear state, a setting of an air conditioner, and the like to provide various information is provided near the driver seat of the automobile 5700. A display device for displaying the information may be provided near the driver seat.

In particular, by displaying an image captured by an imaging device (not shown) provided in the automobile 5700 on the display device, it is possible to supplement a view blocked by a pillar or the like, a blind spot of a driver's seat, or the like, and thus it is possible to improve safety. That is, by displaying an image captured by a camera provided outside the automobile 5700, a field of view can be supplemented to avoid dead angles, so that safety can be improved.

By applying the semiconductor device according to one embodiment of the present invention to a mobile body, it is possible to quickly cope with an interruption process or the like occurring when the mobile body is operated, such as an emergency stop measure.

Although an automobile is described as one example of the moving body in the above example, the moving body is not limited to an automobile. For example, the moving body may be an electric car, a monorail, a ship, a flying object (helicopter, unmanned plane (unmanned plane), airplane, rocket), or the like.

[ Camera ]

The semiconductor device described in the above embodiment modes can be applied to a camera.

Fig. 27H shows a digital camera 6240 which is an example of an imaging device. The digital camera 6240 includes a housing 6241, a display portion 6242, an operation switch 6243, a shutter button 6244, and the like, and a detachable lens 6246 is mounted. Here, the digital camera 6240 has a structure in which the lens 6246 can be detached from the housing 6241, but the lens 6246 may not be detached. The digital camera 6240 may further include a flash device, a viewfinder, and the like which are additionally mounted.

By using the semiconductor device described in the above embodiment modes for the digital camera 6240, the digital camera 6240 with low power consumption can be realized. Further, by virtue of low power consumption, heat generation from the circuit can be reduced, whereby adverse effects on the circuit itself, peripheral circuits, and modules due to heat generation can be reduced.

[ Video camera ]

The semiconductor device described in the above embodiment modes can be applied to a video camera.

Fig. 27I shows a video camera 6300 which is an example of an image pickup apparatus. The video camera 6300 includes a first housing 6301, a second housing 6302, a display portion 6303, an operation switch 6304, a lens 6305, a connection portion 6306, and the like. The operation switch 6304 and the lens 6305 are provided in the first casing 6301, and the display portion 6303 is provided in the second casing 6302. The first housing 6301 and the second housing 6302 are connected by a connection portion 6306, and an angle between the first housing 6301 and the second housing 6302 may be changed by the connection portion 6306. The image of the display portion 6303 may be switched according to an angle between the first casing 6301 and the second casing 6302 in the connection portion 6306.

By using the semiconductor device described in the above embodiment modes for the video camera 6300, the video camera 6300 with low power consumption can be realized. Furthermore, with low power consumption, the imaging time can be prolonged. In addition, by virtue of low power consumption, heat generation from the circuit can be reduced, whereby adverse effects on the circuit itself, peripheral circuits, and modules due to heat generation can be reduced.

[ICD]

The semiconductor device described in the above embodiment modes can be applied to a buried cardioverter defibrillator (ICD: implantable Cardioverter Defibrillator).

Fig. 27J is a schematic cross-sectional view showing an example of an ICD. ICD body 5400 includes at least a battery 5401, electronics 700, a regulator, control circuitry, an antenna 5404, a wire 5402 for the right atrium, a wire 5403 for the right ventricle.

The ICD body 5400 is surgically placed in the body with two wires passing through the subclavian vein 5405 and superior vena cava 5406 of the human body and with the leading end of one wire placed in the right ventricle and the leading end of the other wire placed in the right atrium.

The ICD body 5400 functions as a cardiac pacemaker and paces the heart when the heart rhythm is outside a prescribed range. In addition, treatment using defibrillation is performed when the heart rhythm (ventricular tachycardia, ventricular fibrillation, etc.) is not improved even when pacing is performed.

The ICD body 5400 requires frequent monitoring of heart rhythm in order to properly pace and defibrillate. Accordingly, ICD body 5400 includes a sensor for detecting heart rhythms. In addition, ICD body 5400 may store data of heart rhythm measured by the sensor, number of treatments with pacing, time, etc. in electronic component 700.

Further, since power is received by the antenna 5404, the power is charged to the battery 5401. Further, by having ICD body 5400 include multiple batteries, safety may be improved. In particular, even if some of the batteries in ICD body 5400 fail, other batteries may function to serve as auxiliary power sources.

In addition to the antenna 5404 capable of receiving electric power, an antenna capable of transmitting a physiological signal may be included, and for example, a system for monitoring heart activity may be configured so that physiological signals such as pulse, respiration rate, heart rhythm, and body temperature can be confirmed by an external monitoring device.

By applying the semiconductor device described in the above embodiment modes to the ICD body 5400, the ICD body 5400 with low power consumption can be realized. In addition, by virtue of low power consumption, miniaturization and weight saving of the battery can be achieved. Further, with low power consumption, heat generation of the ICD body 5400 can be reduced, whereby the load on the human body can be reduced.

[ Computer ]

The computer 5600 shown in fig. 28A is an example of a mainframe computer (supercomputer) mainly used for scientific calculation. Since scientific calculation requires a huge operation at high speed, power consumption is large and heat generation of a chip is high. For example, in a data center including a plurality of supercomputers, the amount of digital data used is very large. Specifically, it is estimated that the global digital data amount exceeds 10 ²⁴ (yota (yao)) bytes or 10 ³⁰ (quetta (kun)) bytes.

By using the semiconductor device according to one embodiment of the present invention for the computer 5600, a low-power-consumption supercomputer can be realized. Further, by virtue of low power consumption, heat generation from the circuit can be reduced, whereby adverse effects on the circuit itself, peripheral circuits, and modules due to heat generation can be reduced. In addition, by using the semiconductor device according to one embodiment of the present invention, a low-power-consumption supercomputer can be realized. Thus, measures can be expected that reduce the amount of global digital data and can greatly contribute to global warming.

In the computer 5600, a plurality of rack-mounted computers 5620 are housed in a rack 5610. The computer 5620 may have a structure of a perspective view shown in fig. 28B, for example. In fig. 28B, the computer 5620 includes a motherboard 5630, and the motherboard 5630 includes a plurality of slots 5631 and a plurality of connection terminals. The slot 5631 has a personal computer card 5621 inserted therein. Also, the personal computer card 5621 includes a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, which are connected to the motherboard 5630.

The personal computer card 5621 shown in fig. 28C is an example of a processing board including a CPU, a GPU, a storage device, and the like. The personal computer card 5621 has a board 5622. The board 5622 includes a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629. Note that fig. 28C shows semiconductor devices other than the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628, and for description of these semiconductor devices, reference is made to the description of the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 described below.

The connection terminal 5629 has a shape that can be inserted into the slot 5631 of the motherboard 5630, and the connection terminal 5629 is used as an interface for connecting the personal computer card 5621 with the motherboard 5630. The specification of the connection terminal 5629 includes PCIe, for example.

The connection terminals 5623, 5624, 5625 can be used as interfaces for supplying power to the personal computer card 5621, inputting signals, or the like, for example. Further, for example, an interface for outputting a signal calculated by the personal computer card 5621 or the like may be used. Examples of the specifications of the connection terminals 5623, 5624, and 5625 include USB, SATA (SERIAL ATA: serial ATA), SCSI (Small Computer SYSTEM INTERFACE: small Computer system interface), and the like. When video signals are output from the connection terminals 5623, 5624, and 5625, HDMI (registered trademark) and the like are given as respective specifications.

The semiconductor device 5626 includes a terminal (not shown) for inputting and outputting a signal, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) included in the board 5622.

The semiconductor device 5627 includes a plurality of terminals, and the semiconductor device 5627 and the board 5622 can be electrically connected by soldering the terminals to wiring included in the board 5622 by reflow. Examples of the semiconductor device 5627 include an FPGA (Field Programmable GATE ARRAY: field programmable gate array), a GPU, and a CPU. As the semiconductor device 5627, for example, the electronic component 700 can be used.

The semiconductor device 5628 includes a plurality of terminals, and the semiconductor device 5628 and the board 5622 can be electrically connected by soldering the terminals to wiring included in the board 5622, for example, by reflow soldering. The semiconductor device 5628 includes, for example, a memory device.

Computer 5600 can be used as a parallel computer. By using the computer 5600 as a parallel computer, for example, large-scale calculation required for learning and inference of artificial intelligence can be performed.

By using the semiconductor device according to one embodiment of the present invention for the above-described various electronic devices and the like, interrupt processing and the like occurring when a program is executed can be promptly handled. By using the semiconductor device according to one embodiment of the present invention for the various electronic devices, power consumption of the electronic devices can be reduced. By virtue of the low power consumption, heat generation from the circuit is reduced, whereby adverse effects on the circuit itself, peripheral circuits, and modules can be reduced. Further, by using the semiconductor device according to one embodiment of the present invention, an electronic device that stably operates even in a high-temperature environment can be realized. Thus, the reliability of the electronic device can be improved.

The structure shown in this embodiment mode can be implemented in appropriate combination with the structure shown in other embodiment modes.

Embodiment 6

The semiconductor device according to one embodiment of the present invention includes an OS transistor. The OS transistor has small variation in electrical characteristics due to irradiation of radiation. In other words, since the resistance to radiation is high, the composition can be suitably used even in an environment where radiation is likely to be incident. For example, an OS transistor can be used appropriately in the case of use in a cosmic space. In this embodiment, a specific example of a case where the semiconductor device according to one embodiment of the present invention is applied to space equipment will be described with reference to fig. 29.

In fig. 29, a satellite 6800 is shown as an example of a space device. The satellite 6800 includes a main body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Fig. 29 shows an example in which a planet 6804 exists in the space. Note that, the space means, for example, a height of 100km or more, but the space shown in the present specification may include a thermal layer, an intermediate layer, and a stratosphere.

In addition, the space is an environment in which the radiation dose is 100 times or more of that of the ground. Examples of the radiation include electromagnetic waves (electromagnetic radiation rays) typified by X-rays and γ -rays, and particle radiation rays typified by α -rays, β -rays, neutron rays, proton rays, heavy ion rays, and meson rays.

When sunlight irradiates the solar cell panel 6802, electric power required for the artificial satellite 6800 to operate is generated. However, for example, in the case where sunlight is not irradiated to the solar cell panel or in the case where the amount of sunlight irradiated to the solar cell panel is small, the amount of generated electric power is reduced. Therefore, there is a possibility that electric power required for the artificial satellite 6800 to operate is not generated. In order to operate the artificial satellite 6800 even when the generated electric power is small, it is preferable to provide the secondary battery 6805 in the artificial satellite 6800. In addition, the solar cell panel is sometimes referred to as a solar cell module.

The satellite 6800 may generate signals. The signal is transmitted via an antenna 6803, for example, which may be received by a receiver on the ground or other satellite vehicle. By receiving the signal transmitted by the satellite 6800, the position of the receiver that received the signal can be measured. Thus, the satellite 6800 can constitute a satellite positioning system.

The control device 6807 also has a function of controlling the satellite 6800. The control device 6807 is configured using one or more selected from a CPU, a GPU, and a storage device, for example. Further, as the control device 6807, a semiconductor device including an OS transistor according to one embodiment of the present invention is preferably used. The OS transistor has less variation in electrical characteristics due to irradiation of radiation than the Si transistor. That is, the OS transistor has high reliability even in an environment where radiation is likely to be incident and can be suitably used.

In addition, the satellite 6800 can include sensors. For example, by including a visible light sensor, the satellite 6800 can have the function of detecting sunlight reflected by objects on the ground. Alternatively, the satellite 6800 may have a function of detecting thermal infrared rays released from the ground surface by including a thermal infrared sensor. Thus, the satellite 6800 can be used as an earth observation satellite, for example.

Note that in the present embodiment, an artificial satellite is shown as an example of a space device, but is not limited thereto. For example, the semiconductor device according to one embodiment of the present invention can be suitably applied to space equipment such as spacecraft, space capsule, space probe, and the like.

The structure shown in this embodiment mode can be implemented in appropriate combination with the structure shown in other embodiment modes.

[ Description of the symbols ]

100:Semiconductor device, 110:CPU core, 111:operation part, 120:bus, 130:PMU, 131:control circuit, 140:input/output IF, 150:cache, 160:state control part, 200:register group, 201:register, 210:OSF, 220:scan, 221:selector, 222:flip-flop, 230:data holding circuit, 231:storage circuit, 232:transistor, 233:transistor, 234:capacitor, 250:flip-flop group, 255:storage unit, 260:group storage

Claims (5)

1.A semiconductor device, comprising:

a flip-flop group of n flip-flops (n is any one of integers of 2 or more);

A first memory cell including n memory circuits disposed on the flip-flop group, and

A second memory cell including p (p is an integer of 1 or more and less than n) memory circuits provided on the first memory cell,

Wherein the flip-flop includes a first transistor including silicon in a semiconductor layer forming a channel,

The n memory circuits and the p memory circuits each include a second transistor including an oxide semiconductor in a semiconductor layer forming a channel,

The semiconductor device has the following functions:

When the data held by the trigger group is n-bit first data, holding the first data in the first memory cell in a first operation, and

And when the data held by the trigger group is p-bit second data, the second data is held in the second storage unit in a second operation.

2. The semiconductor device according to claim 1,

Wherein the n memory circuits and the p memory circuits each include two of the second transistors and one capacitor.

3. The semiconductor device according to claim 2,

Wherein both of the second transistors have a region overlapping the capacitor.

4. The semiconductor device according to claim 1 or 2,

Wherein the second transistor is a vertical channel transistor.

5. The semiconductor device according to claim 1,

Wherein the first operation is an operation accompanied by power gating,

And the second job is a job accompanied by interrupt processing.