CN119894069A - Multi-capacitance grid structure, preparation method and application thereof - Google Patents
Multi-capacitance grid structure, preparation method and application thereof Download PDFInfo
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Abstract
本申请提出了多电容栅极结构，依次包括第一栅极介质层、第一金属层、第二栅极介质层、第二金属层；第二金属层连接电源或电路输出端。本发明在第一金属层上方串联一个电容，在不影响第一金属层直流导通的情况下，使得输入电容降低，从而提升器件的数据传输速率，降低整个器件的寄生电容，提高器件的线性特性；尤其应用于高频金属氧化物半导体场效应晶体管时，由于具有较多的栅极电容结构，对于高电压的抗击穿能力增强，从而提高器件栅极抗浪涌或瞬时击穿特性。
The present application proposes a multi-capacitor gate structure, which includes a first gate dielectric layer, a first metal layer, a second gate dielectric layer, and a second metal layer in sequence; the second metal layer is connected to a power supply or a circuit output terminal. The present invention connects a capacitor in series above the first metal layer, and reduces the input capacitance without affecting the DC conduction of the first metal layer, thereby increasing the data transmission rate of the device, reducing the parasitic capacitance of the entire device, and improving the linear characteristics of the device; especially when applied to high-frequency metal oxide semiconductor field effect transistors, due to having more gate capacitor structures, the ability to resist high voltage breakdown is enhanced, thereby improving the device gate surge resistance or transient breakdown characteristics.
Description
Technical Field
The application belongs to the technical field of semiconductor devices, and particularly relates to a multi-capacitance grid structure and a manufacturing method thereof, and application of the multi-capacitance grid structure in the fields of communication and the like is described.
Background
The semiconductor device with the gate structure, such as a metal oxide field effect transistor, is widely applied to the field of communication, such as 5G radio frequency communication, 6G radio frequency communication, quantum communication and other scenes. These communication scenarios have high requirements on data transmission speed, efficiency, stability, fidelity, etc. However, the parasitic parameters of the grid electrode caused by the process can increase signal transmission delay, so that the data transmission rate is limited, like in a high-speed 5G or even future higher-speed communication scene, the signal transmission rate is reduced, distortion conditions such as waveform distortion and the like can be possibly caused, so that a receiving end is difficult to accurately restore an original signal to influence the communication quality, unstable phenomena such as self-oscillation and the like of a circuit are easily caused, the processing and transmission of normal communication signals are interfered, the error rate is increased, the reliable communication is not facilitated, and finally, unnecessary power loss is caused by the additional parasitic parameters, and the duration time and the like can be shortened for communication equipment (such as a mobile terminal and the like) with strict requirements on power consumption.
Taking a Si-based N-type channel metal oxide field effect transistor (N-MOSFET) as an example, the source region and the drain region are formed by adopting ion implantation and high-temperature annealing, parasitic capacitance is formed by a grid electrode and the source drain due to ion diffusion process and process fluctuation, and linearity of the device is reduced under a high-frequency condition due to an uncertain parasitic capacitance value. By adopting complex process integration and optimization, such as adjusting the photoetching overlapping degree of a grid electrode and a source electrode and a drain electrode, optimizing the doping concentration and dosage of relevant ion implantation, and the like, higher requirements are provided for the working condition of a machine and the mutual coordination of various processes, and more wafer flowing processes are consumed in the process coordination process to determine the optimal conditions, so that more manpower, material resources and time cost are consumed. Even so, it is difficult to directly adopt a core device to form a circuit structure to satisfy the linearity requirement.
Advanced power amplification techniques such as power supply modulation, inverse modulation, or Doherty may be used to improve the linearity and efficiency of the amplifier. However, these techniques are generally considered expensive solutions because they require additional components, such as a power modulator or baseband processor, requiring the addition of dc power or consuming additional area. However, it is undeniable that reducing the parasitic parameters of the core device can fundamentally reduce the linearity challenges, and if the integration and optimization of the existing complex process can be bypassed, the device structure can be directly innovated, which has important significance for the overall optimization effect and time cost control of the device.
Disclosure of Invention
The application provides a multi-capacitance grid structure, which greatly reduces parasitic parameters brought by a grid.
The multi-capacitance grid structure comprises a first grid dielectric layer, a first metal layer, a second grid dielectric layer and a second metal layer in sequence, wherein the second metal layer is connected with a power supply or a circuit output end, and the first metal layer, the second grid dielectric layer and the second metal layer form a capacitor. According to the application, the capacitor is connected in series above the first metal layer, so that the input capacitance is reduced under the condition that the direct current conduction of the first metal layer is not influenced.
The multi-capacitance gate structure is basically suitable for any semiconductor device requiring a gate, including but not limited to silicon-based Metal Oxide Semiconductor (MOSFET), laterally Diffused Metal Oxide Semiconductor (LDMOS), drain-extended metal oxide semiconductor (DEMOS), silicon carbide metal oxide semiconductor (SiC MOSFET), etc. The device has more grid capacitance structures, so that the anti-breakdown capability of high voltage is enhanced, and the anti-surge or instantaneous breakdown characteristic of the grid electrode of the device is improved.
The multi-capacitance gate structure is basically suitable for any application scenario requiring reduction of parasitic parameters of the gate, including but not limited to 5G rf communication, 6G rf communication, quantum communication, etc.
The invention further provides a preparation method of the multi-capacitor gate structure, which at least comprises the step of sequentially forming the first gate dielectric layer, the first metal layer, the second gate dielectric layer and the second metal layer through deposition. The preparation process has good compatibility with the traditional metal oxide semiconductor field effect transistor preparation process, and mass production can be realized by less adjustment of the existing process.
The invention also relates to a high-frequency metal oxide semiconductor field effect transistor which comprises the multi-capacitance grid structure. In a high-frequency state, the second metal layer, the second gate dielectric layer and the first metal layer form a smaller capacitor, and the smaller capacitor is connected in series with the metal oxide semiconductor capacitor, so that the input capacitance is reduced, the data transmission rate of the device is obviously improved, and the adverse effect of the parasitic capacitance of the gate on the linearity of the power amplifier is reduced.
In the embodiment of the invention, in order to balance the contradictory relationship between improving linearity and reducing power efficiency, reasonable capacitance values are constructed, and the areas of the second gate dielectric layer and the second metal layer should be between 0.5 and 1.5 times that of the first metal layer, respectively. In the manufacturing method provided by the embodiment of the invention, the first gate dielectric layer 2, the first metal layer 3 and the second gate dielectric layer 4 are etched by using two photolithography plates so as to meet the area ratio, thereby greatly reducing the manufacturing cost caused by increasing the photolithography plates.
In the embodiment of the present invention, in order to balance the contradictory relationship between improving linearity and reducing power efficiency, a reasonable capacitance value is constructed, and the thickness of the second gate dielectric layer should be between 0.5 and 1.5 times that of the first gate dielectric layer.
The gate dielectric layer of the present invention may be an oxide, nitride or high K insulating dielectric as is known in the art. It can be obtained by chemical vapor deposition, atomic layer deposition, molecular beam epitaxy, etc., and the deposition temperature is generally not higher than 900 ℃.
The invention has the advantages that the direct current conduction mode of the device is not changed, the input capacitance is reduced under the high-frequency state, so that the data transmission rate of the device is improved, the parasitic capacitance is reduced, the linearity of the device is improved, and the anti-surge or instantaneous breakdown characteristic of the grid electrode of the device is improved due to the fact that the device has more grid electrode capacitance structures.
Drawings
Fig. 1 is a schematic cross-sectional structure of a conventional mosfet device;
FIG. 2 is a schematic cross-sectional view of a multi-capacitance gate structure according to an embodiment of the present application;
FIG. 3 is a schematic cross-sectional view of a MOSFET including a multi-capacitance gate structure according to an embodiment of the present application;
FIG. 4 is a small signal schematic diagram of a MOSFET including a multi-capacitance gate structure according to an embodiment of the present application;
FIG. 5 is a flow chart of one of the steps for fabricating a MOSFET according to the present application;
FIG. 6 is a flow chart of one of the steps for fabricating a MOSFET according to the present application;
FIG. 7 is a schematic flow chart of one step of the preparation of the MOSFET according to the present application;
FIG. 8 is a flow chart of one of the steps for fabricating a MOSFET according to the present application;
FIG. 9 is a flow chart of one of the steps for fabricating a MOSFET according to the present application;
FIG. 10 is a flow chart of one of the steps for fabricating a MOSFET according to the present application;
Fig. 11 is a flow chart of one of the steps for fabricating a mosfet according to the present application.
The reference numerals are expressed as:
1. A source electrode; 2, a first grid electrode dielectric layer, 3, a first metal layer, 4, a second grid electrode dielectric layer, 5, a grid electrode side wall, 6, a second metal layer, 7, a drain electrode, 8, a substrate electrode, 9, a source region, 10, a lightly doped drain region, 11, a drain region, 12, a substrate heavily doped region and 13, and a substrate.
Detailed Description
In the description of the present application, it should be understood that the directions or positional relationships indicated by the terms "top", "above", "extended position", "upper surface", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience in describing the present application and simplifying the description, and do not indicate or imply that the apparatus or element to be referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present application.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature.
In the present application, unless explicitly specified and limited otherwise, the terms "through", "connected", and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected, mechanically connected, electrically connected, directly connected, or indirectly connected through an intermediate medium, or may be communication between two elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art according to the specific circumstances.
The preferred embodiments of the present invention will be described below with reference to the accompanying drawings, it being understood that the preferred embodiments described herein are for illustration and explanation of the present invention only, and are not intended to limit the present invention.
A Power Amplifier (PA) is one of the most critical rf chips, and is considered to be one of the most critical constituent modules in a wireless transceiver, and its performance generally determines the linearity and energy efficiency of the overall system formed by the various rf chips of the entire wireless transmitter. In order to achieve high data rates, some high order complex modulation schemes, such as Quadrature Amplitude Modulation (QAM), are employed to improve the high power peak-to-average (PAPR) and wideband of the power amplifier. These complex modulation schemes used in these standards require a high degree of linear amplification to preserve signal integrity. Furthermore, the power amplifier must operate in a power back-off state to accommodate the high signal peak-to-average power ratio.
The CMOS process has the advantages of high integration level, low cost, low leakage current, good heat conductivity, high design flexibility and the like, and is widely applied to various radio frequency chip power amplifiers. An Si-based N-type channel metal oxide field effect transistor (N-MOSFET) is a core device constructed by a CMOS process, and because a source region and a drain region are formed by adopting ion implantation and high-temperature annealing, parasitic capacitance is formed by a gate and the source and the drain due to ion diffusion process and process fluctuation, and linearity of the device is reduced under a high-frequency condition due to an uncertain parasitic capacitance value. By adopting complex process integration and optimization, such as adjusting the photoetching overlapping degree of a grid electrode and a source electrode and a drain electrode, the doping concentration and the dosage of relevant ion implantation and the like, higher requirements are provided for the working condition of a machine and the mutual coordination of various processes, and more wafer flowing processes are consumed in the process coordination process to determine the optimal conditions, so that more manpower, material resources and time cost are consumed. Even so, it is difficult to directly adopt a core device to form a circuit structure to satisfy the linearity requirement.
Advanced power amplification techniques such as power supply modulation, inverse modulation, or Doherty may be used to improve the linearity and efficiency of the amplifier. However, these techniques are generally considered expensive solutions because they require additional components, such as a power modulator or baseband processor, requiring the addition of dc power or consuming additional area.
However, it is undeniable that reducing the parasitic parameters of the core device can fundamentally reduce the linearity challenges, and if the integration and optimization of the existing complex process can be bypassed, the device structure can be directly innovated, which has important significance for the overall optimization effect and time cost control of the device.
The invention aims to provide a multi-capacitance grid structure which can be suitable for a Si-based MOSFET and sequentially comprises a first grid dielectric layer 2, a first metal layer 3, a second grid dielectric layer 4 and a second metal layer 6, wherein the second metal layer 6 is connected with a power supply or a circuit output end, and the first metal layer 3, the second grid dielectric layer 4 and the second metal layer 6 form a capacitor (hereinafter referred to as an additional capacitor). As shown in fig. 4, the capacitor is connected in series with the native mos capacitor to form a multi-capacitor gate structure. Under the condition of not influencing the direct current conduction of the first metal layer 3, the device is connected in series with the original metal oxide semiconductor capacitor in a high-frequency state, so that the total input capacitance is reduced, the data transmission rate of the device is improved, the parasitic capacitance of the whole device is reduced, and the linear characteristic of the device is improved.
According to the principle shown in fig. 4, the smaller the additional capacitance is, the smaller the parasitic capacitance formed after the parasitic capacitance is connected in series with the original capacitance is, and the linearity characteristic is effectively improved. In some application scenarios, for example, the gate of the power amplifier is too small, the amplification efficiency of the device will be affected, and in general, the amplification efficiency and the linearity of the power amplifier will be effectively ensured when the additional capacitance is in the range of 0.5-1.5 times that of the original capacitance.
The size of the additional capacitance can be regulated by a person skilled in the art by setting the thickness, area, dielectric constant, etc. of the second gate dielectric layer 4. Generally, the larger the area, the smaller the thickness, the higher the dielectric constant, and the larger the additional capacitance.
Or a person skilled in the art may determine the parameters of the second gate dielectric layer 4 according to the following formula.
C=
R is the relative dielectric constant, k is the electrostatic force constant, S is the facing area of the two plates, and d is the distance between the two plates.
Referring to the gate structure shown in fig. 3, the substrate 13 is made of silicon, but may also be made of silicon carbide, silicon germanium, a multi-element semiconductor material composed of III-V elements, silicon On Insulator (SOI), or Germanium On Insulator (GOI). Wherein the III-V element comprises a multi-component semiconductor material comprising InP, gaAs, inAs, inSb, inGaAs or InGaAsP.
The first gate dielectric layer 2 may be made of silicon oxide, or may be made of a high dielectric constant gate dielectric layer material such as silicon nitride or hafnium oxide. Through testing, this native capacitance was found to be 0.67pF.
And continuously constructing a second gate dielectric layer 4 and a second metal layer 6 on the first metal layer 3, wherein the second gate dielectric layer adopts silicon oxide or high dielectric constant gate dielectric layer materials such as silicon nitride, hafnium oxide and the like. The thickness is 0.5-1 times of the first gate dielectric layer, and the area is the same as that of the first gate dielectric layer. The second metal layer 6 is made of tungsten, has no requirement on thickness and has the same area as the first metal layer. In this embodiment, the additional capacitance used is 1pF. Because the additional capacitance is connected in series with the original capacitance, the obtained total capacitance is 0.4 times of the original capacitance, so that the influence of the original capacitance is reduced. The equivalent structure is applied to the common source amplifier, and the stable feedback network and the input/output network are matched, so that the third-order intermodulation parameters and the power growth efficiency of the obtained power amplifier are improved, and the design contradiction tradition between the three-order intermodulation parameters and the power growth efficiency is broken. And compared with the circuit implementation, the device implementation is easier to implement and has lower cost due to simple process variation in the existing machine.
As shown in fig. 3, according to an aspect of an embodiment of the present application, there is provided an N-MOSFET including:
the semiconductor device comprises a substrate 13, a substrate heavily doped region 12 positioned on the top of the substrate, a substrate electrode 8 positioned above the substrate heavily doped region, a source region 9 and a drain region 11 positioned on the top of the substrate, a source electrode 1 and a drain electrode 7 positioned above the source region, a lightly doped drain region 10 positioned at the expansion position of the source region and the drain region, a first gate dielectric layer 2 positioned above the lightly doped drain region, a first metal layer 3 positioned above the first gate dielectric layer, a second gate dielectric layer 4 positioned above the first metal layer, gate side walls 5 positioned around the first gate, and a second metal layer 6 positioned above the second gate dielectric layer, wherein one end of the second metal layer is connected with the second gate dielectric layer, and the other end of the second metal layer is connected with rear-section interconnection metal.
According to the N-MOSFET provided by the embodiment of the invention, the capacitor similar to the metal oxide semiconductor capacitor is connected in series above the first metal layer, as shown in fig. 4, and is connected in series with the metal oxide semiconductor capacitor in series in a high-frequency state, so that a smaller capacitor is formed, the input capacitor is reduced, the data transmission rate of the device is improved, and secondly, the influence of parasitic capacitance on the whole device is reduced, and the linearity characteristic of the device is improved.
The N-MOSFET includes a substrate 13, where the substrate 13 may be a multi-component semiconductor material composed of silicon, silicon carbide, silicon germanium, III-V elements, silicon On Insulator (SOI), or Germanium On Insulator (GOI). Wherein the III-V element comprises a multi-component semiconductor material comprising InP, gaAs, inAs, inSb, inGaAs or InGaAsP. Specifically, in the embodiment of the present application, the substrate 13 is a P-type silicon substrate.
The area of the second gate dielectric layer is between 0.5 and 1.5 times of the area of the first metal layer. Wherein the area of the second metal layer is between 0.5 and 1.5 times of the area of the first metal layer.
The thickness of the second gate dielectric layer is between 0.5 and 1.5 times of that of the first gate dielectric layer.
In another aspect of the embodiments of the present application, referring to fig. 5 to 11, a manufacturing method is provided, where the parasitic parameters of the gate of the N-MOSFET fabricated by the method are smaller in a radio frequency scenario, so that the linearity of a circuit formed by devices is improved. In addition, the device constructed by the preparation process has a higher grid capacitance structure, so that the breakdown resistance of the device to high voltage is enhanced, and the surge resistance or instantaneous breakdown characteristic of the grid of the device is improved; finally, the preparation process has good compatibility with the traditional metal oxide semiconductor field effect transistor preparation process, and mass production can be realized basically without specially adjusting the existing process. If not specifically described, the processes of ion implantation, film deposition, etching, photolithography, thermal oxidation, high temperature annealing, and the like in the present application may all be conventional processes, and will not be described herein.
Referring to fig. 5 to 11, the manufacturing method includes:
Step S101, a first gate dielectric layer 2 is formed on a substrate 13, see fig. 5. Wherein, a thermal oxidation process can be adopted to form a first gate dielectric layer 2 on the P-type substrate 13, and the gate thickness is 10-120A.
Step S201, a first metal layer 3 is obtained through thin film deposition and growth on the first gate dielectric layer 2. See fig. 6. Wherein the thickness of the first metal layer is 50-600A.
Step S301, a second gate dielectric layer 4 is obtained by thin film deposition growth on top of the first metal layer 3. See fig. 7.
Step S401 is to etch the first gate dielectric layer 2, the first metal layer 3 and the second gate dielectric layer 4 simultaneously. See fig. 8.
Step S501 is to etch the second gate dielectric layer 4, see fig. 9.
In step S601, a lightly doped drain region 10 is formed near the first gate electrode 3 by ion implantation, and a gate sidewall 5 is formed by thermal oxidation, see fig. 10.
Step S701, forming a source region, a drain region and a substrate heavily doped region by ion implantation, see fig. 11. Specifically, the source region and the drain region are N-type ion implantation, and the heavily doped region of the substrate is P-type ion implantation.
Step S801 forms the second metal layer 6, the source electrode 1, the drain electrode 7 and the substrate electrode 8 by dry etching and thin film deposition, see fig. 3. One end of the second metal layer is connected with the second grid electrode, and the other end of the second metal layer is connected with the rear-section interconnection metal.
The above description is not intended to limit the application to the particular embodiments disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the application. The foregoing is merely a preferred embodiment of the present application, and it should be noted that it will be apparent to those skilled in the art that modifications and variations can be made without departing from the technical principles of the present application, and these modifications and variations should also be regarded as the scope of the application.
Claims (10)
1. A multi-capacitor grid structure is characterized by sequentially comprising a first grid dielectric layer, a first metal layer, a second grid dielectric layer and a second metal layer, wherein the second metal layer is connected with a power supply or a circuit output end.
2. The multi-capacitor gate structure of claim 1, wherein the first metal layer, the second gate dielectric layer, and the second metal layer form a capacitor.
3. The method of claim 1, wherein the first gate dielectric layer, the first metal layer, the second gate dielectric layer, and the second metal layer are sequentially formed by deposition.
4. A method of preparing according to claim 3, wherein the deposition method is chemical vapor deposition, atomic layer deposition or molecular beam epitaxy.
5. The method of claim 3, wherein the second gate dielectric layer is an oxide, nitride or high-K dielectric.
6. The method of claim 3, wherein the second gate dielectric layer is deposited at a temperature not exceeding 900 degrees celsius.
7. A semiconductor device characterized in that the gate of the device has the multi-capacitance gate structure of claim 1.
8. Use of the multi-capacitance gate structure of claim 1 as a gate of a high frequency mosfet.
9. The method of claim 4, wherein the second gate dielectric layer and the second metal layer are each between 0.5 and 1.5 times the area of the first metal layer.
10. The use of claim 4 wherein the thickness of the second gate dielectric layer should be between 0.5 and 1.5 times the thickness of the first gate dielectric layer.
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| US6210999B1 (en) * | 1998-12-04 | 2001-04-03 | Advanced Micro Devices, Inc. | Method and test structure for low-temperature integration of high dielectric constant gate dielectrics into self-aligned semiconductor devices |
| US20090302317A1 (en) * | 2006-09-20 | 2009-12-10 | Advantest Corporation | Switching device and testing apparatus |
| CN107658321A (en) * | 2016-07-25 | 2018-02-02 | 南京大学 | Double device photodetector unit, detector and its methods based on composite dielectric gate |
| CN117525098A (en) * | 2023-10-23 | 2024-02-06 | 南京大学 | Composite dielectric grating photosensitive detector based on high-resolution night vision and its working method |
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- 2025-01-20 CN CN202510086473.6A patent/CN119894069A/en active Pending
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH118362A (en) * | 1997-06-18 | 1999-01-12 | Sanyo Electric Co Ltd | Dielectric element, dielectric memory, manufacture of dielectric memory, and method for actuating ferroelectric memory |
| US6210999B1 (en) * | 1998-12-04 | 2001-04-03 | Advanced Micro Devices, Inc. | Method and test structure for low-temperature integration of high dielectric constant gate dielectrics into self-aligned semiconductor devices |
| US20090302317A1 (en) * | 2006-09-20 | 2009-12-10 | Advantest Corporation | Switching device and testing apparatus |
| CN107658321A (en) * | 2016-07-25 | 2018-02-02 | 南京大学 | Double device photodetector unit, detector and its methods based on composite dielectric gate |
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