CN119892567B

CN119892567B - A high-bitwidth Ethernet GFP scrambling method and system

Info

Publication number: CN119892567B
Application number: CN202510016726.2A
Authority: CN
Inventors: 李路; 桂可; 刘力; 许雷; 陈俊俊
Original assignee: Fiberhome Telecommunication Technologies Co Ltd; Wuhan Fisilink Microelectronics Technology Co Ltd
Current assignee: Fiberhome Telecommunication Technologies Co Ltd; Wuhan Fisilink Microelectronics Technology Co Ltd
Priority date: 2025-01-06
Filing date: 2025-01-06
Publication date: 2025-10-14
Anticipated expiration: 2045-01-06
Also published as: CN119892567A

Abstract

The application discloses a high-bit-width Ethernet gfp scrambling method and a system, which relate to the technical field of optical communication, wherein the high-bit-width Ethernet gfp scrambling method comprises the steps of moving data needing scrambling in one beat to high positions, completely replacing invalid data which does not need scrambling when moving to low positions with 0, and recording the moving byte quantity; the method comprises the steps of converting single bit scrambling into parallel scrambling with the current bit width, carrying out exclusive OR operation on the data after shifting and a parallel polynomial to obtain scrambled data and new scrambling state data, taking the remainder of the scrambling state shifting condition number based on the byte number of invalid data, determining a shifting compensation value to reversely shift the new scrambling state data to obtain the scrambling state data after compensation, reversely shifting the scrambled data based on the recorded moving byte number to carry out shifting recovery. The application can make gfp scrambling with high bit width feasible in the implementation of an asic circuit, and can save resources and improve time sequence.

Description

High bit width Ethernet gfp scrambling method and system

Technical Field

The application relates to the technical field of optical communication, in particular to a high bit width Ethernet gfp scrambling method and a system.

Background

With the continuous development of technology, the current demand for data bandwidth is higher and higher, and in this background, 5G has been generated, so that in order to meet the transmission of characteristics of high capacity, low delay and the like of 5G signals, networks tend to be fused and interworking.

The trend of the PTN (Packet Transport Network ) and OTN (Optical Transport Network, optical transport network) devices has been to integrate, in a high-speed pots (Packet over Optical Network, packet switched on optical network) chip, ethernet traffic is mapped into the OTN frame structure by GFP (GENERIC FRAMING Procedure ).

With the increase of capacity, in order to reduce the system clock of the chip, the processing bit width of data is increased. With the continuous increase of system demands, the transmission bandwidth requirements from the initial 1G, 10G, 100G and 400G to the current 1.6T are reapplied. The bit width of the data processing is also from 8b, 64b, 512b to 2024b. Scrambling is a key core technology in the GFP processing process, a plurality of parallel multi-bit processing methods exist at present, but because Eth (Ethernet) data are bubble-bearing, the mapping from Eth to GFP is carried out, the rates of two sides are different, so that the rate adjustment is carried out, IPGs (Inter-PACKET GAP, inter-packet intervals) are inserted between Eth packets to adjust the rate, the size of the inserted IPGs (i.e. bubbles) is variable, and the frame length is variable, and the range is 64-9600B. The number of active bytes in a beat is not fixed and the position is not fixed. Therefore, the data amount of scrambling in one beat is different, the parallel scrambling polynomials with different bit widths are needed for scrambling the different data amounts, when the data bit width is lower, the different data amounts can be scrambled by a selected method, and when the bit width is wider, the method can cause the defects of consuming logic resources, poor time sequence and the like.

Disclosure of Invention

The application provides a high-bit-width Ethernet gfp scrambling method and a system, which can enable the high-bit-width gfp scrambling to be feasible on an asic circuit, and can save resources and time sequences.

In a first aspect, an embodiment of the present application provides a high bandwidth ethernet gfp scrambling method, where the high bandwidth ethernet gfp scrambling method includes:

Moving data to be scrambled in one beat to high order, replacing all invalid data which is not required to be scrambled and is moved to low order by 0, and recording the moving byte quantity;

Converting the single bit scrambling to the parallel scrambling of the current bit width, and performing exclusive-or operation on the shifted data and the parallel polynomial to obtain scrambled data and new scrambling state data;

Determining a shift compensation value based on the surplus of the shift situation number of the scrambling state based on the byte number of the invalid data so as to reversely shift the new scrambling state data to obtain the scrambling state data after compensation;

The scrambled data is inversely shifted based on the recorded shifted byte amount to perform shift recovery.

With reference to the first aspect, in one embodiment, the invalid data that does not need to be scrambled is determined according to a sop and eop identification of the data packet.

In combination with the first aspect, in an embodiment, the invalid data that does not need to be scrambled includes bubble data and a core header of a gfp frame.

In combination with the first aspect, in one embodiment, when there are multiple gfp frames within a beat, the bubble data at the low level is moved first, and then the bubble data at the high level is moved.

With reference to the first aspect, in one implementation manner, the performing an exclusive-or operation on the shifted data and the parallel polynomial to obtain scrambled data includes:

the shifted data are subjected to two-stage serial data exclusive OR to obtain first data;

And carrying out exclusive OR on the first data and a first scrambling coefficient of the parallel polynomial based on bit width cyclic expansion to obtain scrambled data.

With reference to the first aspect, in one embodiment, the parallel polynomial is y=x ⁴³ +1.

In combination with the first aspect, in one embodiment, the shift compensation value cm is calculated according to the formula cm= (wd/8-sz)% 43, where wd is the data bit width and sz is the number of bytes that need to be scrambled in one beat.

In a second aspect, an embodiment of the present application provides an high bandwidth ethernet gfp scrambling system, the high bandwidth ethernet gfp scrambling system comprising:

A shift unit for shifting data requiring scrambling in one beat to high order, replacing all invalid data requiring no scrambling to low order by 0, and recording the amount of bytes shifted;

The scrambling unit is used for converting the single bit scrambling into parallel scrambling with the current bit width, and performing exclusive OR operation on the shifted data and the parallel polynomial to obtain scrambled data and new scrambling state data;

a compensation unit which takes the remainder of the number of scrambling state shift cases based on the number of bytes of the invalid data, determines a shift compensation value, and reversely shifts the new scrambling state data to obtain the scrambling state data after compensation;

and a shift recovery unit that inversely shifts the scrambled data based on the recorded shifted byte amount to perform shift recovery.

With reference to the second aspect, in one embodiment, the shifting unit determines invalid data that does not need scrambling according to sop and eop identification of the data packet.

With reference to the second aspect, in one embodiment, the invalid data that does not need to be scrambled includes bubble data and a core header of a gfp frame;

When there are multiple gfp frames in one beat, the shift unit moves the bubble data at the low level first and then moves the bubble data at the high level.

The technical scheme provided by the embodiment of the application has the beneficial effects that at least:

The application discloses a high-bit-width Ethernet gfp scrambling method, which comprises the steps of moving data to be scrambled in one beat to high, completely replacing invalid data which is not required to be scrambled and is moved to low by 0, recording the moving byte quantity, converting single-bit scrambling into parallel scrambling of the current bit width, carrying out exclusive OR operation on the data after being shifted and a parallel polynomial to obtain scrambled data and new scrambling state data, taking the remainder of the scrambling state shift condition number based on the byte quantity of the invalid data, determining a shift compensation value, carrying out reverse shift on the new scrambling state data to obtain compensated scrambling state data, and carrying out reverse shift on the scrambled data based on the recorded moving byte quantity to carry out shift recovery.

The application uses general bit width parallel algorithm to scramble, then compensates according to invalid byte number, and optimizes the compensation value to realize one-beat compensation, reduce the constraint to upstream module, and provide time sequence to make gfp scrambling of high bit width feasible in the implementation of the asic circuit. And saves resources and timing. The method has a general line, so that the method is more widely applicable to a scene of scrambling and descrambling data with bubbles.

Drawings

FIG. 1 is a serial scrambler of an implementation of the present application;

FIG. 2 is a flow chart of an embodiment of a high bandwidth Ethernet gfp scrambling method according to the present application;

FIG. 3 is a pre-scrambling shift scenario diagram in the present application;

FIG. 4 is a pre-scrambling shift scenario diagram in the present application;

FIG. 5 is a parallel processing flow chart of the present application;

FIG. 6 is a schematic diagram of a data portion of a scrambling coefficient of a 512bit parallel scrambler of the present application;

FIG. 7 is a schematic diagram of a 43bit state portion of a scrambling coefficient of a 512bit parallel scrambler in accordance with the present application;

fig. 8 is a block diagram illustrating an embodiment of an ethernet gfp scrambling system.

Detailed Description

In order that those skilled in the art will better understand the present application, a technical solution in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

In order to solve the problems in the prior art, the application provides a compensation-based general gfp scrambler parallel scrambling for bubble-bearing data. Therefore, the logic resource consumption is reduced, the chip power consumption is reduced, the chip cost and the risk of chip throwing are reduced, and the system equipment competitiveness is enhanced.

First, it should be noted that the derivation process of the compensation type generic gfp scrambler is as follows:

As shown in fig. 1, according to the g.7041 protocol, the scrambling procedure of gfp is y=x ⁴³ +1 auto-sync scrambling, where X is an input value or a current state and Y is an output value or a next state. gfp's serial scrambler:

Y(t)=X(t)^Y(t-43);

state update of scrambler:

{Y(t-43),Y(t-42),Y(t-41),...,Y(t-2),Y(t-1)}={Y(t-42),Y(t-41),...,Y(t-1),Y(t)};

when X (t) is 0:

Y(t)=X(t)^Y(t-43)=Y(t-43);

state update of scrambler:

{Y(t-43),Y(t-42),Y(t-41),...,Y(t-2),Y(t-1)}={Y(t-42),Y(t-41),...,Y(t-1),Y(t-43)};

Corresponding to the state cycle of the scrambler being shifted one bit to the left. If the state of the scrambler is circularly right shifted by one bit, this is equivalent to not scrambling 0.

If N consecutive 0s are scrambled, this corresponds to a state cycle of the scrambler being shifted left by N bits. If the state of the scrambler is circularly shifted to the right by N bits, the original state is restored as well.

If the bus bit width is wdbit, the sz bytes in one beat of data need to be scrambled, in order to use the same scrambler, the data of the current beat which does not need to be scrambled can be replaced by 0, and the valid data of the sz bytes is moved to the top of the whole beat, and the tail is 0. Scrambling is performed on the whole-beat wdbit data, and the front sz bytes after scrambling are the valid data after scrambling. Then the scrambler is circularly shifted to the right by (wd/8-sz)% 43 bits, so that the state after scrambling only sz bytes is obtained. The next beat of data is then scrambled using the same method.

The compensation optimization method comprises the following steps:

When N is larger, the situation that cyclic shift is needed is more, the cyclic shift is difficult to realize on a circuit in one beat, the common method is realized by adopting a multi-stage pipelining mode, and the subsequent data cannot participate in the scrambler in the multi-stage processing process. This introduces two problems:

1. The bandwidth utilization rate is reduced;

2. if the serialization channel processing is performed, the upstream module is limited, and the same channel cannot be continuously shot;

Based on the above, when the input x (t) is 0, the value of the scrambler's stat43bit does not change, but the sliding occurs, stat [42:0] < = { stat [41:0], stat [42] }. Then if all the data to be scrambled within a beat is moved to the top, then the invalid data is replaced with all 0 s, all the whole beat of data is scrambled, then the invalid 0 s are compensated, the scrambling polynomials are unified and realizable.

In addition, the scrambling states { Y (t-43), Y (t-42), Y (t-41),. The use of the scrambling states of Y (t-2), Y (t-1) } are only 43 cases in the shifting process, so that the data quantity to be compensated can be converted into 43 through (wd/8-sz)% 43, and thus only 43 cases need to be processed in one beat, and then the requirement can be met in one beat in time sequence.

For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the embodiments of the present application will be described in further detail with reference to the accompanying drawings.

In a first aspect, an embodiment of the present application provides a high bandwidth ethernet gfp scrambling method.

In one embodiment, referring to fig. 2, fig. 2 is a flow chart illustrating an embodiment of the gfp scrambling method of the present application. As shown in fig. 2, the high bit width ethernet gfp scrambling method includes:

s1, moving data which need to be scrambled in one beat to high positions, completely replacing invalid data which do not need to be scrambled when moving to low positions with 0, and recording the moving byte quantity;

It should be noted that, referring to fig. 3, the left side of the picture is a mac frame and the right side is a gfp frame;

for gfp frames:

PLI+cHEC is core header

Type+tHEC is TYPE HEADER

Gfp externsion header is an extension head, which is not generally used;

Gfp payload, namely a payload field, and a mac message is filled in the payload field;

the whole gfp frame is only unscrambled by the core header and is scrambled by the other parts.

When the data bit width comes to 512b, 2028b, etc., there may be multiple gfp frames in one beat of the bus structure of the ethernet, and more valid bytes need to be scrambled in one beat, the conventional traversal method cannot meet the requirement of circuit design.

Taking 512b as an example, 3 kinds of scenes in fig. 4 may occur, where the shift processing needs to be performed on the scenes 1-3, and the data needing scrambling is shifted to high order, and the invalid data in low order is replaced with 0.

Referring to fig. 4, in this embodiment, invalid data that does not need to be scrambled is determined mainly according to the sop and eop identifiers of the data packets, where the invalid data that does not need to be scrambled includes bubble data and core header of gfp frame.

The following describes the processing mode of scenes 1-3:

scene 1. Eop (e.g., eop _a) of the previous frame and the sop of the next frame (e.g., sop_a) are in the same beat, invalid data between eop of the previous frame and the sop of the next frame needs to be moved to the data tail, and the tail invalid data is replaced with 0.

Since the position of each sop and eop is known at the time of shifting, if the positions of eop _b and sop_b are changed by shifting the invalid byte between eop _a and sop_a first, the marks eop _b and sop_b are also changed, increasing the design complexity, and the positions of eop _a and sop_a are not changed by shifting the invalid byte between eop _b and sop_b first, so that the position information does not need to be recalculated. Therefore, in this embodiment, the invalid byte between eop _b and sop_b is shifted first, then the invalid byte between eop _a and sop_a is shifted, and the shifted byte amount is recorded;

Scene 2, namely, only a sop exists in one beat, then the invalid data is in front of the sop, the invalid bytes in front of the sop are moved to the tail of the data, the tail invalid data is replaced by 0, and the moving byte quantity is recorded;

Scene 3-there are only eop in a beat, eop preceded by the relevant bytes of the core header, which typically has 4 bytes, and the number of bytes the current beat core header occupies is determined in combination with the last beat. In this embodiment, the core header is used as the data that does not need scrambling, and the core header is also used as the invalid data to be moved to the tail of the data, the tail invalid data is replaced by 0, and the moving byte size is recorded.

In particular, three different circuits may be designed for three scenes, each for identifying and processing its corresponding scene, so that the relevant scene may be shifted by the cooperation of the three circuits to move invalid data to a lower position. It can be appreciated that, if there are other scenes that need to be shifted, the above manner may also be adopted, which is not described herein.

S2, converting the single bit scrambling into parallel scrambling with the current bit width, and performing exclusive OR operation on the shifted data and a parallel polynomial to obtain scrambled data and new scrambling state data;

Taking 512 bits as an example, the whole calculation process firstly converts single bit winding into 512bit parallel winding through an algorithm as shown in fig. 5. And performing exclusive OR operation on the shifted data and the parallel polynomial to obtain scrambled data and scrambled state data. The data scrambling includes that a data part is firstly subjected to exclusive or by two pipelining (d2_r and d2_l) to obtain first data d3_reg, and then is subjected to exclusive or with a first scrambling coefficient d_s3 based on bit width cyclic extension to obtain scrambled data. Obtaining new_st43, wherein the same data part is xored by two stages of pipelining (stat2_r and stat2_l) to obtain second data stat3_reg, and is xored with a second scrambling coefficient stat_s3 to obtain new scrambling state data new_st43.

When the one-beat processing logic is large, the logic needs to be developed separately to perform the multi-beat processing, which is called a pipeline design.

The structure of the scrambler shown in fig. 1, the input data is xored with the scrambling coefficients to obtain scrambled data and new scrambling coefficients, which are single bit; if a plurality of bits are processed and scrambling is performed at the same time, for example, one beat of 512 bits is processed, a serial scrambler is designed into a parallel scrambler through an algorithm;

Specifically, the st_43 is processed by an algorithm to obtain d_s3, for example, d_s3 is 512 bits, and exclusive-or processing is performed on the d_s3 and 512 bits of data according to bits, which can be seen in fig. 6, and the last column in fig. 6 is d_s3.

FIG. 6 is a data portion of a scrambling coefficient of a 512bit parallel scrambler, where s 42-s 0 represent a scrambling state coefficient of a scrambler 43bit, d 511-d 0 represent 512 data to be scrambled, high priority, and data [511] to data [0] represent scrambled data.

The process of pushing the parallel scrambling coefficients is based on the principle of serial scrambler Y (t) =x (t)/(Y) (t-43),

1 St data scrambling:

data[511]=d511+s42;

new Y (t-43) =s41,..y (t) =d511+s42;

data scrambling 2:

data[510]=d510+s41,

New Y (t-43) =s40..y (t) =d510+s41

Similarly, data scrambling 43:

data[469]=d469+s0;

New Y (t-43) =d511+s42, & Y (t) =d469+s0

Data scrambling 44:

data[468]=d468+d511+s42;

New Y (t-43) =d510+s41, once again, Y (t) =d468+ d511+s42.

The scrambling of the remaining data also follows the above manner, and this embodiment is not described here again.

The st_43 is processed by an algorithm to obtain a st_s3, the st_s3 is 43bit, and the st is exclusive-or to obtain a new scrambling coefficient. For specific reference, see fig. 7, the last column in fig. 7 is stat_s3.

FIG. 7 is a 43bit state portion of a scrambling coefficient of a 512bit parallel scrambler, and s [42] s [0] should be the last 43 data after this scrambling, namely, scrambled data [42] data [0], according to the rule of the scrambling serial scrambler.

S3, taking the remainder of the number of the scrambling state shift conditions based on the number of bytes of the invalid data, and determining a shift compensation value to reversely shift the new scrambling state data to obtain the scrambling state data after compensation;

it should be noted that the movement to the high position in step S1 refers to a left shift (upward shift in fig. 3), and the reverse shift in step S3 refers to a right shift.

It will be appreciated that through the above steps, the number of invalid bytes M (i.e., wd/8-sz) is known, an optimized compensation value is obtained through cm= (wd/8-sz)% 43, the new_st43 is circularly shifted right through the optimized compensation value to obtain the compensated new_st43, and then the new_st43 is stored according to channels to realize serialization.

S4, reversely shifting the scrambled data based on the recorded moving byte quantity so as to carry out shift recovery.

Taking the above scenario as an example, the processing flow of the resume after winding and the data shift before winding are just opposite, and the processing sequence is scenario 3, scenario 2 and scenario 1 in sequence:

Scene 3, directly shifting the data to the right by the same byte according to the number of bytes marked with the left shift at the time;

Scene 2, right shifting the data by the same byte according to the number of bytes marked with the left shift at the time;

Scene 1, move first to recover the invalid byte between eop _a and sop_a, then move the invalid byte between eop _b and sop_b.

Thus, high bit width Ethernet gfp scrambling is achieved.

In summary, the high-bit-width Ethernet gfp scrambling method of the application moves the data to be scrambled in one beat to high position, replaces the invalid data which is not required to be scrambled in low position with 0, records the moving byte quantity, converts the single-bit scrambling into the parallel scrambling of the current bit width, carries out exclusive OR operation on the data after the shifting and the parallel polynomial to obtain the scrambled data and the new scrambled state data, and determines a shift compensation value based on the residual of the byte number of the invalid data on the basis of the number of the shifting conditions of the scrambled state, so as to reversely shift the new scrambled state data to obtain the scrambled state data after compensation, and reversely shifts the scrambled data based on the recorded moving byte quantity to carry out shift recovery.

In a second aspect, the embodiment of the application further provides an ethernet gfp scrambling system.

In one embodiment, referring to fig. 8, fig. 8 is a block diagram illustrating an embodiment of an ethernet gfp scrambling system. As shown in fig. 8, the high bit width ethernet gfp scrambling system includes:

Further, in an embodiment, the shift unit determines invalid data that does not need scrambling according to sop and eop identifiers of the data packets.

Further, in one embodiment, the invalid data that does not need to be scrambled includes bubble data and core header of gfp frame;

Further, in an embodiment, the performing an exclusive-or operation on the shifted data and the parallel polynomial to obtain scrambled data includes:

Further, in an embodiment, the parallel polynomial is y=x ⁴³ +1, and the compensation unit calculates the shift compensation value cm according to the formula cm= (wd/8-sz)% 43, where wd is the data bit width and sz is the number of bytes to be scrambled for one beat.

From the above description of the embodiments, it will be clear to those skilled in the art that the above-described embodiment method may be implemented by means of software plus a necessary general hardware platform, but of course may also be implemented by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art in the form of a software product stored in a storage medium (e.g. ROM/RAM, magnetic disk, optical disk) as described above, comprising several instructions for causing a terminal device to perform the method according to the embodiments of the present application.

The terms "comprising" and "having" and any variations thereof in the description and claims of the application and in the foregoing drawings are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus. The terms "first," "second," and "third," etc. are used for distinguishing between different objects and not necessarily for describing a sequential or chronological order, and are not limited to the fact that "first," "second," and "third" are not identical.

In describing embodiments of the present application, "exemplary," "such as," or "for example," etc., are used to indicate by way of example, illustration, or description. Any embodiment or design described herein as "exemplary," "such as" or "for example" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary," "such as" or "for example," etc., is intended to present related concepts in a concrete fashion.

In the description of the embodiment of the present application, "/" means or, for example, a/B may mean a or B, and "and/or" in the text is merely an association relationship describing an association object, means that three relationships may exist, for example, a and/or B, three cases where a exists alone, a and B exist together, and B exists alone, and further, in the description of the embodiment of the present application, "a plurality" means two or more.

In some of the processes described in the embodiments of the present application, a plurality of operations or steps occurring in a particular order are included, but it should be understood that the operations or steps may be performed out of the order in which they occur in the embodiments of the present application or in parallel, the sequence numbers of the operations merely serve to distinguish between the various operations, and the sequence numbers themselves do not represent any order of execution. In addition, the processes may include more or fewer operations, and the operations or steps may be performed in sequence or in parallel, and the operations or steps may be combined.

The foregoing description is only of the preferred embodiments of the present application, and is not intended to limit the scope of the application, but rather is intended to cover any equivalents of the structures or equivalent processes disclosed herein or in the alternative, which may be employed directly or indirectly in other related arts.

Claims

1. A high-bitwidth Ethernet GFP scrambling method, characterized in that the high-bitwidth Ethernet GFP scrambling method comprises:

Move the data that needs to be scrambled within a beat to the high bit, replace all the invalid data that does not need to be scrambled and is moved to the low bit with 0, and record the number of bytes moved;

Convert the single-bit scrambling into parallel scrambling of the current bit width, and perform XOR operation on the shifted data and the parallel polynomial to obtain the scrambled data and the new scrambled state data;

Taking the modulus of the number of scrambling state shift situations based on the number of bytes of invalid data, determining a shift compensation value, and performing a reverse shift on the new scrambling state data to obtain compensated scrambling state data;

The scrambled data is shifted inversely based on the recorded shifted byte amount to perform shift recovery.

2. The high-bitwidth Ethernet GFP scrambling method according to claim 1, wherein:

Invalid data that does not need to be scrambled is determined based on the sop and eop identifiers of the data packet.

3. The high-bitwidth Ethernet GFP scrambling method according to claim 1 or 2, wherein:

The invalid data that does not need to be scrambled includes bubble data and a core header of a gfp frame.

4. The high-bitwidth Ethernet GFP scrambling method according to claim 3, wherein:

When there are multiple gfp frames in one shot, the bubble data at the lower position is moved first, and then the bubble data at the higher position is moved.

5. The high-bitwidth Ethernet GFP scrambling method according to claim 1, wherein the step of performing an XOR operation on the shifted data and the parallel polynomial to obtain the scrambled data comprises:

The shifted data is XORed in two stages to obtain the first data;

Performing an exclusive OR operation on the first data and a first scrambling coefficient of a parallel polynomial based on bit-width cyclic extension to obtain scrambled data.

6. The high-bitwidth Ethernet GFP scrambling method according to claim 1 or 5, wherein:

The parallel polynomial is Y=X ⁴³ +1.

7. The high-bitwidth Ethernet GFP scrambling method according to claim 6, wherein:

The shift compensation value cm is calculated according to the formula: cm=(wd/8-sz)%43, where wd is the data bit width and sz is the number of bytes that need to be scrambled in one beat.

8. A high-bitwidth Ethernet GFP scrambling system, characterized in that the high-bitwidth Ethernet GFP scrambling system comprises:

A shift unit is used to move the data that needs to be scrambled within a beat to the high bit, replace all invalid data that does not need to be scrambled and is moved to the low bit with 0, and record the number of bytes moved;

The scrambling unit is used to convert the single-bit scrambling into parallel scrambling of the current bit width, and perform an XOR operation on the shifted data and the parallel polynomial to obtain the scrambled data and the new scrambled state data;

a compensation unit, which determines a shift compensation value by taking the modulus of the number of scrambling state shift situations based on the number of bytes of invalid data, so as to reversely shift the new scrambling state data to obtain compensated scrambling state data;

A shift recovery unit reversely shifts the scrambled data based on the recorded shifted byte amount to perform shift recovery.

9. The high-bitwidth Ethernet GFP scrambling system according to claim 8, wherein:

The shift unit determines invalid data that does not need to be scrambled according to the sop and eop identifiers of the data packet.

10. The high-bitwidth Ethernet GFP scrambling system according to claim 8, wherein:

The invalid data that does not need to be scrambled includes bubble data and the core header of the gfp frame;

When there are multiple gfp frames in one shot, the shift unit first shifts the bubble data at a lower position and then shifts the bubble data at a higher position.