CN119718208A - Backup method for SSD user data in internal cache - Google Patents
Backup method for SSD user data in internal cache Download PDFInfo
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Abstract
本发明提供一种SSD用户数据在内部缓存中的备份方法，能保证SSD内部开启数据备份功能后，顺序写性能均值及性能一致性均不受影响。该方法需在SSD内部增加DMA硬件模块。在上位机向SSD发送写命令后，为写命令分配SRAM用户数据缓存单元及关联的DDR用户数据备份缓存单元，在上位机向SSD传输数据完成后，将SRAM用户数据缓存单元中的数据传输到DDR用户数据备份缓存单元，并将SRAM用户数据缓存单元中的数据写入闪存颗粒，数据传输到闪存颗粒数据寄存器后，释放SRAM用户数据缓存单元并更新与其关联的DDR用户数据备份缓存集信息，当数据写入闪存颗粒存储介质后，再释放DDR用户数据备份缓存单元。
The present invention provides a method for backing up SSD user data in an internal cache, which can ensure that after the data backup function is turned on inside the SSD, the sequential write performance mean and performance consistency are not affected. The method needs to add a DMA hardware module inside the SSD. After the host computer sends a write command to the SSD, an SRAM user data cache unit and an associated DDR user data backup cache unit are allocated for the write command. After the host computer completes data transmission to the SSD, the data in the SRAM user data cache unit is transferred to the DDR user data backup cache unit, and the data in the SRAM user data cache unit is written into a flash memory particle. After the data is transferred to the flash memory particle data register, the SRAM user data cache unit is released and the DDR user data backup cache set information associated with it is updated. After the data is written into the flash memory particle storage medium, the DDR user data backup cache unit is released.
Description
Technical Field
The invention relates to the field of flash memory storage control, in particular to a backup method of SSD user data in an internal cache.
Background
The sequential writing performance of the Solid state disk (Solid STATE DRIVE, SSD) product is mainly determined by the DMA (direct memory access) performance from the upper computer to the internal cache of the SSD, the DMA performance from the internal cache of the SSD to the flash granule data register and the flash granule data writing storage medium performance (hereinafter abbreviated as flash granule writing performance), wherein the flash granule writing performance cannot be changed after the flash granule type is determined, and the sequential writing performance can only be improved by optimizing the use medium and the use scheme of the internal cache of the SSD. SSDs typically use DDR (double rate synchronous dynamic random access memory, double Data Rate Synchronous Dynamic Random Access Memory) as their internal system information management medium, while also being able to transfer user data as an internal cache, but this approach suffers from poor sequential write performance because DDR performance is relatively low. To further improve sequential write performance, some mainstream SSD products use higher performance SRAM (Static Random-Access Memory) as an internal buffer to transfer user data. The SRAM buffer capacity configured in the product is typically low, limiting costs, and in order to increase the SRAM buffer utilization, the SRAM buffer is released in advance after data is transferred from the SRAM buffer to the flash granule data register, rather than after the flash granule writes the data to the storage medium. This solution needs to ensure that the flash granule can find the original user data and write it to other locations in the flash granule when the writing of the data to the storage medium fails, and therefore needs to back up the user data, i.e. needs to back up it to the DDR before releasing the SRAM cache. Under the scheme, the sequential write performance is lower than an expected value when the data volume of each backup is too large or too small, and the performance fluctuation is too large when the data volume of each backup is inconsistent. Currently, no mature backup scheme for SSD user data in an internal cache can ensure high performance and high consistency of sequential writing at the same time, so that it is necessary to design and develop a backup scheme for user data in an internal cache with reliable performance.
Disclosure of Invention
The invention aims to provide a backup method for SSD user data in an internal cache, which can improve SSD sequential writing performance and consistency.
The invention aims to achieve the above purpose by the following technical scheme.
A backup method for SSD user data in an internal cache includes the steps of:
S1, an SRAM user data caching unit and a DDR user data backup caching unit execute initialization operation;
s2, the upper computer issues a write command to the SSD, the SSD distributes an SRAM user data buffer unit for the upper computer write command, the upper computer write command successfully acquires the SRAM user data buffer unit, a DMA operation is started, and upper computer user data is transmitted to the SRAM user data buffer unit;
S3, starting DMA operation from the specified quantity of SRAM user data cache unit data to the associated DDR user data backup cache unit, and finishing SSD SRAM user data cache unit backup;
s4, executing flash memory grain writing operation on all SRAM user data caching units;
s5, writing the flash grain data register data into the flash grain storage medium.
Further, step S1 includes:
For a pair of All members perform an initialization operation:
,;
For a pair of All members perform an initialization operation:
,;
For a pair of All members perform an initialization operation:
,;
Will be Put 0, willSetting 0;
Wherein, the array Representing the DDR user data backup cache set number associated with each SRAM user data cache unit, the array index is the SRAM user data cache unit number, the array member is the DDR user data backup cache set number for backing up the current SRAM user data cache unit,The number of the SRAM user data buffer units is represented, and the calculation formula is as follows:
;
representing the SRAM user data buffer capacity, The capacity of a user data cache unit is represented, and the units are Byte;
Array of arrays Representing the state of each SRAM user data cache cell, the array index being the SRAM user data cache cell number, the array member being the state of the SRAM user data cache cell,Representing an idle state of the SRAM user data buffer unit;
Array of arrays Representing the state of each DDR user data backup cache unit, the array index is the DDR user data backup cache unit number, the array member is the state of the DDR user data backup cache unit,Indicating the number of DDR user data backup cache units,Representing the idle state of the DDR user data backup cache unit;
Representing the currently allocatable SRAM user data cache unit number, Representing the number of the SRAM user data cache unit currently waiting for backup.
Further, step S2 includes:
s201, after an upper computer issues a write command to an SSD, the SSD checks whether a current SRAM user data buffer unit is idle, and if so, the next step is performed;
s202, calculating the number of the DDR user data backup cache unit associated with the current SRAM user data cache unit, checking whether the DDR user data backup cache unit is idle, and if so, performing the next step;
S203, updating the states of the SRAM user data caching unit and the DDR user data backup caching unit, associating the SRAM user data caching unit with an upper computer write command, and starting DMA operation from the user data associated with the upper computer write command to the SRAM user data caching unit.
Further, the SSD allocates an SRAM user data buffer unit for the upper computer write command and performs data transmission including:
Inspection of Whether or not the value isIf yes, carrying out the next step, otherwise, suspending the allocation of the SRAM user data buffer unit;
From the following components Obtain number ofDDR user data backup cache set associated with SRAM user data cache unit, useThe DDR user data backup cache unit numbers associated with the SRAM user data cache unit are temporarily recorded, and the method concretely comprises the following steps:
;
Inspection of Whether or not the value isIf yes, carrying out the next step, otherwise, suspending the allocation of the SRAM user data buffer unit;
Will be Updated toWill beUpdated to;
Assign a number to a write commandSRAM user data buffer unit of (c) willIs arranged as;
For a pair ofExecuting the 1 adding operation, repeatedly executing the step of distributing the SRAM user data buffer unit untilEqual toWill thenSetting 0;
Wherein, Indicating the number of DDR user data backup cache units,Indicating the DDR user data backup cache unit idle state,Representing the state of transmitting the upper computer user data to the SRAM user data buffer unit,Representing the state in which the DDR user data backup cache unit waits for the SRAM user data cache unit to initiate a backup operation,Representing the number of the SRAM user data cache unit obtained by the current upper computer write command;
Write command get number is After the SRAM user data buffer unit, starting DMA operation, transmitting the user data of the upper computer to the data transmission unit with the serial numberSRAM user data cache unit of (c).
Further, step S3 includes:
s301, updating the state of the SRAM user data caching unit associated with the writing command after the DMA operation from the user data associated with the writing command of the upper computer to the SRAM user data caching unit is finished;
S302, acquiring the number of the SRAM user data cache units waiting for the backup operation currently, and starting to check the states of the specified number of the SRAM user data cache units from the number;
s303, after confirming that the specified number of SRAM user data cache units complete the DMA operation of the upper computer, starting the DMA operation from the specified number of SRAM user data cache units to the associated DDR user data backup cache units.
Further, the specific steps include:
S301-1, will Updated toWhereinRepresenting the state of each SRAM user data cache cell, the array index is the SRAM user data cache cell number,Representing the data transmission completion state of the upper computer user;
S302-1, will Is arranged as,Indicating the SRAM user data cache cell number that needs to be status checked before performing a backup operation,Representing the number of the user data cache unit of the SRAM waiting for backup currently;
S302-2, check Whether or not it isIf yes, continuing, otherwise, exiting the operation;
s302-3, pair Performing 1-adding operation, repeatedly performing the above-mentioned checking of the states of the specified number of SRAM user data cache units untilEqual toWill thenThe water is placed in the water tank to be 0,Representing the number of SRAM user data cache units;
s302-4, check Whether or not to be equal toOr 0, if so, then continues, otherwise returns to S302-2,Representing the number of the set SRAM user data cache units for executing the backup operation each time;
s303-1, calculation number is DDR user data backup cache unit number associated with SRAM user data cache unit:
;
S303-2, starting DMA inside SSD, slave serial number isStarting with the SRAM user data buffer unit of the number ofSRAM user data buffer cell data transfer to slave numberThe starting DDR user data backup cache unit;
S303-3, will Is arranged as;
S303-4, willIs arranged as,Representing a state of transmitting the SRAM user data buffer unit data to the DDR user data backup buffer unit;
S303-5 pair Performing 1-adding operation, repeatedly performing the DMA operation untilEqual toWill thenSetting 0;
S303-6, check Whether or not to be equal toOr equal to 0, if yes, executing the next step, otherwise returning to S303-4;
s303-7, numbering the initial SRAM user data cache unit of the backup operation Is arranged asWill beIs arranged as。
Further, step S4 includes:
s401, updating all states of the SRAM user data buffer units associated with backup operation after the DMA operation from the data of the SRAM user data buffer units to the associated DDR user data backup buffer units is finished;
S402, executing flash memory grain writing operation on all SRAM user data caching units, and associating DDR user data backup caching units associated with all SRAM user data caching units into the flash memory grain writing operation.
Further, before the operation of writing the SRAM user data cache unit data into the flash memory granule, the following steps are further performed:
s401-1, obtaining initial SRAM user data buffer unit numbers associated with the backup operation Will beIs arranged as,The SRAM user data cache cell number indicating the need for status update after the completion of the backup operation is performed,Representing initial SRAM user data cache cell numbering in backup operation execution
S401-2, willUpdated to,Representing the state of each SRAM user data cache cell, the array index is the SRAM user data cache cell number,Representing the transmission completion state of the SRAM user data buffer unit data to the DDR user data backup buffer unit;
s401-3, calculation number is DDR user data backup cache unit number associated with SRAM user data cache unitSpecifically, as follows,
;
S401-4, willUpdated to,Representing the status of each DDR user data backup cache unit, the array index is the DDR user data backup cache unit number,Representing the transmission completion state of the SRAM user data buffer unit data to the DDR user data backup buffer unit;
S401-5, pair Performing 1-adding operation, repeating the steps S401-1 to S401-4, ifEqual toWill thenSetting 0;
S401-6, check Whether or not to be equal toOr equal to 0, if yes, continuing, otherwise returning to S401-2;
S401-7, will Is arranged as,Representing the initial SRAM user data cache unit number of the flash memory grain to be written currently;
S401-8, calculation number is DDR user data backup cache unit number associated with SRAM user data cache unit:
S401-9, willAndCorrelating to a flash grain write operation to be performed;
S402-1, when the flash memory grain writing operation is executed, if the data in the SRAM user data caching unit is transmitted to the flash memory grain data register, the initial SRAM user data caching unit number associated with the operation is obtained ;
S402-2, willIs arranged as,Representing the number of the SRAM user data cache unit which needs to be updated in state after the SRAM user data cache unit data are written into the flash granule data register;
S402-3, will Updated to,Representing an idle state of the SRAM user data buffer unit;
s402-4 pair Performing the 1-adding operation ifEqual toWill thenThe water is placed in the water tank to be 0,Representing the number of DDR user data backup cache sets,Is a positive integer and;
S402-5 pairPerforming 1-adding operation, repeating steps S402-3 to S402-4, ifEqual toWill thenSetting 0;
s402-6, check Whether or not to be equal toOr equal to 0, if yes, the operation is exited, otherwise S402-3 is returned.
Further, step S5 includes:
S501, after all SRAM user data cache units associated with a flash memory grain writing operation are written into a flash memory grain data register, releasing all SRAM user data cache units, and updating DDR user data backup cache set numbers associated with all SRAM user data cache units;
s502, writing the flash granule data register data into a flash granule storage medium, and releasing all DDR user data backup cache units associated with a flash granule writing operation after writing.
Further, the method further comprises the steps of:
S502-1, after writing the data in the data register into the storage medium, obtaining the associated initial DDR user data backup cache unit number ,The DDR user data backup cache unit number associated with the initial SRAM user data cache unit number representing the current flash memory grain to be written;
S502-2, will Is arranged as,The DDR user data backup cache unit number which indicates that the status update is required after the flash memory grain data register data is written into the flash memory grain storage medium;
S502-3, will Updated to;
S502-4, pairExecuting the 1-adding operation, repeating the step S502-3 untilEqual toWill thenSetting 0;
S502-5, check Whether or not to be equal toOr equal to 0, if yes, the operation is exited, otherwise S502-3 is returned.
The SSD user data backup method has the advantages that the average sequential write performance and the consistency of the performance are not affected on the premise that the user data is not lost. The data backup operation of caching the SRAM to the DDR cache is independent from the write command processing flow from the upper computer to the SSD, so that the data volume of each backup operation of the SSD is basically consistent, and the performance fluctuation is reduced and the performance average value is improved.
Drawings
FIG. 1 is a flow chart of a process for obtaining SSD SRAM user data buffer unit by an upper computer write command;
FIG. 2 is a schematic diagram of a backup process of a SSD SRAM user data cache unit;
FIG. 3 is a flowchart of the process after the backup of the SSD SRAM user data buffer unit is completed.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.
The core of the backup method for SSD user data in the internal cache is that after a data backup function is started in the SSD, the average sequential write performance and the consistency of the performance are not affected.
In order to realize the function of caching and backing up SSD user data internally, a DMA hardware module is required to be added in the SSD and used for realizing the data transmission operation from the SRAM to the DDR.
Before the backup method of SSD user data in the internal cache is implemented, the following parameters are required to be obtained:
SRAM user data buffer capacity The unit is Byte;
user data buffer unit capacity The unit is Byte;
SRAM user data buffer cell number The definition is as follows,
。
Numbering all SRAM user data buffer units from 0, and using set management, there is a setWhereinRepresenting the ith user data buffer unit.
DDR user data backup cache set capacityWherein, the method comprises the steps of, wherein,。
DDR user data backup cache set number,Is a positive integer, and。
DDR user data backup cache capacityThe unit is Byte.
DDR user data backup cache unit number。
Numbering all DDR user data backup cache units from 0, and using set management, then having setWhereinRepresenting an ith DDR user data backup cache unit;
numbering all DDR user data backup cache sets from 0, and managing the sets, wherein the sets are provided WhereinRepresenting the ith DDR user data backup cache set.
After the parameters related to the SRAM user data cache and the DDR user data backup cache are obtained, the following management information is needed to manage the SRAM user data cache and the DDR user data backup cache:
Using arrays Recording the DDR user data backup cache set number associated with each SRAM user data cache unit, wherein the array index is the SRAM user data cache unit number, and the array member is the DDR user data backup cache set number for backing up the current SRAM user data cache unit.
Using arraysRecording the state of each SRAM user data buffer unit, wherein the array index is the number of the SRAM user data buffer unit, the array member is the state of the SRAM user data buffer unit, and the state types comprise:
The SRAM user data buffer unit is in idle state;
transmitting the user data of the upper computer to the state of the SRAM user data buffer unit;
the user data transmission completion state of the upper computer;
Transmitting the data of the SRAM user data buffer unit to the DDR user data backup buffer unit;
the transmission completion state from the SRAM user data buffer unit data to the DDR user data backup buffer unit.
UsingRecording the number of the current allocable SRAM user data caching unit;
Using Recording the serial numbers of the SRAM user data caching units obtained by the current upper computer writing command;
Using Temporarily recording the DDR user data backup cache unit numbers associated with the SRAM user data cache units with the designated numbers;
Using Recording the number of the user data cache unit of the SRAM waiting for backup currently;
Using Recording the number of the SRAM user data cache unit which needs to be subjected to state check before backup operation is executed;
Using Recording the initial SRAM user data caching unit number in the backup operation execution;
Using Recording the number of the SRAM user data cache unit which needs to be subjected to state update after the backup operation is completed;
Using Recording the serial number of a starting SRAM user data cache unit to be written into the flash memory particle currently;
Using Recording the number of the SRAM user data cache unit which needs to be updated in state after the SRAM user data cache unit data are written into the flash memory granule data register;
Using Recording DDR user data backup cache unit numbers associated with initial SRAM user data cache unit numbers of flash memory particles to be written currently;
Using Recording the DDR user data backup cache unit number which needs to be updated in state after writing the flash memory grain data register data into the flash memory grain storage medium;
Using Representing the number of SRAM user data cache cells per backup operation, the value being user-definable;
Using arrays Recording the state of each DDR user data backup cache unit, wherein the array index is the number of the DDR user data backup cache unit, the array member is the state of the DDR user data backup cache unit, and the state types comprise:
DDR user data backup buffer unit idle state;
the DDR user data backup caching unit waits for the state that the SRAM user data caching unit starts backup operation;
the transmission completion state from the SRAM user data buffer unit data to the DDR user data backup buffer unit.
The backup method of SSD user data in the internal cache comprises the steps of:
S1, an SRAM user data caching unit and a DDR user data backup caching unit execute initialization operation;
s2, the upper computer issues a write command to the SSD, the SSD distributes an SRAM user data buffer unit for the upper computer write command, the upper computer write command successfully acquires the SRAM user data buffer unit, a DMA operation is started, and upper computer user data is transmitted to the SRAM user data buffer unit;
S3, starting DMA operation from the specified quantity of SRAM user data cache unit data to the associated DDR user data backup cache unit, and finishing SSD SRAM user data cache unit backup;
s4, executing flash memory grain writing operation on all SRAM user data caching units;
s5, writing the flash grain data register data into the flash grain storage medium.
The step S1 initialization includes:
(1) For a pair of All members perform an initialization operation:
,;
(2) For a pair of All members perform an initialization operation:
,;
(3) For a pair of All members perform an initialization operation:
,;
(4) Will be Put 0, willAnd setting 0.
Step S2 referring to FIG. 1, the steps include the following.
(1) After the upper computer issues a write command to the SSD, the SSD checksWhether or not the value isIf yes, carrying out the next step, otherwise, suspending the allocation of the SRAM user data buffer unit;
(2) From the following components Obtain number ofDDR user data backup cache set associated with SRAM user data cache unit, useThe DDR user data backup cache unit numbers associated with the SRAM user data cache unit are temporarily recorded, and the method concretely comprises the following steps:
;
(3) Inspection of Whether or not the value isIf yes, carrying out the next step, otherwise, suspending the allocation of the SRAM user data buffer unit;
(4) Will be Updated toWill beUpdated to;
(5) Assign a number to a write commandSRAM user data buffer unit of (c) willIs arranged as;
(6) For a pair ofExecuting the 1 adding operation, repeatedly executing the step of distributing the SRAM user data buffer unit untilEqual toWill thenAnd setting 0.
(7) Write command get number isAfter the SRAM user data buffer unit, starting DMA operation, transmitting the user data of the upper computer to the data transmission unit with the serial numberSRAM user data cache unit of (c).
Step S3 referring to FIG. 2, the steps include the following.
(1) Will beUpdated to;
(2) Will beIs arranged as;
(3) Inspection ofWhether or not it isIf yes, continuing, otherwise, exiting the operation;
(4) For a pair of Performing 1-adding operation, repeatedly performing the above-mentioned checking of the states of the specified number of SRAM user data cache units untilEqual toWill thenSetting 0;
(5) Inspection of Whether or not to be equal toOr equal to 0, if yes, continuing, otherwise returning to S302-2;
(6) Calculation number is DDR user data backup cache unit number associated with SRAM user data cache unit:
;
(7) Starting DMA inside SSD, slave number isStarting with the SRAM user data buffer unit of the number ofSRAM user data buffer cell data transfer to slave numberThe starting DDR user data backup cache unit;
(8) Will be Is arranged as;
(9) Will beIs arranged as;
(10) For a pair ofPerforming 1-adding operation, repeatedly performing the DMA operation untilEqual toWill thenSetting 0;
(11) Inspection of Whether or not to be equal toOr equal to 0, if yes, executing the next step, otherwise returning to the step (9);
(12) Numbering the initial SRAM user data cache unit of the backup operation Is arranged asWill beIs arranged as。
Step S4 referring to FIG. 3, the steps include the following.
(1) Obtaining the initial SRAM user data buffer unit number associated with the backup operationWill beIs arranged as;
(2) Will beUpdated to;
(3) Calculation number isDDR user data backup cache unit number associated with SRAM user data cache unitSpecifically, as follows,
;
(4) Will beUpdated to;
(5) For a pair ofPerforming 1-adding operation, repeating the steps S401-1 to S401-4, ifEqual toWill thenSetting 0;
(6) Inspection of Whether or not to be equal toOr 0, if so, continuing, otherwise, returning to (2);
(7) Will be Is arranged as;
(8) Calculation number isDDR user data backup cache unit number associated with SRAM user data cache unit:
(9) Will beAndIs associated with a flash granule write operation to be performed.
When the flash memory grain writing operation is executed, if the data in the SRAM user data caching unit is transmitted to the flash memory grain data register, the initial SRAM user data caching unit number associated with the operation is obtainedAnd performs the following steps.
(1) Will beIs arranged as;
(2) Will beUpdated to,Representing an idle state of the SRAM user data buffer unit;
(3) For a pair of Performing the 1-adding operation ifEqual toWill thenSetting 0;
(4) For a pair of Performing 1-adding operation, repeating steps S402-3 to S402-4, ifEqual toWill thenSetting 0;
(5) Inspection of Whether or not to be equal toOr 0, if yes, the operation is exited, otherwise (2) is returned.
Step S5 referring to FIG. 3, the steps include the following.
(1) After writing the data in the data register into the storage medium, obtaining the associated initial DDR user data backup cache unit number;
(2) Will beIs arranged as;
(3) Will beUpdated to;
(4) For a pair ofExecuting the 1-adding operation, repeating the step S502-3 untilEqual toWill thenSetting 0;
(5) Inspection of Whether or not to be equal toOr 0, if yes, the operation is exited, otherwise (3) is returned.
Finally, it should be understood that the foregoing description is merely illustrative of the preferred embodiments of the present invention and is not intended to limit the invention to the particular embodiments disclosed, but on the contrary, the intention is to cover all modifications, equivalents, alternatives, and alternatives falling within the spirit and scope of the invention.
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