CN119690906A - A MCU controller - Google Patents
A MCU controller Download PDFInfo
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- CN119690906A CN119690906A CN202510222178.9A CN202510222178A CN119690906A CN 119690906 A CN119690906 A CN 119690906A CN 202510222178 A CN202510222178 A CN 202510222178A CN 119690906 A CN119690906 A CN 119690906A
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Abstract
The application provides an MCU controller, which comprises a kernel, a read-only memory, a read-write memory, a register, a flash memory controller and a flash memory, wherein the read-only memory and the read-write memory are different in stored data types and different in mapping addresses, the kernel is respectively connected with the read-only memory, the read-write memory and the register through a plurality of buses, the buses are separated and parallel, the flash memory controller is connected with the read-only memory and the read-write memory, the flash memory controller is switched between a bus master device and a bus slave device, when the flash memory controller is switched into the bus master device, the flash memory controller transmits data to be transmitted from the flash memory to the read-write memory, when the flash memory controller is switched into the bus slave device, the kernel performs read-write operation on the register, parallel access of instructions, data and external data is realized through separated bus interfaces, the system efficiency is improved, the flash memory controller is dynamically switched between the master and slave, and the starting efficiency and the flexibility in running are optimized.
Description
Technical Field
The embodiment of the application relates to the field of semiconductors, in particular to an MCU controller.
Background
For MCU controller architectures, it is currently mainly the reading of instructions and data from NOR FLASH. But is limited by the read-write delay of FLASH, and on MCU products with main frequency of more than 100MHz, the read-write efficiency is low due to the mode, so that the system performance is difficult to improve.
Disclosure of Invention
The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.
The application aims to at least solve one of the technical problems existing in the related technology to a certain extent, and the embodiment of the application provides an MCU controller which can improve the system performance.
The MCU controller comprises a kernel, a plurality of read-only memories, a plurality of read-write memories, a register, a flash memory controller and a flash memory, wherein the read-only memories and the read-write memories are different in data types and different in mapping addresses, the kernel is respectively connected with the read-only memories, the read-write memories and the register through a plurality of different buses, the buses are separated and parallel, the flash memory controller is connected with the read-only memories and the read-write memories, the flash memory controller is switched between a bus master device and a bus slave device, when the flash memory controller is switched to the bus master device, the flash memory controller transmits data to be transmitted from the flash memory to the read-write memory, when the flash memory controller is switched to the bus slave device, the flash memory controller performs read-write operation on the register.
According to the embodiment of the first aspect of the application, the buses comprise a first bus, a second bus and a third bus, the read-only memory comprises a first read-only memory and a second read-only memory, the read-write memory comprises a first read-write memory and a second read-write memory, the first read-only memory is used for storing a bootstrap program, the second read-only memory is used for storing instructions and constants, the first read-write memory is used for storing stacks and variables, and the second read-write memory is used for storing external data.
According to an embodiment of the first aspect of the present application, the core is connected to the first read only memory, the second read only memory and the first read write memory through the first bus.
According to an embodiment of the first aspect of the present application, the core is connected to the first read only memory, the second read only memory and the first read write memory through the second bus.
According to an embodiment of the first aspect of the present application, the core is connected to the second read-write memory through the third bus.
According to an embodiment of the first aspect of the present application, the mapping address of the first read-only memory ranges from 0x00000000 to 0x00007FFF, the mapping address of the second read-only memory ranges from 0x00008000 to 0x0002FFFF, the mapping address of the first read-write memory ranges from 0x00030000 to 0x00057FFF, and the mapping address of the second read-write memory ranges from 0x20000000 to 0x20037FFF.
According to an embodiment of the first aspect of the present application, when the flash memory controller is switched to the bus slave, the core performs a read/write operation on the register through the third bus.
According to an embodiment of the first aspect of the present application, the MCU controller further includes an AHB bus, the core is connected to the AHB bus through a third bus, and the flash memory controller and the register are connected to the AHB bus.
According to the embodiment of the first aspect of the application, the first bus, the second bus, the third bus and the fourth bus are integrated into a bus matrix, and the fourth bus is a data line for connecting the first read-only memory, the second read-only memory and the first read-write memory to the flash memory controller.
According to an embodiment of the first aspect of the present application, when the MCU controller is powered on for reset, the kernel reads the boot program from the first read only memory, configures the flash memory controller as a bus master according to the boot program, transmits instructions and constants in the flash memory to the first read write memory, jumps a program counter of the kernel to a mapping address of the first read write memory, and the kernel runs a main program.
The scheme has the advantages that the data types stored by the read-only memory and the read-write memory are different and the mapping addresses are different, the kernel is respectively connected with the read-only memory, the read-write memory and the register through a plurality of buses, the buses are separated and parallel, the flash memory controller is connected with the read-only memory and the read-write memory, the flash memory controller is switched between the bus master device and the bus slave device, when the flash memory controller is switched into the bus master device, the flash memory controller transmits data to be transmitted from the flash memory to the read-write memory, when the flash memory controller is switched into the bus slave device, the kernel performs read-write operation on the register, parallel access of instructions, data and external data is realized through separated bus interfaces, the system efficiency is improved, and the flash memory controller is dynamically switched between the master and slave, so that the starting efficiency and the operation flexibility are optimized.
Drawings
The accompanying drawings are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate and do not limit the application.
FIG. 1 is a block diagram of an MCU controller according to an embodiment of the present application
FIG. 2 is a specific block diagram of an MCU controller provided by an embodiment of the present application;
FIG. 3 is a block diagram of a bus matrix provided by an embodiment of the present application;
Fig. 4 is a power-on flowchart of the MCU controller.
Detailed Description
The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
It should be noted that although functional block division is performed in a device diagram and a logic sequence is shown in a flowchart, in some cases, the steps shown or described may be performed in a different order than the block division in the device, or in the flowchart. The terms first, second and the like in the description, in the claims and in the above-described figures, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order.
For MCU controller architectures, the traditional approach is mainly to read instructions and data from NOR FLASH. But is limited by the read-write delay of FLASH, and on MCU products with main frequency of more than 100MHz, the system performance is difficult to improve.
In order to solve the above problems, embodiments of the present application provide an MCU controller.
Embodiments of the present application will be further described below with reference to the accompanying drawings.
Referring to fig. 1, the mcu controller includes a core, a plurality of read-only memories, a plurality of read-write memories, a register, a flash memory controller and a flash memory, wherein the plurality of read-only memories and the plurality of read-write memories store different data types and different mapping addresses, the core is respectively connected with the plurality of read-only memories, the plurality of read-write memories and the register through a plurality of different buses, the plurality of buses are separated and parallel, the flash memory controller is connected with the plurality of read-only memories and the plurality of read-write memories, the flash memory controller is switched between a bus master device and a bus slave device, when the flash memory controller is switched into the bus master device, the flash memory controller transmits data to be transmitted from the flash memory to the read-write memory, and when the flash memory controller is switched into the bus slave device, the core performs read-write operation on the register.
The core adopts ARM Cortex-M3 core. Of course, in other embodiments, other types of processor cores of similar structures may be used.
The bus comprises a first bus, a second bus and a third bus, the read-only memory comprises a first read-only memory and a second read-only memory, the read-write memory comprises a first read-write memory and a second read-write memory, the first read-only memory is used for storing a bootstrap program, the second read-only memory is used for storing instructions and constants, the first read-write memory is used for storing stacks and variables, and the second read-write memory is used for storing external data.
The ARM Cortex-M3 kernel is provided with an ICODE bus interface, a DCODE bus interface and a SYS bus interface.
The first bus is an ICODE bus, the second bus is a DCODE bus, and the third bus is a SYS bus. The ICODE bus and DCODE bus can access only addresses 0x00000000 to 0x1fffffff (512 MB), while the SYS bus can access addresses after 0x 20000000. The three buses are separated, and the three buses can access different address intervals in parallel.
Referring to fig. 2, the core is connected to the ICODE bus via an ICODE bus interface, to the DCODE bus via a DCODE bus interface, and to the SYS bus via a SYS bus interface.
The read-only memory comprises a first read-only memory and a second read-only memory, and the read-write memory comprises a first read-write memory and a second read-write memory. The first read-only memory is a ROM memory and is marked as BOOT_ROM, the second read-only memory is an SRAM memory and is marked as SRAM1, the first read-write memory is an SRAM memory and is marked as SRAM2, and the second read-write memory is an SRAM memory or a register of a FLASH controller of a module hung on an AHB bus and is marked as SRAM3.
A Static Random-Access Memory (SRAM) is a semiconductor Memory that stores each bit of data using a bi-stable latch circuit (flip-flop). SRAM can hold data as long as power is supplied, and therefore is fast and low in density. When the power supply is stopped, the data stored in the SRAM disappears.
The first read-only memory is used for storing a bootstrap program, the second read-only memory is used for storing instructions and constants, the first read-write memory is used for storing stacks and variables, and the second read-write memory is used for storing external data.
Referring to fig. 3, the core is connected to the first read only memory, the second read only memory, and the first read write memory through a first bus.
The kernel is connected with the first read-only memory, the second read-only memory and the first read-write memory through the second bus.
The kernel is connected with the second read-write memory through a third bus.
Different buses are mapped to different storage areas (such as Flash, SRAM and peripheral registers), and bus conflict is further optimized and parallel efficiency is improved by strictly dividing SRAM1 (read-only instruction area) and SRAM2 (read-write data area).
The first read-only memory has a mapping address ranging from 0x00000000 to 0x00007FFF (32 KB), the second read-only memory has a mapping address ranging from 0x00008000 to 0x0002FFFF (160 KB), the first read-write memory has a mapping address ranging from 0x00030000 to 0x00057FFF (160 KB), and the second read-write memory has a mapping address ranging from 0x20000000 to 0x20037FFF (224 KB).
The address interval is divided more finely (such as capacity and authority allocation of SRAM1/SRAM2/SRAM 3), and the access priority is optimized for Cortex-M3 bus characteristics.
The core can access the BOOT ROM, SRAM1 and SRAM2 through the ICODE bus. The core can access the BOOT ROM, SRAM1 and SRAM2 through DCODE bus, and the core can access SRAM3 through SYS bus.
The maximized bus interface (ICODE bus/DCODE bus/SYS bus) separated by the Cortex-M3 kernel can enable the MCU to reach the CPU main frequency (SMIC 40nm, tt) of 200MHz, and the overall system performance of the MCU is greatly improved. And through the separated bus interface, parallel access of instructions, data and external data is realized, and the system efficiency is improved.
The SRAM1 is accessed to read instructions and constants through the ICODE bus, the stack and variables of the SRAM2 are accessed through the DCODE bus, the SRAM3 and a module register are accessed through the SYS bus, the SRAM3 can store some external data needing to be processed, such as data acquired by a camera, voice data and the like, and the register is used as a software interface to achieve the function of programmable configuration MCU. Different address intervals can be accessed in parallel through 3 separate buses of Cortex-M3 cores.
The MCU controller also comprises an AHB bus, the kernel is connected with the AHB bus through a third bus, and the flash memory controller and the register are connected with the AHB bus.
When the flash memory controller is switched into the bus MASTER device, namely the flash memory controller is used as an AHB MASTER, the flash memory controller obtains the access permission of the AHB bus, and the flash memory controller transmits the data to be transmitted from the flash memory to the read-write memory. The data to be transmitted are codes and variables. The flash controller transfers the code and variables into SRAM1 or SRAM 2.
Compared with the data carried by the CPU, the data carried by the flash memory controller can save the complicated processes of CPU instruction fetching, instruction translating and execution.
The benefit of transferring code and constants to SRAM1 is that Cortex-M3 core access SRAM1 fetch does not require an intervening wait period. The zero waiting period of the SRAM partition is isolated from data, and bus competition is reduced.
When the flash memory controller is switched to the bus slave device, the kernel performs read-write operation on the register through the third bus.
The flash memory controller dynamically switches between master and slave, and optimizes the starting efficiency and the flexibility in running.
The first bus, the second bus, the third bus, and the fourth bus are integrated into a bus matrix. The fourth bus is a bus for connecting the first read-only memory, the second read-only memory and the first read-write memory by the flash memory controller.
The FLASH memory is NAND FLASH, and the FLASH memory controller is a FLASH controller.
The inner core is connected with an ICODE_S interface of the bus matrix through an ICODE bus, and the ICODE bus led out from the ICODE_S interface is connected with a BOOT_ROM_M interface, an SRAM1_M interface and an SRAM2_M interface of the bus matrix.
The core is connected with DCODE _S interface of the bus matrix through DCODE bus, and DCODE bus led out from DCODE _S interface is connected with BOOT_ROM_M interface, SRAM1_M interface and SRAM2_M interface of the bus matrix.
The kernel is connected with SYSBUS _S interface of the bus matrix through SYS bus, and SYS bus led out from SYSBUS _S interface is connected with SRAM3_M interface of the bus matrix. The kernel is connected to the AHB bus through a SYS bus.
The FLASH memory controller is connected with the AHB bus through an AHB_SLAVE_IF interface, is connected with a FLASH_CTRL_S interface of the bus matrix through an AHB_MASTER_IF interface, and is connected with a BOOT_ROM_M interface, an SRAM1_M interface and an SRAM2_M interface of the bus matrix through a fourth bus led out from the FLASH_CTRL_S interface.
The BOOT_ROM_M interface is connected with the BOOT_ROM, the SRAM1_M interface is connected with the SRAM1, and the SRAM2_M interface is connected with the SRAM2.
When the FLASH memory controller is switched to the bus MASTER device, the FLASH controller downloads codes and variables from NAND FLASH, and the codes and the variables are sequentially transmitted to the SRAM1 or the SRAM2 through the AHB_MASTER_IF interface, the FLASH_CTRL_S interface and the SRAM1_M interface.
When the flash memory controller is switched into the bus slave device, the kernel performs read-write operation on the register through the SYS bus, SYSBUS _S interface and SRAM3_M interface.
Referring to fig. 4, for the start-up and operation process of the MCU controller, when the MCU controller is powered on for reset, the kernel reads the boot program from the first read-only memory, the kernel configures the flash memory controller as the bus master according to the boot program, transmits the instructions and constants in the flash memory to the first read-write memory, the program counter of the kernel jumps to the mapped address of the first read-write memory, and the kernel operates the main program.
For example, when the MCU controller is powered on and reset, the program counter of the kernel jumps to the mapped address range of the BOOT ROM, the kernel reads the BOOT program from the BOOT ROM, the kernel configures the flash memory controller as the bus master according to the BOOT program, the flash memory controller transfers the instructions and constants in NAND FLASH to SRAM1, the program counter jumps to the mapped address range of SRAM1, and the kernel runs the main program.
A Program Counter (PC) is a register for storing an address of a next instruction to be executed, and is one of core components of the MCU executing the instruction, so as to ensure that the Program can be executed in sequence.
When the MCU controller is powered on reset, the program counter is initialized to the start address of the BOOT ROM (e.g., 0x 00000000) from which the kernel reads the BOOT program. After the boot program is executed, the program counter is updated to the address range of SRAM1 (e.g., 0x 00008000), and the kernel runs the main program.
While the preferred embodiment of the present application has been described in detail, the present application is not limited to the embodiments, and those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present application, and the equivalent modifications or substitutions are intended to be included in the scope of the present application as defined in the appended claims.
Claims (10)
1. The MCU controller is characterized by comprising a kernel, a plurality of read-only memories, a plurality of read-write memories, a register, a flash memory controller and a flash memory, wherein the read-only memories and the read-write memories are different in data types and different in mapping addresses, the kernel is respectively connected with the read-only memories, the read-write memories and the register through a plurality of different buses, the buses are separated and parallel, the flash memory controller is connected with the read-only memories and the read-write memories, the flash memory controller is switched between a bus master device and a bus slave device, when the flash memory controller is switched to the bus master device, the flash memory controller transmits data to be transmitted from the flash memory to the read-write memory, when the flash memory controller is switched to the bus slave device, the kernel checks the register to perform reading operation.
2. The MCU controller of claim 1, wherein the buses include a first bus, a second bus, and a third bus, the read-only memory includes a first read-only memory and a second read-only memory, the read-write memory includes a first read-write memory and a second read-write memory, the first read-only memory is used to store a bootstrap program, the second read-only memory is used to store instructions and constants, the first read-write memory is used to store stacks and variables, and the second read-write memory is used to store external data.
3. The MCU controller of claim 2, wherein the core is coupled to the first read only memory, the second read only memory, and the first read write memory via the first bus.
4. The MCU controller of claim 2, wherein the core is coupled to the first read only memory, the second read only memory, and the first read write memory via the second bus.
5. The MCU controller of claim 2, wherein the core is coupled to the second read-write memory via the third bus.
6. The MCU controller of claim 2, wherein the first read only memory has a mapping address ranging from 0x00000000 to 0x00007FFF, the second read only memory has a mapping address ranging from 0x00008000 to 0x0002FFFF, the first read write memory has a mapping address ranging from 0x00030000 to 0x00057FFF, and the second read write memory has a mapping address ranging from 0x20000000 to 0x20037FFF.
7. The MCU controller of claim 2, wherein when the flash controller switches to the bus slave, the core performs a read/write operation on the register through the third bus.
8. The MCU controller of claim 2, further comprising an AHB bus, wherein the core is coupled to the AHB bus via a third bus, wherein the flash controller and the register are coupled to the AHB bus.
9. The MCU controller of claim 2, wherein the first bus, the second bus, the third bus, and a fourth bus are integrated into a bus matrix, the fourth bus being a data line of the flash memory controller connecting the first ROM, the second ROM, and the first read-write memory.
10. The MCU controller of claim 2, wherein when the MCU controller is powered on reset, the kernel reads the boot program from a first read-only memory, configures the flash memory controller as a bus master according to the boot program, transfers instructions and constants in the flash memory to the first read-write memory, jumps a program counter of the kernel to a mapped address of the first read-write memory, and the kernel runs a subject program.
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| CN202510222178.9A CN119690906A (en) | 2025-02-27 | 2025-02-27 | A MCU controller |
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| CN202510222178.9A CN119690906A (en) | 2025-02-27 | 2025-02-27 | A MCU controller |
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| CN119493596A (en) * | 2024-10-12 | 2025-02-21 | 珠海英集芯半导体有限公司 | Microprocessing system and program execution method |
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Patent Citations (4)
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| US20050055481A1 (en) * | 2003-09-10 | 2005-03-10 | Super Talent Flash, Inc | Flash drive/reader with serial-port controller and flash-memory controller mastering a second ram-buffer bus parallel to a cpu bus |
| CN202838325U (en) * | 2012-03-29 | 2013-03-27 | 佛山华芯微特科技有限公司 | Micro controller unit (MCU) chip |
| CN118427131A (en) * | 2024-07-04 | 2024-08-02 | 江苏云途半导体有限公司 | A method and system for dynamically allocating storage of multi-core system chips |
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