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CN119678253A - Laminated substrate for power package - Google Patents

Laminated substrate for power package Download PDF

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Publication number
CN119678253A
CN119678253A CN202280099044.7A CN202280099044A CN119678253A CN 119678253 A CN119678253 A CN 119678253A CN 202280099044 A CN202280099044 A CN 202280099044A CN 119678253 A CN119678253 A CN 119678253A
Authority
CN
China
Prior art keywords
conductive pads
layer
major surface
substrate
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202280099044.7A
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Chinese (zh)
Inventor
拉塞·彼得里·帕尔姆
吉尔伯托·库拉托拉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Huawei Digital Power Technologies Co Ltd
Original Assignee
Huawei Digital Power Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Digital Power Technologies Co Ltd filed Critical Huawei Digital Power Technologies Co Ltd
Publication of CN119678253A publication Critical patent/CN119678253A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H01L23/49844—Geometry or layout for individual devices of subclass H10D
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

The invention relates to a laminated substrate (110) for a power package (100). The laminate substrate (110) includes an electrically insulating layer (120) and a plurality of electrically conductive pads (131 a to 131 e) encapsulated in the electrically insulating layer (120). The conductive pads (131 a to 131 e) are arranged to form a staggered structure. The electrically conductive pads extend through the electrically insulating layer (120) from the first major surface (110 a) to the second major surface (110 b) of the insulating layer (120). The conductive pads (131 a-131 e) are aligned along a first long axis on the second major surface (110 b). The laminate substrate (110) includes a plurality of parallel conductors (132 a-132 e) mounted on the second major surface (110 b) of the electrically insulating layer (120). The shunt conductors (132 a-132 e) are aligned along a second long axis on the second major surface (110 b) of the electrically insulating layer (120). The first major axis is substantially perpendicular to the second major axis at a location on the second major surface (110 b) of the electrically insulating layer (120), and respective pads (131 a-131 e) electrically connect respective conductors (132 a-132 e).

Description

Laminated substrate for power package
Technical Field
The present invention relates to the field of advanced build-up substrate and flip chip packaging technology for manufacturing power packages and components. More particularly, the present invention relates to a laminate substrate for a power package, a power package comprising such laminate substrate and a method for manufacturing such laminate substrate. Specifically, a build-up package for GaN with controlled isolation distance is disclosed.
Background
In high speed Gallium Nitride (GaN) packages, it is critical to minimize parasitic effects and maximize heat flow from the bare chip to the printed circuit board (printed circuit board, PCB) and cooling structure. The high speed/low parasitic GaN packages currently available are face down packages in which the bare chip is bonded to a laminate substrate by Flip Chip (FC) technology or to a half etched leadframe or simpler chip scale package (CHIP SCALE PACKAGE, CSP). However, CSP and FC on half-etched leadframe packages are not suitable for complex multi-die packages, such as half-bridges with drivers. FC on a laminate substrate may be used on a multi-die package, for example, as shown in US10,074,597B2, but since thin copper (Cu) wiring and small-sized plated micro holes and Plated Through Holes (PTHs) are used for connection through the laminate substrate, heat transfer and current carrying capability from the die to the PCB are limited.
Disclosure of Invention
The invention provides a technical scheme for a high-performance low-parasitic package, which can be used as a single-bare-chip GaN package, a multi-bare-chip GaN package or other transverse current and even vertical current power device packages.
The above and other objects are achieved by the features of the independent claims. Other implementations are apparent in the dependent claims, the description and the drawings.
The embodiments described in the present invention provide similar electrical and thermal performance and are also compatible with existing half-etched leadframe flip-chip variants on the footprint, but with improved performance and reduced parasitic characteristics.
These embodiments provide an alternative and improved method for manufacturing low parasitic GaN (or other lateral current power device) packages that have good thermal performance due to the large cross-section of the wiring and vias between the top and bottom of the package. In addition, these embodiments can properly address the multi-chip system problem in package integration, which is one of the most stringent limitations of current leadframe-based approaches.
The packages and fabrication processes described below may be based on the use of flip-chip bonding on a laminate substrate and a simplified fabrication process that is capable of fabricating a substrate with thick copper wiring and large cross-section Cu vias through the package.
The embodiments described in this invention can produce complex (e.g., intricate) multi-die packages, such as half-bridges with drivers.
The embodiments described in this invention are based on a laminate substrate rather than a leadframe. This has the advantage that intricate wiring can be performed on the substrate. In this way several power dies and even driver dies can be integrated into one package. In contrast to lead frames where all traces (leads) are connected to the frame, e.g., no "floating" wires can be used, the disclosed embodiments may use such "floating" wires to connect bare chips. Although all leads are visible at the package edge during the lead frame process, the disclosed embodiments may use a laminate substrate in which all sidewalls may be isolated to improve creepage distance.
Another advantage of the disclosed solution is that it can be processed on larger size panels than lead frames. This allows panel-level machining to be achieved, thereby reducing manufacturing costs, because the machining time for parallel machining is shorter and the machining time for each component in sequential machining is also shorter due to shorter setup, wait, and start-up times. The larger panel size also reduces material waste because the total processing area required to process multiple small panels is greater than the total processing area required to process a larger panel.
By using a pre-fabricated laminate substrate, additional integration of passive devices and other components is made possible very simply. Passive devices or other components can be easily placed in the desired locations of the package to ensure optimal electrical performance.
The present invention provides a package, substrate and structure for manufacturing a low parasitic single or multi-die GaN package, and a method for manufacturing a simplified build-up substrate on which GaN power die can be mounted by flip-chip technology. The substrate may be fabricated by using a lamination process of a commercially available molded interconnect substrate (molded interconnection substrate, MIS), via bar technology, or by a new simplified lamination substrate process, as described in detail below. If necessary, the back side of the die may be exposed to improve thermal performance.
The disclosed embodiments may be used to fabricate single die and multi-die packages with or without integrated passive devices. The examples described in connection with the following figures illustrate various structures in which one or more GaN die have a structure in which source pads and gate pads are alternately arranged. However, similar structural and design concepts may be used for other types of gate-source configurations. While the disclosed embodiments are primarily described with respect to packaging GaN die, they may be equally applicable to other types of lateral current power die, even vertical current die where Cu clamps are used to make die backside connections, etc.
Embodiments described herein include single die GaN packages, multi-die GaN packages, e.g., half-bridges with or without drivers and/or passive devices, multi-die GaN packages, e.g., parallel die with or without drivers and/or passive devices, and two simplified process flows for fabricating a laminate substrate.
As described above, the embodiments in the present invention are not limited to only GaN bare chips or GaN designs. It will be appreciated that conventional laminate substrates may also be used instead of the simplified laminate substrates described in the embodiments presented below.
For the purposes of describing the present invention in detail, the following terms, abbreviations and symbols will be used:
PCB printed circuit board (Printed Circuit Board)
GaN Gallium Nitride (Galium Nitride)
FC Flip Chip (Flip Chip)
MIS molded interconnect substrate (Molded Interconnect Substrate)
Chip embedding techniques are described. There are several different types of embedding processes in which electronic components (chips, capacitors, resistors, etc.) are either placed in openings in the central layer of a PCB or soldered to two or more layers of a PCB board. When actually embedded in the interior of the final PCB board, the FR4 prepreg or other polymer sheet may be laminated above and below the center layer that houses the components to be embedded. The electrical connection between the embedded component and the PCB metal layer may be formed by soldering the component terminals to the inner laminate layer and then uniformly laminating the PCB layer. In more advanced embedding techniques, the components may be electrically connected through current filled micro-vias, which is more robust because no solder remelting occurs inside the package or circuit board, which must be taken into account when mounting other components to the outer layers of the PCB. The micro-vias are typically formed after lamination by laser drilling, specifically laser drilling from the top surface through the thin laminate layer to the active chip pads or terminals of the embedded component package.
According to a first aspect, the invention relates to a laminate substrate for a power package. The laminate substrate includes an electrically insulating layer having a first major surface and an opposing second major surface, a plurality of electrically conductive pads encapsulated in the electrically insulating layer, wherein the plurality of electrically conductive pads are arranged to form a staggered structure, the electrically conductive pads extending through the electrically insulating layer from the first major surface to the second major surface, the electrically conductive pads being aligned along a first long axis on the second major surface of the electrically insulating layer, a plurality of parallel conductors mounted on the second major surface of the electrically insulating layer, wherein the parallel conductors are aligned along a second long axis on the second major surface of the electrically insulating layer, the first long axis being substantially perpendicular to the second long axis at a location on the second major surface of the electrically insulating layer, the respective pads electrically connecting respective conductors.
By "substantially perpendicular" is meant herein that the first long axis and the second long axis are at an angle of 90 ° with respect to each other, including minor positive or negative deviations from 90 °, e.g., deviations below 0.1 °, 0.25 °, 0.5 °,1 °,2 °,3 °,4 °, or 5 °.
The advantage of such a laminate substrate is that the laminate structure is simple, e.g. the laminate substrate may have 1.5 layers, one of which is embedded with pre-plated via bars, e.g. conductive pads. This simplifies the structure and reduces the manufacturing cost.
The package design with the laminate substrate can be easily extended to multi-die packages and different voltage levels to improve the clearance and creepage distance.
The embedded large via bars through the package substrate also define the package footprint or pads of the component (depending on which side the wiring is on). Thus, both electrical and thermal properties are improved compared to conventional laminate structures.
The laminate substrate does not use a lead frame, but the lead frame can be regarded as a lead frame type package with isolation sidewalls. The advantage of this is that no Cu leads are exposed on the package side walls, thereby reducing creepage distance.
In one exemplary implementation of the laminate substrate, the conductive pads are arranged in an interdigitated pattern.
This has the advantage that the available area of the laminate substrate can be optimally utilized. The creepage distance can be efficiently specified.
In one exemplary implementation of the laminate substrate, a respective pad of the plurality of conductive pads is defined by a length and a width of the respective pad, the length of the respective pad being greater than the width of the respective pad, the first major axis extending along the length direction of the respective pad.
This has the advantage that the source and drain pads and even the gate pads of the transistors can be arranged in rows, thereby helping to optimise the package footprint.
The thickness of the conductive pads may typically be between 80 μm and 150 μm and in the range of about 40 μm to 250 μm. These conductive pads may be made of pre-plated embedded Cu strips or the like.
In one exemplary implementation of the laminate substrate, the plurality of conductive pads form vias through the electrically insulating layer of the laminate substrate.
This has the advantage that a simple laminate structure can be obtained at reduced manufacturing costs. These through holes through the package substrate may also define a package footprint. The via design improves electrical and thermal performance compared to conventional laminate structures.
In one exemplary implementation of the laminate substrate, the plurality of conductive pads are formed according to a predetermined electrode pattern of at least one electronic chip included in the power package.
This has the advantage that the conductive pads of the laminate substrate are aligned with the electrode patterns of the chip. This enables mapping of the electrode pattern to the package substrate design.
In one exemplary implementation of the laminate substrate, the plurality of conductive pads and the plurality of parallel conductors are covered by the electrically insulating layer at edges of the laminate substrate to provide lateral electrical insulation of the laminate substrate.
This has the advantage that no leads are exposed on the laminate substrate, thus enabling an optimal creepage design with controllable isolation distances, which is not possible with lead frame based packages.
In one exemplary implementation of the laminate substrate, at least one of the plurality of conductive pads is electrically isolated from at least one other of the plurality of conductive pads by the electrically insulating layer, and/or at least one of the plurality of conductors is electrically isolated from at least one other of the plurality of conductors by the electrically insulating layer.
This has the advantage that the design options are flexible.
The laminate substrate may be used to fabricate single die and multi-die packages with or without integrated passive devices. For example, the laminate substrate may be used for one or more GaN bare chips having a structure in which source pads and gate pads are alternately arranged. Similar structures and the same design concepts may be used for other types of gate source configurations.
Although the embodiments disclosed herein were developed primarily for packaging GaN die, they could equally be used for other types of lateral current power die, even for vertical current die where Cu clips are used for die backside connection and the like.
In one exemplary implementation of the laminate substrate, the electrically insulating layer comprises at least one or a combination of a laminate material or a molding material, and/or the plurality of conductive pads and the plurality of conductors comprise electroplated Cu structures.
This has the advantage that the electrical and thermal properties are improved.
The thickness of the conductive pads may typically be between 80 μm and 150 μm and in the range of about 40 μm to 250 μm. These conductive pads may be made of pre-plated embedded Cu strips or the like.
The thickness of the conductor may typically be between 20 μm and 35 μm and in the range of about 10 μm to 150 μm. These conductors may be made of Cu seed layers, electroplated Cu, and the like.
According to a second aspect, the invention relates to a power package. The power package includes a laminate substrate according to the first aspect, at least one electronic chip including a first major surface and a second major surface opposite the first major surface, wherein the at least one electronic chip includes at least one first terminal electrically connected to at least one of the plurality of conductive pads and at least one second terminal electrically connected to at least one other of the plurality of conductive pads, an encapsulant encapsulating at least a portion of the at least one electronic chip, or an underfill attaching the at least one electronic chip to the laminate substrate.
This has the advantage that the package design with the laminated substrate can be easily extended to multi-die packages and different voltage levels to improve the gap and creepage distance.
The embedded large via bars through the package substrate may also define a package footprint. Thus, both electrical and thermal properties are improved compared to conventional laminate structures.
The laminate substrate does not use a lead frame, but the lead frame can be regarded as a lead frame type package with isolation sidewalls. The advantage of this is that no Cu leads are exposed on the package side walls, thereby reducing creepage distance.
In one exemplary implementation of the power package, the second major surface of the at least one electronic chip faces the first major surface of the electrically insulating layer, and the at least one first terminal and the at least one second terminal are disposed on the second major surface of the at least one electronic chip and mounted on respective ones of the plurality of conductive pads.
This has the advantage of a flexible design. The power package may be designed according to a first design option, wherein the chip is placed on the first main surface of the laminate substrate, i.e. on the first main surface of the electrically insulating layer.
In one exemplary implementation of the power package, the second major surface of the at least one electronic chip faces the second major surface of the electrically insulating layer, and the at least one first terminal and the at least one second terminal are disposed on the second major surface of the at least one electronic chip and mounted on respective ones of the plurality of conductors.
This has the advantage of a flexible design. The power package may be designed according to a second design option, also known as flip chip mounting, wherein the chip is placed on the second main surface of the laminate substrate, i.e. on the second main surface of the electrically insulating layer.
In one exemplary implementation of the power package, the at least one electronic chip includes a plurality of sides disposed between the first and second major surfaces of the at least one electronic chip, and the encapsulant covers the first and side surfaces of the at least one electronic chip, or the first major surface of the at least one electronic chip is not covered by the encapsulant, which at least partially covers the side surfaces of the at least one electronic chip, or the first major surface of the at least one electronic chip is not covered by the underfill, which partially covers the side surfaces of the at least one electronic chip.
This has the advantage of a flexible design. The design may be based on an overmolding process, an overmolding process with the back side of the die exposed, or an underfill process.
In one exemplary implementation of the power package, the power package forms a single die GaN package or a multi-die GaN package in a half-bridge or parallel die configuration with or without drivers and/or passive devices.
This has the advantage of a flexible design. Different types of single die or multi-die packages may be formed.
In one exemplary implementation of the power package, the power package includes at least one first solder layer disposed between the at least one first terminal and the at least one of the plurality of conductive pads, wherein the at least one first solder layer electrically connects the at least one first terminal to the at least one of the plurality of conductive pads, and/or at least one second solder layer disposed between the at least one second terminal and the at least one other of the plurality of conductive pads, wherein the at least one second solder layer electrically connects the at least one second terminal to the at least one other of the plurality of conductive pads.
This has the advantage that the solder layer can be used efficiently for attaching and electrically connecting the chip to the laminate substrate.
In one exemplary implementation of the power package, the power package forms a leadless leadframe package.
This has the advantage that the leadless package improves the creepage performance.
According to a third aspect, the invention relates to a method of manufacturing a laminate substrate for a power package according to the first aspect. The method includes providing a carrier having a metal layer attached thereto, wherein the metal layer has a first major surface and an opposite second major surface facing the carrier, treating a first photoresist layer on the first major surface of the metal layer and forming openings in the first photoresist layer, metal plating the openings in the first photoresist layer, removing the first photoresist layer to form the plurality of conductive pads, applying a laminate or molding material over the first major surface of the metal layer and the metal plated plurality of conductive pads, partially removing the laminate or molding material from the first major surface of the metal layer until the metal plated plurality of conductive pads are exposed and removing the carrier from the second major surface of the metal layer, treating a second photoresist layer on the second major surface of the metal layer and forming openings in the second photoresist layer, removing the metal layer from the openings in the second photoresist layer and removing the second photoresist layer from the metal layer to form the plurality of conductors.
Such a method may be used to manufacture a laminate substrate at reduced manufacturing costs.
In a first process step, a metal foil may be attached to the carrier. Alternatively, this may also be done by the foil manufacturer, and a carrier covered with a metal foil may be used in the first process step.
According to a fourth aspect, the invention relates to a method of manufacturing a laminate substrate for a power package according to the first aspect. The method includes providing a carrier having a first metal layer attached thereto, wherein the first metal layer has a first major surface and an opposing second major surface facing the carrier, treating a first photoresist layer on the first major surface of the first metal layer and forming openings in the first photoresist layer, metal plating the openings in the first photoresist layer, removing the first photoresist layer from the first metal layer to form the plurality of conductive pads, applying a laminate or a molding material on the first major surface of the first metal layer and the plurality of conductive pads of the metal plating, and partially removing the laminate or molding material from the first major surface of the first metal layer until the plurality of conductive pads of the metal plating are exposed, applying a second metal layer on the exposed plurality of conductive pads of the metal plating and the partially removed laminate or molding material, wherein the second metal layer has a first major surface and an opposing second major surface, the second photoresist layer is removed from the first major surface and the partially removed from the second metal layer and the exposed metal layer, and partially removing the second metal layer from the second metal layer and the exposed metal layer is partially removed from the first photoresist layer and the second metal layer is partially removed from the second major surface of the metal layer.
Such a method may be used to manufacture a laminate substrate at reduced manufacturing costs.
The embodiments described in this invention introduce a new type of GaN package that is different from existing packages. Advanced laminate substrates are employed, as described herein, rather than half-etched lead frames of conventional laminate substrates.
Drawings
Other embodiments of the invention will be described in conjunction with the following drawings, in which:
FIG. 1a shows a schematic cross-section of a laminate substrate 110 for a power package 100 provided by the present invention;
FIG. 1b illustrates an exemplary package pad layout of the power package 100 shown in FIG. 1 a;
FIG. 1c illustrates an exemplary package footprint of the power package 100 shown in FIG. 1 a;
Fig. 2a shows a schematic cross-section of an overmolded power package 100 with a laminate substrate 110 provided by the first embodiment;
fig. 2b shows a schematic cross-section of an overmolded and exposed power package 100b with a laminate substrate 110 provided by a second embodiment;
Fig. 2c shows a schematic cross-section of an underfill power package 100c with a build-up substrate 110 provided by a third embodiment;
fig. 2d shows a schematic cross-section of an overmolded power package 100d with a laminate substrate 110 provided by a fourth embodiment;
Fig. 2e shows a schematic cross-section of an overmolded and exposed power package 100e with a laminate substrate 110 provided by a fifth embodiment;
fig. 2f shows a schematic cross-section of an underfill power package 100f with a build-up substrate 110 provided by a sixth embodiment;
FIGS. 3 a-3 f are schematic diagrams illustrating an exemplary assembly process for manufacturing a power package using a build-up substrate provided by the present invention;
Fig. 4a to 4c show schematic diagrams of an exemplary die pad layout 400a, an exemplary package pad layout 400b, and an exemplary package base surface 400c of a power package with a build-up substrate provided by the present invention;
Fig. 4d to 4f show schematic diagrams of alternative examples of die pad layout 400d, alternative examples of package pad layout 400e, and alternative examples of package base surface 400f of a power package with a build-up substrate;
FIGS. 4g and 4h show schematic diagrams of exemplary base surfaces 400c, 400h of a power package with a laminate substrate;
FIG. 5 illustrates a top view of a multi-die GaN package 500 in a half-bridge configuration on a build-up substrate provided by one embodiment;
fig. 6a and 6b show top views of the multi-die GaN package 500 of fig. 5, with the source and drain connections (fig. 6 a) and PGRD, VSWH, and VIN connections (fig. 6 b) shown in detail;
FIG. 7 illustrates a top view of a multi-die GaN package 700 integrating drivers and passive devices on a build-up substrate, as provided by one embodiment;
FIG. 8 illustrates a top view of a multi-die GaN package 800 employing a parallel die configuration on a build-up substrate, provided by one embodiment;
fig. 9a and 9b show top views of the multi-die GaN package 800 of fig. 8, with the drain connection (fig. 9 a) and the source connection (fig. 9 b) shown in detail;
fig. 10a to 10h show schematic views of an exemplary process flow for manufacturing a laminated substrate provided by the first embodiment;
Fig. 11a to 11k show schematic views of an exemplary process flow for manufacturing a laminated substrate provided by the second embodiment.
Detailed Description
In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific aspects of the invention which may be practiced. It is to be understood that other aspects may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.
It should be understood that the explanations pertaining to the described methods may also apply equally to the corresponding devices or systems for performing the methods, and vice versa. For example, if a specific method step is described, the corresponding apparatus may comprise means for performing the described method step, even if such means are not elaborated or illustrated in the figures. Furthermore, it should be understood that features of the various exemplary aspects described herein may be combined with each other, unless explicitly stated otherwise.
Fig. 1a shows a schematic cross-section of a laminate substrate 110 for a power package 100 provided by the present invention. Fig. 1b shows an exemplary package pad layout of the power package 100, and fig. 1c shows an exemplary package footprint of the power package 100.
A laminate substrate 110 for a power package 100 is shown in fig. 1 a. The laminated substrate 110 includes an electrically insulating layer 120, a plurality of conductive pads 131a to 131e encapsulated in the electrically insulating layer 120, and a plurality of parallel conductors 132a to 132e.
As shown in fig. 1a, electrically insulating layer 120 has a first major surface 110a and an opposite second major surface 110b.
The plurality of conductive pads 131a to 131e are arranged to form a staggered structure. The conductive pads 131a to 131e extend from the first main surface 110a to the second main surface 110b through the electrically insulating layer 120. As can be seen from the package pad layout shown in fig. 1b, the conductive pads 131 a-131 e are aligned along a first long axis on the second major surface 110b of the electrically insulating layer 120. In the example of fig. 1b, the first long axis is shown as the vertical axis.
A plurality of parallel conductors 132a through 132e are mounted on the second major surface 110b of the electrically insulating barrier 120. As can be seen from the package footprint shown in fig. 1c, the shunt conductors 132 a-132 e are aligned along a second long axis on the second major surface 110b of the electrically insulating layer 120. In the example of fig. 1c, the second long axis is shown as the horizontal axis.
The first major axis is substantially perpendicular to the second major axis at a location on the second major surface 110b of the electrically insulating layer 120, and the respective pads 131 a-131 e electrically connect the respective conductors 132 a-132 e.
As can be seen from fig. 1b, the conductive pads 131a to 131e may be arranged in an interdigitated pattern.
Respective pads of the plurality of conductive pads 131a to 131e may be defined by a length and a width of the respective pads. As can be seen from fig. 1b, the length of the respective pad may be greater than the width of the respective pad.
As can be seen from fig. 1b, the first long axis may extend along the length of the respective pad.
The thickness of the conductive pads 131a to 131e may be generally between 80 μm and 150 μm, and in the range of about 40 μm to 250 μm. These conductive pads 131a to 131e may be made of pre-plated embedded Cu strips or the like. Further details are described below in connection with fig. 4g and 4 h.
As can be seen from fig. 1a, a plurality of conductive pads 131a to 131e may form a via through the electrically insulating layer 120 of the laminate substrate 110.
The plurality of conductive pads 131a to 131e may be formed according to a predetermined electrode pattern of at least one electronic chip 140 included in the power package 100, for example, as shown in fig. 2a to 2f below.
The plurality of conductive pads 131a to 131e and the plurality of parallel conductors 132a to 132e may be covered by an electrically insulating layer 120 at the edges of the laminate substrate 110 to provide lateral electrical insulation of the laminate substrate, for example, as shown in fig. 1b and 1 c. Thus, embodiments in accordance with the present invention provide more freedom in that leads at the edges of the package may be exposed or electrically isolated. On the other hand, in the conventional lead frame method, the leads are always exposed.
At least one of the plurality of conductive pads 131a through 131e may be electrically isolated from at least one other of the plurality of conductive pads 131a through 131e by the electrically insulating layer 120.
Additionally or alternatively, at least one of the plurality of conductors 132 a-132 e may be electrically isolated from at least one other of the plurality of conductors 132 a-132 e by the electrically insulating layer 120. Additional solder masks may be formed on the second major surface 110b, for example, as shown in fig. 10g and 10 h. Such additional solder mask can leave openings only in the basal plane area.
The laminate substrate may be used to fabricate single die and multi-die packages with or without integrated passive devices. For example, the laminate substrate may be used for one or more GaN bare chips having a structure in which source pads and gate pads are alternately arranged. Similar structures and the same design concepts may be used for other types of gate source configurations.
Although the embodiments disclosed herein were developed primarily for packaging GaN die, they could equally be used for other types of lateral current power die, even for vertical current die where Cu clips are used for die backside connection and the like.
The electrically insulating layer 120 may comprise at least one of a laminate or a molded material, or a combination thereof.
Additionally or alternatively, the plurality of conductive pads 131 a-131 e and the plurality of conductors 132 a-132 e may include electroplated Cu structures.
The thickness of the conductive pads 131a to 131e may be generally between 80 μm and 150 μm, and in the range of about 40 μm to 250 μm. These conductive pads 131a to 131e may be made of pre-plated embedded Cu strips or the like. Further details are described below.
The thickness of conductors 132 a-132 e may generally be between 20 μm and 35 μm, and in the range of between about 10 μm and 150 μm. These conductors 132a to 132e may be made of Cu seed layers, electroplated Cu, and the like. Further details are described below.
Fig. 1a to 1c also show a power package 100 with a laminate substrate 110.
The power package 100 includes the laminate substrate 110, at least one electronic chip 140, and an encapsulant 150 encapsulating at least a portion of the at least one electronic chip 140 as described above or an underfill 151 attaching the at least one electronic chip 140 to the laminate substrate 110, for example, as shown below in connection with fig. 2 a-2 f.
The at least one electronic chip 140 includes a first major surface 140a and a second major surface 140b opposite the first major surface 140 a.
The at least one electronic chip 140 comprises at least one first terminal 141 electrically connected to at least one pad 131a of the plurality of conductive pads 131a to 131e and at least one second terminal 142 electrically connected to at least one other pad 131c of the plurality of conductive pads 131a to 131e, for example as shown below in connection with fig. 2a to 2 f.
The second major surface 140b of the at least one electronic chip 140 may face the first major surface 110a of the electrically insulating layer 120.
The at least one first terminal 141 and the at least one second terminal 142 may be disposed on the second main surface 140b of the at least one electronic chip 140, and may be mounted on respective pads of the plurality of conductive pads 131a to 131 e.
The second major surface 140b of the at least one electronic chip 140 may face the second major surface 110b of the electrically insulating layer 120.
The at least one first terminal 141 and the at least one second terminal 142 may be disposed on the second main surface 140b of the at least one electronic chip 140, and may be mounted on respective ones of the plurality of conductors 132a to 132 e.
The at least one electronic chip 140 may include a plurality of sides disposed between the first and second major surfaces 140a, 140b of the at least one electronic chip 140.
The encapsulant 150 may cover the first main surface 140a and the sides of the at least one electronic chip 140.
Alternatively, the first main surface 140a of the at least one electronic chip 140 may be uncovered by the encapsulant 150, and the encapsulant 150 may at least partially cover the sides of the at least one electronic chip 140.
Alternatively, the first main surface 140a of the at least one electronic chip 140 may be uncovered by the underfill 151, and the underfill 151 may partially cover the side surface of the at least one electronic chip 140.
The power package 100 may form a single die GaN package or a multi-die GaN package employing a half-bridge or parallel die configuration with or without drivers and/or passive devices, etc.
The power package 100 may include at least one first solder layer 133a disposed between at least one first terminal 141 and at least one pad 131a of the plurality of conductive pads 131 a-131 e, for example, as shown in fig. 2 a-2 c. The at least one first solder layer 133a may electrically connect the at least one first terminal 141 to at least one pad 131a of the plurality of conductive pads 131a to 131 e. In fig. 2d to 2f, the first solder layer 133a is not directly disposed between the first terminal 141 and the conductive pad 131a, but is indirectly disposed therebetween through the conductor 132 a.
The power package 100 may include at least one second solder layer 133c disposed between the at least one second terminal 142 and at least one other pad 131c of the plurality of conductive pads 131 a-131 e, for example, as shown in fig. 2 a-2 f. The at least one second solder layer 133c may electrically connect the at least one second terminal 142 to at least one other pad 131c of the plurality of conductive pads 131a to 131 e.
The power package 100 may form a leadless frame package.
Fig. 1a depicts the different layers. Layer 101 represents a Cu metallization layer or a bump of Cu, nickel Ni, etc., and so on. The thickness of layer 101 may be between about 8 μm and 12 μm, even between 3 μm and 80 μm, etc. Layer 101 may be made of power metal on a bare chip or non-solderable bumps on top of aluminum copper (AlCu), etc.
Layer 102 represents a solder layer or the like. The thickness of layer 102 may be between about 20 μm and 80 μm, even between 10 μm and 150 μm, etc. Layer 102 may be made of solder bumps, and printed solder or printed solder, etc.
Layer 103 represents the conductive pads 131a to 131e referred to in the present invention and layer 104 represents the shunt conductors 132a to 132e referred to in the present invention. However, layer 103 may also be referred to as a via bar, e.g., a Cu via bar (for flip chip pads), and layer 104 may also be referred to as a pad (for package footprint).
The thickness of layer 103 may be between about 80 μm and 150 μm, even between 40 μm and 250 μm, etc. Layer 103 may be made of pre-plated embedded Cu strips or the like.
The thickness of layer 104 may be between about 20 μm and 35 μm, even between 10 μm and 150 μm, etc. Layer 104 may be made of a Cu seed layer, electroplated Cu, and the like.
Fig. 2 a-2 c and fig. 2 d-2 f illustrate three different types of molding or underfill options. The protection of the die may be accomplished by overmolding as shown in fig. 2a and 2d, e.g., panel level overmolding or smaller sized bar overmolding, and if better top cooling is desired, the die backside may be exposed by grinding or the like, as shown in fig. 2b and 2 e. Overmolding may also be avoided if a conventional underfill process is used, as shown in fig. 2c and 2 f.
The overmolded power package 100 with the laminate substrate 110 shown in fig. 2a corresponds to the power package 100 described above in connection with fig. 1.
In fig. 2a to 2c, at least one electronic chip 140 is mounted on the laminate substrate 110 such that the second main surface 140b of the chip 140 faces the first main surface 110a of the laminate substrate 110. In these embodiments, the shunt conductors 132 a-132 e are exposed at the bottom of the packages 100, 100b, 100 c.
In fig. 2d to 2f, the opposite mounting technique is used, for example flip chip mounting. That is, at least one electronic chip 140 is mounted on the laminate substrate 110 such that the second major surface 140b of the chip 140 faces the second major surface 110b of the laminate substrate 110. In these embodiments, the shunt conductors 132a to 132e are embedded in the encapsulant 150, and the conductive pads 131a to 131e are disposed and exposed at the bottom of the packages 100d, 100e, 100 f.
Fig. 3a to 3f are schematic diagrams illustrating an exemplary assembly process for manufacturing a power package using a build-up substrate provided by the present invention.
This assembly process may be used to fabricate a single die GaN package, such as power package 100d or 100f as described above in connection with fig. 2d and 2e, using flip-chip bonding and build-up substrate 110.
The process option depicted in fig. 3a to 3f is to use a laminate substrate 110 (see fig. 3 a), wherein the footprint and vias 131a to 131e through the substrate 110 are large area Cu strips, which can be produced by an electroplating process, which are then embedded inside a molding material or laminate.
The bond pads of GaN die 140 are located on top of the package. The solders 133a to 133e are printed or coated onto the substrate 110 (see fig. 3 b), the bare chip 140 is picked up and placed on top of the solders 13a to 13e (see fig. 3 c), and then the connection is completed by conventional reflow soldering (see fig. 3 d). After soldering, the bare chip 140 may be protected by overmolding (see fig. 3 e) or underfilling (see fig. 3 f). The bare chip 140 has solder bumps or solderable bumps 104.
Fig. 4 a-4 c show schematic diagrams of an exemplary die pad layout 400a, an exemplary package pad layout 400b, and an exemplary package base plane 400c of a power package with a build-up substrate provided by the present invention. Fig. 4d to 4f show schematic diagrams of alternative examples of die pad layout 400d, alternative examples of package pad layout 400e, and alternative examples of package base surface 400f of a power package with a build-up substrate.
Fig. 4 a-4 f show examples of a bare chip, solder bumps, and package top and bottom. In this variation, the bare chip has a structure in which source lines and drain lines are alternately arranged. Typically, the source and drain lines on the die are too small in distance and width to achieve the correct gap distance or large enough pad size and space for soldering/final assembly on the PCB. To convert the small L/S on the die to the proper L/S at the bottom of the package, two or more layers are required.
Fig. 4a to 4c show 2-layer designs 400a to 400c (substrate top and bottom) in which the drain and source lines of the bare chip are rotated 90 degrees by the package wiring so that the gap can be increased to meet the voltage class requirements. If a 2-layer or 1.5-layer substrate is used (only wiring layer is calculated), the line space and gap can be enlarged without rotating the source line and the drain line on the substrate by 90 degrees.
As shown in fig. 4 d-4 f, alternative pad layouts 400e and base surface designs 400f may also be used depending on the substrate manufacturing process, which are not possible when using a leadframe.
It should be noted that fig. 4 a-4 f are for illustration only, the die design and package base surface design may be modified, e.g., the size, shape, location, and number of source and drain lines on the die and package may be modified. These figures also illustrate a structure in which one or more GaN die have an alternating arrangement of source pads and gate pads, but similar packaging structures and the same design concepts can be used for other types of gate-source configurations.
Although the embodiments disclosed herein were developed primarily for packaging GaN die, they could equally be used for other types of lateral current power die, even for vertical current die where Cu clips are used for die backside connection and the like.
Fig. 4g and 4h show schematic diagrams of exemplary base surfaces 400c, 400h of a power package with a laminate substrate.
The drain and source pads and the gate pad of the package footprint may be arranged in rows as shown in fig. 4g or may be arranged as separate pads as shown in fig. 4 f.
In fig. 4g, a minimum of 2 rows can be implemented. Fig. 4g shows n rows. The maximum number of rows may depend on the package size and voltage class. Taking a package size of 5 x 6mm, a voltage of 50 to 150V as an example, the maximum number of rows is 5.
Fig. 4g shows exemplary 5 rows and exemplary 5 columns. In the example of fig. 4g, a minimum of 2 rows may be implemented. The maximum number of rows may depend on the package size and voltage class. Taking a package size of 5 x 6mm, a voltage of 50 to 150V as an example, the maximum number of rows is 5. In the example of fig. 4f, a minimum of 2 columns may be implemented. The maximum number of columns may depend on the package size. Taking the package size of 5 x 6mm as an example, the maximum number of columns is 5.
In fig. 4g, W 1a represents a source line width or a drain line width in which the source or the drain and the gate are in the same row. W 1a may depend on the package width and the maximum package width. In fig. 4g, W 1b represents a source line width or a drain line width when the sources or the drains are aligned without the gate. W 1b may depend on the package width and the maximum package width. Typical values may be 200 μm to 400 μm or less than the package width, etc. An exemplary range of W 1b may be 0 μm to 600 μm less than the package width.
In fig. 4g, W 2 represents the width of 1 or 2 gate pads. The pad locations may be located at corners or in the middle depending on the die design. Typical values of W 2 may be 400 μm to 600 μm, etc. An exemplary range of W 2 may be 300 μm to 1200 μm, etc.
In fig. 4h, W 3 denotes the width of the pads in the matrix, which may be square, rectangular or circular. Typical values of W 3 may be 400 μm to 600 μm, etc. An exemplary range of W 3 may be 300 μm to 1200 μm, etc.
In fig. 4g and 4H, H represents a pad height. Typical values of H may be 400 μm to 600 μm etc. An exemplary range of H may be 300 μm to 1200 μm.
In fig. 4g, C represents a gap, possibly depending on the voltage level. Typical values of C may be 0.6mm, etc.
Fig. 5 illustrates a top view of an exemplary multi-die GaN package 500 employing a half-bridge configuration on a build-up substrate, provided by one embodiment. The figure shows die metallization, solder bumps (circles) on the die, and package top metallization. In fig. 5, the HS and LS die have the same size, which is just one example. The locations and connections may be different, as may die sizes and shapes.
In addition to the GaN die, the multi-die GaN package 500 may also include drivers and/or passive components. The fabrication process and embodiments of the multi-die option are the same as for the single die. Fig. 5 shows die metallization, solder bumps, and package top metallization.
In the half-bridge package 500, the right side die 501 is rotated 180 degrees with respect to the left side die 502, and the half-bridge connection is completed by package wiring. It can be seen from fig. 5 how the source line 502a of the left die 502 is connected to the drain line 501b of the right die 501 by solder bumps 503. Both die 501, 502 are designed using the same solder bump 503.
Fig. 6a and 6b show top views of the multi-die GaN package 500 of fig. 5, with the source and drain connections (fig. 6 a) and PGRD, VSWH, and VIN connections (fig. 6 b) shown in detail.
In fig. 6a, the electrical connector of the source line is on the left side and the electrical connector of the drain line is on the right side. Fig. 6b shows in detail three connections of PGRD, VSWH and VIN.
Fig. 7 illustrates a top view of a multi-die GaN package 700 integrating drivers and passive devices on a laminate substrate, provided by one embodiment. The figure shows package top metallization 704, solder bumps 503 (circles) on the die, and package base metallization 703.
In addition to the half-bridge configuration package 500 shown in fig. 5, 6a and 6b, in fig. 7, a driver 701 may also be integrated into the package 700. The base surface of package 700 is labeled 702.
Fig. 8 illustrates a top view of a multi-die GaN package 800 employing a parallel die configuration on a laminate substrate, according to one embodiment.
Fig. 8 illustrates that embodiments of the invention may be used to fabricate packages with die in parallel. The parallel connection of power die can reduce RDSon and reduce conduction losses. The parallel connection can also achieve higher currents if the chip size is limited (e.g., siC). The fabrication process and embodiments of the multi-die option are the same as for the single die.
Fig. 8 shows the connection between two bare chips 801, 802. As in the half-bridge package, in the parallel bare chip package, the right bare chip 801 is rotated 180 degrees with respect to the left bare chip 802, and connection between the bare chips is completed by package wiring.
Fig. 8 shows how the sources, drains and gates of two bare chips 801, 802 are connected to each other by short lines 803a, 803b, 803 c. By proper ground plane design, the gate, source and drain connections to the PCB can be balanced.
Fig. 9a and 9b show top views of the multi-die GaN package 800 of fig. 8, with the drain connection (fig. 9 a) and the source connection (fig. 9 b) shown in detail.
Fig. 10a to 10h show schematic diagrams of an exemplary process flow for manufacturing the laminated substrate 110 provided in the first embodiment.
These figures depict fabrication and PCB structures to fabricate the laminate substrate 110 for GaN using a simplified and cost-optimized fabrication process.
The process flow represents a simple process that can use existing processes, but all unnecessary process steps are skipped compared to conventional process flows to reduce processing time and processing costs.
This process uses a carrier 1001 in which a Cu seed layer 1010 (with an exemplary thickness of about 1 μm to 150 μm) is attached to a temporary carrier 1011 shown in fig. 10 a.
The first step after the manufacture of the carrier (temporary carrier 1011+ cu foil 1010) is the lithographic process 1002 shown in fig. 10 b. A large area opening 1013 is fabricated on the photoresist 1012 by a photolithographic process. These large area openings 1013 form through holes through the package and the substrate footprint.
After the Cu pattern plating 1003 shown in fig. 10c is performed, the resist is removed 1004 as shown in fig. 10d, and the PCB material 1014 is laminated 1005 or a molding material is molded over the plated Cu 131a to 131e as shown in fig. 10 e.
As can be seen from fig. 10f, the electroplated Cu structure is exposed from the top by a grinding or milling process.
After exposing the large area electroplated Cu strips 131 a-131 e, the temporary carrier 1011 is removed 1006 as shown in fig. 10f, and after performing the photolithography step 1007 shown in fig. 10g, the Cu carrier 1010 is etched 1008 to form the top or bottom of the package shown in fig. 10 h. The final step is an optional solder mask and surface treatment (solderable surfaces, e.g., ENIG, etc.)
The laminated substrate 110 described above in connection with fig. 1 and 2a to 2f may be manufactured through the processes shown in fig. 10a to 10 h.
The process flow shown in fig. 10 a-10 h may be described by a method 1000 of manufacturing a laminate substrate 110 for a power package 100, e.g., as described above in connection with fig. 1 and 2 a-2 f, the method 1000 comprising the steps of:
Providing 1001 a carrier 1011 to which a metal layer 1010 is attached, wherein the metal layer 1010 has a first main surface 1010a and an opposite second main surface 1010b facing the carrier;
processing 1002 a first photoresist layer 1012 on a first major surface of the metal layer and forming openings 1013 in the first photoresist layer;
performing metal electroplating 1003 on the opening in the first photoresist layer;
Removing 1004 the first photoresist layer to form a plurality of conductive pads 131a to 131e;
Applying 1005 a laminate or molding material 1014 over the first major surface of the metal layer and the plurality of metal plated conductive pads 131 a-131 e;
removing 1006 the laminate or molding material from the first major surface portion of the metal layer until the metal plated plurality of conductive pads 131a through 131e are exposed and removing the carrier from the second major surface of the metal layer;
processing 1007 the second photoresist layer on the second major surface of the metal layer and forming an opening in the second photoresist layer;
The metal layer is removed 1008 from the opening of the second photoresist layer and the second photoresist layer is removed from the second major surface of the metal layer to form the plurality of conductors 132a through 132e.
In addition to or instead of the conventional PCB patterning process (photolithography + etch + resist removal, wherein the resist is used as an etch mask) described in step 1007, step 1008, a pattern plating process (photolithography + plating + resist removal + etch, wherein the resist is used as a plating mask and the plating pattern is used as an etch mask) may also be used.
In a first process step 1001, a metal foil 1010 may be attached to a carrier 1011. Alternatively, this may be done by the foil manufacturer and a carrier 1011 covered with a metal foil 1010 may be used in the first process step 1001.
Fig. 11a to 11k show schematic views of an exemplary process flow for manufacturing a laminated substrate provided by the second embodiment.
These figures depict fabrication and PCB structures to fabricate the laminate substrate 110 for GaN using a simplified and cost-optimized fabrication process.
The process flow represents a simple process that can use existing processes, but all unnecessary process steps are skipped compared to conventional process flows to reduce processing time and processing costs.
The process shown in fig. 11a to 11k also uses a carrier 1101, wherein a Cu seed layer 1110 is attached to a temporary carrier 1111. The first step 1102 after the manufacture 1101 of the carrier (temporary carrier 1111+ cu foil 1110) is a lithographic process 1102. Through the photolithography process 1102, a large area opening 1113 is fabricated on the photoresist 1112. These large area openings 1113 form through holes through the package and substrate footprint.
After Cu pattern plating 1103 is performed, the resist is removed 1104, and PCB material is laminated 1105 or a molding material is molded over the plated Cu 131a to 131 e. The electroplated Cu structures 131a to 131e are exposed from the top by a grinding or milling process, as shown in fig. 11 e.
After exposing the large area electroplated Cu strips, a seed layer 1115 is sputtered 1106 on the exposed side of the panel as shown in fig. 11 f. Followed by a photolithography process 1107, a pattern plating process 1108, a resist removal process 1109, and a seed layer etching process 1120.
Prior to the optional solder mask and surface treatment process (solderable surfaces, e.g., ENIG, etc.), temporary Cu carrier 1111 is removed 1121 as shown in fig. 11k, and the seed layer is etched or structured 1120 as shown in fig. 11 j.
The laminated substrate 110 described above in connection with fig. 1 and 2 a-2 f may be manufactured by the process shown in fig. 11 a-11 k.
The process flow shown in fig. 11 a-11 k may be described by a method 1100 of manufacturing a laminate substrate 110 for a power package 100, e.g., as described above in connection with fig. 1 and 2 a-2 f, the method 1100 comprising the steps of:
providing 1101 a carrier 1111 having a first metal layer 1110 attached thereto, wherein the first metal layer has a first major surface and an opposite second major surface facing the carrier 1111;
Processing 1102 a first photoresist layer 1112 on the first major surface of the first metal layer and forming an opening 1113 in the first photoresist layer;
Performing metal electroplating 1103 on the opening in the first photoresist layer;
removing 1104 the first photoresist layer from the first metal layer to form a plurality of conductive pads 131a to 131e;
applying 1105 a laminate or molding material 1114 over the first major surface of the first metal layer and the plurality of metal plated conductive pads 131a to 131e and removing the laminate or molding material from the first major surface portion of the first metal layer until the plurality of metal plated conductive pads 131a to 131e are exposed;
Applying 1106 a second metal layer 1115 over the exposed metal plated plurality of conductive pads 131 a-131 e and the partially removed laminate or molding material, wherein the second metal layer has a first major surface 1115a and an opposing second major surface 1115b, the second major surface 1115b facing the exposed metal plated plurality of conductive pads 131 a-131 e and the partially removed laminate or molding material;
Processing 1107 a second photoresist layer 1116 on the first major surface of the second metal layer and forming openings 1117 in the second photoresist layer;
performing metal plating 1108 on the opening in the second photoresist layer;
Removing 1109 the second photoresist layer from the first major surface of the second metal layer to form a plurality of conductors 132a through 132e;
Removing 1120 the second metal layer from the laminate or molding material;
the carrier and the first metal layer are removed 1121.
The carrier and the first metal layer may also remain at least partially in the final structure, for example by means of a photolithographic and etching process. This may be the same as the process described above in connection with fig. 10g and 10 h.
While a particular feature or aspect of the invention may have been disclosed with respect to only one of several implementations, such feature or aspect may be combined with one or more other features or aspects of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms "includes," has, "" having, "or other variants thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term" comprising. Also, the terms "exemplary," "such as," and "for example," are merely meant as examples, rather than as being best or optimal. The terms "coupled" and "connected," along with their derivatives, may be used. It should be understood that these terms may be used to indicate that two elements co-operate or interact with each other regardless of whether they are in direct physical or electrical contact or they are not in direct contact with each other.
Although specific aspects have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific aspects shown and described without departing from the scope of the present application. This disclosure is intended to cover any adaptations or variations of the specific aspects discussed herein.
Although elements in the following claims are recited in a particular order with corresponding labeling, unless the claim recitations otherwise imply a particular order for implementing some or all of those elements, those elements are not necessarily limited to being implemented in that particular order.
Many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the above teachings. Of course, those skilled in the art will readily recognize that there are numerous other applications of the present invention in addition to those described herein. While the invention has been described in connection with one or more specific embodiments, those skilled in the art will recognize that many changes may be made thereto without departing from the scope of the present invention. It is, therefore, to be understood that within the scope of the appended claims and equivalents thereof, the invention may be practiced otherwise than as specifically described herein.

Claims (17)

1.一种用于功率封装件(100)的积层基板(110)，其特征在于，所述积层基板(110)包括：1. A build-up substrate (110) for a power package (100), characterized in that the build-up substrate (110) comprises: 具有第一主表面(110a)和相对的第二主表面(110b)的电绝缘层(120)；an electrically insulating layer (120) having a first major surface (110a) and an opposing second major surface (110b); 封装在所述电绝缘层(120)中的多个导电焊盘(131a至131e)，其中，所述多个导电焊盘(131a至131e)设置为形成交错结构，所述导电焊盘穿过所述电绝缘层(120)从所述第一主表面(110a)延伸到所述第二主表面(110b)，所述导电焊盘(131a至131e)沿着所述电绝缘层(120)的所述第二主表面(110b)上的第一长轴对齐；A plurality of conductive pads (131a to 131e) encapsulated in the electrical insulation layer (120), wherein the plurality of conductive pads (131a to 131e) are arranged to form a staggered structure, the conductive pads extend from the first main surface (110a) to the second main surface (110b) through the electrical insulation layer (120), and the conductive pads (131a to 131e) are aligned along a first long axis on the second main surface (110b) of the electrical insulation layer (120); 安装在所述电绝缘层(120)的所述第二主表面(110b)上的多个并联导体(132a至132e)，其中，所述并联导体(132a至132e)沿着所述电绝缘层(120)的所述第二主表面(110b)上的第二长轴对齐，a plurality of parallel conductors (132a to 132e) mounted on the second major surface (110b) of the electrical insulating layer (120), wherein the parallel conductors (132a to 132e) are aligned along a second long axis on the second major surface (110b) of the electrical insulating layer (120), 所述第一长轴在所述电绝缘层(120)的所述第二主表面(110b)上的位置处与所述第二长轴基本上垂直，相应焊盘(131a至131e)电连接相应导体(132a至132e)。The first long axis is substantially perpendicular to the second long axis at a position on the second major surface (110b) of the electrical insulating layer (120), and the corresponding pads (131a to 131e) are electrically connected to the corresponding conductors (132a to 132e). 2.根据权利要求1所述的积层基板(110)，其特征在于，2. The build-up substrate (110) according to claim 1, characterized in that: 所述导电焊盘(131a至131e)设置为交叉指状图案。The conductive pads (131a to 131e) are arranged in an interdigitated pattern. 3.根据权利要求1或2所述的积层基板(110)，其特征在于，3. The build-up substrate (110) according to claim 1 or 2, characterized in that: 所述多个导电焊盘(131a至131e)中的相应焊盘由所述相应焊盘的长度和宽度限定；A corresponding pad among the plurality of conductive pads (131a to 131e) is defined by a length and a width of the corresponding pad; 所述相应焊盘的所述长度大于所述相应焊盘的所述宽度；The length of the corresponding pad is greater than the width of the corresponding pad; 所述第一长轴沿着所述相应焊盘的所述长度方向延伸。The first major axis extends along the length direction of the corresponding pad. 4.根据上述权利要求中任一项所述的积层基板(110)，其特征在于，4. The laminate substrate (110) according to any one of the preceding claims, characterized in that: 所述多个导电焊盘(131a至131e)形成穿过所述积层基板(110)的所述电绝缘层(120)的通孔。The plurality of conductive pads (131a to 131e) form through holes penetrating the electrical insulating layer (120) of the build-up substrate (110). 5.根据上述权利要求中任一项所述的积层基板(110)，其特征在于，5. The laminate substrate (110) according to any one of the preceding claims, characterized in that: 所述多个导电焊盘(131a至131e)根据所述功率封装件(100)中包括的至少一个电子芯片(140)的预定电极图案形成。The plurality of conductive pads (131a to 131e) are formed according to a predetermined electrode pattern of at least one electronic chip (140) included in the power package (100). 6.根据上述权利要求中任一项所述的积层基板(110)，其特征在于，6. The laminate substrate (110) according to any one of the preceding claims, characterized in that: 所述多个导电焊盘(131a至131e)和所述多个并联导体(132a至132e)在所述积层基板(110)的边缘处被所述电绝缘层(120)覆盖，以提供所述积层基板的横向电绝缘。The plurality of conductive pads (131a to 131e) and the plurality of parallel conductors (132a to 132e) are covered by the electrical insulation layer (120) at the edge of the build-up substrate (110) to provide lateral electrical insulation of the build-up substrate. 7.根据上述权利要求中任一项所述的积层基板(110)，其特征在于，7. The laminate substrate (110) according to any one of the preceding claims, characterized in that: 所述多个导电焊盘(131a至131e)中的至少一个焊盘通过所述电绝缘层(120)与所述多个导电焊盘(131a至131e)中的至少一个其它焊盘电隔离；和/或At least one of the plurality of conductive pads (131a to 131e) is electrically isolated from at least one other of the plurality of conductive pads (131a to 131e) by the electrical insulation layer (120); and/or 所述多个导体(132a至132e)中的至少一个导体通过所述电绝缘层(120)与所述多个导体(132a至132e)中的至少一个其它导体电隔离。At least one conductor of the plurality of conductors (132a to 132e) is electrically isolated from at least one other conductor of the plurality of conductors (132a to 132e) by the electrical insulation layer (120). 8.根据上述权利要求中任一项所述的积层基板(110)，其特征在于，8. The laminate substrate (110) according to any one of the preceding claims, characterized in that: 所述电绝缘层(120)包括层压材料或成模材料中的至少一种或组合；和/或The electrical insulating layer (120) comprises at least one or a combination of a laminate material or a molded material; and/or 所述多个导电焊盘(131a至131e)和所述多个导体(132a至132e)包括电镀的Cu结构。The plurality of conductive pads (131a to 131e) and the plurality of conductors (132a to 132e) include a plated Cu structure. 9.一种功率封装件(100)，其特征在于，包括：9. A power package (100), characterized by comprising: 根据上述权利要求中任一项所述的积层基板(110)；A laminate substrate (110) according to any one of the preceding claims; 包括第一主表面(140a)和与所述第一主表面(140a)相对的第二主表面(140b)的至少一个电子芯片(140)，其中，所述至少一个电子芯片(140)包括电连接到所述多个导电焊盘(131a至131e)中的至少一个焊盘(131a)的至少一个第一端子(141)和电连接到所述多个导电焊盘(131a至131e)中的至少一个其它焊盘(131c)的至少一个第二端子(142)；以及At least one electronic chip (140) comprising a first main surface (140a) and a second main surface (140b) opposite to the first main surface (140a), wherein the at least one electronic chip (140) comprises at least one first terminal (141) electrically connected to at least one pad (131a) of the plurality of conductive pads (131a to 131e) and at least one second terminal (142) electrically connected to at least one other pad (131c) of the plurality of conductive pads (131a to 131e); and 封装所述至少一个电子芯片(140)的至少一部分的密封剂(150)；或者将所述至少一个电子芯片(140)附着到所述积层基板(110)的底部填充(151)。an encapsulant (150) encapsulating at least a portion of the at least one electronic chip (140); or an underfill (151) attaching the at least one electronic chip (140) to the build-up substrate (110). 10.根据权利要求9所述的功率封装件(100)，其特征在于，10. The power package (100) according to claim 9, characterized in that: 所述至少一个电子芯片(140)的所述第二主表面(140b)朝向所述电绝缘层(120)的所述第一主表面(110a)；The second main surface (140b) of the at least one electronic chip (140) faces the first main surface (110a) of the electrical insulation layer (120); 所述至少一个第一端子(141)和所述至少一个第二端子(142)设置在所述至少一个电子芯片(140)的所述第二主表面(140b)上，并且安装在所述多个导电焊盘(131a至131e)的相应焊盘上。The at least one first terminal (141) and the at least one second terminal (142) are arranged on the second main surface (140b) of the at least one electronic chip (140) and are mounted on corresponding pads of the plurality of conductive pads (131a to 131e). 11.根据权利要求9所述的功率封装件(100)，其特征在于，11. The power package (100) according to claim 9, characterized in that: 所述至少一个电子芯片(140)的所述第二主表面(140b)朝向所述电绝缘层(120)的所述第二主表面(110b)；The second main surface (140b) of the at least one electronic chip (140) faces the second main surface (110b) of the electrical insulation layer (120); 所述至少一个第一端子(141)和所述至少一个第二端子(142)设置在所述至少一个电子芯片(140)的所述第二主表面(140b)上，并且安装在所述多个导体(132a至132e)中的相应导体上。The at least one first terminal (141) and the at least one second terminal (142) are disposed on the second main surface (140b) of the at least one electronic chip (140) and are mounted on corresponding conductors among the plurality of conductors (132a to 132e). 12.根据权利要求9至11中任一项所述的功率封装件(100)，其特征在于，12. The power package (100) according to any one of claims 9 to 11, characterized in that: 所述至少一个电子芯片(140)包括设置在所述至少一个电子芯片(140)的所述第一主表面(140a)和所述第二主表面(140b)之间的多个侧面；以及The at least one electronic chip (140) comprises a plurality of side surfaces disposed between the first main surface (140a) and the second main surface (140b) of the at least one electronic chip (140); and 所述密封剂(150)覆盖所述至少一个电子芯片(140)的所述第一主表面(140a)和所述侧面；或者The sealant (150) covers the first main surface (140a) and the side surfaces of the at least one electronic chip (140); or 所述至少一个电子芯片(140)的所述第一主表面(140a)未被所述密封剂(150)覆盖，所述密封剂(150)至少部分覆盖所述至少一个电子芯片(140)的所述侧面；或者The first main surface (140a) of the at least one electronic chip (140) is not covered by the sealant (150), and the sealant (150) at least partially covers the side surface of the at least one electronic chip (140); or 所述至少一个电子芯片(140)的所述第一主表面(140a)未被所述底部填充(151)覆盖，所述底部填充(151)部分覆盖所述至少一个电子芯片(140)的所述侧面。The first main surface (140a) of the at least one electronic chip (140) is not covered by the bottom fill (151), and the bottom fill (151) partially covers the side surface of the at least one electronic chip (140). 13.根据权利要求9至12中任一项所述的功率封装件(100)，其特征在于，13. The power package (100) according to any one of claims 9 to 12, characterized in that: 形成采用带或不带驱动器和/或无源器件的半桥或并联裸芯片配置的单裸芯片GaN封装件或多裸芯片GaN封装件。Form single die GaN packages or multi-die GaN packages in half-bridge or parallel die configurations with or without drivers and/or passives. 14.根据权利要求9至13中任一项所述的功率封装件(100)，其特征在于，包括：14. The power package (100) according to any one of claims 9 to 13, characterized by comprising: 设置在所述至少一个第一端子(141)和所述多个导电焊盘(131a至131e)中的所述至少一个焊盘(131a)之间的至少一个第一焊料层(133a)，其中，所述至少一个第一焊料层(133a)将所述至少一个第一端子(141)电连接到所述多个导电焊盘(131a至131e)中的所述至少一个焊盘(131a)；和/或At least one first solder layer (133a) is disposed between the at least one first terminal (141) and the at least one pad (131a) among the plurality of conductive pads (131a to 131e), wherein the at least one first solder layer (133a) electrically connects the at least one first terminal (141) to the at least one pad (131a) among the plurality of conductive pads (131a to 131e); and/or 设置在所述至少一个第二端子(142)和所述多个导电焊盘(131a至131e)中的所述至少一个其它焊盘(131c)之间的至少一个第二焊料层(133c)，其中，所述至少一个第二焊料层(133c)将所述至少一个第二端子(142)电连接到所述多个导电焊盘(131a至131e)中的所述至少一个其它焊盘(131c)。At least one second solder layer (133c) is arranged between the at least one second terminal (142) and the at least one other pad (131c) among the multiple conductive pads (131a to 131e), wherein the at least one second solder layer (133c) electrically connects the at least one second terminal (142) to the at least one other pad (131c) among the multiple conductive pads (131a to 131e). 15.根据权利要求9至14中任一项所述的功率封装件(100)，其特征在于，15. The power package (100) according to any one of claims 9 to 14, characterized in that: 形成无引线框封装件。A leadframe-less package is formed. 16.一种制造根据权利要求1至7中任一项所述的用于功率封装件(100)的积层基板(110)的方法(1000)，其特征在于，所述方法包括：16. A method (1000) for manufacturing a build-up substrate (110) for a power package (100) according to any one of claims 1 to 7, characterized in that the method comprises: 提供(1001)附着有金属层(1010)的载体(1011)，其中，所述金属层(1010)具有第一主表面(1010a)和朝向所述载体的相对的第二主表面(1010b)；Providing (1001) a carrier (1011) having a metal layer (1010) attached thereto, wherein the metal layer (1010) has a first main surface (1010a) and an opposite second main surface (1010b) facing the carrier; 在所述金属层的所述第一主表面上处理(1002)第一光刻胶层(1012)，并且在所述第一光刻胶层中形成开口(1013)；processing (1002) a first photoresist layer (1012) on the first major surface of the metal layer, and forming an opening (1013) in the first photoresist layer; 对所述第一光刻胶层中的所述开口进行金属电镀(1003)；Performing metal electroplating on the opening in the first photoresist layer (1003); 去除(1004)所述第一光刻胶层以形成所述多个导电焊盘(131a至131e)；removing (1004) the first photoresist layer to form the plurality of conductive pads (131a to 131e); 在所述金属层的所述第一主表面和所述金属电镀的多个导电焊盘(131a至131e)上施加(1005)层压材料或成模材料(1014)；applying (1005) a laminating or molding material (1014) onto the first major surface of the metal layer and the plurality of metal-plated conductive pads (131a to 131e); 从所述金属层的所述第一主表面部分去除(1006)所述层压材料或成模材料，直到所述金属电镀的多个导电焊盘(131a至131e)外露，并且从所述金属层的所述第二主表面去除所述载体；removing (1006) the laminate or molding material from the first major surface portion of the metal layer until the plurality of metal-plated conductive pads (131a to 131e) are exposed, and removing the carrier from the second major surface of the metal layer; 在所述金属层的所述第二主表面上处理(1007)第二光刻胶层，并且在所述第二光刻胶层中形成开口；processing (1007) a second photoresist layer on the second major surface of the metal layer and forming an opening in the second photoresist layer; 从所述第二光刻胶层的所述开口去除(1008)所述金属层，并且从所述金属层的所述第二主表面去除所述第二光刻胶层以形成所述多个导体(132a至132e)。The metal layer is removed (1008) from the openings of the second photoresist layer, and the second photoresist layer is removed from the second major surface of the metal layer to form the plurality of conductors (132a to 132e). 17.一种制造根据权利要求1至8中任一项所述的用于功率封装件(100)的积层基板(110)的方法(1100)，其特征在于，所述方法包括：17. A method (1100) for manufacturing a build-up substrate (110) for a power package (100) according to any one of claims 1 to 8, characterized in that the method comprises: 提供(1101)附着有第一金属层(1110)的载体(1111)，其中，所述第一金属层具有第一主表面和朝向所述载体(1111)的相对的第二主表面；Providing (1101) a carrier (1111) having a first metal layer (1110) attached thereto, wherein the first metal layer has a first main surface and an opposite second main surface facing the carrier (1111); 在所述第一金属层的所述第一主表面上处理(1102)第一光刻胶层(1112)，并且在所述第一光刻胶层中形成开口(1113)；processing (1102) a first photoresist layer (1112) on the first major surface of the first metal layer, and forming an opening (1113) in the first photoresist layer; 对所述第一光刻胶层中的所述开口进行金属电镀(1103)；Performing metal electroplating on the opening in the first photoresist layer (1103); 从所述第一金属层去除(1104)所述第一光刻胶层以形成所述多个导电焊盘(131a至131e)；removing (1104) the first photoresist layer from the first metal layer to form the plurality of conductive pads (131a to 131e); 在所述第一金属层的所述第一主表面和所述金属电镀的多个导电焊盘(131a至131e)上施加(1105)层压材料或成模材料(1114)，并且从所述第一金属层的所述第一主表面部分去除所述层压材料或成模材料，直到所述金属电镀的多个导电焊盘(131a至131e)外露；Applying (1105) a laminate or molding material (1114) on the first major surface of the first metal layer and the plurality of metal-plated conductive pads (131a to 131e), and removing the laminate or molding material from the first major surface portion of the first metal layer until the plurality of metal-plated conductive pads (131a to 131e) are exposed; 在所述外露的金属电镀的多个导电焊盘(131a至131e)和所述部分去除的层压材料或成模材料上施加(1106)第二金属层(1115)，其中，所述第二金属层具有第一主表面(1115a)和相对的第二主表面(1115b)，所述第二主表面(1115b)朝向所述外露的金属电镀的多个导电焊盘(131a至131e)和所述部分去除的层压材料或成模材料；Applying (1106) a second metal layer (1115) on the exposed metal-plated plurality of conductive pads (131a to 131e) and the partially removed laminate or molding material, wherein the second metal layer has a first major surface (1115a) and an opposing second major surface (1115b), the second major surface (1115b) facing the exposed metal-plated plurality of conductive pads (131a to 131e) and the partially removed laminate or molding material; 在所述第二金属层的所述第一主表面上处理(1107)第二光刻胶层(1116)，并且在所述第二光刻胶层中形成开口(1117)；processing (1107) a second photoresist layer (1116) on the first major surface of the second metal layer and forming an opening (1117) in the second photoresist layer; 对所述第二光刻胶层中的所述开口进行金属电镀(1108)；performing metal electroplating on the opening in the second photoresist layer (1108); 从所述第二金属层的所述第一主表面去除(1109)所述第二光刻胶层以形成所述多个导体(132a至132e)；removing (1109) the second photoresist layer from the first major surface of the second metal layer to form the plurality of conductors (132a to 132e); 从所述层压材料或成模材料去除(1120)所述第二金属层；removing (1120) the second metal layer from the laminate or molded material; 去除(1121)所述载体和所述第一金属层。The carrier and the first metal layer are removed (1121).
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