CN119668389A - Chip state control method, chip state control circuit and NFC device - Google Patents

Abstract

The present disclosure relates to a chip state control method, a chip state control circuit, and an NFC device, the method including determining a current state of a bus in response to a sleep enable command; and judging whether to limit the slave device chip to be adjusted to a sleep state based on the current state of the bus to form a judging result, and adjusting the working state of the slave device chip based on the judging result. The method aims at judging by means of the current state of the bus before the slave device chip is adjusted to a sleep state, ensuring that no data transmission is performed, preventing data from being lost or damaged and improving the reliability of the system.

Description

Chip state control method, chip state control circuit and NFC equipment

Technical Field

The disclosure relates to the field of communication technologies, and in particular, to a chip state control method, a chip state control circuit and an NFC device.

Background

I2C is used as a universal peripheral interface with strong adaptability and wide application range, but has weak functionality and slower speed, and the request state of the slave cannot be completed from the self bus and does not support multi-master multi-slave communication. For hot plug (the slave is abnormally disconnected in a connection state, the master is required to have the capability of recovering the slave state), the slave is not adapted, and the slave is connected to the bus protocol again after the slave is disconnected, so that the normal work can not be guaranteed to be continued.

Thus, based on the shortcomings of I2C, I3C is generated, and two wires are used as in I2C, and meanwhile, the functions of hot plug and slave active interruption are supported, the communication frequency is increased from 3.4MHz to 12.5MHz, and the communication system is compatible.

However, in actual operation, it was found that when I3C IP is integrated in SoC, it has a disadvantage in sleep management, resulting in that the reliability of wake-up and data transmission is affected.

Disclosure of Invention

In order to solve the above technical problems or at least partially solve the above technical problems, the present disclosure provides a chip state control method, a chip state control circuit, and an NFC device.

In a first aspect, the present disclosure provides a chip state control method, which is applicable to a slave device in an I3C communication system, the method including:

determining a current state of the bus in response to the sleep enable command;

judging whether to limit the slave device chip to be adjusted to a sleep state based on the current state of the bus to form a judging result;

And adjusting the working state of the slave device chip based on the judging result.

In a second aspect, the present disclosure further provides a chip status control circuit, where the chip status control circuit is configured in a slave device in an I3C communication system, and the status control circuit includes a judging module and an adjusting signal output module:

the judging module is connected with the I3C bus and is used for judging whether the slave device chip is limited to be adjusted to a sleep state or not based on the current state of the bus and a sleep enabling command to form a judging result;

The adjusting signal output module is connected between the judging module and the slave device and is used for forming a state adjusting signal based on the judging result so that the slave device chip adjusts the working state of the slave device chip based on the state adjusting signal.

In a third aspect, the present disclosure also provides an NFC device comprising a device host, a controller, and a secure element;

the controller and the safety element are all in communication connection through an I3C bus;

the controller and/or the secure element being adapted to perform the steps of the chip state control method as described above, or

The controller and/or the secure element comprises a chip state control circuit as described above.

Compared with the prior art, the technical scheme provided by the embodiment of the disclosure has the following advantages:

The technical scheme provided by the embodiment of the disclosure comprises the steps of determining the current state of a bus by setting a response to a sleep enabling command, judging whether to limit the slave device chip to be adjusted to the sleep state based on the current state of the bus to form a judging result, and adjusting the working state of the slave device chip based on the judging result.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure.

In order to more clearly illustrate the embodiments of the present disclosure or the solutions in the prior art, the drawings that are required for the description of the embodiments or the prior art will be briefly described below, and it will be obvious to those skilled in the art that other drawings can be obtained from these drawings without inventive effort.

Fig. 1 is a schematic diagram of an I3C communication system according to the present application;

FIG. 2 is a flow chart of a chip state control method provided by the application;

fig. 3 is a schematic structural diagram of a chip status control circuit according to an embodiment of the disclosure;

FIG. 4 is a schematic diagram of another chip status control circuit according to an embodiment of the disclosure;

FIG. 5 is a schematic diagram of another chip status control circuit according to an embodiment of the disclosure;

Fig. 6 is a block diagram of an NFC device according to an embodiment of the present disclosure.

Detailed Description

In order that the above objects, features and advantages of the present disclosure may be more clearly understood, a further description of aspects of the present disclosure will be provided below. It should be noted that, without conflict, the embodiments of the present disclosure and features in the embodiments may be combined with each other.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure, but the present disclosure may be practiced otherwise than as described herein, and it is apparent that the embodiments in the specification are only some, rather than all, of the embodiments of the present disclosure.

As described in the background art, when the I3C IP is integrated in the SoC, the reliability of data transmission is easily affected in the sleep management process.

In view of this, the present application provides a chip state control method. The chip controller is suitable for slave devices in the I3C communication system.

Fig. 1 is a schematic diagram of an I3C communication system according to the present application. The communication system is a multi-master multi-slave system. Specifically, the I3C communication system includes four master devices and 3 slave devices. The chip state control method provided by the application can be executed by at least one of the 3 slave devices.

Fig. 2 is a flowchart of a chip status control method provided by the present application. Referring to fig. 2, the method includes:

S110, responding to the sleep enabling command, and determining the current state of the bus.

In practice, the sleep enable command may be a command that is automatically generated by the slave device after the slave device detects that the preset sleep enable command generating condition is satisfied, and is used to control the slave device to enter a sleep state. The sleep enable command generation conditions are specifically what conditions, and the present application is not limited thereto. Illustratively, the sleep enable command generation condition may include at least one of the slave device not receiving any I3C communication instructions for a continuous preset period of time, the slave device receiving an instruction to enter a sleep state sent by the master device, or the state of the bus being an idle state for a preset period of time.

S120, judging whether to limit the slave device chip to be adjusted to a sleep state based on the current state of the bus, and forming a judging result.

There are various ways to implement this step, and the present application is not limited thereto. The method includes the steps of determining that the slave device chip is limited to be adjusted to a sleep state if the current state of the bus is a busy state, and determining that the slave device chip is not limited to be adjusted to the sleep state if the current state of the bus is an idle state.

S130, adjusting the working state of the slave device chip based on the judging result.

If the judging result is that the slave device chip is not limited to be adjusted to the sleep state, the state of the slave device chip is adjusted to the sleep state. Here, the sleep state is a low power consumption state.

The application determines the current state of the bus by setting the response to the sleep enabling command, judges whether to limit the slave device chip to be adjusted to the sleep state based on the current state of the bus to form a judging result, and adjusts the working state of the slave device chip based on the judging result.

In practical applications, when the slave device is awakened by using the address matching manner, the sleep enable command may be used as the system clock source logic, and may occur asynchronously and simultaneously with the I3C bus clock source logic. For this case, based on the current state of the bus, it is determined whether to limit the slave chip to be adjusted to the sleep state, which is also essentially the processing of asynchronous signals, reducing metastability problems due to asynchronous signals.

On the basis of the technical scheme, optionally, the method can further comprise the step of responding to the wake-up instruction aiming at the slave device chip when the slave device chip is in the sleep state, and adjusting the state of the slave device chip to be in the wake-up state. The purpose of this arrangement is to ensure that the slave chip can wake up in time, determining the normal transfer of data.

Fig. 3 is a schematic structural diagram of a chip status control circuit according to an embodiment of the disclosure. Referring to fig. 3, the chip state control circuit is used in a slave device configured in an I3C communication system, and the state control circuit includes a judging module and an adjusting signal output module. The judging module is connected with the I3C bus and used for judging whether the slave device chip is limited to be adjusted to be in a sleep state based on the current state of the bus and a sleep enabling command to form a judging result, and the adjusting signal output module is connected between the judging module and the slave device and used for forming a state adjusting signal based on the judging result so that the slave device chip adjusts the working state of the slave device chip based on the state adjusting signal.

The technical scheme is that the device comprises a judging module, an adjusting signal output module and a state adjusting signal output module, wherein the judging module is connected with an I3C bus and used for judging whether to adjust a slave device chip into a sleep state based on the current state of the bus and a sleep enabling command to form a judging result, and the adjusting signal output module is connected between the judging module and the slave device and used for forming a state adjusting signal based on the judging result so that the slave device chip adjusts the working state of the device chip based on the state adjusting signal. The method aims at judging by means of the current state of the bus before the slave device chip is adjusted to a sleep state, ensuring that no data transmission is performed, preventing data from being lost or damaged and improving the reliability of the system.

Fig. 4 is a schematic structural diagram of another chip status control circuit according to an embodiment of the disclosure. Referring to fig. 4, in the chip state control circuit, the judging module comprises an and gate, the state adjusting module comprises a first register, a first input end of the and gate is used for accessing a sleep enabling command sleep, a second input end of the and gate is used for accessing a bus current state signal i3c_busy, an output end of the and gate is connected with an input end D of the first register, and an output end Q of the first register is connected with a slave chip.

Further, the reset end R of the first register is connected with a sleep enabling command sleep, or referring to FIG. 4, the state control circuit further comprises a first OR gate, one input end of the first OR gate is connected with the sleep enabling command sleep, and the output end of the OR gate is connected with the reset end R of the first register. The other inputs of the first or gate are used to access other signals, illustratively in fig. 4, "|a_flag" and "|b_flag" are used to represent other signals. The application is not limited as to what other signals are specifically.

With continued reference to fig. 4, after receiving the sleep enable command sleep, the sleep enable command sleep is transmitted to the reset terminal R of the first register, to lock the first register, and the signal output by the output terminal Q of the first register is consistent with the signal input by the input terminal D thereof. The signal input by the input end D of the first register is the logic operation result of the sleep enabling command sleep and the current state i3c_busy of the bus. Specifically, when receiving the sleep enable command sleep, the first input terminal of the and gate is at a high level, and if the current state i3c_busy of the bus is in a busy state, the second input terminal of the and gate is at a high level, and the trans_sleep_reg signal output by the output terminal Q of the first register is used to limit the slave device chip to enter a sleep state. If a sleep enabling command sleep is received, a first input end of the AND gate is at a high level, if a current bus state is in an idle state i3c_busy, a second input end of the AND gate is at a low level, and a trans_sleep_reg signal output by the output end Q of the first register is used for allowing the slave device chip to enter a sleep state, and finally the slave device chip enters the sleep state.

It should be emphasized that, just because the sleep enable command sleep is transmitted to the reset terminal R of the first register, the first register may be locked, so that when the current state of the bus changes, the data transmitted on the bus can be input into the slave device chip, and the slave device chip will not lose the data.

Further, the chip state control circuit further comprises a wake-up module, wherein the wake-up module is used for responding to a wake-up instruction aiming at the slave device chip when the slave device chip is in a sleep state, and adjusting the state of the slave device chip to be in a wake-up state.

There are various specific circuit design methods for the wake-up module, and the application is not limited thereto. The wake-up module includes a second or gate and a second register, where multiple input ends of the second or gate are respectively connected to wake-up instructions from different sources, and an output end of the second or gate is connected to an input end D of the second register, and an output end Q of the second register is connected to the slave device chip, as shown in fig. 5.

In fig. 5, ccc_wakeup and addr_match_wakeup represent wakeup instructions of different sources.

Further, a reset end of the second register is accessed to a sleep enabling command.

The wake-up instruction may be, for example, an instruction for waking up the slave device chip obtained by using address matching, and an instruction for waking up the slave device chip from another source is obtained.

When the slave chip enters a sleep state under the action of a sleep enable command, the sleep enable command sleep locks the second register, and the wake-up instruction obtained from any source is at a high level. When a wake-up instruction from a certain source is received, the output end Q of the second register outputs a high level, and finally the slave device chip is waken up.

The present application also provides an NFC device, see fig. 6, comprising a device host, a controller and a secure element, both the controller and the secure element being communicatively connected via an I3C bus, the controller and/or the secure element being arranged to perform the steps of the chip state control method mentioned in the foregoing, or the controller and/or the secure element comprising the chip state control circuit mentioned in the foregoing.

The NFC device may be a mobile terminal or a computer, and the mobile device may include, for example, a mobile phone, a PAD, a wearable device, a virtual reality device, an internet of things device, a payment device, an access control device, and the like, or any combination thereof. The wearable device comprises a smart watch, a smart bracelet, a pedometer and the like. The NFC equipment can be applied to scenes such as mobile payment, identity authentication, intelligent access control, public transportation ticketing and the like. The analog card can be used for realizing various functions such as mobile payment, identity authentication, intelligent access control, public transportation ticketing and the like.

The controller and/or the secure element are/is used for executing the steps of the chip state control method mentioned in the foregoing in the NFC device submitted by the present application, or the controller and/or the secure element comprise the chip state control circuit mentioned in the foregoing, which has the same or corresponding advantageous effects of the method or circuit included therein, and will not be described in detail herein.

It should be noted that, for simplicity of description, the foregoing method embodiments are all described as a series of acts, but it should be understood by those skilled in the art that the present invention is not limited by the order of acts described, as some steps may be performed in other orders or concurrently in accordance with the present invention. Further, those skilled in the art will also appreciate that the embodiments described in the specification are all preferred embodiments, and that the acts and modules referred to are not necessarily required for the present invention.

It should be noted that in this document, relational terms such as "first" and "second" and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.

The foregoing is merely a specific embodiment of the disclosure to enable one skilled in the art to understand or practice the disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown and described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. A chip state control method, wherein the chip state control method is applicable to a slave device in an I3C communication system, the method comprising:

determining a current state of the bus in response to the sleep enable command;

judging whether to limit the slave device chip to be adjusted to a sleep state based on the current state of the bus to form a judging result;

And adjusting the working state of the slave device chip based on the judging result.

2. The method of claim 1, wherein determining whether to limit the slave device chip from being adjusted to a sleep state based on the current state of the bus, forming a determination result, comprises:

If the current bus state is a busy state, the judging result is that the slave device chip is limited to be adjusted to a sleep state;

and if the current state of the bus is an idle state, the judging result is that the slave device chip is not limited to be adjusted to be in a sleep state.

3. The method as recited in claim 1, further comprising:

And under the condition that the slave device chip is in a sleep state, responding to a wake-up instruction for the slave device chip, and adjusting the state of the slave device chip to be in a wake-up state.

4. The chip state control circuit is used in slave equipment configured in an I3C communication system, and comprises a judging module and an adjusting signal output module:

the judging module is connected with the I3C bus and is used for judging whether the slave device chip is limited to be adjusted to a sleep state or not based on the current state of the bus and a sleep enabling command to form a judging result;

The adjusting signal output module is connected between the judging module and the slave device and is used for forming a state adjusting signal based on the judging result so that the slave device chip adjusts the working state of the slave device chip based on the state adjusting signal.

5. The circuit of claim 4, wherein the determination module comprises an AND gate, and wherein the adjustment signal output module comprises a first register;

The first input end of the AND gate is used for accessing a sleep enabling command, the second input end of the AND gate is used for accessing a bus current state signal, the output end of the AND gate is connected with the input end of the first register, and the output end of the first register is connected with the slave device chip.

6. The circuit of claim 5, wherein the circuit further comprises a logic circuit,

The reset end of the first register is accessed with a sleep enabling command, or

The adjusting signal output module further comprises a first OR gate, one input end of the first OR gate is connected with a sleep enabling command, and the output end of the OR gate is connected with the reset end of the first register.

7. The circuit of claim 4, further comprising a wake module to adjust a state of the slave chip to a wake state in response to a wake instruction for the slave chip if the slave chip is in a sleep state.

8. The circuit of claim 7, wherein the wake-up module comprises a second or gate and a second register;

A plurality of input ends of the second OR gate are respectively connected with wake-up instructions from different sources;

The output end of the second OR gate is connected with the input end of the second register, and the output end of the second register is connected with the slave device chip.

9. The state control circuit of claim 8, wherein,

And a reset end of the second register is accessed to a sleep enabling command.

10. An NFC device, comprising a device host, a controller, and a secure element;

the controller and the safety element are all in communication connection through an I3C bus;

The controller and/or the secure element being adapted to perform the steps of the chip state control method as claimed in any one of claims 1 to 3, or

The controller and/or the secure element comprising the chip state control circuit of any one of claims 4-9.