CN119630137A - Light emitting diode and light emitting device - Google Patents

Abstract

The present invention relates to the field of semiconductor manufacturing technology, and in particular to a light-emitting diode, which comprises an unintentionally doped layer, a first dielectric layer, a first n-type layer, a second n-type layer, a second dielectric layer, a light-emitting layer and a p-type layer stacked in sequence, wherein the doping concentration of the first n-type layer is higher than the doping concentration of the second n-type layer, the first dielectric layer and the second dielectric layer comprise aluminum components, and the aluminum component in the first dielectric layer is higher than the aluminum component in the second dielectric layer. Thus, the light-emitting diode can solve the problems of many internal defects, carrier crowding, and poor ESD performance, thereby improving the quality of the light-emitting diode.

Description

Light emitting diode and light emitting device

Technical Field

The present invention relates to the field of semiconductor manufacturing technology, and in particular, to a light emitting diode and a light emitting device.

Background

A light emitting Diode (LIGHT EMITTING Diode, abbreviated as LED) is a semiconductor light emitting element, and is generally made of a semiconductor such as GaN, gaAs, gaP, gaAsP, and the core thereof is a PN junction having a light emitting characteristic. LEDs have the advantages of high luminous intensity, high efficiency, small volume, long service life, etc., and are considered to be one of the most potential light sources at present. The LED is widely applied to the fields of illumination, monitoring command, high-definition performance, high-end cinema, office display, conference interaction, virtual reality and the like.

At present, light emitting diodes (such as Mini LEDs) with small size are widely used for backlight display to realize more precise dynamic backlight effect. However, the existing small-sized light emitting diode generally has the problems of more defects, carrier crowding and poor ESD performance. Therefore, how to solve the above problems has become one of the technical difficulties that a person skilled in the art needs to solve.

It should be noted that the information disclosed in this background section is only for the purpose of increasing the understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person of ordinary skill in the art.

Disclosure of Invention

The invention provides a light-emitting diode, which comprises a semiconductor lamination layer, wherein the semiconductor lamination layer at least comprises an unintentional doped layer, a first dielectric layer, a first n-type layer, a second dielectric layer, a light-emitting layer and a p-type layer which are sequentially laminated. The first n-type layer has a higher doping concentration than the second n-type layer, and the materials in the first and second dielectric layers include an aluminum composition, the aluminum composition in the first dielectric layer being higher than the aluminum composition in the second dielectric layer.

The invention also provides a light emitting diode which comprises a semiconductor lamination layer, wherein the semiconductor lamination layer at least comprises a first semiconductor layer, a light emitting layer and a second semiconductor layer which are sequentially laminated. The first semiconductor layer at least comprises an unintentional doped layer, a first n-type layer and a second n-type layer, the doping concentration of the first n-type layer is higher than that of the second n-type layer, the first semiconductor layer is provided with an aluminum concentration curve, the aluminum concentration curve at least comprises a first peak shape and a second peak shape, the first peak shape is positioned on one side of the first n-type layer far away from the light emitting layer, and the second peak shape is positioned on one side of the first n-type layer close to the light emitting layer.

The invention also provides a light-emitting device, which comprises a light-emitting diode, wherein the light-emitting diode adopts the light-emitting diode provided by any embodiment.

According to the light emitting diode and the light emitting device provided by the embodiment of the invention, the problems of multiple internal defects, crowding of current carriers and poor ESD performance of the light emitting diode can be solved by inserting the aluminum-containing dielectric layers into the front and rear of the highly doped first n-type layer, so that the quality of the light emitting diode is improved. Specifically, a first dielectric layer with high aluminum content is inserted between the unintentional doping layer and the first n-type layer with high doping, so that the effect of defect shielding is achieved, the ESD performance can be improved, and the reliability of the chip is further improved; the mode of inserting the second dielectric layer with low aluminum content between the second n-type layer with low doping and the light-emitting layer can achieve the effect of defect shielding on one hand, and on the other hand, the wide energy gap material characteristic of the second dielectric layer can be utilized to achieve the effect of electron blocking, so that the phenomenon of carrier crowding is effectively reduced, and meanwhile, the composite light-emitting efficiency of electrons and holes in the light-emitting layer can be improved, and the light-emitting efficiency of the light-emitting diode is improved.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, a brief description will be given below of the drawings required for the embodiments or the prior art descriptions, and it is obvious that some of the drawings in the following description are some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic structural view of a light emitting diode according to a first embodiment of the present invention;

FIG. 2 is a schematic diagram of a composite layer according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of a light emitting diode according to a second embodiment of the present invention;

Fig. 4 is a schematic diagram of an aluminum concentration curve of a light emitting diode according to an embodiment of the present invention.

Reference numerals:

10-substrate, 12-unintentionally doped layer, 14-first dielectric layer, 16-first n-type layer, 18-second n-type layer, 20-second dielectric layer, 22-composite layer, 221-GaN layer, 222-InGaN layer, 24-light emitting layer, 26-p-type layer, 30-n-type electrode, 32-p-type electrode, n 1-first peak shape, n 2-second peak shape.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments, technical features designed in different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other, and all other embodiments obtained by those skilled in the art without making creative efforts on the basis of the embodiments of the present invention are all within the scope of protection of the present invention.

In the description of the present invention, it should be understood that the terms "center," "lateral," "upper," "lower," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like indicate orientations or positional relationships based on the orientation or positional relationships shown in the drawings, merely to facilitate describing the present invention and simplify the description, and do not indicate or imply that the devices or components referred to must have a specific orientation or be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, unless otherwise indicated, the meaning of "a plurality" is two or more. In addition, the term "comprising" and any variations thereof are meant to be "at least inclusive".

An embodiment of the present invention provides a light emitting diode, which includes a semiconductor stack including at least an unintentionally doped layer, a first dielectric layer, a first n-type layer, a second dielectric layer, a light emitting layer, and a p-type layer stacked in order. The doping concentration of the first n-type layer is higher than that of the second n-type layer, the first dielectric layer and the second dielectric layer comprise aluminum components, and the aluminum components in the first dielectric layer are higher than those in the second dielectric layer. The first dielectric layer with high aluminum content is inserted between the unintentional doping layer and the first n-type layer with high doping, so that the effect of shielding defects is achieved, specifically, defects generated in the growth process of the unintentional doping layer are filled by utilizing the characteristic that the Al atoms in the first dielectric layer are small in volume, the growth of subsequent structural layers is facilitated, the lattice quality is improved, the leakage risk is reduced, the ESD performance is improved, and the reliability of a chip is further improved; the second dielectric layer with low aluminum content is inserted between the second n-type layer with low doping and the light-emitting layer, so that on one hand, the effect of shielding defects is achieved, defects formed in the growth process of the unintentionally doped layer can be further prevented, new defects generated in the growth process of the first n-type layer with high doping can be prevented, on the other hand, the characteristic of the material with wide energy gap can be utilized, the effect of blocking electrons is achieved, the spatial distribution density of carriers can be improved, the phenomenon of carrier crowding is effectively reduced, meanwhile, the composite light-emitting efficiency of electrons and holes in the light-emitting layer can be improved, and therefore the light-emitting efficiency is improved, and the overall quality of the light-emitting diode is improved. And meanwhile, the aluminum component in the first dielectric layer is controlled to be higher than that in the second dielectric layer, so that the effect of effectively blocking dislocation defects of the first dielectric layer can be ensured, and the possibility of lattice mismatch between the active layer and the second dielectric layer is avoided.

In some embodiments, the material of the first dielectric layer and the second dielectric layer comprises Al _xGa_(1-x) N material, wherein 0< x.ltoreq.1. The materials of the first dielectric layer and the second dielectric layer can be AlN or AlGaN, the characteristic of wide energy gap of AlN or AlGaN is utilized, the effect of isolating electrons is effectively achieved, the carrier space distribution density can be improved, the phenomenon of carrier crowding is effectively reduced, too many and too fast transition of electrons into the p-type layer can be prevented from being subjected to non-radiative recombination with holes, the combination of electrons and holes in the light-emitting layer is facilitated, and the composite light-emitting efficiency of electrons and holes in the light-emitting layer is improved, so that the light-emitting efficiency is improved.

In some embodiments, the aluminum component in the first dielectric layer accounts for 5% -50%, so that the dislocation defect blocking effect of the first dielectric layer is improved. If the aluminum content in the first dielectric layer is too high (e.g., greater than 50%), lattice mismatch may occur, e.g., lattice mismatch occurs between the unintentionally doped layer and the first n-type layer, and if the aluminum content in the first dielectric layer is too low (e.g., less than 5%), the dislocation defect cannot be effectively blocked, and optionally, the aluminum content in the first dielectric layer is 15% -30%, preferably 20% -25%.

In some embodiments, the second dielectric layer is doped with n-type impurities, the doping concentration of the second dielectric layer is less than 1E19atoms/cm ³, and the second dielectric layer is doped with n-type impurities with low concentration, which is beneficial to current diffusion and reduces the operation voltage.

In some embodiments, the first n-type layer has a doping concentration greater than 1E19atoms/cm ³. In some embodiments, the doping concentration of the second n-type layer is less than 1E19atoms/cm ³. The first n-type layer is doped with high-concentration n-type impurities, which is beneficial to current diffusion and reduces the operating voltage, because the flowing direction of current at the first n-type layer is horizontal, when the Si doping concentration is high, the resistance can be effectively reduced, and therefore, the high-doped first n-type layer is more beneficial to current diffusion. And the second n-type layer is a low-doped layer, because the current flows in the vertical direction from the light-emitting layer to the second n-type layer, and the Si doping concentration is low, high resistance can be formed, so that the low doping at the second n-type layer is more beneficial to current diffusion.

In some embodiments, the semiconductor stack further includes a composite layer between the second dielectric layer and the light emitting layer, the composite layer primarily functioning as a transition layer.

In some embodiments, the thickness of the first dielectric layer is greater than the thickness of the second dielectric layer, which is thinner to reduce the possibility of lattice mismatch, and the first dielectric layer is thicker to ensure effective blocking of dislocation defects.

In some embodiments, the first dielectric layer has a thickness in the range of 20-50 nm and the second dielectric layer has a thickness in the range of 15-45 nm. If the first dielectric layer is too thick (e.g., greater than 50 nm), there is a lattice mismatch problem, and if the second dielectric layer is too thin (e.g., less than 15 nm), the dislocation defect may not be effectively blocked.

An embodiment of the present invention provides a light emitting diode, which includes a semiconductor stack including at least a first semiconductor layer, a light emitting layer, and a second semiconductor layer stacked in order. The first semiconductor layer at least comprises an unintentional doped layer, a first n-type layer and a second n-type layer, the doping concentration of the first n-type layer is higher than that of the second n-type layer, the first semiconductor layer is provided with an aluminum concentration curve, the aluminum concentration curve at least comprises a first peak shape and a second peak shape, wherein the first peak shape is positioned on one side of the first n-type layer far away from the light-emitting layer, the second peak shape is positioned on one side of the first n-type layer close to the light-emitting layer, and by forming an Al-containing peak shape before and after the first n-type layer which is highly doped, defects generated in the growth process of the unintentional doped layer and the first n-type layer are filled with Al atoms, the growth of each subsequent structural layer is facilitated, so that lattice quality is improved, the leakage risk is reduced, the ESD performance is improved, the reliability of the chip is further improved, the second Al peak shape can also play the effect of blocking electrons, the space distribution density of the carriers is improved, the phenomenon of the carriers is effectively reduced, the composite light-emitting efficiency of electrons and the holes in the light-emitting layer is improved, and the overall light-emitting efficiency of the light-emitting diode is further improved.

In some embodiments, the first n-type layer has a doping concentration greater than 1E19atoms/cm ³. In some embodiments, the doping concentration of the second n-type layer is less than 1E19atoms/cm ³. By this arrangement, current spreading will be facilitated and the operating voltage will be reduced.

In some embodiments, the maximum value of the first peak shape is greater than the maximum value of the second peak shape, and the first peak shape has a higher Al concentration, so that an effect of effectively blocking defects formed in the growth process of the unintentional doped layer can be ensured, and the second peak shape has a lower Al concentration, so that a problem of lattice mismatch with the light emitting layer can be avoided.

In some embodiments, the maximum value of the first peak shape is not less than 1.5 times the maximum value of the second peak shape, thereby further improving the overall quality of the light emitting diode.

In some embodiments, the first peak shape is located between the unintentional doped layer and the first n-type layer, the second peak shape is located between the first n-type layer and the light-emitting layer, defects generated in the growth process of the unintentional doped layer can be blocked by forming the first peak shape between the unintentional doped layer and the high doped first n-type layer, so that the effect of shielding the defects is achieved, and defects formed in the growth process of the unintentional doped layer and new defects generated in the growth process of the high doped first n-type layer can be further blocked by forming the second peak shape between the high doped first n-type layer and the light-emitting layer.

In some embodiments, the semiconductor stack further includes a composite layer between the second n-type layer and the light emitting layer, the second peak shape being between the first n-type layer and the composite layer. The second peak shape may be formed between the first n-type layer and the composite layer, and the possibility of lattice mismatch with the light emitting layer may be reduced by the composite layer functioning as a transition layer.

In some embodiments, a second peak shape is located between the second n-type layer and the composite layer, and the second peak shape may be formed between the second n-type layer and the composite layer, which may further reduce the possibility of lattice mismatch with the light emitting layer.

In some embodiments, the light emitting diode has a side length of no more than 200 μm, and the light emitting diode is a small-sized light emitting diode.

An embodiment of the invention provides a light emitting device, which is characterized in that the light emitting device comprises a light emitting diode, and the light emitting diode adopts any one of the light emitting diodes.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a light emitting diode according to a first embodiment of the present invention. To achieve at least one of the advantages and other advantages, a first embodiment of the present invention provides a light emitting diode. As shown, the light emitting diode includes a semiconductor stack including at least an unintentionally doped layer 12, a first dielectric layer 14, a first n-type layer 16, a second n-type layer 18, a second dielectric layer 20, a light emitting layer 24, and a p-type layer 26, which are stacked in this order.

An unintentionally doped layer 12 is provided on the substrate 10. The substrate 10 may be a transparent substrate 10 or a translucent substrate 10, wherein the transparent substrate 10 or the translucent substrate 10 may allow light radiated from the light emitting layer 24 to pass through the substrate 10 to a side of the substrate 10 remote from the semiconductor stack, for example, the substrate 10 may be any one of a sapphire flat substrate 10, a sapphire patterned substrate 10, a silicon carbide substrate 10, a gallium nitride substrate 10, a glass substrate 10. In some embodiments, the substrate 10 may be thinned or the thin film-formed chip removed.

The material of the unintentionally doped layer 12 may comprise GaN, which mainly serves as a buffer, which may be used to adjust the lattice difference between the substrate 10 and the first n-type layer 16.

The material of both the first N-type layer 16 and the second N-type layer 18 may be N-type doped nitride material layers, such as GaN layers, that provide electrons by doping N-type impurities, which may include one or a combination of Si, ge, sn, se and Te. Optionally, in this embodiment, the ions doped in the first n-type layer 16 and the second n-type layer 18 comprise silicon. The first n-type layer 16 is a highly doped layer and the second n-type layer 18 is a lowly doped layer compared to the first n-type layer 16 and the second n-type layer 18, i.e. the doping concentration of the first n-type layer 16 is higher than the doping concentration of the second n-type layer 18. The first dielectric layer 14 is arranged to play a role of defect shielding, so that the lattice quality can be improved, the first n-type layer 16 which is doped directly and is doped highly is not needed to be doped firstly and then is graded to be doped highly, and the current diffusion is facilitated due to the high doping concentration, so that the operation voltage is reduced. This is because the Si doping concentration is high, and the resistance can be effectively reduced, and since the flow direction of current at the first n-type layer 16 is a horizontal direction (e.g., flows in the left-to-right direction in the drawing), the low resistance is advantageous for current diffusion. In addition, the second n-type layer 18 is a low doped layer to facilitate current diffusion and reduce operating voltage. The low Si doping concentration results in a high resistance, which is more advantageous for current diffusion because the current flows in the direction of the light emitting layer 24 to the second n-type layer 18 (e.g., in the up-down direction in the figure) and thus low doping is used at the second n-type layer 18.

The materials in the first dielectric layer 14 and the second dielectric layer 20 include an aluminum composition. The first dielectric layer 14 mainly has a defect shielding effect, for example, the first dielectric layer can block defects generated in the growth process of the unintentionally doped layer 12, and because Al atoms are smaller, the defects can be filled by the Al atoms, and the growth of subsequent structural layers is facilitated, so that the lattice quality is improved, the leakage risk is reduced, and the ESD capability and the chip reliability are improved. The second dielectric layer 20 may further block defects formed during the growth of the unintentionally doped layer 12 on the one hand, and the highly doped first n-type layer 16 may also generate new defects during the growth, and the second dielectric layer 20 may serve to block defects newly formed during the growth of the first n-type layer 16 and prevent the defects from extending to the light emitting layer 24 on the other hand. In some embodiments, the characteristic of the wide energy gap can be utilized to effectively isolate electrons, so that the spatial distribution density of carriers can be improved, the phenomenon of carrier crowding can be effectively reduced, and meanwhile, too many and too fast transitions of electrons into the p-type layer 26 to be subjected to non-radiative recombination with holes can be prevented, so that the combination of electrons and holes in the light-emitting layer 24 is facilitated, the composite light-emitting efficiency of the electrons and the holes in the light-emitting layer 24 is improved, and the light-emitting efficiency is improved, and the overall quality of the light-emitting diode is further improved.

The aluminum composition in the first dielectric layer 14 is higher than the aluminum composition in the second dielectric layer 20. By inserting the first dielectric layer 14 with high aluminum content between the unintentionally doped layer 12 and the highly doped first n-type layer 16, a defect shielding effect is achieved, and the relatively high aluminum content in the first dielectric layer 14 can enhance the defect blocking capability. By inserting the second dielectric layer 20 with low aluminum content between the second n-type layer 18 with low doping and the light emitting layer 24, the pit density is reduced, and the characteristic of the wide energy gap material is utilized to play a role in blocking electrons, so that the carrier space distribution density can be improved, the carrier crowding can be effectively reduced, the ESD performance is improved, and the quality of the light emitting diode is improved. The relatively low aluminum composition In the second dielectric layer 20 is to avoid the problem of lattice mismatch between the light emitting layer 24 and the second dielectric layer 20, and considering that the well layer of the light emitting layer 24 is lnGaN and the second dielectric layer 20 is AlGaN, the In atomic ratio is relatively large and the Al atomic ratio is relatively small, if the Al composition is too high, the problem of lattice mismatch between the light emitting layer 24 and the second dielectric layer 20 may occur.

The light emitting layer 24 may be a Quantum Well (QW) structure. In some embodiments, the light emitting layer 24 may also be a multiple quantum Well structure (Multiple Quantum Well, abbreviated as MQW), where the multiple quantum Well structure includes a plurality of quantum Well layers (Well) and a plurality of quantum Barrier layers (Barrier) alternately arranged in a repetitive manner, such as a multiple quantum Well structure that may be GaN/AlGaN, inAlGaN/InAlGaN, inGaN/AlGaN or InGaN/GaN. The composition and thickness of the well layer in the light-emitting layer 24 determine the wavelength of the generated light. To increase the light emitting efficiency of the light emitting layer 24, this may be achieved by varying the depth of the quantum wells, the number of layers, thickness and/or other features of the pairs of quantum wells and quantum barriers in the light emitting layer 24.

The p-type layer 26 may provide holes to the light emitting layer 24 under the power supply. In some embodiments, P-type layer 26 comprises a P-type doped nitride layer. The P-doped nitride layer may include one or more P-type impurities. The P-type impurity may include one or a combination of Mg, zn, be, ca, sr and Ba, and in this embodiment, it is preferable that the P-type impurity is Mg. The p-type layer 26 may have a single-layer structure or a multi-layer structure having different compositions.

In some embodiments, the aluminum component in the first dielectric layer 14 accounts for 5% -50%, so as to improve the effect of blocking dislocation defects of the first dielectric layer 14. If the aluminum content in the first dielectric layer 14 is too high (e.g., greater than 50%), there is a lattice mismatch problem, such as a lattice mismatch between the unintentionally doped layer 12 and the first n-type layer 16, and if the aluminum content in the first dielectric layer 14 is too low (e.g., less than 5%), the dislocation defect can not be effectively blocked, and optionally, the aluminum content in the first dielectric layer 14 is 15% -30%, preferably 20% -25%.

In some embodiments, the material of the first dielectric layer 14 and the second dielectric layer 20 comprises an Al _xGa(_1-x) N material, where 0< x.ltoreq.1. For example, the materials of the first dielectric layer 14 and the second dielectric layer 20 are AlN or AlGaN materials, and by utilizing the characteristic of wide energy gap of AlN or AlGaN, the effect of isolating electrons is effectively achieved, so that the spatial distribution density of carriers can be improved, the phenomenon of carrier crowding can be effectively reduced, too many and too fast transition of electrons into the p-type layer 26 can be prevented from carrying out non-radiative recombination with holes, the combination of electrons and holes in the light-emitting layer 24 is facilitated, the composite light-emitting efficiency of electrons and holes in the light-emitting layer 24 is improved, and the light-emitting efficiency is further improved.

In some embodiments, the second dielectric layer 20 is doped with an n-type impurity, such as silicon. The first dielectric layer 14 is unintentionally doped.

In some embodiments, the doping concentration of the second dielectric layer 20 is less than 1E19atoms/cm ³. Optionally, in some preferred embodiments, the doping concentration of the second dielectric layer 20 is in the range of 1E18atoms/cm ³~1E19atoms/cm³. The second dielectric layer 20 is doped with a low concentration of n-type impurities, which is advantageous for current diffusion and operation voltage reduction.

The doping concentration of the first n-type layer 16 is greater than 1E19atoms/cm ³. The doping concentration of the second n-type layer 18 is less than 1E19atoms/cm ³. Alternatively, in some preferred embodiments, the first n-type layer 16 has a doping concentration in the range of 1E19atoms/cm ³~1E20atoms/cm³ and the second n-type layer 18 has a doping concentration less than 5E18atoms/cm ³. The first n-type layer 16, which is directly doped with high doping concentration, is beneficial to current diffusion and reduces the operation voltage. This is because the Si doping concentration is high, and the resistance can be effectively reduced, and since the flow direction of current at the first n-type layer 16 is a horizontal direction (e.g., flows in the left-to-right direction in the drawing), the low resistance is advantageous for current diffusion. In addition, the second n-type layer 18 is a low doped layer to facilitate current diffusion and reduce operating voltage. The low Si doping concentration results in a high resistance, which is more advantageous for current diffusion because the current flows in the direction of the light emitting layer 24 to the second n-type layer 18 (e.g., in the up-down direction in the figure) and thus low doping is used at the second n-type layer 18.

In some embodiments, the thickness of the first dielectric layer 14 is greater than the thickness of the second dielectric layer 20 to reduce the likelihood of lattice mismatch. And, the thicker first dielectric layer 14 can ensure the effect of effectively blocking dislocation defects, and the thinner second dielectric layer 20 can effectively avoid lattice mismatch. Optionally, the thickness of the first dielectric layer 14 ranges from 20 nm to 50nm, and the thickness of the second dielectric layer 20 ranges from 15nm to 45nm. If the first dielectric layer 14 is too thick (e.g., greater than 50 nm), there is a lattice mismatch problem, and if the second dielectric layer 20 is too thin (e.g., less than 15 nm), it may not be effective in blocking dislocation defects.

In some embodiments, the semiconductor stack further includes a composite layer 22, the composite layer 22 being located between the second dielectric layer 20 and the light emitting layer 24. The composite layer 22 acts primarily as a transition layer.

In some embodiments, the light emitting diode is a small-sized light emitting diode, the light emitting diode having a side length of no more than 200 μm. Generally, in order to improve ESD performance, the existing light emitting diode is usually realized by doping Si into an epitaxial structure or reducing defects, however, in order to avoid too high capacitance, the small-sized light emitting diode is more suitable for improving ESD performance by reducing defects, so that the embodiment can be applied to the small-sized light emitting diode while improving ESD performance. However, the present invention is not limited thereto, and the present invention can be applied to various sizes of light emitting diodes.

Referring to fig. 2, fig. 2 is a schematic structural diagram of a composite layer 22 according to an embodiment of the invention. As shown, the composite layer 22 includes a multi-layered structure of GaN layers 221 and InGaN layers 222 alternately arranged to effectively function as a transition layer. For example, from the second n-type layer 18 to the light emitting layer 24 and from the GaN material to the InGaN material. In some embodiments, the In composition In the composite layer 22 is lower than the light emitting layer 24. However, the present invention is not limited thereto, and the composite layer 22 may be a multi-layer structure formed by alternately arranging the AlGaN layer and the InGaN layer 222.

Referring to fig. 3, fig. 3 is a schematic structural diagram of a light emitting diode according to a second embodiment of the present invention. The main difference between the light emitting diode of the present embodiment and the light emitting diode of the first embodiment is that the light emitting diode further includes an n-type electrode 30 and a p-type electrode 32. An n-type electrode 30 is connected to the first n-type layer 16 and a p-type electrode 32 is connected to the p-type layer 26.

The n-type electrode 30 may have a single-layer, double-layer or multi-layer structure, such as a laminated structure of Ti/Al, ti/Al/Ti/Au, ti/Al/Ni/Au, V/Al/Pt/Au, or the like. In some embodiments, the n-type electrode 30 may be formed directly on the mesa of the epitaxial structure.

The p-type electrode 32 may be made of a transparent conductive material or a metal material, which may be adaptively selected according to the doping of the p-type layer 26 (e.g., the p-type GaN surface layer). In some embodiments, the p-type electrode 32 is made of a transparent conductive material, which may include Indium Tin Oxide (ITO), zinc indium oxide (indium zinc oxide, IZO), indium oxide (InO), tin oxide (tin oxide, snO), cadmium tin oxide (cadmium tin oxide, CTO), tin antimony oxide (antimony tin oxide, ATO), aluminum zinc oxide (aluminum zinc oxide, AZO), zinc tin oxide (zinc tin oxide, ZTO), zinc oxide doped gallium (gallium doped zinc oxide, GZO), indium oxide doped tungsten (tungsten doped indium oxide, IWO), or zinc oxide (zinc oxide, znO), but the embodiments of the present disclosure are not limited thereto.

Referring to fig. 4 in conjunction with fig. 1, in the present embodiment, the semiconductor stack includes at least a first semiconductor layer, a light emitting layer 24, and a second semiconductor layer sequentially stacked. The second semiconductor layer is a p-type layer 26. The first semiconductor layer includes at least an unintentionally doped layer 12, a first n-type layer 16 and a second n-type layer 18. The first n-type layer p-type layer has a higher doping concentration than the second n-type layer 18.

As shown in fig. 4, the first semiconductor layer has an aluminum concentration profile that generally follows the top-down sequence of fig. 1. The concentration profile of aluminum is illustrated by the blue profile in fig. 4, with the p-type layer 26, the light emitting layer 24, the second n-type layer 18, the first n-type layer 16, and the unintentionally doped layer 12 being structured from left to right in fig. 4. The concentration profile of aluminum includes at least a first peak shape n1 and a second peak shape n2. Wherein the first peak n1 is located on a side of the first n-type layer 16 remote from the light emitting layer 24 and the second peak n2 is located on a side of the first n-type layer 16 near the light emitting layer 24. By forming an Al-containing peak shape before and after the first n-type layer 16 with high doping, defects generated in the growth process of the first n-type layer 16 and the first n-type layer 12 with unintentional doping resistance are filled with Al atoms, so that the growth of each subsequent structural layer is facilitated, the lattice quality is improved, the electric leakage risk is reduced, the ESD performance is improved, the chip reliability is further improved, meanwhile, the second peak shape n2 of Al can also play a role in blocking electrons, the carrier space distribution density is improved, the phenomenon of carrier crowding is effectively reduced, and meanwhile, the composite luminous efficiency of electrons and holes in the luminous layer 24 is improved, so that the luminous efficiency is improved, and the overall quality of the light-emitting diode is further improved.

In some embodiments, the maximum value of the first peak n1 is greater than the maximum value of the second peak n2, and setting the first peak n1 to have a higher Al concentration can ensure the effect of effectively blocking defects formed during the growth of the unintentionally doped layer 12, and setting the second peak n2 to have a lower Al concentration can avoid the problem of lattice mismatch with the light emitting layer 24. Optionally, the maximum value of the first peak shape n1 is not less than 1.5 times of the maximum value of the second peak shape n2, thereby further improving the overall quality of the light emitting diode. Preferably, the maximum value of the first peak shape n1 is 1.5 to 4 times the maximum value of the second peak shape n2, for example, the maximum value of the first peak shape n1 is 1.6 times, 2 times, 2.5 times, 3 times, 3.5 times, etc. the maximum value of the second peak shape n 2.

In some embodiments, the doping concentration of the first n-type layer 16 is greater than 1E19atoms/cm ³. The doping concentration of the second n-type layer 18 is less than 1E19atoms/cm ³. Alternatively, in some preferred embodiments, the first n-type layer 16 has a doping concentration in the range of 1E19atoms/cm ³~1E20atoms/cm³ and the second n-type layer 18 has a doping concentration less than 5E18atoms/cm ³. By the arrangement, current diffusion is facilitated, and the operating voltage is reduced.

In some embodiments, the first peak n1 is located between the unintentionally doped layer 12 and the first n-type layer 16, the second peak n2 is located between the first n-type layer 16 and the light emitting layer 24, and by forming the first peak n1 between the unintentionally doped layer 12 and the highly doped first n-type layer 16, defects generated during the growth process of the unintentionally doped layer 12 can be blocked, so as to achieve the effect of shielding defects, and by forming the second peak n2 between the highly doped first n-type layer 16 and the light emitting layer 24, defects generated during the growth process of the unintentionally doped layer 12 and new defects generated during the growth process of the highly doped first n-type layer 16 can be further blocked, and on the other hand, an effect of blocking electrons can be achieved, so that the phenomenon of carrier crowding can be effectively reduced, and meanwhile, the composite light emitting efficiency of electrons and holes in the light emitting layer 24 can be improved, so as to improve the light emitting efficiency.

In some embodiments, the semiconductor stack further includes a composite layer 22, the composite layer 22 being located between the second n-type layer 18 and the light emitting layer 24, the second peak shape n2 being located between the first n-type layer 16 and the composite layer 22. By the composite layer 22 acting as a transition layer, the likelihood of lattice mismatch with the light emitting layer 24 may be reduced.

However, the present disclosure is not so limited, and in some embodiments, the second peak shape n2 is located between the second n-type layer 18 and the composite 22 layer. The second peak shape n2 may be formed between the second n-type layer 18 and the composite layer 22, which may further reduce the likelihood of lattice mismatch with the light emitting layer 24.

The invention also provides a light-emitting device, which comprises a light-emitting diode, wherein the light-emitting diode adopts the light-emitting diode provided by any embodiment, and the specific structure and the technical effect are not repeated.

In summary, in the light emitting diode and the light emitting device provided by the embodiments of the present invention, the first dielectric layer 14 with high aluminum content is inserted between the unintentionally doped layer 12 and the first n-type layer 16 with high doping, so as to achieve the effect of shielding defects, and the second dielectric layer 20 with low aluminum content is inserted between the second n-type layer 18 with low doping and the light emitting layer 24, so as to reduce the pit density and utilize the characteristic of the wide energy gap material, thereby achieving the effect of electron blocking, improving the carrier space distribution density, effectively reducing the carrier crowding, improving the ESD performance, and improving the quality of the light emitting diode.

In addition, it should be understood by those skilled in the art that although there are many problems in the prior art, each embodiment or technical solution of the present invention may be modified in only one or several respects, without having to solve all technical problems listed in the prior art or the background art at the same time. Those skilled in the art will understand that nothing in one claim should be taken as a limitation on that claim.

It should be noted that the above embodiments are merely for illustrating the technical solution of the present invention and not for limiting the same, and although the present invention has been described in detail with reference to the above embodiments, it should be understood by those skilled in the art that the technical solution described in the above embodiments may be modified or some or all of the technical features may be equivalently replaced, and these modifications or substitutions do not make the essence of the corresponding technical solution deviate from the scope of the technical solution of the embodiments of the present invention.

Claims (19)

1. A light emitting diode comprises a semiconductor lamination, and is characterized in that the semiconductor lamination at least comprises an unintentional doped layer, a first dielectric layer, a first n-type layer, a second dielectric layer, a light emitting layer and a p-type layer which are sequentially laminated;

The doping concentration of the first n-type layer is higher than that of the second n-type layer, the first dielectric layer and the second dielectric layer comprise aluminum components, and the aluminum components in the first dielectric layer are higher than those in the second dielectric layer.

2. The light emitting diode of claim 1, wherein the material of the first dielectric layer and the second dielectric layer comprises Al _xGa_(1-x) N material, wherein 0< x.ltoreq.1.

3. The light-emitting diode of claim 1, wherein the aluminum component in the first dielectric layer is 5% -50%.

4. The light-emitting diode of claim 1, wherein the second dielectric layer is doped with n-type impurities, and the doping concentration of the second dielectric layer is less than 1E19atoms/cm ³.

5. The light emitting diode of claim 1, wherein the first n-type layer has a doping concentration greater than 1E19atoms/cm ³.

6. The light emitting diode of claim 1, wherein the second n-type layer has a doping concentration of less than 1E19atoms/cm ³.

7. The light emitting diode of claim 1, wherein the semiconductor stack further comprises a composite layer, the composite layer being located between the second dielectric layer and the light emitting layer.

8. The light emitting diode of claim 1, wherein the first dielectric layer has a thickness greater than a thickness of the second dielectric layer.

9. The light-emitting diode of claim 1, wherein the first dielectric layer has a thickness ranging from 20nm to 50nm and the second dielectric layer has a thickness ranging from 15 nm to 45nm.

10. A light emitting diode comprising a semiconductor stack including at least a first semiconductor layer, a light emitting layer, and a second semiconductor layer stacked in this order;

The light-emitting diode is characterized in that the first semiconductor layer at least comprises an unintentional doped layer, a first n-type layer and a second n-type layer, the doping concentration of the first n-type layer is higher than that of the second n-type layer, the first semiconductor layer is provided with an aluminum concentration curve, the aluminum concentration curve at least comprises a first peak shape and a second peak shape, the first peak shape is positioned on one side, far away from the light-emitting layer, of the first n-type layer, and the second peak shape is positioned on one side, close to the light-emitting layer, of the first n-type layer.

11. The light emitting diode of claim 10, wherein the first n-type layer has a doping concentration greater than 1E19atoms/cm ³.

12. The light emitting diode of claim 10, wherein the second n-type layer has a doping concentration of less than 1E19atoms/cm ³.

13. The light emitting diode of claim 10, wherein the maximum of the first peak shape is greater than the maximum of the second peak shape.

14. A light emitting diode according to claim 13 wherein the maximum value of the first peak shape is not less than 1.5 times the maximum value of the second peak shape.

15. A light emitting diode as set forth in claim 10, wherein the first peak is located between the unintentionally doped layer and the first n-type layer and the second peak is located between the first n-type layer and the light emitting layer.

16. The light emitting diode of claim 10, wherein the semiconductor stack further comprises a composite layer, the composite layer being between the second n-type layer and the light emitting layer, the second peak being between the first n-type layer and the composite layer.

17. The light emitting diode of claim 16, wherein the second peak shape is located between the second n-type layer and the composite layer.

18. A light emitting diode according to claim 1 or 10, wherein the light emitting diode has a side length of not more than 200. Mu.m.

19. A light emitting device, characterized in that the light emitting device comprises a light emitting diode, wherein the light emitting diode is as claimed in any one of claims 1 to 18.