CN119618398A - Temperature sensor and control method - Google Patents
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Abstract
The invention discloses a temperature sensor and a control method, the method comprises the steps of outputting a clock pulse signal to a pulse extractor and a non-overlapping clock and phase generator through a voltage-controlled ring oscillator so as to output a fractional pulse signal and a working control signal, outputting a delay voltage signal through a temperature sensing front end according to the working control signal, linearly transforming and chopping the delay voltage signal through a time domain amplifier according to the working control signal, outputting the delay pulse signal, outputting the pulse control signal through a frequency discriminator according to the delay pulse signal, performing voltage regulation on a notch filter through a charge pump according to the pulse control signal, and outputting the control voltage signal through the notch filter according to the working control signal.
Description
Technical Field
The invention relates to the field of temperature sensor design, in particular to a temperature sensor and a control method thereof.
Background
The resistance-based temperature sensor has a compact area and has a high accuracy and an excellent resolution quality factor (R-FoM) (< 100fj·k 2). In contrast to active device sensing elements based on the need for biasing (e.g., bipolar transistor BJTs and field effect transistor MOSFETs), resistive has no limitation on the supply voltage VDD. This feature facilitates the design of a resistance-based temperature sensor in advanced processes with an operating voltage VDD <1V (e.g., 0.9V in a selected 28nm process) to achieve an integrated temperature sensing solution. However, in the conventional temperature sensor design, there are problems of high power consumption, large area and difficulty in maintaining accuracy due to non-ideal characteristics of the transistor (gate tunneling, leakage current, short channel effect, etc.).
Disclosure of Invention
The present invention aims to solve at least one of the technical problems existing in the prior art to a certain extent.
It is therefore an object of embodiments of the present invention to provide a temperature sensor and control method that achieve compact design, low power consumption, and high resolution of the sensor at low voltages by employing a fractional charge bleed scheme and introducing a time-domain amplifier with chopping.
The first technical scheme adopted by the invention is as follows:
A temperature sensor comprising a temperature sensing front end, a time domain amplifier, a phase frequency detector, a charge pump, a notch filter, a voltage controlled ring oscillator, a pulse extractor and a non-overlapping clock and phase generator, said temperature sensing front end and said phase frequency detector being connected to said time domain amplifier, said phase frequency detector and said notch filter being connected to said charge pump, said notch filter and said pulse extractor being connected to said voltage controlled ring oscillator, said temperature sensing front end, said time domain amplifier, said notch filter, said voltage controlled ring oscillator and said pulse extractor being connected to said non-overlapping clock and phase generator, said voltage controlled ring oscillator being adapted to output a clock signal to said pulse extractor and said non-overlapping clock and phase generator, said pulse extractor being adapted to output a fractional pulse signal in dependence on said clock signal, said notch filter and said pulse extractor being adapted to output a fractional pulse signal in dependence on said clock signal, said notch filter being adapted to control a voltage controlled signal, said notch filter being adapted to output a voltage controlled signal in dependence on said time domain signal, said voltage controlled ring oscillator being adapted to delay said phase generator, said voltage controlled filter being adapted to output a phase-locked signal in dependence on said clock signal, the voltage-controlled ring oscillator is also used for adjusting the frequency of the clock pulse signal according to the control voltage signal.
Further, the voltage controlled ring oscillator includes a control voltage signal input, a ring inverter chain, a level shifter array, a bias reference current input, the ring inverter chain, the control voltage signal input, and the level shifter are all connected with the ring inverter chain, the ring inverter chain includes a plurality of inverters, the control voltage input is used for inputting the control voltage signal into the ring inverter chain, the bias reference current input is used for providing a bias reference current for the ring inverter chain, the ring inverter chain is used for determining delays between the plurality of inverters according to the bias reference current, the ring inverter chain is also used for adjusting delays between the plurality of inverters according to the control voltage signal, the ring inverter chain is also used for outputting a delay oscillation signal according to the delays between the plurality of inverters, and the level shifter array is used for converting the delay oscillation signal into the clock pulse signal.
Further, the pulse extractor includes a plurality of logic gates for outputting fractional pulse signals according to the clock pulse signal.
Further, the operation control signals include a reset control signal, a discharge control signal, an amplification control signal, a chopping control signal, a hold control signal, and a sampling control signal.
Further, the temperature extraction front end comprises a first discharging switch, a second discharging switch, a first reset switch, a second reset switch, a first capacitor, a second capacitor, a first temperature-sensitive resistor and a second temperature-sensitive resistor, wherein the first temperature-sensitive resistor, the first reset switch and the time domain amplifier are all connected with an upper polar plate of the first capacitor, the second temperature-sensitive resistor, the second reset switch and the time domain amplifier are all connected with a lower polar plate of the second capacitor, the first temperature-sensitive resistor is connected with the first discharging switch, the second temperature-sensitive resistor is connected with the second discharging switch, the first discharging switch, a lower polar plate of the first capacitor and an upper polar plate of the second capacitor are all grounded, the second discharging switch and the first reset switch are all connected with a power supply, the first reset switch and the second reset switch are used for controlling charging time of the first capacitor and the second capacitor according to the working control signal, and the second switch is used for controlling discharging time of the first capacitor and the second capacitor according to the working control signal and the second capacitor.
Further, the first temperature-sensitive resistor comprises 5 layers of stacked metal resistors, an upper shielding layer and a lower shielding layer, and the structure of the second temperature-sensitive resistor is the same as that of the first temperature-sensitive resistor.
Further, the time domain amplifier comprises a first field effect transistor, a second field effect transistor, a third field effect transistor, a fourth field effect transistor, a fifth field effect transistor, a sixth field effect transistor, a first amplifying switch, a second amplifying switch, a third amplifying switch, a fourth amplifying switch, a third capacitor, a fourth capacitor, a bias voltage input end, an amplifying signal input end, a first differential voltage input end, a second differential voltage input end, a first common mode voltage input end, a second common mode voltage input end, a first differential pulse output end, a second differential pulse output end, a first chopper and a second chopper, wherein the grid electrode of the sixth field effect transistor is connected with the bias voltage input end, the source electrode of the sixth field effect transistor is grounded, the grid electrode of the sixth field effect transistor, the grid electrode of the fourth field effect transistor and the grid electrode of the fifth field effect transistor are all connected with the amplifying signal input end, the source electrode of the first field effect transistor, the source electrode of the second field effect transistor and the differential voltage input end are all connected with the drain electrode plate of the fourth field effect transistor, the drain electrode of the fourth field effect transistor and the fourth chopper are all connected with the drain electrode of the fourth field effect transistor, the drain electrode of the fourth field effect transistor is all connected with the drain electrode of the fourth field effect transistor and the fourth chopper is all connected with the drain electrode of the fourth field effect transistor, the first differential voltage input end is connected with the second amplifying switch, the first amplifying switch and the second amplifying switch are connected with the grid electrode of the first field effect transistor, the second common-mode voltage input end is connected with the third amplifying switch, the second differential voltage input end is connected with the fourth amplifying switch, and the third amplifying switch and the fourth amplifying switch are connected with the grid electrode of the second field effect transistor.
Further, the notch filter includes a sampling control switch, a holding control switch, a fifth capacitor, a sixth capacitor and a seventh capacitor, wherein the fifth capacitor and the sixth capacitor are both connected with the sampling control switch, the sixth capacitor and the seventh capacitor are both connected with the holding control switch, the sampling control switch and the holding control switch are both used for switching according to the operation control signal, the fifth capacitor is used for outputting an integral voltage signal, the sixth capacitor is used for sampling the integral voltage signal and outputting a sampling voltage signal, and the seventh capacitor is used for holding the sampling voltage signal and outputting a control voltage signal.
Further, the pulse control signal includes a pull-up pulse signal and a pull-down pulse signal, and the phase frequency detector and the charge pump are specifically configured to:
detecting a phase difference of the delayed pulse signal by the phase frequency detector;
When the phase difference is positive, outputting a pull-up pulse signal to the charge pump through the phase frequency detector, and charging the fifth capacitor through the charge pump;
and when the phase difference is negative, outputting a pull-down pulse signal through the phase frequency detector, and discharging the fifth capacitor through the charge pump.
The second technical scheme adopted by the invention is as follows:
A control method of a temperature sensor, for being implemented by the temperature sensor, comprising the following steps:
outputting a clock pulse signal to the pulse extractor and the non-overlapping clock and phase generator by the voltage controlled ring oscillator;
Outputting a fractional pulse signal according to the clock pulse signal by the pulse extractor;
Outputting a working control signal according to the clock pulse signal and the fractional pulse signal through the non-overlapping clock and phase generator;
Outputting a delay voltage signal according to the working control signal through the temperature sensing front end;
the time domain amplifier is used for carrying out linear transformation and chopping on the delay voltage signal according to the working control signal, and outputting a delay pulse signal;
Outputting a pulse control signal according to the delay pulse signal through the phase frequency detector;
The charge pump adjusts the voltage of the notch filter according to the pulse control signal;
outputting a control voltage signal according to the operation control signal through the notch filter;
And adjusting the frequency of the clock pulse signal according to the control voltage signal through the voltage-controlled ring oscillator.
The invention has the beneficial effects that the fractional charge discharging scheme is adopted to extract fractional pulses from the voltage-controlled ring oscillator, only one fractional pulse is used for discharging in each amplifying period, the discharging time is greatly shortened, the requirement on the resistance area of the sensor is reduced, the whole area of the sensor is further reduced under the condition of keeping the power consumption, meanwhile, the time domain amplifier with a chopper function is introduced to process the input of the temperature sensing front end, the direct current offset voltage and 1/f noise are effectively eliminated, and the high resolution quality factor of the sensor is realized.
Drawings
FIG. 1 is a schematic diagram of a temperature sensor according to an embodiment of the present invention;
FIG. 2 is a signal timing diagram of a temperature sensor according to an embodiment of the present invention;
FIG. 3 is an area division diagram of a temperature sensor according to an embodiment of the present invention;
FIG. 4 is a graph showing an area distribution ratio of a temperature sensor according to an embodiment of the present invention
FIG. 5 is a graph showing a relationship between a temperature and an output frequency of a temperature sensor according to an embodiment of the present invention;
FIG. 6 is a graph showing a relationship between temperature and temperature error of a temperature sensor according to an embodiment of the present invention;
FIG. 7 is a temperature error diagram of a temperature sensor after third-order polynomial fitting according to an embodiment of the present invention;
FIG. 8 is a temperature error diagram of a temperature sensor after single-point and two-point calibration according to an embodiment of the present invention;
FIG. 9 is a graph showing the relationship between power and power of a temperature sensor according to an embodiment of the present invention;
FIG. 10 is a graph showing a relationship between a power supply and a temperature error of a temperature sensor according to an embodiment of the present invention;
FIG. 11 is a graph showing the resolution ratio of a temperature sensor before and after a chopper technique according to an embodiment of the present invention;
Fig. 12 is a schematic structural diagram of a voltage-controlled ring oscillator according to an embodiment of the present invention;
FIG. 13 is a schematic diagram of a pulse extractor according to an embodiment of the present invention;
FIG. 14 is a timing diagram of fractional pulse signals and multi-level clock cycle signals provided by an embodiment of the present invention;
FIG. 15 is a schematic diagram of a metal line resistor according to an embodiment of the present invention;
fig. 16 is a schematic structural diagram of a time domain amplifier according to an embodiment of the present invention;
Fig. 17 is a schematic diagram of an operation principle of a time domain amplifier according to an embodiment of the present invention;
FIG. 18 is a graph showing the comparison of effects before and after using the chopping technique according to the embodiment of the present invention;
Fig. 19 is a schematic step diagram of a control method of a temperature sensor according to an embodiment of the present invention.
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the invention. The step numbers in the following embodiments are set for convenience of illustration only, and the order between the steps is not limited in any way, and the execution order of the steps in the embodiments may be adaptively adjusted according to the understanding of those skilled in the art.
In the description of the present invention, the plurality means two or more, and if the description is made to the first and second for the purpose of distinguishing technical features, it should not be construed as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the precedence of the indicated technical features. Furthermore, unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art.
Referring to fig. 1, an embodiment of the present invention provides a temperature sensor, which is characterized by comprising a temperature sensing front end, a time domain amplifier, a phase discriminator, a charge pump, a notch filter, a voltage controlled ring oscillator, a pulse extractor and a non-overlapping clock and phase generator, wherein the temperature sensing front end and the phase discriminator are both connected with the time domain amplifier, the phase discriminator and the notch filter are both connected with the charge pump, the notch filter and the pulse extractor are both connected with the voltage controlled ring oscillator, the temperature sensing front end, the time domain amplifier, the notch filter, the voltage controlled ring oscillator and the pulse extractor are both connected with the non-overlapping clock and phase generator, the voltage controlled ring oscillator is used for outputting a clock pulse signal to the pulse extractor and the non-overlapping clock and phase generator, the pulse extractor is used for outputting a fractional pulse signal according to the clock pulse signal, the non-overlapping clock and phase generator is used for outputting an operation control signal according to the clock pulse signal, the temperature sensing front end is used for outputting a delayed voltage signal according to the operation control signal, the notch filter is used for performing a linear transformation on the delayed voltage signal according to the operation control signal, the voltage signal is used for adjusting the voltage signal, the voltage controlled by the voltage generator is used for controlling the notch filter is also used for adjusting the voltage signal according to the pulse signal.
Specifically, referring to fig. 1, the CMOS temperature sensor based on fractional charge draining according to the embodiment of the present invention uses a Frequency Locked Loop (FLL) as a readout circuit for detecting the temperature of a temperature sensing resistor (R M, 25kΩ), and includes a temperature sensing front end, a Time Domain Amplifier (TDA), a Phase Frequency Detector (PFD), a Charge Pump (CP), a notch filter, a 5-stage Voltage Controlled Ring Oscillator (VCRO), a Pulse Extractor (PE), and a non-overlapping clock and phase generator. The temperature sensing front end includes a pair of R M C filters, where C (1.4 pF) is a MOM capacitor with a negligible temperature coefficient TC (50 ppm/°C). The FLL can detect the temperature dependent time constant of the filter (τ=r M C, or 35ns at 25 ℃) because it can lock its output frequency (F OUT) at a fixed ratio τ in steady state by adjusting the bias current (I VCRO) of the VCRO and adjusting the center frequency F OUT period (T OUT) once trimming after sensor fabrication is completed, locking T OUT at 7τ in steady state, where F OUT =4 MHz, where the output of R M C filter (V RC+/-) equals 0.5V DD, controlling the voltage signal V C＝0.5VDD. the sensor's workflow is such that during the reset phase (RST), FLL pre-charges C to V DD/VSS. During the discharge phase (DIS), the R M C filter will discharge C within 0.7τ, outputting a delayed voltage signal (V i+/-), and in the initial state, the R M C filter may discharge C to 0.5V DD within 0.7τ, and the delayed voltage signal (V i+/-) will have no difference, and when the external temperature changes, τ will also change, resulting in a difference in the delayed voltage signal (V i+/-) output by the R M C filter. When DIS goes low, FLL goes into an amplifying stage (AMP) where TDA converts the delayed voltage signal (V i+/-) into a delayed pulse signal (V O+/-);VO+/-), the differential delay (t d) between V O+/-);VO+/- being proportional to the difference between Vi +/-. The FLL then generates a pair of pull-UP or pull-down (UP/DN) pulses through the PFD, and the CP integrates the charge and discharge of capacitor C INT in accordance with the UP/DN control to generate an integrated voltage signal V INT. The notch filter controls the capacitor C M and the capacitor C H to sample and hold V INT, respectively, according to the sampling control signal (Φ S) hold control signal (Φ H), and outputs the sampling voltage signal V M and the control voltage signal V C. The control voltage signal V C controls the VCRO and re-locks its period at a fixed ratio of τ, and at this time, the output frequency F OUT of the VCRO is an indication signal of temperature change information. While the five-stage delayed output (Φ 1-5) of the VCRO is fed to a pulse extractor, which extracts each stage of the output of the VCRO by means of a NAND gate and a NOR gate, resulting in 10 fractional pulse signals (D 1-10), each pulse having a width of 10% of T OUT, each pulse being used to control the discharge of C in the temperature sensing front end, and a non-overlapping clock and phase generator, which outputs a series of control signals based on the first stage output (Φ 1) of the VCRO and D 1-10, including a reset control signal (RST), The discharge control signal (DIS), the amplification control signal (AMP), the chopping control signal (CHP), the hold control signal (Φ H), the sampling control signal (Φ S) are used for controlling the switching of each period of different modules, and the time sequence of each signal is shown in fig. 2.
In terms of the design of fractional charge bleed schemes, embodiments of the present invention utilize the 5-stage delayed output (Φ 1-5) of VCRO to generate 10 pulses (D 1-10) in one F OUT period, each pulse having a width of 10% of T OUT, and utilize 1 pulse to discharge C and amplify and integrate it, we can get T OUT =0.7τ10 in steady state. By shortening the discharge time, embodiments of the present invention can reduce the required R M C value by a factor of 10 while maintaining FLL power consumption (which is proportional to F OUT), thereby optimizing the overall chip area by a factor of 2.6 at the same F OUT. In practice, due to mismatch between delay cells within the VCRO, the pulse width between D 1-10 may not be equal if not properly handled, resulting in inaccurate temperature sensor output. To address this problem, embodiments of the present invention sequentially select D 1-10 to produce a discharge of C in 10 separate comparison Cycles (CMP), and this feature ensures that the total duration of 10 consecutive discharges remains stable under mismatch and process/voltage variations, since the sum of the widths of D 1-10 is equal to T OUT.
In terms of chopping, the embodiment of the invention amplifies the output of the sensing front end by using the TDA with a chopping function without chopping at the comparator, thereby avoiding the problem that the chopping caused by nonlinear quantization of the comparator cannot eliminate 1/f noise and DC offset of the comparator and avoiding noise and inaccuracy brought to the output of the sensor.
It can be realized that the embodiment of the invention extracts fractional pulses from the voltage-controlled ring oscillator by adopting a fractional charge discharging scheme, only uses one fractional pulse for discharging in each amplifying period, greatly shortens the discharging time, reduces the requirement on the resistance area of the sensor, further reduces the whole area of the sensor under the condition of keeping the power consumption, and simultaneously processes the input of the temperature sensing front end by introducing the time domain amplifier with the chopping function, effectively eliminates the direct current offset voltage and 1/f noise, and realizes the high resolution quality factor of the sensor. Specifically, the embodiment of the invention realizes a temperature sensor in a 28nm CMOS process, the structure of the temperature sensor is shown in figure 3, wherein each symbol respectively represents a front end A, a bias reference source E, a time domain amplifier B, a voltage-controlled ring oscillator F, a phase frequency detector C, a notch filter G, a charge pump D, a phase generation and pulse extractor H, the area of the temperature sensor is 4,100 mu m 2, the area of each component occupies the area shown in figure 4, and 44.6% of the temperature sensor is occupied by the notch filter. In the performance test, the frequency versus temperature error is shown in FIG. 5, and the average F OUT measured for 30 chips ranges from 4.1MHz (-40 ℃) to 2.8MHz (125 ℃) with a corresponding average TC of 0.22%/°C, very close to the TC of R M. The nonlinear errors of the sensor after the first-order fitting are shown in fig. 6, and the temperature errors after the 1-point calibration, the 2-point calibration and the third-order polynomial fitting are shown in fig. 8 and 7, respectively, and the temperature errors (3σ) are +/-1.5 ℃ and +/-0.2 ℃ respectively (0.24%). As shown in fig. 9, at room temperature, when V DD was 0.8V, its power consumption was 10.5 μw, with VCRO accounting for 31% (from simulation verification). Since the DC offset of TDA is mitigated using chopping techniques, as shown in FIG. 10, the sensor achieves an average power supply sensitivity of 0.34C in the range of 0.7 to 0.9V. As shown in fig. 11, the chopping technique used by TDA increased the resolution from 22.6 to 1.2mK RMS in 3ms conversion time, ultimately achieving R-FoM of 45fj·k 2.
Further alternatively, the voltage-controlled ring oscillator includes a control voltage signal input, a ring inverter chain, a level shifter array, and a bias reference current input, the ring inverter chain, the control voltage signal input, and the level shifter are all connected to the ring inverter chain, the ring inverter chain includes a plurality of inverters, the control voltage input is used for inputting the control voltage signal into the ring inverter chain, the bias reference current input is used for providing the ring inverter chain with the bias reference current, the ring inverter chain is used for determining a delay between the plurality of inverters according to the bias reference current, the ring inverter chain is also used for adjusting the delay between the plurality of inverters according to the control voltage signal, the ring inverter chain is also used for outputting a delayed oscillation signal according to the delay between the plurality of inverters, and the level shifter array is used for converting the delayed oscillation signal into a clock signal.
Specifically, as shown in fig. 12, the VCRO is a current starved type 5-stage ring oscillator. Each stage includes an inverter and a MOSCAP for frequency adjustment. After fabrication, we make a one-time trimming to adjust the bias current (I VCRO) of the VCRO and adjust the center frequency (when V C＝0.5VDD).VC controls the delay of the stages, T OUT is locked at 7τ in steady state).
Further alternative embodiments, the pulse extractor comprises a plurality of logic gates for outputting fractional pulse signals from the clock pulse signal.
Specifically, in the embodiment of the invention, in order to realize the proposed fractional discharge scheme, the PE derives D 1-10 from the VCRO based on Φ 1-5 using a logic gate, thereby ensuring the stability and accuracy of the temperature sensor. As shown in fig. 13, the PE extracts the 5-stage delayed output (Φ 1-5) of the VCRO through the nand gate and the nor gate, and the connection of the logic gates is shown, 10 pulses are generated in one F OUT period (the timing relationship between D 1-10),Φ1-5 and D 1-10 is shown in fig. 14.
Further alternative embodiments, the operation control signals include in particular a reset control signal, a discharge control signal, an amplification control signal, a chopping control signal, a hold control signal, and a sampling control signal.
Further as an alternative embodiment, the temperature extraction front end includes a first discharging switch, a second discharging switch, a first reset switch, a second reset switch, a first capacitor, a second capacitor, a first temperature sensitive resistor and a second temperature sensitive resistor, the first reset switch and the time domain amplifier are all connected with an upper polar plate of the first capacitor, the second temperature sensitive resistor, the second reset switch and the time domain amplifier are all connected with a lower polar plate of the second capacitor, the first temperature sensitive resistor is connected with the first discharging switch, the second temperature sensitive resistor is connected with the second discharging switch, the first discharging switch, the second reset switch, the lower polar plate of the first capacitor and the upper polar plate of the second capacitor are all grounded, the second discharging switch and the first reset switch are all connected with a power supply, the first reset switch and the second reset switch are used for controlling the charging time of the first capacitor and the second capacitor according to a working control signal, and the first discharging switch and the second discharging switch are used for controlling the discharging time of the first capacitor and the second capacitor according to the working control signal, and the second capacitor are used for outputting a delay voltage signal.
Further as an optional implementation manner, the first temperature-sensitive resistor comprises 5 layers of stacked metal resistors, an upper shielding layer and a lower shielding layer, and the structure of the second temperature-sensitive resistor is the same as that of the first temperature-sensitive resistor.
Specifically, it is preferable to select a resistor having a higher Temperature Coefficient (TC) at the temperature sensing in the present embodiment. In the 28nm process used in the present invention, there are two types of resistors with higher 1 st order TC (> 0.1%/° C), a metal resistor with TC of about 0.2%/° C and a metal silicide diffusion resistor with TC of 0.15%/° C, respectively. Although metal resistors have a high TC, they are limited to being rarely used as temperature sensing front-ends in mature processes (e.g., 180 nm) due to their extremely low sheet resistance (0.5 Ω/≡). However, as the spacing of metal interconnects in deep submicron processes is reduced, adding to the availability of multiple metal layers, which helps to reduce the overall area thereof, the present embodiment uses 5 layers of metal to achieve a 25k omega resistor with an area that is 12% less than that implemented using metal silicide diffusion resistors. Therefore, as shown in fig. 15, the present embodiment implements a temperature sensing resistor (R M, 25kΩ) using 5 stacked metal resistors and upper and lower shield layers. It is noted that metal interconnect lines are common throughout all CMOS processes, and as metal interconnect dimensions continue to shrink, metal interconnect lines can still be utilized as temperature sensors in advanced processes in more compact dimensions.
Further as an alternative embodiment, the time domain amplifier comprises a first field effect transistor, a second field effect transistor, a third field effect transistor, a fourth field effect transistor, a fifth field effect transistor, a sixth field effect transistor, a first amplifying switch, a second amplifying switch, a third amplifying switch, a fourth amplifying switch, a third capacitor, a fourth capacitor, a bias voltage input terminal, an amplifying signal input terminal, a first differential voltage input terminal, a second differential voltage input terminal, a first common mode voltage input terminal, a second common mode voltage input terminal, a first differential pulse output terminal, a second differential pulse output terminal, a first chopper and a second chopper, the grid electrode of the sixth field effect transistor is connected with the bias voltage input terminal, the source electrode of the sixth field effect transistor is grounded, the grid electrode of the sixth field effect transistor, the grid electrode of the fourth field effect transistor and the grid electrode of the fifth field effect transistor are all connected with the amplifying signal input terminal, the source electrode of the first field effect transistor, the source electrode of the second field effect transistor and the second field effect transistor are all connected with the third field effect transistor, the drain electrode of the fourth field effect transistor and the fourth field effect transistor are both connected with the fourth field effect transistor, the drain electrode of the fourth field effect transistor is connected with the fourth field effect transistor, the fourth field effect transistor is both connected with the drain electrode of the fourth field effect transistor, the fourth field effect transistor is connected with the fourth field-transistor, the fourth field effect transistor is connected with the fourth field transistor, and the fourth field effect transistor is connected with the fourth field amplifier, the second common-mode voltage input end is connected with a third amplifying switch, the second differential voltage input end is connected with a fourth amplifying switch, and the third amplifying switch and the fourth amplifying switch are both connected with the grid electrode of the second field effect transistor.
In particular, for deep submicron processes with V DD <1V, a sophisticated design is required for a sufficiently gain voltage mode amplifier support to be accurate. The comparator of the digital FLL may operate at voltages as low as 0.4V. However, due to the non-linear quantization, the 1/f noise and dc offset of the comparator cannot be eliminated by using the chopping technique for the comparator, thereby giving noise and inaccuracy to the sensor output. For this purpose, the embodiment converts the differential input voltage (DeltaV i) to t d by using TDA with a structure shown as 16 and including a first FET M 1, a second FET M 2, Third field effect transistor M 3, fourth field effect transistor M 4, fifth field effect transistor M 5, sixth field effect transistor M 0, A first amplifying switch, a second amplifying switch, a third amplifying switch, a fourth amplifying switch, a third capacitor C L, a fourth capacitor C L, a bias voltage input terminal V BN, an amplified signal input terminal AMP, a first differential voltage input terminal V i+, A second differential voltage input terminal V i-, a first common-mode voltage input terminal V CM, a second common-mode voltage input terminal V CM, a first differential pulse output terminal V O+, the second differential pulse output V O-, as shown in fig. 1, the first chopper and the second chopper are located at both ends of the time-domain amplifier. As shown in fig. 17, when AMP is low, V L+/- is charged to V DD through M 4/5, at which time V o+/- is all at V SS, and when AMP is changed to V DD, V L+/- is discharged to V SS through a discharge current I M1/2 of M 1/2, and since the difference between I M1 and I M2 is related to Δv i, the discharge rate difference on V L+/- is also proportional to Δv i. Once V L+/- falls below the threshold of the inverter, V o+/- flips to V DD, where the delay between V o+/- (i.e., t d) is proportional to Δvi. The present embodiment sets t d/Δvi to 3 μs/V to ensure that the detection error caused by CP leakage at a high temperature of 125 ℃ is <0.1 ℃ and suppress in-band noise. Since t d is not quantized, a chopping technique can be applied to the TDA and the DC offset and 1/f noise modulated to high frequency. As shown in fig. 18, the simulated residual dc offset (1σ) of TDA was 0.12mV after chopping, which was reduced by a factor of 20 compared to the non-chopped case (2.4 mV).
Further alternatively, the notch filter includes a sampling control switch, a holding control switch, a fifth capacitor, a sixth capacitor, and a seventh capacitor, where the fifth capacitor and the sixth capacitor are both connected to the sampling control switch, the sixth capacitor and the seventh capacitor are both connected to the holding control switch, the sampling control switch and the holding control switch are both used for switching according to the operation control signal, the fifth capacitor is used for outputting an integrated voltage signal, the sixth capacitor is used for sampling the integrated voltage signal, the sampled voltage signal is output, and the seventh capacitor is used for holding the sampled voltage signal, and the control voltage signal is output.
Further as an alternative embodiment, the pulse control signal includes a pull-up pulse signal and a pull-down pulse signal, and the phase frequency detector and the charge pump are specifically configured to:
Specifically, the output of the TDA (at about 100kHz after chopping at F OUT/40) drives the PFD to output a pair of pull-UP or pull-down UP/DN pulses that polarity the information of t d and control the current delivered to the notch filter. The notch filter operates in the sample (Φ S) and hold (Φ H) phases according to the control signal. In the case of fractional discharge schemes and TDA chopping, the mismatch present in VCRO and TDA can cause ripple on V INT. Accordingly, FLL samples V INT and acquires V C by alternating Φ S and Φ H at a sampling frequency of F OUT/80 (-50 kHz) every 10 cycles, thereby mitigating the effects of such ripple on VCRO. Φ S and Φ H generated by the non-overlapping clock modules can avoid unnecessary charge sharing between capacitors.
Detecting a phase difference of the delayed pulse signal by a phase frequency detector;
When the phase difference is positive, outputting a pull-up pulse signal to a charge pump through the phase frequency detector, and charging a fifth capacitor through the charge pump;
when the phase difference is negative, a pull-down pulse signal is output through the phase frequency detector, and the fifth capacitor is discharged through the charge pump.
Referring to fig. 19, an embodiment of the present invention provides a control method of a temperature sensor, which is implemented by the temperature sensor, including the following steps:
S101, outputting a clock pulse signal to a pulse extractor and a non-overlapping clock and phase generator through a voltage-controlled ring oscillator;
S102, outputting a fractional pulse signal according to a clock pulse signal through a pulse extractor;
S103, outputting a working control signal according to the clock pulse signal and the fractional pulse signal through a non-overlapping clock and phase generator;
s104, outputting a delay voltage signal through the temperature sensing front end according to the working control signal;
s105, performing linear transformation and chopping on the delayed voltage signal according to the working control signal through a time domain amplifier, and outputting a delayed pulse signal;
s106, outputting a pulse control signal according to the delay pulse signal through the phase frequency detector;
S107, voltage regulation is carried out on the notch filter through a charge pump according to the pulse control signal;
S108, outputting a control voltage signal according to the working control signal through a notch filter;
s109, adjusting the frequency of the clock pulse signal according to the control voltage signal through the voltage-controlled ring oscillator.
It can be understood that the content in the above system embodiment is applicable to the method embodiment, and the specific functions implemented by the method embodiment are the same as those of the above system embodiment, and the achieved beneficial effects are the same as those of the above system embodiment.
It should be appreciated that embodiments of the invention may be implemented or realized by computer hardware, a combination of hardware and software, or by computer instructions stored in a non-transitory computer readable memory. The above-described methods may be implemented in a computer program using standard programming techniques, including a non-transitory computer readable storage medium configured with a computer program, where the storage medium so configured causes a computer to operate in a specific and predefined manner, in accordance with the methods and drawings described in the specific embodiments. Each program may be implemented in a high level procedural or object oriented programming language to communicate with a computer system. However, the program(s) can be implemented in assembly or machine language, if desired. In any case, the language may be a compiled or interpreted language. Furthermore, the program can be run on a programmed application specific integrated circuit for this purpose.
Furthermore, the operations of the processes described herein may be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The processes (or variations and/or combinations thereof) described herein may be performed under control of one or more computer systems configured with executable instructions, and may be implemented as code (e.g., executable instructions, one or more computer programs, or one or more applications), by hardware, or combinations thereof, collectively executing on one or more processors. The computer program includes a plurality of instructions executable by one or more processors.
Further, the above-described methods may be implemented in any type of computing platform operatively connected to a suitable computing platform, including, but not limited to, a personal computer, mini-computer, mainframe, workstation, network or distributed computing environment, a separate or integrated computer platform, or in communication with a charged particle tool or other imaging device, and so forth. Aspects of the invention may be implemented in machine-readable code stored on a non-transitory storage medium or device, whether removable or integrated into a computing platform, such as a hard disk, optical read and/or write storage medium, RAM, ROM, etc., such that it is readable by a programmable computer, which when read by a computer, is operable to configure and operate the computer to perform the processes described herein. Further, the machine readable code, or portions thereof, may be transmitted over a wired or wireless network. When such media includes instructions or programs that, in conjunction with a microprocessor or other data processor, implement the steps described above, the invention described herein includes these and other different types of non-transitory computer-readable storage media. The invention also includes the computer itself when programmed according to the methods and techniques described herein.
The computer program can be applied to input data to perform the functions described herein, thereby converting the input data to generate output data that is stored to the non-volatile memory. The output information may also be applied to one or more output devices such as a display. In a preferred embodiment of the invention, the transformed data represents physical and tangible objects, including specific visual depictions of physical and tangible objects produced on a display.
The present invention is not limited to the above embodiments, but can be modified, equivalent, improved, etc. by the same means to achieve the technical effects of the present invention without departing from the spirit and principle of the present invention. Various modifications and variations are possible in the technical solution and/or in the embodiments within the scope of the invention.
Claims (10)
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