CN119601543A - Chip packaging structure and electronic equipment - Google Patents
Chip packaging structure and electronic equipment Download PDFInfo
- Publication number
- CN119601543A CN119601543A CN202411656893.5A CN202411656893A CN119601543A CN 119601543 A CN119601543 A CN 119601543A CN 202411656893 A CN202411656893 A CN 202411656893A CN 119601543 A CN119601543 A CN 119601543A
- Authority
- CN
- China
- Prior art keywords
- differential signal
- signal line
- chip
- capacitor
- electrically connected
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
The application discloses a chip packaging structure and electronic equipment, which belong to the technical field of semiconductors and comprise a packaging substrate, an adapter plate and a plurality of chips. The adapter plate comprises a base layer, a plurality of capacitors and a plurality of differential signal wires, wherein the capacitors are embedded in the base layer. According to the technical scheme, the capacitor is directly formed on the adapter plate, and each differential signal wire in the pair of differential signal wires between the two chips is connected with one capacitor in series, so that the two chips can bypass the limitation of the DDR or UCIE interface to realize interconnection communication, the additional configuration of the surface mount capacitor in the chip packaging structure can be avoided, the area of the packaging substrate is saved, the problem that the mounting process of the surface mount capacitor is incompatible with the mounting process of the chip packaging structure is avoided, the cost is reduced, the higher integration level is realized, and the yield is improved.
Description
Technical Field
The present application relates to semiconductor technology, and more particularly, to a chip package structure and an electronic device.
Background
With the development of artificial intelligence and high-performance calculation, the requirements on the computing power of the chip are higher and higher, the functions of the chip are also more and more complex, the main mass production chip packaging solution in the field of AI high-computing power chips is a 2.5D packaging technology, the packaging solution ensures the integration level of the system, the high-computing power chips of advanced process nodes can be used, and the problem of yield reduction caused by the enlarged chip size is also solved. Under the packaging structure, most of communication interfaces between chips are DDR or UCIE and other high-density parallel signal interfaces.
However, the application of the DDR interface is limited due to the domestic process production capacity, and there is no mature UCIE interface standard protocol in China, so how to solve the problem of communication interface connection between chips is a problem to be solved in the field.
Disclosure of Invention
The application provides a chip packaging structure which comprises a packaging substrate, an adapter plate and a plurality of chips. The adapter plate is arranged on the packaging substrate and is electrically connected with the packaging substrate. The plurality of chips are arranged on one side of the adapter plate far away from the packaging substrate. In addition, the adapter plate comprises a base layer, a plurality of capacitors and a plurality of differential signal wires, wherein the base layer comprises a first surface far away from one side of the packaging substrate, the capacitors are embedded into the first surface, and the capacitors comprise a first capacitor and a second capacitor. The plurality of differential signal lines are arranged on one side of the base layer far away from the packaging substrate, each differential signal line comprises a first differential signal line, a second differential signal line, a third differential signal line and a fourth differential signal line, the first differential signal line is electrically connected with one electrode of the first capacitor, and the second differential signal line is electrically connected with the other electrode of the first capacitor. The third differential signal line is electrically connected to one electrode of the second capacitor, and the fourth differential signal line is electrically connected to the other electrode of the second capacitor. The plurality of chips includes a first chip having a first interface and a second chip having a second interface, the first interface being electrically connected to the first differential signal line and the third differential signal line, the second interface being electrically connected to the second differential signal line and the fourth differential signal line.
In some embodiments, the first chip and the second chip are spaced apart along a first direction, the first direction being parallel to the first surface, at least a portion of the first capacitor being located between the first chip and the second chip, and at least a portion of the second capacitor being located between the first chip and the second chip in the first direction.
In some embodiments, the interposer further includes an insulating layer disposed between the base layer and the plurality of differential signal lines, and a plurality of conductive structures extending through the insulating layer. The plurality of conductive structures include a first conductive structure, a second conductive structure, a third conductive structure, and a fourth conductive structure, the first differential signal line is electrically connected to one electrode of the first capacitor through the first conductive structure, and the second differential signal line is electrically connected to the other electrode of the first capacitor through the second conductive structure. The third differential signal line is electrically connected to one electrode of the second capacitor through the third conductive structure, and the fourth differential signal line is electrically connected to the other electrode of the second capacitor through the fourth conductive structure.
In some embodiments, the plurality of capacitors further includes a third capacitor and a fourth capacitor, and the plurality of differential signal lines further includes a fifth differential signal line, a sixth differential signal line, a seventh differential signal line, and an eighth differential signal line. The fifth differential signal line is electrically connected to one electrode of the third capacitor, and the sixth differential signal line is electrically connected to the other electrode of the third capacitor. The seventh differential signal line is electrically connected to one electrode of the fourth capacitor, and the eighth differential signal line is electrically connected to the other electrode of the fourth capacitor. The second chip further has a third interface, the plurality of chips includes a third chip having a fourth interface, the third interface is electrically connected to the fifth differential signal line and the seventh differential signal line, and the fourth interface is electrically connected to the sixth differential signal line and the eighth differential signal line.
In some embodiments, the second chip and the third chip are spaced apart along a first direction, the first direction being parallel to the first surface, at least a portion of the third capacitor being located between the second chip and the third chip in the first direction, and at least a portion of the fourth capacitor being located between the second chip and the third chip.
In some embodiments, the first surface of the base layer is provided with a plurality of trenches extending from the first surface into the base layer, each capacitor including a first electrode, a dielectric layer, and a second electrode extending from the first surface into the plurality of trenches, respectively, the dielectric layer being disposed between the first electrode and the second electrode.
In some embodiments, the first interface and the second interface are both PCIE interfaces.
On the other hand, the application also provides electronic equipment, which comprises the chip packaging structure and the circuit board in any one of the embodiments, wherein the chip packaging structure is electrically connected with the circuit board.
In an embodiment of the present application, a communication channel between a first chip and a second chip of a chip package structure includes a pair of differential signal lines, wherein one differential signal line includes a first differential signal line and a second differential signal line, and the other differential signal line includes a third differential signal line and a fourth differential signal line. In addition, the adapter plate of the chip packaging structure further comprises a plurality of capacitors embedded in the adapter plate, the first differential signal wire is electrically connected with one electrode of the first capacitor, the second differential signal wire is electrically connected with the other electrode of the first capacitor, the third differential signal wire is electrically connected with one electrode of the second capacitor, and the fourth differential signal wire is electrically connected with the other electrode of the second capacitor, so that each differential signal wire in the pair of differential signal wires is connected with one capacitor in series. Based on the above, the limitation of the DDR or UCIE interface can be bypassed by the first interface of the first chip and the second interface of the second chip, for example, PCIE interface and the like can be adopted to implement interconnection communication between the two chips, and the capacitor connected in the pair of differential signal lines between the two chips is a capacitor directly formed in the interposer, so that the additional configuration of the surface mount capacitor in the chip package structure is avoided, the area of the package substrate is saved, the problem that the mounting process of the surface mount capacitor is incompatible with the mounting process of the chip package structure is also avoided, the cost is reduced, the higher integration level is realized, and the yield is improved.
Additional aspects and advantages of the application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application.
Drawings
The foregoing and/or additional aspects and advantages of the application will become apparent and may be better understood from the following description of embodiments taken in conjunction with the accompanying drawings in which:
Fig. 1 is a schematic cross-sectional view of a chip package structure according to an embodiment of the present application;
FIG. 2 is a top view of a chip package structure provided by the embodiment of FIG. 1;
FIG. 3 is a partial enlarged view of the chip package structure at A provided by the embodiment shown in FIG. 1;
fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
Embodiments of the present application are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the application.
The terms first, second and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged, as appropriate, such that embodiments of the present application may be implemented in sequences other than those illustrated or described herein, and that the objects identified by "first," "second," etc. are generally of a type, and are not limited to the number of objects, such as the first object may be one or more. Furthermore, in the description and claims, "and/or" means at least one of the connected objects, and the character "/", generally means that the associated object is an "or" relationship.
In the description of the present application, "plurality" means two or more.
In the description of the present specification, reference to the terms "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
In describing some embodiments, the expression "connected" and its derivatives may be used. The term "coupled" is used in a broad sense, and may be either permanently coupled, detachably coupled, or integrally formed, or indirectly coupled via an intervening medium, for example. The term "electrically connected" for example means that two or more elements are in direct physical or electrical contact, and may also mean that two or more elements are not in direct contact with each other but yet still co-operate or interact with each other. The embodiments disclosed herein are not necessarily limited to the disclosure herein.
Currently, chip-on-wafer-on-substrate technology (CoWoS) is a 2.5D packaging scheme of high-power chips which are more commonly used internationally, and under the packaging structure, most of communication interfaces between chips are high-density parallel signal interfaces such as DDR or UCIE.
However, the application of the DDR interface is limited by the domestic process capacity, and the UCIE interface standard protocol is not yet mature in the country, and the commercial UCIE interface is not mature. If these two interfaces are bypassed and other interfaces are used, other corresponding problems exist, for example, taking a PCIE interface as an example, according to PCIE interconnection protocol, a blocking capacitor with a certain capacitance value needs to be connected to two differential signal lines of a pair of differential signal lines respectively, however, since the mounting process of the surface mount capacitor is not compatible with the mounting process of the chip package structure, the surface mount capacitor cannot be connected to and integrated on the chip package structure.
Based on this, the present application provides a chip package structure, as shown in fig. 1 to 3, fig. 1 is a schematic cross-sectional view of the chip package structure provided by the embodiment of the present application, fig. 2 is a top view of the chip package structure provided by the embodiment of fig. 1, and fig. 3 is a partial enlarged view of the chip package structure at a provided by the embodiment of fig. 1.
As shown in fig. 1, the chip package structure 100 includes a package substrate 1, an interposer 2, and a plurality of chips 3. The interposer 2 is disposed on the package substrate 1, and is electrically connected to the package substrate 10 through a C4 solder bump. The plurality of chips 3 are disposed on a side of the interposer 2 away from the package substrate 1.
As shown in fig. 2 and 3, the interposer 2 includes a base layer 20, a plurality of capacitors 21, and a plurality of differential signal lines 22, the base layer 20 includes a first surface P1 away from a side of the package substrate 1, the plurality of capacitors 21 are embedded in the first surface P1, and the plurality of capacitors 21 include a first capacitor 211 and a second capacitor 212. The plurality of differential signal lines 22 are disposed on a side of the base layer 20 away from the package substrate 1, and the plurality of differential signal lines 22 include a first differential signal line 221, a second differential signal line 222, a third differential signal line 223, and a fourth differential signal line 224, the first differential signal line 221 being electrically connected to one electrode of the first capacitor 211, and the second differential signal line 222 being electrically connected to the other electrode of the first capacitor 211. The third differential signal line 223 is electrically connected to one electrode of the second capacitor 212, and the fourth differential signal line 224 is electrically connected to the other electrode of the second capacitor 212.
As shown in fig. 1 and 2, the plurality of chips 3 includes a first chip 31 and a second chip 32, the first chip 31 having a first interface 311, the second chip 32 having a second interface 321, the first interface 311 being electrically connected to the first differential signal line 221 and the third differential signal line 223, the second interface 321 being electrically connected to the second differential signal line 222 and the fourth differential signal line 224.
In the embodiment of the present application, the plurality of capacitors 21 are directly formed on the interposer 2, that is, the plurality of capacitors 21 are of the type of deep trench capacitors. The communication channel between the two chips of the chip package structure 100, taking the first chip 31 and the second chip 32 as an example, includes a pair of differential signal lines, which may be denoted as a differential signal line L1 and a differential signal line L2. One of the differential signal lines L1 includes a first differential signal line 221 and a second differential signal line 222, which are electrically connected to two electrodes of the first capacitor 211, respectively, so that the first capacitor 211 is connected in series to the differential signal line L1. The other differential signal line L2 includes a third differential signal line 223 and a fourth differential signal line 224, which are electrically connected to two electrodes of the second capacitor 212, respectively, so that the second capacitor 212 is connected in series to the differential signal line L2.
Based on this, a capacitor is connected in series to each differential signal line of a pair of differential signal lines between the first chip 31 and the second chip 32, so as to block direct current signals, and accordingly, the first interface 311 and the second interface 321 may bypass the limitation of the DDR or UCIE interface, for example, the first interface 311 and the second interface 321 may use PCIE interfaces, and a PCIE communication protocol is used to implement communication interconnection between the two chips.
In addition, since the capacitors 21 connected in series on the pair of differential signal lines between the two chips are deep slot capacitors directly formed on the adapter plate 2, the additional configuration of surface mount capacitors (such as multi-layer chip ceramic capacitors) in the chip package structure 100 is avoided, the area of the package substrate 1 is saved, the problem that the mounting process of the surface mount capacitors is not compatible with the mounting process of the chip package structure 100 is avoided, the cost is reduced, the higher integration level is realized, and the yield is improved.
Since the capacitor 21 is directly formed on the interposer 2, the capacitance value of the capacitor 21 can be precisely designed as required, and the limitation of the fixed capacitance value of the surface mount capacitor is avoided.
In addition, in the embodiment of the application, the capacitor 21 is directly formed on the adapter plate 2, the parasitic resistance and parasitic inductance of the capacitor 21 are lower, and in combination with the relevant regulations of the communication protocol, the capacitor 21 in the embodiment of the application can realize the communication effect regulated by the protocol with a lower capacitance value, so that the occupied area of the capacitor 21 on the adapter plate 2 can be further reduced, the size of the chip packaging structure 100 can be further reduced, and the integration level can be further improved.
In some embodiments, as shown in fig. 3, the first chip 31 and the second chip 32 are arranged at intervals along a first direction (X-axis direction), which is parallel to the first surface P1, in which at least part of the first capacitor 211 is located between the first chip 31 and the second chip 32, and at least part of the second capacitor 212 is located between the first chip 31 and the second chip 32.
Compared with the connection scheme adopting the surface-mounted capacitor in the related art, the capacitor 21 in the embodiment of the application is directly formed on the adapter plate 2, and based on the fact that the distribution position of the capacitor 21 is more flexible, the connection of the differential signal line 22 is facilitated by locating at least part of the first capacitor 211 between the first chip 31 and the second chip 32, the length of the differential signal line 22 is facilitated to be reduced, and the signal transmission time is reduced. In addition, the distribution position of the capacitor 21 is more flexible, so that the area of the adapter plate 2 can be fully utilized, and the size of the adapter plate 2 is beneficial to optimization.
In some embodiments, as shown in fig. 3, the interposer 2 further includes an insulating layer 23 and a plurality of conductive structures 24, the insulating layer 23 is disposed between the base layer 20 and the plurality of differential signal lines 22, and the plurality of conductive structures 24 penetrate the insulating layer 23. The plurality of conductive structures 24 includes a first conductive structure 241, a second conductive structure 242, a third conductive structure 243, and a fourth conductive structure 244, the first differential signal 221 line is electrically connected to one electrode of the first capacitor 211 through the first conductive structure 241, and the second differential signal line 222 is electrically connected to the other electrode of the first capacitor 211 through the second conductive structure 242. Similarly, the third differential signal 223 line is electrically connected to one electrode of the second capacitor 212 through the third conductive structure 243, and the fourth differential signal 224 line is electrically connected to the other electrode of the second capacitor 212 through the fourth conductive structure 244.
The plurality of conductive structures 24 are used for realizing the electrical connection between the plurality of differential signal lines 22 and the corresponding capacitors 21, so that the electrode of the capacitor 21 and the layered arrangement of the differential signal lines 22 on the adapter plate 2 are facilitated under the condition that the capacitors 21 are embedded in the adapter plate 2, the wiring design of the plurality of differential signal lines 22 on the adapter plate 2 is further facilitated to be optimized, the area of the adapter plate 2 is reduced, and the packaging integration level is improved.
In some embodiments, as shown in fig. 2, the plurality of capacitors 21 further includes a third capacitor 213 and a fourth capacitor 214, and the plurality of differential signal lines 22 further includes a fifth differential signal line 225, a sixth differential signal line 226, a seventh differential signal line 227, and an eighth differential signal line 228. The fifth differential signal line 225 is electrically connected to one electrode of the third capacitor 213, and the sixth differential signal line 226 is electrically connected to the other electrode of the third capacitor 213. The seventh differential signal line 227 is electrically connected to one electrode of the fourth capacitor 214, and the eighth differential signal line 228 is electrically connected to the other electrode of the fourth capacitor 214. The second chip 32 further has a third interface 322, the plurality of chips 3 includes a third chip 33, the third chip 33 has a fourth interface 331, the third interface 322 is electrically connected to the fifth differential signal line 225 and the seventh differential signal line 227, and the fourth interface 331 is electrically connected to the sixth differential signal line 226 and the eighth differential signal line 228.
In an embodiment of the present application, a plurality of interfaces may be included on each chip, for example, the second chip 32 includes a second interface 321 and a third interface 322. Similar to the communication interconnection between the first interface 311 of the first chip 31 and the second interface 321 of the second chip 32, the communication channel between the third interface 322 and the fourth interface 331 also includes a pair of differential signal lines, which may be denoted as a differential signal line L3 and a differential signal line L4. Wherein the differential signal line L3 includes a fifth differential signal line 225 and a sixth differential signal line 226, which are electrically connected to both electrodes of the third capacitor 213, respectively, thereby connecting the third capacitor 213 in series to the differential signal line L3. The other differential signal line L4 includes a seventh differential signal 227 line and an eighth differential signal line 228, which are electrically connected to the two electrodes of the fourth capacitor 214, respectively, so that the fourth capacitor 214 is connected in series to the differential signal line L4.
Based on this, it is realized that each differential signal line of the pair of differential signal lines between the second chip 32 and the third chip 33 is connected to a capacitor, so as to block the direct current signal, and the corresponding third interface 322 and fourth interface 331 may bypass the limitation of the DDR or UCIE interface, for example, adopt a PCIE interface, and utilize a PCIE communication protocol to implement communication interconnection between the two chips.
In some embodiments, as shown in fig. 2, the second chip 32 and the third chip 33 are arranged at intervals along a first direction, where the first direction may be an X-axis direction as shown in fig. 2, or a Y-axis direction, or other directions parallel to the X-Y plane, and specifically may be appropriately designed according to the chip packaging requirement, and in the first direction, at least part of the third capacitor 213 is located between the second chip 32 and the third chip 33, and at least part of the fourth capacitor 214 is located between the second chip 32 and the third chip 33.
By reasonably arranging the positions of the third capacitor 213 and the fourth capacitor 214, connection of the differential signal line 22 is facilitated, the length of the differential signal line 22 is reduced, the signal transmission time is reduced, and the size of the interposer 2 is optimized.
In some embodiments, as shown in fig. 3, the first surface P1 of the base layer 20 is provided with a plurality of trenches T1, the plurality of trenches T1 extend from the first surface P1 into the base layer 20, each capacitor 21 includes a first electrode D1, a dielectric layer D3, and a second electrode D2, the first electrode D1 and the second electrode D2 extend from the first surface P1 into the plurality of trenches T1, respectively, and the dielectric layer D3 is disposed between the first electrode D1 and the second electrode D2.
As shown in fig. 3, for example, each capacitor 211 includes a plurality of trenches, and in each trench, the first electrode D1, the dielectric layer D3 and the second electrode D2 may form a staggered multi-layer structure, so that it is beneficial to implementing designs of different capacitance values, meeting the communication requirements between chips, and reducing the area of the capacitor 21 occupied by the interposer 2, thereby reducing the size of the chip package structure 100, reducing the cost, and improving the integration level,
In some embodiments, the first interface 311 and the second interface 321 are PCIE interfaces. Because the deep slot capacitor is integrated on the adapter plate 2, the scheme of connecting the capacitor 21 in series to the differential signal line is simple to operate, based on the scheme, communication interconnection between two chips is possible by using the PCIE communication protocol, and PCIE interface technology development is mature, so that the technology limit is broken, and the interconnection performance between the chips is improved.
In a second aspect, as shown in fig. 4, fig. 4 is an electronic device provided in an embodiment of the present application, where the electronic device 200 includes the above-mentioned chip package structure 100, and a circuit board 201, and the chip package structure 200 is electrically connected to the circuit board 201.
In the chip packaging structure 100 in the electronic device 200, the capacitor 21 is connected in series to the differential signal line, based on the fact that the interconnection communication between the two chips can bypass the limit of the DDR or UCIE interface, for example, the limitation can be realized by adopting a PCIE interface and the like, and the capacitor connected to the pair of differential signal lines between the two chips is a deep groove capacitor embedded in the adapter plate, so that the surface mounting capacitor is prevented from being additionally arranged in the chip packaging structure 100, the area of the packaging substrate 1 is favorably saved, the problem that the mounting process of the surface mounting capacitor is incompatible with the mounting process of the chip packaging structure is also avoided, the cost is reduced, the higher integration level is realized, and the yield is favorably improved.
Although embodiments of the present application have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the spirit and scope of the application as defined by the appended claims and their equivalents.
Claims (8)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202411656893.5A CN119601543A (en) | 2024-11-19 | 2024-11-19 | Chip packaging structure and electronic equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202411656893.5A CN119601543A (en) | 2024-11-19 | 2024-11-19 | Chip packaging structure and electronic equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN119601543A true CN119601543A (en) | 2025-03-11 |
Family
ID=94833600
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202411656893.5A Pending CN119601543A (en) | 2024-11-19 | 2024-11-19 | Chip packaging structure and electronic equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN119601543A (en) |
-
2024
- 2024-11-19 CN CN202411656893.5A patent/CN119601543A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100390997C (en) | Multilayer capacitors with multiple plates per layer | |
| CN209929298U (en) | Chip package | |
| US6970362B1 (en) | Electronic assemblies and systems comprising interposer with embedded capacitors | |
| US7986532B2 (en) | Split thin film capacitor for multiple voltages | |
| CN101527199B (en) | Capacitor device and circuit | |
| KR100543853B1 (en) | Capacitors with extended surface lands and methods of manufacturing the same | |
| JP5124150B2 (en) | Multilayer printed wiring board | |
| KR20060103540A (en) | Array Capacitor with Space to Enable Full-Grid Sockets | |
| CN102638931B (en) | Electronic assembly, method for minimizing parasitic capacitance, and method for manufacturing circuit board structure | |
| CN1809974B (en) | Capacitor-related systems for addressing package/motherboard resonance | |
| CN221201179U (en) | Packaging structure | |
| CN119601543A (en) | Chip packaging structure and electronic equipment | |
| JP2008124072A (en) | Semiconductor device | |
| CN103426633B (en) | Capacitance structure | |
| CN114501796A (en) | Vehicle-mounted gateway printed circuit board | |
| CN113422589A (en) | Acoustic surface filter | |
| CN222051740U (en) | Chip packaging structure, packaging module and electronic device | |
| US6525945B1 (en) | Method and system for wide band decoupling of integrated circuits | |
| KR100669963B1 (en) | Multilayer Wiring Board and Manufacturing Method Thereof | |
| CN217936067U (en) | Printed circuit boards and electronic equipment including printed circuit boards | |
| CN218647936U (en) | Semiconductor capacitor structure | |
| CN209947823U (en) | Chip packaging structure | |
| CN115831937A (en) | Semiconductor structure | |
| CN118352337A (en) | Electric connection structure and semiconductor packaging structure | |
| CN117352505A (en) | Chip packaging structure, packaging method and electronic equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |