Disclosure of Invention
The invention aims to provide an automatic photomask pattern data generating system and a using method thereof, which realize unified processing of template information of masks in different formats through a whole set of system, the processed data can be read out through the whole set of system, and the molding precision after reading out is ensured. And meanwhile, the possibility of divulging the template information of the mask is reduced.
In order to achieve the purpose, the automatic photomask graphic data generating system comprises a metadata structured shell, and a corresponding metadata base is built based on the metadata structured shell, wherein the metadata structured shell consists of a shell layer, a core layer and an environment adaptation layer, the shell layer stores customer data and a photomask molding data deployment system catalog, the core layer is provided with a specific source file and a photomask molding data deployment system, the environment adaptation layer is provided with an interface which is interconnected with a corresponding operating system, and the metadata structured shell can be identified by the corresponding operating system.
Preferably, the method for manufacturing the metadata structured shell comprises the specific steps of accessing a main chip layout database provided by a customer by a system, acquiring database information provided by the customer, a mask generation table and related files for auxiliary work from the main chip layout database to a customer engineering part, carrying out mask processing planning on a mask by the customer engineering part according to the information acquired from the main chip layout database and combining a specification provided by a chip factory, defining mask requirements and issuing a data release notice, carrying out unit merging and checking and cleaning and judging of design rules based on data acquired by the two data sources at the moment, if the unit merging and checking and cleaning of the design rules are completed, directly transmitting to a mask data engineering department, and generating a source file and a conversion data file recorded in the metadata structured shell by combining a mask grade specification provided by the mask factory and a mask related quality specification. The method for manufacturing the metadata structured shell can effectively improve the accuracy and standardization of the manufactured source file data. The method integrates information and specifications of clients, chip factories and mask factories by accessing the multiparty database, and utilizes a standardized flow to process data so as to reduce human errors.
Preferably, when the process of checking and cleaning the determination unit combination and the design rules is not completed, the layout combination and the rule checking of the design are performed through the design service and the product part, after the layout combination and the rule checking are completed, the layout combination and the rule checking are put into a metadata base, a data release/revision notification is issued, the data is sent to a mask data engineering department, and a source file and a conversion data file recorded in a metadata structured shell are generated by combining the mask grade specification provided by a mask factory and the mask related quality specification. The processing mode can solve the key task which is not finished in the earlier stage by means of the force of a professional department, ensure the compliance and the completeness of data, ensure the smooth promotion of the metadata structured shell generation flow and improve the data quality and the product reliability. Source files with flaws are avoided.
Preferably, the mask material engineering unit generates a field layout based on the acquired data, and data input and data division of the mask material deployment system are required in the field layout generation process, and finally, a workbench view is presented, mask processing information is determined according to the workbench view, and the mask processing information is stored in a source file and a conversion data file, respectively.
Preferably, the foundry provided specifications include at least bias tables, design rules, and specified mask level information. This also serves to ensure that the resulting metadata structured shell is indeed usable.
The invention also comprises a using method of the automatic photomask pattern data generating system, which is characterized in that when a mask is manufactured, local equipment acquires a metadata structured shell from a metadata base, an environment adaptation layer in the metadata structured shell identifies an operating system where the local equipment is located and carries out automatic configuration, the local equipment uploads customer information, the acquired customer information is compared with customer data in a shell layer to confirm the identity of the local equipment, a corresponding mask template modeling data deployment system is selected from a mask template modeling data deployment system catalog after the identity is confirmed, equipment data and software data which can be identified by the local equipment are obtained through the mask template modeling data deployment system, equipment configuration is carried out by utilizing the acquired equipment data, and modeling is carried out by utilizing the acquired software data.
Preferably, when the mask template data deployment system analyzes the corresponding source file, a metadata base is accessed into the mask template data deployment system, the corresponding source file is obtained according to a conversion data file in the mask template data deployment system, the mask template data deployment system at least comprises a database management system, a plate making information processing system, a mask design completion management system and a mask management system, the database management system comprises a mask template login system and a mask typesetting planning system, the mask typesetting planning system is connected with the plate making information processing system, the plate making information processing system is connected with the mask data processing system and the plate making specification management system, the source file is analyzed into equipment data and software data in the mask information processing system, the mask design completion management system is connected with the mask management system, the metadata base outputs software data in standardized information format after the plate making information is read into metadata and metadata, the metadata comprises frame information, element information, the metadata comprises metadata and mask information, and production line metadata, and the metadata belongs to the mask information layer of the mask information.
Preferably, the mask-in management system forms data and optical compensation information, a data file description table and a layout chart, and is connected with the mask data processing system through the process integration module.
Preferably, the typesetting frame information comprises data typesetting frame information, test element information on a cutting line and single modularized test element information, wherein the data typesetting frame information is obtained and then is packed together again and encrypted, and the encrypted file is added with a frame GDSII and a CD picture label of a working file.
Preferably, the mask shop performs mask fabrication by the work-in-process frame GDSII and CD icon, and a mask control system in the mask shop monitors the fabrication process and performs feed quality control and final inspection of the mask.
By adopting the technical scheme, the metadata structured shell is generated, and can be used as an intermediate layer in chip design software and manufacturing flow management systems. When the designer makes a chip design, they input, store and retrieve source files through the metadata structured shell. In the manufacturing step, the production equipment and the process control system also obtain source files required for chip manufacturing through the shell. The metadata structured shell plays a key role in organizing, protecting and transmitting metadata in the field of chip manufacturing, and is beneficial to improving the efficiency and quality of chip design and manufacturing.
Meanwhile, the communication and file communication among the chip generating manufacturer, the mask manufacturer and the clients are simplified, and the communication can be gradually expanded to the same industry standard, so that the operation flow of each manufacturer is simplified. In addition, in outsourcing production, file communication is simplified, so that a friend factory does not need to read the processing mode again, and does not need to transmit the processing mode of a client, and the working efficiency and the data safety are greatly improved. The automated process of data processing is independent and will not be affected by changes in customer processing mode, further ensuring process stability and efficiency. These measures not only save development and testing costs, but also reduce the risk of program modification. The design of the metadata structured shell is easy to read uniformly and reduce errors, is not limited by different databases and database structures, and greatly promotes the unobstructed circulation of data.
Detailed Description
The preferred embodiments of the present invention will be described below with reference to the accompanying drawings, it being understood that the preferred embodiments described herein are for illustration and explanation of the present invention only, and are not intended to limit the present invention.
In order to clearly express the matters related to the present invention, first, a part of abbreviations related to the present invention will be explained.
MPW, i.e. "Multi-Project Wafer", is of particular interest in terms of photomask data for chip fabrication. The background is to reduce the cost of chip design, especially in small volume production or chip prototype fabrication stages. The operation mode is that the foundry receives the layout data of different client chips according to rules and time schedule, and the layout data is reasonably arranged in different areas of the same wafer after being processed, and various functional chip layouts can coexist, and each chip is subjected to photoetching, etching and other processes at the same time. The MPW can greatly reduce the cost, quicken the research and development progress, enable a plurality of design projects to quickly enter the manufacturing stage and shorten the period from design to test.
GDSII graphics data system II (Graphic Data System II) is a standard file format for integrated circuit layout data exchanges. It is a data format that is widely used in the field of chip design and manufacturing, primarily to describe the physical layout of Integrated Circuits (ICs). The file format can accurately record the geometric shapes, position information, hierarchical relations and other contents of various physical structures on the chip.
MEBES mask data preparation System the electron beam exposure standard (Manufacturing Electron-Beam Exposure Standard) is a mask data format that is used primarily in an electron beam exposure system. Plays an important role in the chip manufacturing process, especially in the high-precision mask manufacturing link. It is a format developed to meet the requirements of electron beam lithography for mask data accuracy and complexity.
RDDS reticle modeling data deployment System (RETICLE DATA Deployment System). RDDS data are used for collecting molding data and generating the data according to the process parameters of each technical node. It is a comprehensive data set that covers a variety of critical information from the receipt, processing, to the ultimate application of the molding information to the lithography process.
Masks, i.e., masks or reticles, play a critical role in the chip manufacturing process. It is like a 'mask', on which there are patterns according to the chip layout design. In the photolithography process, light is irradiated to the surface of a silicon wafer coated with photoresist through a transparent portion on a mask, so that the photoresist is chemically changed, thereby transferring a pattern on the mask to the silicon wafer.
Metadata base-by general definition, a Metadata base is a special database that is mainly used to store data about data, i.e., metadata (Metadata). In the invention, the manufactured metadata structured shell, various source files and part of information analyzed from the source files are all stored in the same database, and the database is named as a metadata database.
As an embodiment, an automated photomask pattern data generating system of the present invention includes creating a metadata structured shell and creating a corresponding metadata database based on the created metadata structured shell. As shown in fig. 1, the metadata structured shell is composed of a shell layer, a core layer and an environment adapting layer, wherein the shell layer stores customer data and a reticle modeling data deployment system catalog, the core layer is provided with a specific source file and a reticle modeling data deployment system, and the environment adapting layer is provided with an interface which is interconnected with a corresponding operating system, so that the metadata structured shell can be identified by the corresponding operating system.
As shown in fig. 2, the process is initiated by the customer, the system accesses a main chip layout database provided by the customer, the main chip layout database (Main Chip Layout Data Base) is a basic layout data source according to the whole chip manufacturing process, and the key information such as the layout of the chip is carried in a specific file format, and then is transmitted to other related departments for further operation and processing. The customer engineering part processes and plans the mask according to the information obtained from the main chip layout database and combines the specification provided by the chip factory, confirms the mask requirement and issues the data release notice, at the moment, performs unit merging and checking and cleaning judgment of the design rules based on the data obtained by the two data sources, if the unit merging and the checking and cleaning of the design rules are completed, the data is directly sent to the mask data engineering department, and generates the source file and the conversion data file recorded in the metadata structured shell by combining the mask grade specification provided by the mask factory and the quality specification related to the mask.
The main chip Layout database is a key basis of a chip manufacturing flow and contains important matters of Physical-layer Layout (Physical-layer Layout), which is the representation of a chip Physical structure on a plane. It details the location, shape and size of the various physical components (e.g., transistors, capacitors, resistors, etc.) in the chip. For example, for a transistor, the specific locations of its source, drain and gate and the distances between them are indicated. This information is critical to the process of photolithography, etc., because photolithography requires precise transfer of the pattern of these physical structures onto the silicon wafer. Also included are layouts of different functional blocks (e.g., CPU cores, caches, I/O interfaces, etc.) on the chip. Taking a CPU core as an example, the position relation of components such as an Arithmetic Logic Unit (ALU), a register and the like in the CPU core can be clearly shown in a layout, so that the signal transmission path between the CPU core and the register meets the design requirement.
Metal-Wiring-layer Layout (Metal-Layout):
The layout of the metal wires in the chip is mainly recorded. These metal wires are used to connect the various physical components to effect signal transmission. The information of width, thickness, trend and the like of the lead is contained. For example, in the chip of the prior art, in order to reduce the signal delay, the metal wiring may have a multi-layer structure, the wiring directions of each layer may be perpendicular to each other (for example, one layer is a horizontal wiring, and the other layer is a vertical wiring), and the main chip layout database will describe the specific layout of each layer of metal wiring in detail.
Functional module description (Functional-Module Description) includes module type and function (Module Type and Function):
The type of each functional module is defined, such as a digital signal processing module (DSP), an analog front end module (AFE), etc. The functions of each module are described in detail, for example, the DSP module is responsible for filtering, modulating and other operations of the digital signals, and the database records the specific algorithm implementation mode and the characteristics of the input and output signals. For complex functional modules, such as Graphics Processing Units (GPUs) in a system on a chip (SoC), the graphics rendering algorithms (e.g., vertex shading, pixel shading, etc.) supported by the GPU, and interactions with other modules (e.g., memory controllers, display interfaces, etc.) are included.
Module interface information (Module-INTERFACE INFORMATION):
The interface signals of each functional module are recorded, including the name, type of signal (such as digital signal or analog signal), level standard (such as TTL level, CMOS level), etc. For example, the interface signals of a memory module may include address bus signals, data bus signals, read/write control signals, etc., and the database may specify information such as bit width, transmission direction, etc. of these signals to ensure that the modules can communicate correctly.
Design-Rule-related data (Design-Rule-RELATED DATA), such as Minimum-Size Constraints, are included that specify the Minimum Size of the various physical structures in the chip. Such as the minimum channel length of the transistor, the minimum width of the metal line, etc. These minimum size limitations are set based on the capabilities of the chip manufacturing process to ensure that the chip can reliably perform its design functions during the manufacturing process. If these dimensions are smaller than the prescribed values, process variations in the manufacturing process, such as short circuits, leakage, and the like, may be caused. There is also a minimum size requirement for gaps in the chip (e.g., the spacing between two adjacent metal lines). This is to prevent crosstalk between signals, and to ensure independence and accuracy of signal transmission.
Spacing Rules (Spacing-Rules) are also included, as are Spacing Rules between different functional modules, in addition to the wire Spacing mentioned above. For example, to avoid electromagnetic interference between analog and digital modules, a minimum distance between them may be specified. Meanwhile, in the same functional module, space requirements, such as the space between a transistor and a capacitor, exist between different physical structures so as to ensure that the transistors and the capacitors cannot influence each other in the working process.
The above is specific database Information (d.b. Information), which belongs to one of the important files transmitted from the client, and contains various detailed data descriptions related to the chip layout database. The mask generation table Mask Generation Table is a file for guiding the mask production related plan, and defines various specifications, requirements and the like required for mask production.
Other related documents (Related documents) include other ancillary or complementary documents related to aspects of chip layout, design, etc., such as Electrical Parameters (Electrical-Parameters) including Electrical Parameters of various components of the chip, such as threshold voltages of transistors, on-resistances, capacitance values of capacitors, resistance values of resistors, etc. These electrical parameters directly affect the performance of the chip, such as the operating speed, power consumption, etc. of the chip. For example, by adjusting the threshold voltage of the transistor, the operating current of the chip can be controlled, thereby affecting the balance between power consumption and speed of the chip. For the power network in the chip, parameters such as power voltage, power current and the like, and information such as isolation requirements among different power domains are recorded, so that all parts of the chip can be ensured to stably acquire required power supply. And some Process-Parameters related to the chip manufacturing Process, such as resolution of lithography, depth control Parameters of etching, etc. These parameters are strictly controlled during the chip manufacturing process, and the master chip layout database records these parameters to provide accurate operation basis for the manufacturing equipment. For example, parameters such as exposure dose and focal length in the photolithography process can be adjusted according to the set values in the database, so as to ensure that the chip layout can be accurately copied to the silicon chip.
The customer engineering department carries out mask processing planning on the mask according to the information obtained from the main chip layout database and the specification provided by the chip factory, and confirms the mask requirement and issues data release notification. The mask processing planning (Reticle Tooling planning) refers to the overall planning of mask processing links according to the received file contents such as a mask generation table, and determines the arrangement of processing steps, sequences, process points and the like. And mask molding requirements (Reticle requisition) for specifying specific requirements of masks in terms of quantity, type, precision, etc. in the chip manufacturing process and forming corresponding files. And carrying out data release notification (DATA RELEASE Notice) on the data, wherein the notification is used for notifying the follow-up links of which data can be used or are formally released, and ensuring that each department acquires and uses the corresponding data at the proper time.
The chip factory provides a Data Table (Data Table) and a Design Rule (Design Rule) for defining various rules to be followed in the chip Design process, such as wiring rules, element layout rules and the like, so as to ensure the performance, manufacturability and the like of the chip, and specifies a mask level (SPECIFY MASK GRADE) for determining the mask level required to be used by each part according to different functional requirements, precision requirements and the like of the chip.
And at the moment, carrying out unit merging and checking and cleaning judgment of design rules based on the data acquired by the two data sources, and if the unit merging and the checking and cleaning of the design rules are completed, directly sending the data to a mask data engineering department, and generating a source file and a conversion data file recorded in a metadata structured shell by combining mask grade specifications provided by a mask factory and mask related quality specifications. When the checking and cleaning process of the judging unit merging and the design rule is not finished, carrying out layout merging and rule checking of the design through the design service and the product part, after the layout merging and the rule checking are finished, putting the layout merging and the rule checking into a metadata base, issuing a data release/revision notification, sending the data to a mask data engineering department, and generating a source file and a conversion data file which are recorded in a metadata structured shell by combining mask grade specifications provided by a mask factory and mask related quality specifications.
In the mask data engineering section, the field layout is generated based on the acquired data. The field layout generation (Field Layout Generation) is a technical key point of the invention, and generates a layout structure of a field on a mask according to the related files about the chip layout transmitted before, determines the contents of specific patterns, functional division and the like of different areas on the mask, and provides a detailed layout foundation for the subsequent specific mask manufacturing steps.
It specifically includes functional area division, which includes CPU core area for a processor chip. Within this region, sub-regions of instruction decode units, arithmetic Logic Units (ALUs), register files, etc. are partitioned. For example, the ALU area may be further subdivided according to its operation functions (such as addition, multiplication, etc.), so as to ensure a reasonable layout of different operation units, so as to reduce signal transmission delay. For memory chips, such as DRAMs, the memory cell array area is divided. This area is composed of a large number of memory cells (such as memory cells composed of capacitors and transistors), and there are peripheral circuit areas such as row decoders, column decoders, etc. for performing read and write operations on the memory cells.
For an input/output (I/O) area, physical areas corresponding to various interface pins, such as a power pin, a ground pin, a data input/output pin, and the like of a chip, are included. The layout of these pins needs to take into account signal integrity, electromagnetic compatibility, etc. For example, the high speed data interface pins may be placed in areas close to the chip edge and well isolated from each other to reduce signal reflection and cross-talk. There are also buffer circuit areas for connecting the functional modules inside the chip with external devices, such as input buffers and output buffers, which are laid out to facilitate efficient transfer of signals and adaptation of driving capabilities.
For the auxiliary functional area, a clock generation and distribution circuit area is included. The clock signal is the key to the proper operation of the chip, and the layout of this area is to ensure that the clock signal can be evenly and quickly distributed to each required functional module. For example, a tree or mesh clock distribution network may be employed, the layout of which in the chip may be optimized according to the location of the functional modules and the load requirements of the clock signals.
There is also a test circuit area for functional testing and fault diagnosis after the chip fabrication is completed. The layout of the test circuits is convenient for injecting test signals and collecting test results under the condition of not affecting the normal functions of the chip.
After dividing the areas, generating and arranging patterns, and generating specific layout patterns in each functional area according to the requirements of chip design. Taking a transistor as an example, the shape and size of the pattern of the active region, gate, etc. of the transistor are determined when generating the field layout. For metal wiring, the detailed patterns of the trend, the bending angle, the connection mode and the like of each section of metal wire are determined. These patterns are generated based on layout information in the master chip layout database in combination with requirements of the manufacturing process.
For some special structures, such as via (via) patterns between multiple metal interconnect lines in a chip, designs are designed based on the connection relationship between metal layers and electrical performance requirements. The size, shape, distribution density, etc. of the vias are determined during the field layout generation process to ensure good electrical connection between the different metal layers.
Wherein the pattern arrangement follows a certain symmetry and repeatability rule. In some functional modules of the chip, such as a memory cell array, the memory cells are arranged in a certain matrix form, and this regular arrangement helps to improve the manufacturing efficiency and performance stability of the chip. For example, in a DRAM chip, memory cells are arranged in rows and columns, and the spacing and alignment between rows and columns are in accordance with design rules and manufacturing process requirements.
Meanwhile, the relative positional relationship between different patterns is considered to avoid short circuits and interference. For example, in the analog circuit area of the chip, the wiring of the analog signal and the wiring of the digital signal are ensured to keep a sufficient distance, and the layout is performed according to a certain shielding rule, so as to prevent the digital signal from interfering with the analog signal.
One by one lithographic field division and layout adaptation is also required. The photoetching field division is based on dividing the whole field layout of the chip into a plurality of photoetching fields according to the size and the precision requirement of the exposure area of the photoetching equipment. The size and shape of the lithographic field is generally determined by the technical parameters of the lithographic apparatus. For example, for a common lithographic apparatus, the exposure field may be a square area with a side length of tens of millimeters, and the field layout may be generated by reasonably dividing the chip layout according to the size. The division of the lithography field may also incorporate functional areas of the chip, considering the complexity of the chip layout and the requirements of the manufacturing process. For example, a complete functional module (e.g., a small processor sub-module) is partitioned into one lithography field as much as possible to reduce errors and performance effects that may occur when stitching between different lithography fields.
And the layout adaptation strategy is to adapt the layout of the chip layout in each lithography field. This includes adjusting the position and size of the pattern to ensure that the pattern is accurately transferred to the wafer during the lithographic process. For example, for patterns near the edges of the lithographic field, appropriate scaling or shifting may be performed to compensate for pattern distortions caused by edge effects during the lithographic process.
A stitching strategy between different lithography fields needs to be considered. And a plurality of special alignment marks and splicing patterns are designed in the joint area of the adjacent photoetching fields and are used for realizing accurate alignment and splicing in the photoetching process, so that the integrity and the accuracy of the whole chip layout are ensured.
RDDS data input (RDDS DATA ENTRY) is required in the field layout generation process, namely, relevant RDDS data is input, data segmentation (Data Fracturing) is performed, and received relevant data is subjected to segmentation processing. The necessary data support is provided for the mask making system so that it can accurately make the mask according to the design requirements.
The mask plate pre-exposure View (Job Deck View) shows that before the mask is manufactured on the mask plate exposure machine, the circuit pattern of the mask plate is pre-inspected with the graphic information in front of the computer screen, so that the possible errors of the computer graphic shift can be detected as soon as possible before the cost of the mask plate which is not actually exposed.
Mask processing information Mask Tooling Information includes various process information related to the mask processing process, such as the process equipment parameters used, the specific timing of the processing steps, etc., and provides detailed guidance for the actual mask processing operation.
Finally, the source file and the converted data file (Save Source and Converted Data file, doc.) are saved, wherein the source file and the converted related data file are related in the mask manufacturing process, so that subsequent traceability, rechecking, possible further optimization and other works are facilitated, and the data integrity and traceability of the whole mask manufacturing process are ensured.
The method comprises the steps of obtaining a metadata structured shell from a metadata base by local equipment when a mask is manufactured, identifying an operating system where the local equipment is located by an environment adaptation layer in the metadata structured shell and carrying out automatic configuration, uploading client information by the local equipment, comparing the obtained client information with client data in a shell layer to confirm the identity of the local equipment, selecting a corresponding mask modeling data deployment system from a mask modeling data deployment system catalog after confirming the identity, and unlocking a source file through the mask modeling data deployment system to obtain equipment data and software data identifiable by the local equipment, carrying out equipment configuration by utilizing the obtained equipment data, and carrying out modeling by utilizing the obtained software data. When the mask template modeling data deployment system analyzes the corresponding source files, a metadata base is accessed into the mask template modeling data deployment system, the mask template modeling data deployment system obtains the corresponding source files according to the conversion data files, the mask template modeling data deployment system at least comprises a database management system, a plate making information processing system, a mask design completion management system and a mask leading-in management system, the database management system comprises a mask template logging system and a mask template typesetting planning system, the mask template typesetting planning system is connected with the plate making information processing system, the plate making information processing system is connected with the mask data processing system and the plate making specification management system, the source files are analyzed into equipment data and software data in the plate making information processing system, the mask design completion management system is connected with the mask leading-in management system, the metadata base outputs software data in standardized information formats, wherein the software leading-in management system reads plate making information in different formats and decomposes the plate making information into metadata and metadata, the metadata comprises frame information, elements, the metadata comprises mask metadata and mask typesetting information, and the metadata belongs to mask typesetting information of mask layers. The mask-in management system is connected with the mask data processing system through the process integration module.
As shown in fig. 4, the metadata database outputs software data in standardized information format, namely, plate-making information in different formats is read, and the plate-making information is decomposed into metadata mold data and metadata mask information, wherein the metadata mold data comprises typesetting frame information and component mold information, the metadata mask information comprises product codes and production line information, and mask layer information simultaneously belongs to the metadata mold data and the metadata mask information. The typesetting frame information comprises data typesetting frame information, test element information on a cutting line and single modularized test element information, wherein the data typesetting frame information is obtained and then is packed together again and encrypted, and a work file is added with a frame GDSII and a CD picture label of the work file after encryption. The data source after standardized information format is paper plate making data or electronic file, and the paper plate making data is manually input into metadata base. The mask is introduced into the management system to form data, optical compensation information, a data file description table and a typesetting diagram. The mask-in management system is connected with the mask data processing system through the process integration module. The method comprises the steps of generating a Boolean operation script file for mask data processing through a mask modeling data deployment system, wherein the Boolean operation format and grammar representation of the Boolean operation script file are similar to those of the Boolean operation script file:
FINAL = ((Operand-1)|(Operand-2 {operator Operand-2}*))
Operator = (AND|OR|NOT|XOR|...)
Operand-1 = {REVERSE}* Pattern
Operand-2 = Pattern {(SIZING value)*|(SCALE value)|(ORIENTATION value)}*
Pattern = (Layers|MEBES|OASIS.MASK|CFLT|CREF)
Layers = {[DB#]}*L(ID){(<space>{[DB#]}*L(ID))+}*
ID = (0-9)+{(,0-9)+}*{;(0-9)+{(,0-9)+}*}*。
the instruction file of the brin operation processed by the mask data is made into a specific instruction file combined with the form. For example:
General Information for Mask Tooling
*********************************************************************
STEPPER : ASML Magnification : 1X FLOW : F1001BIWT Unit : MM
PROCESS : BIM35WET
ORDER : 9876543
OPIMIZED ARRAY = 8 X 5
FIELD STEP SIZE X = 25.92000 Y = 27.90000
FIELD EXPOSURE SIZE X = 26.00000 Y = 27.98000
FIELD LAYOUT COORDINATES XLB = -13.00000 YLB = -14.86500
XLT = -13.00000 YLT = 13.11500
XRB = 13.00000 YRB = -14.86500
XRT = 13.00000 YRT = 13.11500
ARRAY OFFSET X = 0.000000 Y = -0.875000
*********************************************************************
1)MAIN CHIP CODE : 9876543
2) LAYOUT WINDOW SIZE : X = 3.160000 Y = 5.500000
3) STREET WIDTH X = 0.080000 Y = 0.080000
4) CHIP SIZE X = 3.240000 Y = 5.580000
5) POSITION LIST : (1X)
CHIP NAME X-COODINATE Y-COODINATE
=========== ============= =============
MAINCHIP_0_8 -11.340000 -12.035000
MAINCHIP_0_8 -8.100000 -12.035000
MAINCHIP_0_8 -4.860000 -12.035000
MAINCHIP_0_8 -1.620000 -12.035000
MAINCHIP_0_8 1.620000 -12.035000
MAINCHIP_0_8 4.860000 -12.035000
MAINCHIP_0_8 8.100000 -12.035000
MAINCHIP_0_8 11.340000 -12.035000
MAINCHIP_1_8 -11.340000 -6.455000
MAINCHIP_1_8 -8.100000 -6.455000
MAINCHIP_1_8 -4.860000 -6.455000
MAINCHIP_1_8 -1.620000 -6.455000
MAINCHIP_1_8 1.620000 -6.455000
MAINCHIP_1_8 4.860000 -6.455000
MAINCHIP_1_8 8.100000 -6.455000
MAINCHIP_1_8 11.340000 -6.455000
MAINCHIP_2_8 -11.340000 -0.875000
MAINCHIP_2_8 -8.100000 -0.875000
MAINCHIP_2_8 -4.860000 -0.875000
MAINCHIP_2_8 -1.620000 -0.875000
...”
As shown in FIG. 2, a mask shop is actually the final application of the metadata structured shell of the present invention, and on the one hand, provides data for generating the metadata structured shell, wherein the provided data comprises mask grade specifications (MASK GRADE spec.) according to the related files such as the specified mask grade transmitted from the previous links, and further refines and determines the specific grade specification of the mask, so as to guide the process selection, quality control and other aspects in the mask manufacturing process to work.
And the quality specification (Mask-Incoming & outlining QC spec) of the Mask is formulated, the quality detection specification of the Mask during feeding and discharging is formulated, and various quality indexes, detection methods and the like are defined, so that the Mask can meet the corresponding quality requirements when entering a factory and discharging after manufacturing is finished, and the quality stability of Mask links in the whole chip manufacturing chain is ensured.
On the other hand, the mask is manufactured (MASK MAKING) after receiving the files transmitted by the mask data engineering, according to the data, specifications and the like provided by all the links, the mask manufacturing work is actually carried out, and the designed mask layout is converted into an actual mask product through a series of complex processes such as photoetching, etching and the like.
And (3) performing mask feeding quality control (Reticle Incoming QC) (IQC) on the manufactured mask, wherein the mask entering a factory is subjected to feeding quality control, and whether the mask meets the requirements or not is checked by various detection means according to preset quality specifications, so that the mask with quality problems is prevented from entering a production link, and the basic quality of subsequent chip manufacturing is ensured.
The final Inspection (RETICLE FINAL Inspection) of the mask is performed in combination with a mask control system of a chip factory, wherein after the mask is manufactured, the final Inspection is performed to comprehensively inspect each quality index of the mask, ensure that the mask completely meets the design requirements and quality standards, and only the mask passing the final Inspection can be used for the subsequent chip manufacturing flow, thereby ensuring the quality and performance of chip manufacturing. Fig. 5 shows the resulting single layer mask structure, while fig. 6 shows the final one-by-one multi-layer mask used to fabricate the chip. The mask structure in fig. 6 is a conventional chip mask structure and thus will not be described in detail herein. However, the same is true of the chip, which was first designed by the design plant. The design process is to design the metal layer according to the instruction, then design the whole semiconductor device from the metal layer, and finally integrate the information of the metal layer and the information of the semiconductor device into the GDSII file of the frame of the working file. And the frame GDSII of the working file is used for the casing. The mask shop then creates the mask based on the information obtained from the document. Through the sequential department collaboration, file transfer and operation flow, the progress from the initial layout data of the chip to the complete chip manufacturing related links of the final mask manufacturing completion is realized.
While the application has been described in terms of preferred embodiments, it is not intended to limit the scope of the application. It is intended that all modifications within the scope of the application, i.e., all equivalents thereof, be embraced by the application as they come within their scope without departing from the application. In the description of the present specification, reference to the terms "one embodiment/manner," "some embodiments/manner," "example," "a particular example," "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment/manner or example is included in at least one embodiment/manner or example of the application. In this specification, the schematic representations of the above terms are not necessarily for the same embodiment/manner or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments/modes or examples. Furthermore, the various embodiments/modes or examples described in this specification and the features of the various embodiments/modes or examples can be combined and combined by persons skilled in the art without contradiction.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present application, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.
It will be appreciated by those skilled in the art that the above-described embodiments are merely for clarity of illustration of the disclosure, and are not intended to limit the scope of the disclosure. Other variations or modifications will be apparent to persons skilled in the art from the foregoing disclosure, and such variations or modifications are intended to be within the scope of the present disclosure.