CN119581335A

CN119581335A - Semiconductor package and method for manufacturing the same

Info

Publication number: CN119581335A
Application number: CN202311143046.4A
Authority: CN
Inventors: 董悦明; 杨家铭; 谢村隆; 潘冠霖; 颜伯晏
Original assignee: Orient Semiconductor Electronics Ltd
Current assignee: Orient Semiconductor Electronics Ltd
Priority date: 2023-09-05
Filing date: 2023-09-05
Publication date: 2025-03-07

Abstract

The semiconductor package of the invention comprises a first chip, a plurality of first conductive blocks, a molding layer and a rewiring layer, wherein the first chip is provided with a top surface and a bottom surface which are opposite, the first conductive blocks are arranged on the top surface of the first chip and are electrically connected with the first chip, the molding layer covers the top surface of the first chip and exposes the first conductive blocks, and the rewiring layer is arranged on the molding layer and is electrically connected with the first conductive blocks. The invention also provides a method for manufacturing the semiconductor package.

Description

Semiconductor package and method for manufacturing the same

Technical Field

The present invention relates to a semiconductor package and a method for fabricating the same, and more particularly, to a semiconductor package including a redistribution layer and a method for fabricating the same.

Background

The thickness of the conventional semiconductor package structure manufactured by flip chip technology generally cannot meet the requirement of thinning, and the manufacturing cost is high for the power component with fewer contacts.

Disclosure of Invention

In view of the above, the present invention provides a semiconductor package and a method for manufacturing the same, which uses a wire bonding process instead of a ball bonding process to reduce the cost, and uses a re-wire bonding process to reduce the thickness of the whole package.

The semiconductor package comprises a first chip, a plurality of first welding pads, a plurality of first conductive blocks, a forming layer and a rewiring layer, wherein the first chip is provided with a top surface and a bottom surface which are opposite, the first welding pads are arranged on the top surface of the first chip, the first conductive blocks are respectively arranged on the first welding pads and are electrically connected with the first chip, the forming layer covers the top surface of the first chip and exposes the first conductive blocks, and the rewiring layer is arranged on the forming layer and is electrically connected with the first conductive blocks.

The manufacturing method of the semiconductor package comprises the steps of arranging a first chip on a carrier, forming a plurality of first conductive blocks on the top surface of the first chip through a wire bonding process, forming a forming layer to cover the first conductive blocks and the first chip, grinding the forming layer to expose the first conductive blocks, forming a rewiring layer on the forming layer to be electrically connected with the first conductive blocks, and removing the carrier.

According to the semiconductor package of the present invention, the wire bonding process is used instead of the ball mounting process to reduce the cost, and the re-wire bonding process is used to reduce the thickness of the whole package to below 0.15 mm.

To make the above and other objects, features, and advantages of the present invention more apparent, embodiments of the present invention are described in detail below with reference to the accompanying drawings.

Drawings

The aspects of the disclosure are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that the various components are not drawn to scale in accordance with standard practices in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 is a schematic view of a semiconductor package of the present invention.

Fig. 2 to 10 illustrate a method of manufacturing the semiconductor package shown in fig. 1.

Symbol description:

110. First chip

111. A first surface

112. A second surface

113. Third surface

114. First bonding pad

120. Second chip

121. A first surface

122. A second surface

123. Third surface

124. Second bonding pad

131. First conductive block

132. Second conductive block

140. Rewiring layer

150. Solder ball

170. Shaping layer

171. A first surface

172. A second surface

180. Release material layer

190. Carrier plate

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, such components and arrangements are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first member over or on a second member may include embodiments in which the first member is formed in direct contact with the second member, and may also include embodiments in which additional members may be formed between the first member and the second member such that the first member and the second member may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

In addition, spatially relative terms such as "underlying," "lower," "overlying," "upper," and the like may be used herein for ease of description to describe one component or member's relationship to another component or member as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Referring to fig. 1, the semiconductor package of the present invention includes one or more chips, for example, a first chip 110 and a second chip 120, wherein the first chip 110 and the second chip 120 are disposed in parallel.

The first chip 110 has a first surface 111, a second surface 112 and a plurality of third surfaces 113 opposite to each other, wherein the first surface 111 is an active surface. The first surface 111 and the second surface 112 are located on different planes, and the third surfaces 113 connect the first surface 111 and the second surface 112. The first surface 111 has a plurality of first pads 114 formed thereon. In one embodiment, the first surface 111 is a top surface, the second surface 112 is a bottom surface, and the third surfaces 113 are side surfaces, but the invention is not limited thereto.

The second chip 120 has a first surface 121, a second surface 122 and a plurality of third surfaces 123 opposite to each other, wherein the first surface 121 is an active surface. The first surface 121 and the second surface 122 are located on different planes, and the third surfaces 123 connect the first surface 121 and the second surface 122. The first surface 121 has a plurality of second pads 124 formed thereon. In one embodiment, the first surface 121 is a top surface, the second surface 122 is a bottom surface, and the third surfaces 123 are side surfaces, but the invention is not limited thereto.

The first pads 114 of the first surface 111 of the first chip 110 are respectively provided with a plurality of first conductive blocks 131 electrically connected with the first chip 110 through the first pads 114, and the second pads 124 of the first surface 121 of the second chip 120 are respectively provided with a plurality of second conductive blocks 132 electrically connected with the second chip 120 through the second pads 124. The first conductive bumps 131 and the second conductive bumps 132 are made of conductive material, such as gold, copper, or alloy. In the present invention, the first conductive bumps 131 and the second conductive bumps 132 can be formed on the first pads 114 of the first chip 110 and the second pads 124 of the second chip 120 by bonding using gold wires, copper wires, alloy wires or other conductive wires through a wire bonding (wire bonding) process.

The semiconductor package of the present invention further includes a molding layer 170 made of an encapsulant material, such as an epoxy material, but is not limited thereto. The molding layer 170 has a first surface 171 and a second surface 172 opposite to each other, and the first surface 171 and the second surface 172 are located on different planes, for example, the first surface 171 is a top surface and the second surface 172 is a bottom surface. The molding layer 170 is formed on the first surface 111 of the first chip 110 and the first surface 121 of the second chip 120, and covers the third surfaces 113 of the first chip 110 and the third surfaces 123 of the second chip 120. The molding layer 170 is not formed on the second surface 112 of the first chip 110 and the second surface 122 of the second chip 120, and does not cover the first conductive bumps 131 and the second conductive bumps 132, and each of the first conductive bumps 131 and the second conductive bumps 132 is partially exposed from the molding layer 170. Thus, the first surface 171 of the molding layer 170 is located above the first surface 111 of the first chip 110 and the first surface 121 of the second chip 120, and the second surface 172 of the molding layer 170 is flush with the second surface 112 of the first chip 110 and the second surface 122 of the second chip 120.

The first surface 171 of the molding layer 170 has a redistribution layer (redistribution layer, RDL) 140 formed thereon, in which conductive traces are disposed. The redistribution layer 140 extends from above the first surface 111 of the first chip 110 to above the first surface 121 of the second chip 120, and contacts the first conductive bumps 131 and the second conductive bumps 132 to be electrically connected. The first chip 110 is electrically connected to the second chip 120 through the redistribution layer 140.

The redistribution layer 140 is provided with a plurality of solder balls 150, and the solder balls 150 are electrically connected to the redistribution layer 140. The first chip 110 and the second chip 120 can be electrically connected to external circuits through the redistribution layer 140 by using the solder balls 150.

Referring to fig. 2 to 10, a method for manufacturing the semiconductor package shown in fig. 1 is shown. As shown in fig. 2, a carrier plate 190 is prepared, which can be made of silicon wafer, glass, metal or other materials that can withstand high temperatures.

As shown in fig. 3, a release material layer 180 is then formed on the carrier plate 190 by coating or adhering, and the release material layer 180 has adhesion and can be released again.

As shown in fig. 4, one or more chips, such as a first chip 110 and a second chip 120, are then adhered to the carrier 190 by the release material layer 180, wherein the first chip 110 and the second chip 120 are disposed in parallel.

The first chip 110 has a first surface 111, a second surface 112 and a plurality of third surfaces 113 opposite to each other, wherein the first surface 111 is an active surface, and the second surface 112 is adhered to the carrier 190. The first surface 111 and the second surface 112 are located on different planes, and the third surfaces 113 connect the first surface 111 and the second surface 112. The first surface 111 has a plurality of first pads 114 formed thereon. In one embodiment, the first surface 111 is a top surface, the second surface 112 is a bottom surface, and the third surfaces 113 are side surfaces, but the invention is not limited thereto.

The second chip 120 has a first surface 121, a second surface 122 and a plurality of third surfaces 123 opposite to each other, wherein the first surface 121 is an active surface, and the second surface 122 is adhered to the carrier 190. The first surface 121 and the second surface 122 are located on different planes, and the third surfaces 123 connect the first surface 121 and the second surface 122. The first surface 121 has a plurality of second pads 124 formed thereon. In one embodiment, the first surface 121 is a top surface, the second surface 122 is a bottom surface, and the third surfaces 123 are side surfaces, but the invention is not limited thereto.

As shown in fig. 5, a plurality of first conductive bumps 131 are then disposed on the first pads 114 of the first surface 111 of the first chip 110, and a plurality of second conductive bumps 132 are disposed on the second pads 124 of the first surface 121 of the second chip 120. The first conductive blocks 131 are electrically connected to the first chip 110 through the first pads 114, and the second conductive blocks 132 are electrically connected to the second chip 120 through the second pads 124.

The first conductive bumps 131 and the second conductive bumps 132 are made of conductive material, such as gold, copper, or alloy. In the present invention, the first conductive bumps 131 and the second conductive bumps 132 can be formed on the first pads 114 of the first chip 110 and the second pads 124 of the second chip 120 by bonding using gold wires, copper wires, alloy wires or other conductive wires through a wire bonding (wire bonding) process.

As shown in fig. 6, a molding layer 170 is formed on the carrier 190 to cover the first conductive bumps 131 and the second conductive bumps 132 by using an encapsulating material, such as an epoxy material. The molding layer 170 has a first surface 171 and a second surface 172 opposite to each other, and the first surface 171 and the second surface 172 are located on different planes, for example, the first surface 171 is a top surface and the second surface 172 is a bottom surface. The molding layer 170 also covers the first surface 111 of the first chip 110 and the first surface 121 of the second chip 120, and covers the third surfaces 113 of the first chip 110 and the third surfaces 123 of the second chip 120. The molding layer 170 is not formed on the second surface 112 of the first chip 110 and the second surface 122 of the second chip 120 due to being masked by the carrier plate 190, and the second surface 172 of the molding layer 170 is flush with the second surface 112 of the first chip 110 and the second surface 122 of the second chip 120.

As shown in fig. 7, the first surface 171 of the molding layer 170 is polished to reduce the thickness of the molding layer 170, so that the top portions of the first conductive bumps 131 and the second conductive bumps 132 are exposed.

As shown in fig. 8, a redistribution layer 140 is formed on the first surface 171 of the molding layer 170 through a circuit redistribution process, and conductive traces are disposed in the redistribution layer 140, which extend from above the first surface 111 of the first chip 110 to above the first surface 121 of the second chip 120, and are in contact with the first conductive bumps 131 and the second conductive bumps 132 for electrical connection. The first chip 110 is electrically connected to the second chip 120 through the redistribution layer 140.

As shown in fig. 9, the first conductive blocks 131 and the second conductive blocks 132 are then rearranged to generate pin contacts for electrical connection with the outside through wires, and then the carrier 190 is removed.

As shown in fig. 10, the molding layer 170 is then divided, and a plurality of solder balls 150 electrically connected to the redistribution layer 140 are disposed on the molding layer to form a plurality of semiconductor packages as shown in fig. 1.

Although the present invention has been described in terms of the foregoing embodiments, it is not intended to limit the invention to the particular embodiments disclosed, but on the contrary, it is intended to cover various modifications and variations within the spirit and scope of the invention as defined by the appended claims. The scope of the invention is therefore defined in the appended claims.

Claims

1. A method for manufacturing a semiconductor package, comprising:

Disposing a first chip on the carrier, wherein the first chip has a top surface and a bottom surface opposite to each other;

forming a plurality of first conductive blocks on the top surface of the first chip by a wire bonding process, wherein the plurality of first conductive blocks are electrically connected to the first chip;

forming a molding layer to cover the plurality of first conductive blocks and the first chip;

Grinding the molding layer to expose the plurality of first conductive blocks;

forming a redistribution layer on the molding layer to be electrically connected to the plurality of first conductive blocks; and

Remove the carrier board.

2. The method for manufacturing a semiconductor package according to claim 1, further comprising:

Disposing a second chip on the carrier;

forming a plurality of second conductive blocks on the second chip by a wire bonding process, wherein the plurality of second conductive blocks are electrically connected to the second chip;

Covering the plurality of second conductive blocks and the second chip with the molding layer;

Exposing the plurality of second conductive blocks from the molding layer; and

The redistribution layer is electrically connected to the plurality of second conductive blocks.

3. The method for manufacturing a semiconductor package as claimed in claim 1 or 2, characterized in that the plurality of first conductive blocks are formed by one of gold wires, copper wires and alloy wires.

4. The method for manufacturing a semiconductor package as claimed in claim 1 or 2, characterized in that the molding layer has a bottom surface which is flush with the bottom surface of the first chip.

5. The method for manufacturing a semiconductor package according to claim 1 or 2, further comprising:

After the redistribution layer is formed, a plurality of solder balls electrically connected to the redistribution layer are arranged on the redistribution layer.

6. The method for manufacturing a semiconductor package as claimed in claim 2, wherein the first chip and the second chip are arranged in parallel.

7. A semiconductor package, comprising:

A first chip having a top surface and a bottom surface opposite to each other;

A plurality of first bonding pads, disposed on the top surface of the first chip;

A plurality of first conductive blocks are respectively disposed on the plurality of first bonding pads, and the plurality of first conductive blocks are electrically connected to the first chip;

a molding layer, covering the top surface of the first chip and exposing the plurality of first conductive blocks; and

The redistribution layer is disposed on the molding layer and is electrically connected to the plurality of first conductive blocks.

8. The semiconductor package according to claim 7, further comprising:

A second chip having a top surface and a bottom surface opposite to each other;

a plurality of second bonding pads, disposed on the top surface of the second chip;

A plurality of second conductive blocks are respectively disposed on the plurality of second bonding pads, and the plurality of second conductive blocks are electrically connected to the second chip, wherein

The molding layer covers the top surface of the second chip, and the plurality of second conductive blocks are exposed from the molding layer.

The redistribution layer is also electrically connected to the plurality of second conductive blocks.

9 . The semiconductor package of claim 7 , wherein the molding layer has a bottom surface that is flush with the bottom surface of the first chip.

10. The semiconductor package according to claim 7 or 8, further comprising:

A plurality of solder balls are formed on the redistribution layer.