CN119543932A - Phase-locked loop circuit, lock detection circuit and method - Google Patents
Phase-locked loop circuit, lock detection circuit and method Download PDFInfo
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Abstract
本发明提供一种锁相环电路、锁定检测电路和方法，检测锁相环电路中输入鉴频鉴相器的参考时钟信号和反馈时钟信号之间的相位差是否小于预定时间窗，检测锁相环电路中的控制电压是否在预定电压范围内，当相位差小于预定阈值且控制电压在预定电压范围之内时，在参考时钟信号上升沿来临时进行计数值加1操作，且在计数值大于设定值时输出第二标志位表示相位环锁定，当相位差不小于预定阈值和/或控制电压不在预定电压范围内时，计数值清零输出第一标志位表示相位环失锁。简洁明了易操作，可以和状态机联合工作，避免由于温度、电压变化导致的环路失锁问题。
The present invention provides a phase-locked loop circuit, a lock detection circuit and a method, which detect whether the phase difference between the reference clock signal input to the frequency detector and the feedback clock signal in the phase-locked loop circuit is less than a predetermined time window, and detect whether the control voltage in the phase-locked loop circuit is within a predetermined voltage range. When the phase difference is less than a predetermined threshold and the control voltage is within the predetermined voltage range, the count value is added by 1 when the rising edge of the reference clock signal comes, and when the count value is greater than a set value, a second flag is output to indicate that the phase loop is locked, and when the phase difference is not less than a predetermined threshold and/or the control voltage is not within the predetermined voltage range, the count value is cleared and the first flag is output to indicate that the phase loop is unlocked. The circuit is concise, clear and easy to operate, and can work in conjunction with a state machine to avoid the problem of loop unlocking caused by temperature and voltage changes.
Description
Technical Field
The present invention relates to the field of phase-locked loop locking detection technology, and in particular, to a phase-locked loop circuit, a locking detection circuit and a method.
Background
For the phase-locked loop, when the output frequency fout of the voltage-controlled oscillator works at a set target frequency, the frequencies of the feedback clock and the reference clock which are divided by the N-bit frequency divider are equal, the phases are aligned, so that the up current and the down current of the input charge pump are conducted together and are also turned off together, the loop filter is not charged or discharged, the control voltage of the output of the filter is kept unchanged, and at the moment, the phase-locked loop is locked. Thus, it is possible to determine whether the phase locked loop is locked by monitoring whether the control voltage is at a dc level. In practical applications, when the ambient temperature (T in fig. 1) or the power supply voltage (V in fig. 1) is changed, the inductance and capacitance in the vco will also change slightly, which will shift the control voltage-output frequency curve in fig. 1 up or down as a whole. Further, since the set target frequency is not changed, the locked control voltage Vctrl voltage is changed from V1 to V2 or V3. Such a control voltage Vctrl is very disadvantageous for the charge pump, in which the current tube has entered the linear region, the current is severely mismatched, and even the current mirror has not operated properly, resulting in loss of lock of the loop. The above situation will be more serious for application scenarios where the voltage controlled oscillator gain is small.
In the prior art, whether a loop is locked or not is judged by testing the voltage value of the control voltage Vctrl, and the Vctrl needs to be pulled from inside to outside of the chip for voltage testing, which occupies a precious input/output port. And after each time the target lock frequency point is switched, whether the loop is locked or not needs to be judged in a test mode. The conventional method does not monitor the voltage value of Vctrl in real time when in use, so Vctrl may be changed to an unfavorable voltage value due to temperature or power supply voltage, resulting in the loss of lock of the phase-locked loop.
Disclosure of Invention
Based on the above problems, the invention provides a phase-locked loop circuit, a lock detection circuit and a method, which only solve the technical problems of low reliability and the like in the prior art of detecting the locking of the phase-locked loop.
A lock detection circuit for a phase locked loop circuit, comprising:
The phase difference detection module is used for detecting whether the phase difference between a reference clock signal and a feedback clock signal input into the phase-locked loop circuit is smaller than a preset time window or not, so as to obtain a first detection result;
The voltage detection module is used for detecting whether the control voltage in the phase-locked loop circuit is in a preset voltage range or not to obtain a second detection result;
The judging module is respectively connected with the phase difference detection module and the voltage detection module and is used for generating an accumulated control signal when the first detection result is that the phase difference is smaller than a preset time window and the second detection result is that the control voltage is within a preset voltage range;
the counter module is connected with the judging module and is used for:
When receiving a zero clearing control signal, performing count value zero clearing operation and outputting a first flag bit;
And outputting a second flag bit when the count value is greater than the set value.
Further, the phase difference detection module includes:
The two input ends of the NOR gate respectively receive a first output signal and a second output signal of the phase frequency detector;
The D input end of the first trigger is connected with the output end of the NOR gate;
the input end of the first inverter is connected with the output end of the NOR gate;
The D input end of the second trigger is input with a high level, and the clock input end of the second trigger is connected with the output end of the first inverter;
The input end of the delay line is connected with the Q output end of the second trigger, the output end of the delay line is connected with the reset end of the second trigger, and the size of the preset time window is determined by the delay line;
The input end of the second inverter is connected with the Q output end of the second trigger;
the clock input end of the first trigger is connected with the output end of the second inverter;
The Q output end of the first trigger is used as the output end of the phase difference detection module and outputs a first detection result to the arbitration module.
Further, the voltage detection module includes:
the positive input end of the first comparator inputs a first reference voltage, and the negative input end of the first comparator inputs a control voltage;
the positive input end of the second comparator inputs the control voltage, and the negative input end of the second comparator inputs the second reference voltage;
The first input end of the first AND gate is connected with the output end of the first comparator, and the second input end of the first AND gate is connected with the output end of the second comparator;
the output end of the first AND gate is used as the output end of the voltage detection module, and outputs a second detection result to the arbitration module;
Wherein the first reference voltage is greater than the second reference voltage.
Further, the arbitration module is a second AND gate;
the first input end of the second AND gate is connected with the output end of the phase difference detection module, and the second input end of the second AND gate is connected with the output end of the voltage detection module;
the output end of the second AND gate is used as the output end of the arbitration module and is connected with the counter module.
Further, the delay line is a 2-bit programmable delay line.
A phase locked loop circuit comprising:
a lock detection circuit for a phase locked loop circuit as described above;
The phase frequency detector is used for generating a first output signal and a second output signal according to the reference clock signal and the feedback clock signal;
the input end of the charge pump is connected with the output end of the phase frequency detector and is used for generating control voltage according to the first output signal and the second output signal;
The input end of the loop filter is connected with the output end of the charge pump and is used for filtering the control voltage generated by the charge pump;
The input end of the voltage control oscillator is connected with the output end of the loop filter and is used for generating output frequency according to the filtered control voltage;
the input end of the frequency dividing module is connected with the output end of the voltage control oscillator, and the output end of the frequency dividing module is connected with the feedback input end of the phase frequency detector and is used for carrying out frequency dividing processing on the output frequency to generate a feedback clock signal to the phase frequency detector;
the input end of the phase difference detection module in the locking detection circuit is connected with the output end of the phase frequency detector;
The input end of the voltage detection module in the locking detection circuit is connected with the output end of the loop filter.
Further, the frequency dividing module includes:
The N-bit frequency divider is used for dividing the output frequency to obtain a feedback clock signal;
The input end of the Sigma-delta modulator is connected with the output end of the N-bit frequency divider, and the output end of the Sigma-delta modulator is connected with the N-bit frequency divider and is used for modulating signals during frequency division processing of the N-bit frequency divider.
A lock detection method for a phase locked loop circuit, using a lock detection circuit for a phase locked loop circuit as described above, comprising:
Step A1, detecting whether the phase difference between a reference clock signal and a feedback clock signal input into a phase frequency detector in a phase-locked loop circuit is smaller than a preset time window, and detecting whether a control voltage in the phase-locked loop circuit is within a preset voltage range:
When the phase difference is not smaller than the preset time window and/or the control voltage is not in the preset voltage range, executing the step A2;
When the phase difference is smaller than the preset time window and the control voltage is within the preset voltage range, executing the step A3;
a2, performing count value zero clearing operation and outputting a first flag bit;
step A3, performing a count value incrementing by 1 when the rising edge of the reference clock signal comes, and then performing step A4:
step A4, judging whether the count value is larger than a preset value:
if yes, executing the step A5;
if not, returning to the step A1;
and step A5, outputting a second flag bit.
The invention has the beneficial technical effects that by arranging the locking detection circuit, the phase difference of the reference clock signal and the feedback clock signal is detected for a long period, the control voltage Vctrl is detected in real time, and the final detection result is output in the form of the flag bit, so that the invention is simple and clear and easy to operate, can work in combination with a state machine, and can avoid the problem of loop unlocking caused by temperature and voltage changes.
Drawings
FIG. 1 is a graph of output frequency versus control voltage in a prior art VCO;
FIG. 2 is a block diagram of a lock detection circuit according to the present invention;
FIG. 3 is a circuit block diagram of the lock detection circuit of the present invention;
FIG. 4 is a circuit timing diagram of the lock detection circuit of the present invention;
FIG. 5 is a circuit block diagram of a phase locked loop circuit of the present invention;
Fig. 6 is a flow chart illustrating steps of a lock detection method for a pll circuit according to the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that, without conflict, the embodiments of the present invention and features of the embodiments may be combined with each other.
The invention is further described below with reference to the drawings and specific examples, which are not intended to be limiting.
Referring to fig. 2, the present invention provides a lock detection circuit for a phase locked loop circuit, comprising:
The phase difference detection module (11) is used for detecting whether the phase difference between a reference clock signal and a feedback clock signal input into the phase-locked loop circuit is smaller than a preset time window or not to obtain a first detection result;
The voltage detection module (12) is used for detecting whether the control voltage in the phase-locked loop circuit is in a preset voltage range or not to obtain a second detection result;
The judging module (13) is respectively connected with the phase difference detecting module (11) and the voltage detecting module (12) and is used for generating an accumulated control signal when the first detection result is that the phase difference is smaller than a preset time window and the second detection result is that the control voltage is within a preset voltage range;
a counter module (14) connected with the arbitration module (13) and used for:
When receiving a zero clearing control signal, performing count value zero clearing operation and outputting a first flag bit;
And outputting a second flag bit when the count value is greater than the set value.
And the phase-locked loop is subjected to locking detection in a mode of combining a time window with a counter, and whether the loop is locked or not is judged only by outputting a flag bit. The control voltage Vctrl is ensured to have a voltage value within a reasonable interval when the phase-locked loop is locked. If the control voltage Vctrl is not in the reasonable interval after locking, the first flag bit is locked and output to be 0, the state machine re-triggers the automatic frequency calibration flow of the voltage control oscillator, and a proper programmable capacitor is re-selected to ensure that the voltage value of the control voltage Vctrl is in a proper position, so that the reliability of the phase-locked loop in practical application is improved. The specific second flag bit is 1, which indicates that the phase-locked loop is locked.
By arranging the locking detection circuit, the phase difference of the reference clock signal and the feedback clock signal is detected for a long period, the control voltage Vctrl is detected in real time, and the final detection result is output in the form of a flag bit, so that the method is simple and clear and easy to operate, can work in combination with a state machine, and can avoid the problem of loop unlocking caused by temperature and voltage changes.
Referring to fig. 3, further, the phase difference detection module (11) includes:
A NOR gate (NOR) having two input terminals for receiving the first output signal and the second output signal of the phase frequency detector, respectively;
the input end of the first trigger (D1) is connected with the output end of the NOR gate;
The input end of the first inverter (INV 1) is connected with the output end of the NOR gate;
The clock input end of the second trigger (D2) is connected with the output end of the first inverter (INV 1);
The input end of the delay line (delay) is connected with the Q output end of the second trigger (D2), the output end of the delay line (delay) is connected with the reset end of the second trigger (D2), and the size of the preset time window is determined by the delay line (delay);
The input end of the second inverter (INV 2) is connected with the Q output end of the second trigger (D2);
the clock input end of the first trigger (D1) is connected with the output end of the second inverter (INV 2);
The Q output end of the first trigger (D1) is used as the output end of the phase difference detection module (11) and outputs a first detection result to the arbitration module (13).
The inverse of the phase difference between the reference clock signal fref and the feedback clock signal ffb is available at point a through a NOR gate (NOR). The pulse width includes a narrow pulse that is generated to overcome the "dead zone" problem of the phase frequency detector.
Specifically, the first output signal of the phase frequency detector is an up signal, and the second output signal is a down signal.
If the up signal and the down signal have the output level of one high and one low, the output result of the nor gate has the low level, namely the point a is 0, and the point C of the Q output end of the first flip-flop D1 outputs the low level, namely the logic level is 0, when the rising edge of the point b is detected, indicating that the phase difference occurs between the reference clock signal and the feedback clock signal.
If the Q output terminal C of the first flip-flop D1 outputs a high level, i.e., a logic level of 1, it indicates that the reference clock signal and the feedback clock signal have no phase difference.
Further, the voltage detection module (12) includes:
A first comparator (COM 1), wherein a positive input end of the first comparator (COM 1) inputs a first reference voltage Vref1, and a negative input end of the first comparator (COM 1) inputs a control voltage Vctrl;
a second comparator (COM 2), wherein the positive input end of the second comparator (COM 2) inputs the control voltage Vctrl, and the negative input end of the second comparator (COM 2) inputs the second reference voltage Vref2;
A first AND gate (AND 1), a first input end of the first AND gate (AND 1) is connected with an output end of the first comparator (COM 1), AND a second input end of the first AND gate (AND 1) is connected with an output end of the second comparator (COM 2);
the output end of the first AND gate (AND 1) is used as the output end of the voltage detection module (12) AND outputs a second detection result to the arbitration module (13);
Wherein the first reference voltage is greater than the second reference voltage.
If the control voltage is between the first reference voltage and the second reference voltage, the first AND gate outputs a high level indicating that the control voltage is within a predetermined voltage range formed by the first reference voltage and the second reference voltage.
Further, the arbitration module (13) is a second AND gate (AND 2);
the first input end of the second AND gate (AND 2) is connected with the output end of the phase difference detection module (11), AND the second input end of the second AND gate (AND 2) is connected with the output end of the voltage detection module (12);
The output of the second AND gate (AND 2) is connected to a counter block (14) as output of the arbitration block (13).
Further, the delay line (delay) is a 2-bit programmable delay line.
Specifically, the Delay line (Delay) is a 2bit programmable Delay line, that is, the predetermined time window of the present invention is also programmable, and is controlled by a 2bit binary number delay_ctrl <1:0>, and the predetermined time window may be 1ns, 2ns, 4ns, and 8ns, respectively.
Specifically, the Counter module of the present invention may be a programmable Counter (Counter), which is a 14-bit wide Counter with counter_bit <13:0 >. When the programmable counter_bit <13:0> is all 1 and the time window is 1ns, the minimum frequency difference that can be identified is 62.5Hz for a 32MHz reference clock signal and 9.375KHz for a voltage controlled oscillator operating at 4.8 GHz.
Referring to fig. 3 and 4, the detection principle of the lock detection circuit of the present invention is as follows:
The second flag bit is required to satisfy 3 conditions simultaneously if the lock flag bit is to be 1. The method comprises the steps of firstly, setting a phase difference between two input signals of a phase frequency detector to be smaller than a set time window, namely a preset time window, secondly, setting a control voltage Vctrl to fall in a proper interval, namely Vref2< Vctrl < Vref1, starting a 14-bit programmable counter when the former conditions are met, adding 1 to the counter every time the rising edge of a reference clock signal fref temporarily, and outputting a first flag bit when the locking flag bit is output to be 1 until the count value is larger than a written set value. If one of the first and second conditions is not satisfied during the process of accumulating the counter, the counter is cleared, and the counter stops counting until both the first and second conditions are satisfied.
By performing a nor operation on the two output signals up and down of the phase detector, a reverse signal of the phase difference between the input reference clock signal fref and the feedback clock signal ffb can be obtained at the point a in the figure, and the pulse width includes a narrow pulse generated to overcome the "dead zone" problem of the phase detector, and the signal at the point a is input as the D end of the first trigger D1. The inverted signal Ab of the inverted signal at the a point of the first inverter is used as the clock input (Clk input) of the second flip-flop D2, the input signal at the D input end of the second flip-flop D2 is always 1 (the logic level is always high), and the output signal at the Q output end is passed through a 2bit programmable delay line, which resets the second flip-flop, and the delay line determines the size of the predetermined time window. Therefore, if the phase difference pulse is smaller than the predetermined time window and the phase difference pulse is inverted by the second inverter, the phase difference inverted signal is changed to 1 after the phase difference pulse signal is already passed by the rising edge of the B-point clock, so that the C-point output is 1, that is, the phase difference pulse falls within the predetermined time window. Conversely, if the phase difference pulse is greater than the time window, then point C will output 0. It is noted that the path delays of the signals at the point a and the point B are different, the delay at the point B is far greater than that at the point a, the delay of the point B more than that at the point a is 2×tinv+tdff+trst, where Tinv represents the delay of the primary inverter, tdff is the path delay from the second flip-flop D2 to the Q output, and Trst is the path delay from the reset end reset to the Q output of the second flip-flop. And the delay of point B being greater than point a is close to the narrow pulse time to overcome the "dead zone". The predetermined time window generated by the delay line can be compared directly with the phase difference approximately in consideration of the above non-ideal factors. When the control voltage Vctrl meets Vref2< Vctrl < Vref1, the D point output is 1, otherwise, the D point output is 0. When C, D are both 1, point E is 1 and as input to the programmable counter, the counter module is triggered to count. If E is 0, the trigger counter is cleared. The Counter module is generated through digital synthesis, the input end comprises an input reference clock signal fref and a 14-bit counting control word counter_bit <13:0>, and the f point is the corresponding flag bit of the output.
Referring to fig. 4, the waveforms at the up, down, A, ab, B, bb, C, D, E, F nodes in fig. 4 are from top to bottom, respectively, where the waveforms are ideal waveforms, and no path delay is considered. The reference clock is 32MHz, the corresponding period T1 is 31.25ns, the reference clock signal fref and the feedback clock signal ffb are in the same frequency and phase, vref 1=0.9V, vref2=0.3V and Vctrl always fall between the two, and the D node is 1, after the set counter_bit <13:0> reference period, the F node is pulled high to output a second flag bit 1, so that the loop is locked. In the Tn period, the phase of the reference clock signal fref (ffb effect is similar to that of the reference clock signal fref) is suddenly advanced, the phase difference between fref and ffb is Terror, and the pulse width corresponding to Terror is larger than the pulse width corresponding to a preset time window, so that the sampling result of the point B to the point A is 0, the node C is 0, the node E is 0, the counter is cleared, the node F is 0, and the loss of lock of the loop is indicated. At any time, if Vctrl falls outside Vref1 and Vref2, point D becomes 0, point e becomes 0, and the counter is also cleared. When the Tn period is passed, the reference clock signal fref is restored to be in phase with ffb identical frequency, and the F node is pulled up and the loop is locked after the set counter_bit is less than 13:0. It is noted that during this process, it is necessary to ensure that fref and ffb always have a phase difference less than the predetermined time window, and Vctrl always falls within Vref1 and Vref 2.
In practical application, the flag bit output by the point F can be used to indicate the working state of the phase-locked loop. If the loop is out of lock, the system state machine may restart the automatic frequency calibration process according to the flag bit as the first flag bit, so that the loop is locked again.
Referring to fig. 5, the present invention further provides a phase locked loop circuit, including:
a lock detection circuit (1) for a phase locked loop circuit as described above;
a phase frequency detector (2) for generating a first output signal and a second output signal from a reference clock signal and a feedback clock signal;
The input end of the charge pump (3) is connected with the output end of the phase frequency detector (2) and is used for generating control voltage according to the first output signal and the second output signal;
the input end of the loop filter (4) is connected with the output end of the charge pump (3) and is used for filtering the control voltage generated by the charge pump;
the input end of the voltage control oscillator (5) is connected with the output end of the loop filter (4) and is used for generating output frequency according to the filtered control voltage;
The input end of the frequency dividing module (6) is connected with the output end of the voltage control oscillator (5), and the output end of the frequency dividing module is connected with the feedback input end of the phase frequency detector (2) and is used for carrying out frequency dividing processing on the output frequency to generate a feedback clock signal to the phase frequency detector (2);
The input end of a phase difference detection module (11) in the lock detection circuit (1) is connected with the output end of the phase frequency detector (2);
The input end of a voltage detection module (12) in the lock detection circuit (1) is connected with the output end of the loop filter (4).
Further, the frequency dividing module (6) includes:
An N-bit frequency divider (61) for dividing the output frequency to obtain a feedback clock signal;
And the input end of the Sigma-delta modulator is connected with the output end of the N-bit frequency divider, and the output end of the Sigma-delta modulator is connected with the N-bit frequency divider and is used for modulating signals when the N-bit frequency divider divides the frequency.
Referring to fig. 6, the present invention also provides a lock detection method for a phase locked loop circuit, using a lock detection circuit for a phase locked loop circuit as described above, comprising:
Step A1, detecting whether the phase difference between a reference clock signal and a feedback clock signal input into a phase frequency detector in a phase-locked loop circuit is smaller than a preset time window, and detecting whether a control voltage in the phase-locked loop circuit is within a preset voltage range:
When the phase difference is not smaller than the preset time window and/or the control voltage is not in the preset voltage range, executing the step A2;
When the phase difference is smaller than the preset time window and the control voltage is within the preset voltage range, executing the step A3;
a2, performing count value zero clearing operation and outputting a first flag bit;
step A3, performing a count value incrementing by 1 when the rising edge of the reference clock signal comes, and then performing step A4:
step A4, judging whether the count value is larger than a preset value:
if yes, executing the step A5;
if not, returning to the step A1;
and step A5, outputting a second flag bit.
The foregoing is merely illustrative of the preferred embodiments of the present invention and is not intended to limit the embodiments and scope of the present invention, and it should be appreciated by those skilled in the art that equivalent substitutions and obvious variations may be made using the description and illustrations of the present invention, and are intended to be included in the scope of the present invention.
Claims (8)
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| CN202411637465.8A CN119543932A (en) | 2024-11-15 | 2024-11-15 | Phase-locked loop circuit, lock detection circuit and method |
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| CN202411637465.8A CN119543932A (en) | 2024-11-15 | 2024-11-15 | Phase-locked loop circuit, lock detection circuit and method |
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