CN119542314A

CN119542314A - Semiconductor device, preparation method and electronic equipment

Info

Publication number: CN119542314A
Application number: CN202311097637.2A
Authority: CN
Inventors: 洪中山
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2023-08-28
Filing date: 2023-08-28
Publication date: 2025-02-28

Abstract

The embodiment of the present application discloses a semiconductor device, a preparation method and an electronic device, wherein the semiconductor device includes: a dielectric layer, a device structure layer, a first insulating layer, a first connection part, a second insulating layer and a second connection part, a transistor is formed in the device structure layer, and a signal is transmitted through the second connection part by electrically connecting the second connection part to the second electrode in the transistor. The first opening is filled by the first connection part and the first connection part is electrically connected to the first electrode, and power is supplied through the first connection part. In addition, the cross-sectional area of the first opening in the first cross section is made larger than the cross-sectional area of the second opening in the first cross section, and the cross-sectional area of the first opening in the first cross section represents the cross-sectional area of the first connection part at the first cross section, so that the resistance of the first connection part in the present application can be reduced compared with the resistance of the bottom connection part in the prior art, thereby reducing IR drop and power consumption.

Description

Semiconductor device, preparation method and electronic equipment

Technical Field

The present application relates to the field of semiconductor technologies, and in particular, to a semiconductor device, a manufacturing method, and an electronic apparatus.

Background

In a semiconductor device, a bottom contact hole is generally disposed at the bottom of the semiconductor device, a bottom connection portion is filled in the bottom contact hole, and a metal wire in a back side power distribution network (Backside power delivery network, BSPDN) is electrically connected with a source or a drain in a transistor through the bottom connection portion, so that a power signal is transmitted to the source or the drain of the transistor by BSPDN to supply power to the transistor. However, as the size of the semiconductor device is reduced, the size of the transistor and the metal line is reduced, which may cause an increase in resistance of the bottom connection portion, which may cause an increase in voltage drop (IR drop), which may in turn cause an increase in power consumption of the semiconductor device.

Disclosure of Invention

The embodiment of the application provides a semiconductor device, a preparation method and electronic equipment, which are used for reducing the resistance of a bottom connecting part and reducing the power consumption of an IR drop and the semiconductor device.

In a first aspect, an embodiment of the present application provides a semiconductor device, including a dielectric layer, a device structure layer, a first insulating layer, a first connection portion, a second insulating layer, and a second connection portion, where the dielectric layer is disposed on the device structure layer, so that the dielectric layer and the device structure layer are stacked, a first opening and a second opening penetrating through the dielectric layer are disposed in the dielectric layer, and bottoms of the first opening and the second opening both open into the device structure layer. The first insulating layer covers the dielectric layer and covers and fills the second opening, and the first insulating layer is arranged around the first opening, i.e. the first insulating layer does not fill the first opening but exposes the first opening. And at least one transistor is formed in the device structure layer, the transistor comprises a channel region, a first electrode and a second electrode, the first electrode and the second electrode are distributed at two ends of the channel region, and the first electrode is exposed in the first opening.

In order to realize signal transmission to the transistor, a first contact hole penetrating through the second insulating layer is arranged in the second insulating layer, the bottom of the first contact hole is led to the device structure layer, and the second electrode is exposed in the first contact hole. The second connecting part is filled in the first contact hole, and is contacted with the second electrode through the first contact hole, so that the electrical connection between the second connecting part and the second electrode is realized, and signals are transmitted to the second electrode through the second connecting part.

And in order to realize power supply to the transistor, the first connecting part is filled in the first opening, namely, the first connecting part is arranged on the back surface of the transistor, and the first connecting part is contacted with the first electrode through the first opening so as to realize electric connection between the first connecting part and the first electrode, so that a power signal is transmitted to the first electrode of the transistor through the first connecting part to supply power to the transistor.

In addition, the first cross section is located between the upper surface and the lower surface of the dielectric layer, the cross section area of the first opening in the first cross section is larger than that of the second opening in the first cross section, and the cross section area of the first opening in the first cross section is the same or gradually increases in the direction from the device structure layer to the dielectric layer. Wherein the cross-section of the first opening in the first cross-section has a cross-sectional area, i.e. represents the cross-sectional area of the first connecting portion at the first cross-section, such that the cross-sectional area of the first connecting portion at the first cross-section is larger than the cross-sectional area of the second opening at the first cross-section. However, the cross-sectional area of the bottom connecting portion in the prior art is substantially the same as the cross-sectional area of the second opening in the first cross-section. Based on this, according to the resistance formula r=ρl/S (R represents a resistance value, ρ represents a resistivity of a material forming the resistor, L represents a length of a wire forming the resistor, and S represents a cross-sectional area forming the resistor), since the cross-sectional area of the first connection portion in the present application at the first cross-section is larger than that of the bottom connection portion in the related art, the resistance of the first connection portion in the present application is reduced compared to that of the bottom connection portion in the related art, thereby enabling reduction of IR drop and power consumption of the semiconductor device.

In some examples, the cross-section of the first opening in the first cross-section is made to have a first length along the first direction and the cross-section of the second opening in the first cross-section is made to have a second length along the first direction, the first area being greater than the second area by making the first length greater than the second length. And the first direction is parallel to the first cross section.

In still other examples, having a cross-section of the first opening in the first cross-section with a sidewall of the first opening in the first direction having a first included angle, and having a cross-section of the second opening in the first cross-section with a sidewall of the second opening in the first direction having a second included angle, may be such that the first included angle is less than the second included angle. By this arrangement, the length of the first opening can be enlarged in the first direction by tilting the side wall of the second opening in the first direction. Of course, the first included angle may be substantially equal to the second included angle, so that the side wall of the second opening in the first direction may be translated in the first direction, thereby expanding the length of the first opening in the first direction.

Further, the cross section of the first opening in the first cross section is made to have a third length in the second direction, and the cross section of the second opening in the first cross section is made to have a fourth length in the second direction by making the third length substantially equal to the fourth length. This arrangement is equivalent to enlarging the length of the first opening in the first direction, but not enlarging the length of the first opening in the second direction, so that a short circuit between the first electrode and the channel can be avoided.

In order to reduce the contact resistance, at least one interface layer is further provided in the semiconductor device, and the at least one interface layer is provided between the first connection portion and the first electrode, so that the contact resistance between the first connection portion and the first electrode is reduced by the interface layer.

The interfacial layer comprises a low resistivity material. Illustratively, the material of the interfacial layer is a semiconductor material. For example, the interfacial layer comprises silicon and also has a highly active dopant therein (wherein the dopant comprises one or both of phosphorus and arsenic). Or the interfacial layer comprises silicon and carbon and also has a highly active dopant therein (wherein the dopant comprises one or both of phosphorus and arsenic). Illustratively, the concentration of the highly active dopant is 4E20cm ^-3 or greater.

In order to further reduce the contact resistance, at least one interface layer is further arranged between the first connection portion and the side wall of the first opening. That is, at least one interface layer is also provided between the first connection portion and the dielectric layer, and at least one interface layer is also provided between the first connection portion and the first insulating layer.

Further, in order to transmit signals to the first electrode, a second contact hole penetrating through the second insulating layer is further formed in the second insulating layer, the bottom of the second contact hole is led to the device structure layer, and the first electrode is exposed in the second contact hole. And a third connecting part is further arranged in the semiconductor device, the third connecting part is filled in the second contact hole, and the third connecting part is in contact with the first electrode through the second contact hole, so that the electric connection between the third connecting part and the first electrode is realized, and signals are transmitted to the first electrode through the third connecting part.

In a transistor, a channel region includes a first connection region, a second connection region, and an active region disposed between the first connection region and the second connection region, a first electrode is in contact with the first connection region, and a second electrode is in contact with the second connection region. The transistor also comprises a grid electrode, wherein the grid electrode covers the active area through a grid insulating layer, so that the active area is controlled through the grid electrode, and the on and off between the first electrode and the second electrode are realized. And the second insulating layers are arranged on two sides of the grid electrode.

Illustratively, the channel includes a plurality of channel layers disposed sequentially in the stacking direction, and the plurality of channel layers are disposed at intervals from one another. The transistor in the present application is formed to surround the gate field effect transistor (Gate All Around Field-Effect Transistor, GAAFET) by surrounding the gate electrode with a gate insulating layer interposed therebetween to the active region of each channel layer. And, the channel layer may be provided as a nano-sheet channel layer or a nano-wire channel layer.

In addition, the transistor also comprises an inner side wall (INNER SPACER), a grid side wall and a grid barrier layer. Two inner side walls are respectively arranged between two adjacent channel layers, and the grid side walls are arranged on two sides of the grid, namely, the grid side walls are respectively arranged on two sides of each grid. In addition, the surface of the side, facing away from the dielectric layer, of the gate barrier layer may be substantially flush with the surface of the side, facing away from the dielectric layer, of the gate sidewall.

To further improve the performance of the transistor, a bottom electrical isolation layer (Bottom dielectric isolation, BDI) is also included in the transistor, the BDI being disposed between the channel region and the dielectric layer with a gate between the BDI and the channel region.

In addition, an interconnection layer and a carrier wafer (CARRIER WAFER) are further arranged on one side, away from the dielectric layer, of the transistor, a first metal interconnection line and a second metal interconnection line are arranged in the interconnection layer, the first metal interconnection line is connected with the second connection portion and the carrier wafer respectively, and the second metal interconnection line is connected with the third connection portion and the carrier wafer respectively. Due to the arrangement, it is possible to transmit signals on the transmission paths formed by the second electrode, the second connection portion, the first metal interconnection line, and the carrier wafer, and to transmit signals on the transmission paths formed by the first electrode, the third connection portion, the second metal interconnection line, and the carrier wafer.

In a second aspect, an embodiment of the present application further provides an electronic apparatus, where the electronic apparatus includes a circuit board and a semiconductor device, and the semiconductor device is connected to the circuit board. Wherein the semiconductor device is a semiconductor device as employing the first aspect or various embodiments of the first aspect. And the principle of the electronic device for solving the problem is similar to that of the semiconductor device, so the implementation of the electronic device can refer to the implementation of the semiconductor device, and the repetition is omitted.

In a third aspect, an embodiment of the present application further provides a method for manufacturing a semiconductor device, including:

Forming a device structure layer and a second insulating layer on the semiconductor substrate; the semiconductor device comprises a device structure layer, a dielectric layer, a first insulating layer, a second insulating layer, a first electrode, a second electrode, a substrate fin part, a second electrode, a first insulating layer, a second insulating layer, a first contact hole and a second contact hole, wherein the dielectric layer is arranged on the device structure layer, a first opening and a second opening penetrating through the dielectric layer are arranged in the dielectric layer, the bottoms of the first opening and the second opening are both communicated with the device structure layer;

depositing a second connecting part, filling the second connecting part in the first contact hole, and enabling the second connecting part to be in contact with the second electrode through the first contact hole;

Etching to remove the fin part of the substrate, after exposing the part of the area facing the side of the dielectric layer, depositing a first insulating layer on the side of the dielectric layer facing away from the device structure layer, so that the first insulating layer covers and fills the second opening and bypasses the first opening, and the first insulating layer covers the surface of the dielectric layer facing away from the side of the device structure layer;

Etching the side wall of the first opening to make the cross section area of the first opening in the first cross section be larger than that of the second opening in the first cross section, wherein the first cross section is positioned between the upper surface and the lower surface of the dielectric layer;

the first opening is filled with the first connection portion, and the first connection portion is brought into contact with the first electrode through the first opening.

An embodiment for etching the sidewall of the first opening includes etching the sidewall of the first opening in a first direction, the first direction being parallel to the first cross-section, using an angled etch process.

Illustratively, the angled etch process includes an angled reactive ion etch process.

The preparation method further comprises the step of forming an interconnection layer on the side, with the transistor, of the semiconductor substrate after the second connection portion is deposited. After bonding the side of the semiconductor substrate having the transistor with the carrier wafer, the semiconductor substrate is removed.

Drawings

Fig. 1 is a schematic structural diagram of an electronic device according to an embodiment of the present application;

fig. 2a is a schematic top view of a semiconductor device according to an embodiment of the present application;

FIG. 2b is a schematic cross-sectional view taken along the direction AA' of FIG. 2 a;

FIG. 2c is a schematic cross-sectional view of the structure of FIG. 2a along the direction BB';

FIG. 2d is a schematic cross-sectional view of the structure of FIG. 2a along the direction CC';

FIG. 2e is a schematic cross-sectional view of FIG. 2a along DD';

FIG. 3a is a schematic view of a further cross-sectional structure along the BB' direction in FIG. 2 a;

FIG. 3b is a schematic view of a further cross-sectional structure taken along the direction CC' in FIG. 2 a;

Fig. 4a is a schematic top view of a semiconductor device according to an embodiment of the present application during a fabrication process;

FIG. 4b is a schematic cross-sectional view taken along the direction AA' of FIG. 4 a;

fig. 5a is a schematic top view of a semiconductor device according to an embodiment of the present application in a manufacturing process;

FIG. 5b is a schematic cross-sectional view taken along the direction AA' of FIG. 5 a;

FIG. 5c is a schematic cross-sectional view along BB' in FIG. 5 a;

FIG. 5d is a schematic cross-sectional view taken along the direction CC' in FIG. 5 a;

Fig. 6a is a schematic top view of a semiconductor device according to an embodiment of the present application in a manufacturing process;

FIG. 6b is a schematic cross-sectional view taken along the direction AA' of FIG. 6 a;

FIG. 6c is a schematic cross-sectional view along BB' in FIG. 6 a;

FIG. 6d is a schematic cross-sectional view taken along the direction CC' in FIG. 6 a;

fig. 7a is a schematic top view of a semiconductor device according to an embodiment of the present application in a manufacturing process;

FIG. 7b is a schematic cross-sectional view taken along the direction AA' of FIG. 7 a;

FIG. 7c is a schematic cross-sectional view taken along BB' in FIG. 7 a;

FIG. 7d is a schematic cross-sectional view taken along the direction CC' in FIG. 7 a;

fig. 8a is a schematic top view of a semiconductor device according to an embodiment of the present application in a manufacturing process;

FIG. 8b is a schematic cross-sectional view taken along the direction AA' of FIG. 8 a;

FIG. 8c is a schematic cross-sectional view along BB' in FIG. 8 a;

FIG. 8d is a schematic cross-sectional view of FIG. 8a taken in the direction CC';

FIG. 8e is a schematic cross-sectional view taken along DD' in FIG. 8 a;

Fig. 9a is a schematic top view of a semiconductor device according to an embodiment of the present application in a manufacturing process;

FIG. 9b is a schematic cross-sectional view taken along the direction AA' of FIG. 9 a;

FIG. 9c is a schematic cross-sectional view taken along the BB' direction in FIG. 9 a;

FIG. 9d is a schematic cross-sectional view taken along the direction CC' in FIG. 9 a;

FIG. 9e is a schematic cross-sectional view taken along DD' in FIG. 9 a;

Fig. 10a is a schematic top view of a semiconductor device according to an embodiment of the present application in a manufacturing process;

FIG. 10b is a schematic cross-sectional view taken along the direction AA' of FIG. 10 a;

FIG. 10c is a schematic cross-sectional view along BB' in FIG. 10 a;

FIG. 10d is a schematic cross-sectional view taken along the direction CC' in FIG. 10 a;

FIG. 10e is a schematic cross-sectional view taken along DD' in FIG. 10 a;

fig. 11a is a schematic top view of a semiconductor device according to an embodiment of the present application in a manufacturing process;

FIG. 11b is a schematic cross-sectional view taken along the direction AA' of FIG. 11 a;

FIG. 11c is a schematic cross-sectional view along BB' in FIG. 11 a;

FIG. 11d is a schematic cross-sectional view taken along the direction CC' in FIG. 11 a;

FIG. 11e is a schematic cross-sectional view taken along DD' in FIG. 11 a;

fig. 12a is a schematic top view of a semiconductor device according to an embodiment of the present application in a manufacturing process;

FIG. 12b is a schematic cross-sectional view taken along the direction AA' of FIG. 12 a;

FIG. 12c is a schematic cross-sectional view along BB' in FIG. 12 a;

FIG. 12d is a schematic cross-sectional view taken along the direction CC' in FIG. 12 a;

FIG. 12e is a schematic cross-sectional view taken along DD' in FIG. 12 a;

fig. 13a is a schematic top view of a semiconductor device according to an embodiment of the present application in a manufacturing process;

FIG. 13b is a schematic cross-sectional view taken along the direction AA' of FIG. 13 a;

FIG. 13c is a schematic cross-sectional view taken along BB' in FIG. 13 a;

FIG. 13d is a schematic cross-sectional view taken along the direction CC' in FIG. 13 a;

FIG. 13e is a schematic cross-sectional view taken along DD' in FIG. 13 a;

Fig. 14a is a schematic top view of a semiconductor device according to an embodiment of the present application in a manufacturing process;

FIG. 14b is a schematic cross-sectional view taken along the direction AA' of FIG. 14 a;

FIG. 14c is a schematic cross-sectional view taken along the BB' direction in FIG. 14 a;

FIG. 14d is a schematic cross-sectional view taken along the direction CC' in FIG. 14 a;

Fig. 14e is a schematic cross-sectional view along DD' in fig. 14 a.

Reference numerals:

100-a housing; 200-a circuit board; 300-semiconductor device, 410-dielectric layer, 500-device structure layer, 510-channel region, 521-first electrode, 522-second electrode, 531-gate, 532-gate insulation layer, 533-inner sidewall, 535-gate sidewall, 534-gate barrier layer, 550-bottom electric isolation layer, 610-first insulation layer, 540-second insulation layer, 710-first connection portion, 720-second connection portion, 730-third connection portion, 810-interconnection layer, 820-carrier wafer, 711-interface layer, F1-first direction, F2-second direction, F3-stacking direction, B1-first connection region, B2-second connection region, B3-active region, SD 1-first surface, SD 2-second surface, KK 1-first opening, KK 2-second opening, KK 3-third opening, SC-first length, h 11-first length, h 12-second length, h 21-third length, h 22-fourth length, beta 1-beta 22-first length, beta 1-second surface, SC-second surface, S11-first length, h 11-first length, beta 11-first cross section beta, beta 11-first end angle between two layers, 11-first semiconductor fin structures, 21-third length, beta 22-fourth length beta 22-first surface, beta 1-beta 2-second surface, S11-first surface, 25, beta 11-first cross section beta 11-first end angle between the semiconductor layers, 23-1-first base layer, 23-1-23/20 c, 23/20 c, 23-base layer, 23-1-base layer, 23-base layer, and 23/20/to be etched.

Detailed Description

In the description of the present application, "at least one" means one or more, wherein a plurality means two or more. In view of this, the term "plurality" may also be understood as "at least two" in embodiments of the present application. "and/or" describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate that there are three cases of a alone, a and B together, and B alone. The character "/", unless otherwise specified, generally indicates that the associated object is an "or" relationship. In addition, it should be understood that in the description of the present application, the words "first," "second," and the like are used merely for distinguishing between the descriptions and not for indicating or implying any relative importance or order. Moreover, the example embodiments are capable of implementation in many forms and should not be construed as limited to the embodiments set forth herein, but rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concept of the example embodiments to those skilled in the art. In addition, the same reference numerals in the drawings denote the same or similar structures, and thus a repetitive description thereof will be omitted. The words expressing the positions and directions described in the present application are described by taking the drawings as an example, but can be changed according to the needs, and all the changes are included in the protection scope of the present application. The drawings of the present application are merely schematic representations of relative positional relationships and are not intended to represent true proportions.

In order to facilitate understanding of the semiconductor device, the manufacturing method and the electronic device provided by the embodiment of the application, an application scenario thereof is first introduced below. The semiconductor device provided by the embodiment of the application can be widely applied to various electronic equipment, including various terminal equipment and electronic devices. For example, terminal devices include, but are not limited to, smart phones, smart televisions, smart television set-top boxes, smart watches, personal computers (personal computer, PCs), wearable devices, smart broadband, and the like. Electronic devices include, but are not limited to, devices such as wireless networks, fixed networks, communication devices such as servers, and device modules, memory, and the like, and are not listed here.

Fig. 1 is a schematic structural diagram of an electronic device according to an embodiment of the present application. Referring to fig. 1, the electronic apparatus includes a housing 100, a circuit board 200 disposed within the housing 100, and a semiconductor device 300 fixed on the circuit board 200. The semiconductor device 300 and the circuit board 200 may be electrically connected by bonding, or the like, so that signal transmission between the semiconductor device 300 and the circuit board 200 is enabled.

Fig. 2a is a schematic top view of a semiconductor device according to an embodiment of the present application, fig. 2b is a schematic cross-sectional view along AA 'in fig. 2a, fig. 2c is a schematic cross-sectional view along BB' in fig. 2a, fig. 2d is a schematic cross-sectional view along CC 'in fig. 2a, and fig. 2e is a schematic cross-sectional view along DD' in fig. 2a. Referring to fig. 2a through 2e, the semiconductor device includes a dielectric layer 410, a device structure layer 500, a first insulating layer 610, and a second insulating layer 540. The dielectric layer 410 and the device structure layer 500 are stacked, the dielectric layer 410 has a first surface SD1 (i.e., an upper surface) and a second surface SD2 (i.e., a lower surface) along a stacking direction F3 of the dielectric layer 410 and the device structure layer 500, the device structure layer 500 is disposed on the first surface SD1 of the dielectric layer 410, the second insulating layer 540 is disposed on a side of the device structure layer 500 facing away from the dielectric layer 410, and the first insulating layer 610 is disposed on the second surface SD2 of the dielectric layer 410. And, the dielectric layer 410 includes a first opening KK1, a second opening KK2, and a third opening KK3 penetrating from the first surface SD1 thereof to the second surface SD2 thereof, that is, the first opening KK1, the second opening KK2, and the third opening KK3 penetrate the dielectric layer 410 in the stacking direction F3, respectively, and bottoms of the first opening KK1, the second opening KK2, and the third opening KK3 all open to the device structure layer 500. The first insulating layer 610 fills the second and third openings KK2 and KK3 and covers the second surface SD2 of the dielectric layer 410, and the first insulating layer 610 bypasses the first opening KK1. A first cross section SC is provided, which is perpendicular to the stacking direction F3, such that the orthographic projection of the first insulating layer 610 on the first cross section SC does not overlap with the orthographic projection of the first slit KK1 on the first cross section SC, so that the first insulating layer 610 does not fill the first slit KK1 but exposes the first slit KK1. Also, the cross-sectional area of the first slit KK1 in the first cross-section gradually increases in the direction from the device structure layer 500 toward the dielectric layer 410 (i.e., the direction indicated by the arrow F3 in fig. 2 d). Also, the cross-sectional area of the second slit KK2 in the first cross-section gradually increases in the direction from the device structure layer 500 toward the dielectric layer 410 (i.e., the direction indicated by the arrow F3 in fig. 2 d). In addition, the cross-sectional area of the third opening KK3 in the first cross-section also gradually increases in the direction from the device structure layer 500 toward the dielectric layer 410 (i.e., the direction indicated by the arrow F3 in fig. 2 d). Of course, the cross-sectional area of the first opening KK1 in the first cross-section may also be the same in the direction from the device structure layer 500 to the dielectric layer 410 (i.e. the direction indicated by the arrow F3 in fig. 2 d). Also, the cross-sectional area of the second slit KK2 in the first cross-section may be the same in the direction from the device structure layer 500 toward the dielectric layer 410 (i.e., the direction indicated by the arrow F3 in fig. 2 d). In addition, the cross-sectional area of the third opening KK3 in the first cross-section may also be the same in the direction from the device structure layer 500 to the dielectric layer 410 (i.e., the direction indicated by the arrow F3 in fig. 2 d). Wherein the same refers to the same in error allowance.

With continued reference to fig. 2 a-2 e, one or more transistors are formed in the device structure layer 500, the transistor including a channel region 510, a first electrode 521, a second electrode 522, one or more gates 531, and a gate insulating layer 532, wherein the first electrode 521, the channel region 510, and the second electrode 522 are aligned along a second direction F2, the gates 531 extend along the first direction F1 and are disposed across the channel region 510, the first electrode 521 is disposed on a side of a first end of the channel region 510 facing away from the second end of the channel region 510 and is in contact with the first end of the channel region 510 so that the first electrode 521 is electrically connected with the channel region 510, and the second electrode 522 is disposed on a side of a second end of the channel region 510 facing away from the first end of the channel region 510 and is in contact with the second end of the channel region 510 so that the second electrode 522 is electrically connected with the channel region 510. And, the front projection of the first electrode 521 on the first cross section SC and the front projection of the first slit KK1 on the first cross section SC have overlapping areas so that the first electrode 521 is exposed in the first slit KK 1. The front projection of the second electrode 522 on the first cross-section SC and the front projection of the second slit KK2 on the first cross-section SC have overlapping areas such that the second electrode 522 is exposed in the second slit KK 2. The orthographic projection of the channel region 510 on the first cross-section SC and the orthographic projection of the third slit KK3 on the first cross-section SC have overlapping areas, and the orthographic projection of the first slit KK1 on the first cross-section SC and the orthographic projection of the second slit KK2 on the first cross-section SC do not overlap with the orthographic projection of the channel region 510 on the first cross-section SC, respectively. In addition, the first opening KK1, the second opening KK2 and the third opening KK3 are respectively communicated with each other in the second direction F2, that is, the sidewalls of the first opening KK1, the second opening KK2 and the third opening KK3 in the first direction F1 are each constituted by the dielectric layer 410. Also, since the first insulating layer 610 fills the second and third openings KK2 and KK3, not only is the first insulating layer 610 brought into contact with the surface of the second electrode 522 toward the dielectric layer 410 side through the second opening KK2, but also the first insulating layer 610 is brought into contact with the surface of the channel region 510 toward the dielectric layer 410 side through the third opening KK3, and the sidewall of the first opening KK1 in the second direction F2 is made of the first insulating layer 610. In practice, a device structure layer may be formed on a semiconductor substrate, after which the semiconductor substrate is removed completely or a portion of the semiconductor substrate is removed during the fabrication process. Alternatively, the device structure layer may be formed in the semiconductor substrate such that the semiconductor substrate is part of the device structure layer.

With continued reference to fig. 2a to 2e, the channel region 510 includes a first connection region B1, a second connection region B2, and an active region B3 disposed between the first connection region B1 and the second connection region B2, the first electrode 521 is in contact with the first connection region B1, the second electrode 522 is in contact with the second connection region B2, and the gate 531 covers the active region B3 via the gate insulating layer 532. Further, the channel region 510 includes a plurality of channel layers 511 sequentially arranged in the stacking direction F3, and the plurality of channel layers 511 are arranged to be spaced apart from each other, and the gate electrode 531 surrounds the active region B3 of each channel layer 511 via the gate insulating layer 532, so that the transistor in the present application is formed to GAAFET. Also, the channel layer 511 may be provided as a nano-sheet channel layer or a nano-wire channel layer. It will be appreciated that the first electrode 521 may be provided as the source of a transistor and the second electrode 522 as the drain of a transistor. Alternatively, the first electrode 521 may be provided as a drain of a transistor, and the second electrode 522 may be provided as a source of a transistor.

In addition, the transistor further comprises an inner side wall (INNER SPACER) 533, a grid side wall 535 and a grid barrier layer 534. Two inner sidewalls 533 are disposed between two adjacent channel layers 511, where an orthographic projection of one inner sidewall 533 on the first cross section SC of the two inner sidewalls 533 and an orthographic projection of the first connection region B1 on the first cross section SC have overlapping regions (or overlap), and an orthographic projection of the other inner sidewall 533 on the first cross section SC and an orthographic projection of the second connection region B2 on the first cross section SC have overlapping regions (or overlap). The gate side walls 535 are disposed at two sides of the gate 531, that is, two sides of each gate 531 are respectively provided with a gate side wall 535, and the orthographic projection of the gate side wall 535 on one side of the gate 531 on the first cross section SC has an overlapping area (or coincides) with the orthographic projection of the first connection region B1 on the first cross section SC, and the orthographic projection of the gate side wall 535 on the other side on the first cross section SC has an overlapping area (or coincides) with the orthographic projection of the second connection region B2 on the first cross section SC. And, a gate barrier 534 overlies the gate 531, and an orthographic projection of the gate barrier 534 on the first cross section SC has an overlapping (or coincident) area with an orthographic projection of the gate 531 on the first cross section SC. In addition, the surface of the gate barrier layer 534 on the side facing away from the dielectric layer 410 may be substantially flush with the surface of the gate sidewall 535 on the side facing away from the dielectric layer 410.

To further enhance the performance of the transistor, referring to fig. 2b and 2c, the transistor further comprises a bottom electrically isolating layer (Bottom dielectric isolation, BDI) 550, the BDI550 being arranged between the channel region 510 and the dielectric layer 410, and the front projection of the BDI550 on the first cross-section SC having an overlap (or overlap) with the front projection of the channel region 510 on the first cross-section SC, and the gate 531 being arranged between the BDI550 and the channel region 510. In addition, when the BDI550 is provided, the first insulating layer 610 contacts the surface of the BDI550 facing the side of the dielectric layer 410 through the third slit KK 3.

With continued reference to fig. 2a to 2e, the second insulating layer 540 is disposed between adjacent gates 531, and a gate sidewall 535 is further disposed between the second insulating layer 540 and the gate 531. In order to realize signal transmission to the second electrode 522, a first contact hole penetrating the second insulating layer 540 along the stacking direction F3 is further provided in the second insulating layer 540, and the orthographic projection of the first contact hole on the first cross section SC and the orthographic projection of at least part of the surface of the second electrode 522 facing away from the dielectric layer 410 on the first cross section SC have overlapping areas, so that at least part of the surface of the second electrode 522 facing away from the dielectric layer 410 is exposed through the first contact hole. Based on this, a second connection portion 720 is further disposed in the semiconductor device, and the second connection portion 720 fills the first contact hole, so that the second connection portion 720 contacts the surface of the second electrode 522 on the side facing away from the dielectric layer 410 through the first contact hole, so as to achieve electrical connection between the second connection portion 720 and the second electrode 522. Thus, a signal may be transmitted to the second electrode 522 through the second connection portion 720.

In order to achieve signal transmission to the first electrode 521, with continued reference to fig. 2c and 2d, a second contact hole penetrating the second insulating layer 540 in the stacking direction F3 is further provided in the second insulating layer 540, and an orthographic projection of the second contact hole on the first cross section SC and an orthographic projection of at least a partial area of a surface of the first electrode 521 facing away from the dielectric layer 410 side on the first cross section SC have an overlapping area, so that the first electrode 521 is exposed in the second contact hole. Based on this, a third connection portion 730 is further provided in the semiconductor device, and the third connection portion 730 is filled in the second contact hole so that the third connection portion 730 is in contact with the first electrode 521 through the second contact hole, thereby achieving electrical connection between the third connection portion 730 and the first electrode 521. Thus, a signal may be transmitted to the first electrode 521 through the third connection 730.

With continued reference to fig. 2a to 2e, an interconnection layer 810 and a carrier wafer 820 (CARRIER WAFER) are further disposed on a side of the device structure layer 500 facing away from the dielectric layer 410, and the interconnection layer 810 has a first metal interconnection line and a second metal interconnection line therein, where the first metal interconnection line is connected to the second connection portion 720 and the carrier wafer 820, respectively, and the second metal interconnection line is connected to the third connection portion 730 and the carrier wafer 820, respectively. Due to the arrangement, it is possible to transmit signals on the transmission paths formed by the second electrode 522, the second connection portion 720, the first metal interconnection line, and the carrier wafer 820, and to transmit signals on the transmission paths formed by the first electrode 521, the third connection portion 730, the second metal interconnection line, and the carrier wafer 820.

To achieve power supply to the transistor, with continued reference to fig. 2a to 2e, the first opening KK1 is filled with a conductive material, forming the first connection portion 710 filled in the first opening KK1, that is, corresponding to the first connection portion 710 being provided at the bottom of the device structure layer 500 (that is, the second surface SD2 of the dielectric layer 410), and the first connection portion 710 is brought into contact with the first electrode 521 through the first opening KK1, so as to achieve electrical connection between the first connection portion 710 and the first electrode 521, that is, the first connection portion 710 corresponds to the bottom connection portion. In this way, after BSPDN is formed on the side, away from the device structural layer 500, of the dielectric layer 410, the metal wire in BSPDN is electrically connected with the first connection portion 710, so that the power signal is transmitted to the first electrode 521 of the device structural layer 500 by adopting BSPDN, and power is supplied to the device structural layer 500. And, the first cross section SC is located between the first surface SD1 of the dielectric layer 410 and the second surface SD2 of the dielectric layer 410, and the cross section area of the first slit KK1 in the first cross section SC is a first area, which represents the cross section area of the first connection portion 710 at the first cross section SC. And, the cross-sectional area of the second slit KK2 in the first cross-section SC is the second area, and the first area is made larger than the second area, so that the cross-sectional area of the first connecting portion 710 at the first cross-section SC is made larger than the second area. However, the cross-sectional area of the bottom connection in the first cross-section SC is substantially the same as the second area. Based on this, as can be seen from the resistance formula r=ρl/S, since the cross-sectional area of the first connection portion 710 at the first cross-section SC in the present application is larger than the cross-sectional area of the bottom connection portion at the first cross-section SC in the related art, the resistance of the first connection portion 710 in the present application is reduced compared to the resistance of the bottom connection portion in the related art, thereby enabling to reduce the power consumption of the IR drop and the semiconductor device.

With continued reference to fig. 2 a-2 e, the cross-section of the first slit KK1 in the first cross-section SC has a first length h11 along the first direction F1, and the cross-section of the second slit KK2 in the first cross-section SC has a second length h12 along the first direction F1, such that the first length h11 is greater than the second length h12. Further, the cross section of the first slit KK1 in the first cross section SC has a third length h21 in the second direction F2, and the cross section of the second slit KK2 in the first cross section SC has a fourth length h22 in the second direction F2, so that the third length h21 and the fourth length h22 may be substantially equal. By this arrangement, the first area can be made larger than the second area. It is understood that by making the third length h21 and the fourth length h22 substantially equal, the first length h11 is greater than the second length h12, which corresponds to enlarging the length of the first slit KK1 in the first direction, and not enlarging the length of the first slit KK1 in the second direction, thereby avoiding a short circuit between the first electrode 521 and the channel region 510. The first direction F1 and the second direction F2 are parallel to the first cross section SC, and the first direction F1 is perpendicular to the second direction F2.

With continued reference to fig. 2d and 2e, the cross section of the first slit KK1 in the first cross section SC and the sidewall of the first slit KK1 in the first direction F1 have a first included angle β1, and the cross section of the second slit KK2 in the first cross section SC and the sidewall of the second slit KK2 in the first direction F1 have a second included angle β2, which may be smaller than the first included angle β1. By this arrangement, the length of the first slit KK1 can be enlarged in the first direction by tilting the side wall of the second slit KK2 in the first direction F1. Of course, the first angle β1 may be substantially equal to the second angle β2, so that the side wall of the second slit KK2 in the first direction F1 may be translated in the first direction F1, thereby enlarging the length of the first slit KK1 in the first direction.

Referring to fig. 2d and 2e, the cross-sectional shape of the first electrode 521 in the stacking direction F3 is a first shape, the cross-sectional shape of the second electrode 522 in the stacking direction F3 is a second shape, and the first shape is different from the second shape. Of course, the first shape and the second shape may be the same, and are not limited herein.

Further, in order to reduce the contact resistance, fig. 3a is a schematic view of a further cross-sectional structure along the direction BB 'in fig. 2a, fig. 3b is a schematic view of a further cross-sectional structure along the direction CC' in fig. 2a, and referring to fig. 3a and 3b, an interface layer 711 is further provided in the semiconductor device, and the interface layer 711 may be provided between the first connection portion 710 and the first electrode 521, so that the contact resistance between the first connection portion 710 and the first electrode 521 is reduced by the interface layer 711. Also, the interface layer 711 includes a low resistivity material. Illustratively, the material of interface layer 711 is a semiconductor material. For example, the interface layer 711 may include silicon or silicon and carbon with a high activity dopant (e.g., one or both of phosphorus and arsenic). In one embodiment, the active dopant concentration is 4E20cm ^-3 or greater. It will be appreciated that fig. 3a and 3b illustrate one interface layer 711, and in practical applications, two, three or more stacked interface layers 711 may be provided, which is not limited herein.

In order to further reduce the contact resistance, referring to fig. 3a and 3b, an interface layer 711 is further provided between the first connection portion 710 and the sidewall of the first slit KK 1. That is, an interface layer 711 is also provided between the first connection portion 710 and the dielectric layer 410, and an interface layer 711 is also provided between the first connection portion 710 and the first insulating layer 610.

It will be appreciated that, in order to clearly illustrate the positional relationship of the relevant layers or structures in fig. 2a, a portion of the layers, for example, the first insulating layer 610, is omitted in fig. 2 a. For the positional relationship of the hidden part of the film layer, refer to fig. 2b to 2d.

The embodiment of the application also provides a preparation method of the semiconductor device, which can comprise the following steps:

Referring to fig. 4a and 4b, fig. 4a is a schematic top view of a semiconductor device in the manufacturing process according to an embodiment of the present application, and fig. 4b is a schematic cross-sectional view along AA' direction in fig. 4 a. Illustratively, a semiconductor substrate 10 is provided, the semiconductor substrate 10 including a first semiconductor layer 11, an Etch stop layer 12 (ESL), and a second semiconductor layer 13, the material of the first semiconductor layer 11 including but not limited to Si, ge, etc., the material of the Etch stop layer 12 including but not limited to SiGe, siO ₂, etc., and the material of the second semiconductor layer 13 including but not limited to Si, ge, etc., being stacked. Illustratively, the semiconductor substrate 10 may be provided as a Silicon-On-Insulator (SOI) substrate in which a bottom Silicon layer serves as the second semiconductor layer 13, a buried oxide layer (e.g., siO ₂) serves as the etch stop layer 12, and a top Silicon layer serves as the first semiconductor layer 11. Thereafter, an initial BDI 30 is epitaxially grown on the first semiconductor layer 11 of the semiconductor substrate 10. Thereafter, the sacrificial layers 21a, 21b, 21c and the channel layers 22a, 22b, 22c are epitaxially grown alternately on the initial BDI 30 to form the stacked film layer 20. In addition, the number of the channel layers and the sacrificial layers in the stacked film layer 20 is not limited, and may be 3 to 7 layers, for example. Fig. 4b illustrates 3 channel layers and 3 sacrificial layers as examples. In addition, the application does not limit the materials of the sacrificial layer and the channel layer, and different channel materials can be matched with different types of sacrificial layer materials according to the requirement of etching selectivity, so that the sacrificial layer has a certain supporting effect on the channel layer and also needs to be selectively etched and removed, namely, when the sacrificial layer is etched and removed, the material of the sacrificial layer has high selectivity compared with the material of the channel layer. Furthermore, the sacrificial layer sometimes needs to provide stress to the channel layer. For example, when the material of the channel layer is Si, the material of the corresponding sacrificial layer may be SiGe, and the material of the initial BDI 30 is SiC or SiGe of a different concentration than the sacrificial layer.

Referring to fig. 5a to 5d, fig. 5a is a schematic top view of a semiconductor device according to an embodiment of the present application during a fabrication process, fig. 5b is a schematic cross-sectional view along AA ' direction in fig. 5a, fig. 5c is a schematic cross-sectional view along BB ' direction in fig. 5a, and fig. 5d is a schematic cross-sectional view along CC ' direction in fig. 5 a. Illustratively, the stacked film 20, the initial BDI30, and the first semiconductor layer 11 are patterned, and shallow trenches are formed in the first semiconductor layer 11, and a plurality of fin structures 20' are formed in the first semiconductor layer 11 and are spaced apart from each other and limited by the shallow trenches. The plurality of fin structures 20' extend along the second direction F2 and are aligned along the first direction F1. The fin structure 20 'includes a substrate fin 23 and a device fin, wherein a portion of the first semiconductor layer 11 limited by the shallow trench is used as the substrate fin 23, and a portion of the first semiconductor layer 11 located between a plane of the bottom of the shallow trench and the ESL12 is used as a reserved substrate 11'. And the device fin includes a patterned initial BDI30 and a stacked structure including alternating layers of sacrificial layers 21 a-21 c and channel layers 22 a-22 c. In addition, the channel layer in the stacked structure may be formed as a nanoplate channel layer (or nanowire channel layer). Thereafter, to isolate the adjacent fin structures 20', a shallow trench isolation (Shallow Trench Isolation, STI) structure may be formed by filling the shallow trenches with a dielectric material, the STI structure being formed as the dielectric layer 410. Thereafter, a plurality of dummy gate structures 41 are formed to extend in the first direction F1 and to be arranged in the second direction F2, the dummy gate structures 41 being disposed across the active region B3 of each stacked structure and being spaced apart from each other. Also, the same dummy gate structure 41 may span multiple fin structures 20'. In addition, for silicon-based devices, the dummy gate structure 41 may include a dummy gate electrode layer and a dummy gate oxide layer disposed between the dummy gate electrode layer and the stacked structure. Alternatively, the material of the dummy gate electrode layer includes, but is not limited to, polysilicon. Thereafter, gate sidewalls 535 are formed at both sides of the dummy gate structure 41 in the second direction F2 to reduce short channel effects. And, the gate side walls 535 also cover the surface of the side of the dummy gate structure 41 facing away from the fin structure 20', and the area where the fin structure 20' between the gate side walls 535 of two adjacent dummy gate structures 41 is located is a source drain area. Optionally, the dielectric material forming the STI structure includes, but is not limited to, one or more of SiO ₂, siON, siNx. And, the material forming the gate sidewall 535 includes, but is not limited to, one or more of SiNx, siON. Furthermore, fig. 5a to 5d illustrate one fin structure 20' and three dummy gate structures 41.

Referring to fig. 6a to 6d, fig. 6a is a schematic top view of a semiconductor device according to an embodiment of the present application during a fabrication process, fig. 6b is a schematic cross-sectional view along AA ' direction in fig. 6a, fig. 6c is a schematic cross-sectional view along BB ' direction in fig. 6a, and fig. 6d is a schematic cross-sectional view along CC ' direction in fig. 6 a. Illustratively, the stacked structure and the initial BDI30 in the source drain region are etched away, the stacked structure and the initial BDI30 under the dummy gate structure 41 and the gate sidewall 535 are retained, the sides of the sacrificial layers 21 a-21 c and the channel layers 22 a-22 c under the gate sidewall 535 are exposed, and the substrate fin 23 in the source drain region is exposed.

Referring to fig. 7a to 7d, fig. 7a is a schematic top view of a semiconductor device according to an embodiment of the present application during a fabrication process, fig. 7b is a schematic cross-sectional view along AA ' direction in fig. 7a, fig. 7c is a schematic cross-sectional view along BB ' direction in fig. 7a, and fig. 7d is a schematic cross-sectional view along CC ' direction in fig. 7 a. Illustratively, an Isotropic etch (isotopic etch) removes the initial BDI 30 and deposits a BDI film layer by a deposition process (e.g., atomic layer deposition). And then, etching the BDI film layer, reserving the BDI film layer below the dummy gate structure 41 and the gate side wall 535, and removing the BDI film layer in the rest area to form a BDI550. Optionally, the material forming the BDI film layer includes, but is not limited to, one or more of SiO2, siCN, siON, siN. It will be appreciated that this step is an alternative, and may or may not be performed, and is not limited in this regard.

Referring to fig. 8a to 8e, fig. 8a is a schematic top view of a semiconductor device according to an embodiment of the present application during a manufacturing process, fig. 8b is a schematic cross-sectional view along AA 'direction in fig. 8a, fig. 8c is a schematic cross-sectional view along BB' direction in fig. 8a, fig. 8d is a schematic cross-sectional view along CC 'direction in fig. 8a, and fig. 8e is a schematic cross-sectional view along DD' direction in fig. 8 a. Illustratively, in a source drain region where a Backside contact (BSC) needs to be formed, etching is performed on the substrate fin 23, removing the substrate fin 23 in the region, and after the substrate fin 23 is removed, forming a first opening KK1 in the dielectric layer 410, because the sidewall of the substrate fin 23 in the region is the dielectric layer 410. Of course, the first semiconductor layer 11 below the substrate fin 23 may be further etched by a distance d1, and a hole may be formed below the first opening KK1. Wherein, since etching to remove the substrate fin portion 23 forms the first slit KK1, a cross-sectional area of the first slit KK1 in the first cross-section SC is SKK1', and SSK1' represents a cross-sectional area of the substrate fin portion 23 in the first cross-section SC. Further, a first length of the cross section of the first slit KK1 in the first cross section SC in the first direction F1 is h11', which is a length of the cross section of the substrate fin 23 in the first cross section SC in the first direction F1. The third length of the cross section of the first slit KK1 in the first cross section SC in the second direction F2 is h21, which h21 represents the length of the cross section of the substrate fin 23 in the first cross section SC in the second direction F2. Further, the first angle between the cross section of the first slit KK1 in the first cross section SC and the sidewall of the first slit KK1 in the first direction F1 is β1', which is an angle (typically 70 degrees to 90 degrees) between the cross section of the substrate fin 23 in the first cross section SC and the sidewall of the first slit KK1 in the first direction F1.

Referring to fig. 9a to 9d, fig. 9a is a schematic top view of a semiconductor device according to an embodiment of the present application during a fabrication process, fig. 9b is a schematic cross-sectional view along AA 'direction in fig. 9a, fig. 9c is a schematic cross-sectional view along BB' direction in fig. 9a, fig. 9d is a schematic cross-sectional view along CC 'direction in fig. 9a, and fig. 9e is a schematic cross-sectional view along DD' direction in fig. 9 a. Illustratively, the sacrificial link film is deposited by a deposition process (e.g., atomic layer deposition), and etched, leaving the sacrificial link film in the first opening KK1 and the hole, etching to remove the sacrificial link film in the remaining regions, and exposing the sidewalls of the sacrificial layers 21 a-21 c and the channel layers 22 a-22 c under the dummy gate structure 41 and the gate sidewall 535, thereby forming the sacrificial link 710' in the first opening KK1 and the hole. Optionally, the material forming the sacrificial link film layer includes, but is not limited to, one or more of SiC, si/Ge, siN, C. Thereafter, an inner sidewall 533 is formed under the gate sidewall 535. Thereafter, a first electrode 521 and a second electrode 522 connected to the channel layer are formed in the source and drain regions on both sides of the dummy gate structure 41 by extension. Thereafter, a second insulating layer 540 is deposited over the first electrode 521 and the second electrode 522. Thereafter, the dummy gate structure 41 is etched away to form a gate opening. And then, etching to remove the sacrificial layer in the gate opening, and releasing the active regions of the channel layers 22 a-22 c. A high-k dielectric material (e.g., a dielectric material having a higher k than silicon oxide) is sampled to form a gate insulating layer 532 over the active region B3. In the gate opening, a gate 531 surrounding each active region is formed. Illustratively, the gate 531 is a metal gate 531, wherein the metal gate 531 is generally a multi-layer structure including, but not limited to, a work function metal (possibly multi-layer work function metal), a liner layer, a wetting layer, an adhesion layer, a metal conductive layer, or a combination of metal silicides, etc. For example, the metal gate 531 includes, but is not limited to, titanium (Ti), ruthenium (Ru), cobalt (Co), titanium nitride (TiN), titanium aluminum (TiAl), tantalum nitride (TaN), titanium aluminum carbide (TiAlC), tungsten (W), and the like. Thereafter, a second contact hole is formed in the second insulating layer 540 on the first electrode 521 to expose a partial region or an entire region of the surface of the first electrode 521 on the side facing away from the ESL12 through the second contact hole. And, a first contact hole is formed in the second insulating layer 540 on the second electrode 522 to expose a partial region or an entire region of the surface of the second electrode 522 on the side facing away from the ESL12 through the first contact hole. Then, a metal material is deposited, and the third connection portion 730 is filled in the second contact hole, so that the third connection portion 730 is in contact with the first electrode 521 through the second contact hole, and the third connection portion 730 is electrically connected with the first electrode 521. The first contact hole is filled with the second connection portion 720, so that the second connection portion 720 is in contact with the second electrode 522 through the first contact hole, and the second connection portion 720 is electrically connected to the second electrode 522.

Referring to fig. 10a to 10d, fig. 10a is a schematic top view of a semiconductor device according to an embodiment of the present application during a fabrication process, fig. 10b is a schematic cross-sectional view along AA 'direction in fig. 10a, fig. 10c is a schematic cross-sectional view along BB' direction in fig. 10a, fig. 10d is a schematic cross-sectional view along CC 'direction in fig. 10a, and fig. 10e is a schematic cross-sectional view along DD' direction in fig. 10a. Illustratively, an interconnect layer 810 is formed on a side of the device structure layer 500 facing away from the ESL12, and a carrier wafer 820 is bonded to the side of the interconnect layer 810 facing away from the ESL 12.

Referring to fig. 11a to 11d, fig. 11a is a schematic top view of a semiconductor device according to an embodiment of the present application during a fabrication process, fig. 11b is a schematic cross-sectional view along AA 'direction in fig. 11a, fig. 11c is a schematic cross-sectional view along BB' direction in fig. 11a, fig. 11d is a schematic cross-sectional view along CC 'direction in fig. 11a, and fig. 11e is a schematic cross-sectional view along DD' direction in fig. 11 a. Illustratively, the semiconductor device is flipped over, the back side of the semiconductor substrate 10 is thinned using a thinning process, the second semiconductor layer 13 is removed, and the thinning stops at the interface of the ESL12 and the second semiconductor layer 13. Thereafter, the ESL12 is etched away. Thereafter, the remaining substrate 11 'is etched away, exposing the sacrificial connection 710'. In this case, the remaining substrate 11' may be completely etched away, or a portion of the remaining substrate 11' may be removed as long as the sacrificial connection portion 710' is exposed.

Referring to fig. 12a to 12d, fig. 12a is a schematic top view of a semiconductor device according to an embodiment of the present application during a manufacturing process, fig. 12b is a schematic cross-sectional view along AA 'direction in fig. 12a, fig. 12c is a schematic cross-sectional view along BB' direction in fig. 12a, fig. 12d is a schematic cross-sectional view along CC 'direction in fig. 12a, and fig. 12e is a schematic cross-sectional view along DD' direction in fig. 12 a. Illustratively, etching removes the substrate fin 23 on a side of the BDI220 facing away from the channel layer, and removes the substrate fin 23 on a side of the second electrode 522 facing away from the second connection portion 720, forming a second opening KK2 and a third opening KK3 in the dielectric layer 410. Wherein, as the substrate fin portion 23 is removed by etching, the second opening KK2 is formed, the cross-sectional area of the second opening KK2 in the first cross-section SC is SKK, the second length of the cross-section of the second opening KK2 in the first cross-section SC in the first direction F1 is h12, and the fourth length of the cross-section of the second opening KK2 in the first cross-section SC in the second direction F2 is h22. Further, a second angle β2 is formed between a cross section of the second slit KK2 in the first cross section SC and a side wall of the first slit KK1 in the first direction F1. And, since the substrate fin portion is etched away, the third opening KK3 is formed, and a length of a cross section of the third opening KK3 in the first cross section SC along the first direction F1 is substantially the same as h 12. Further, the angle between the cross section of the third slit KK3 in the first cross section SC and the side wall of the first slit KK1 in the first direction F1 is substantially the same as β2. Since the first opening KK1 and the second opening KK2 are both formed by removing the substrate fin portion by etching, SKK and SKK ' are substantially the same, h11' and h12 are substantially the same, β1' and β2 are substantially the same, and h22 and h21 are substantially the same. Thereafter, a first insulating layer 610 is deposited on the side of the dielectric layer 410 facing away from the BDI550, and the first insulating layer 610 is caused to fill the second and third openings KK2 and KK3, and the first insulating layer 610 is caused to cover the surface of the side of the dielectric layer 410 facing away from the BDI. Thereafter, the first insulating layer 610 is planarized by a Chemical Mechanical Polishing (CMP) process, exposing the surface of the sacrificial connection on the side facing away from the BDI. It is understood that the material of the first insulating layer 610 may be the same as or different from the material of the dielectric layer 410, which is not limited herein.

Referring to fig. 13a to 13d, fig. 13a is a schematic top view of a semiconductor device according to an embodiment of the present application during a manufacturing process, fig. 13b is a schematic cross-sectional view along AA 'direction in fig. 13a, fig. 13c is a schematic cross-sectional view along BB' direction in fig. 13a, fig. 13d is a schematic cross-sectional view along CC 'direction in fig. 13a, and fig. 13e is a schematic cross-sectional view along DD' direction in fig. 13 a. Illustratively, the sacrificial connection portion 710' is etched away, exposing a partial region or an entire region in the surface of the first electrode 521 facing the first insulating layer 610 through the first slit KK 1. Wherein a first length h11 of the cross section of the first slit KK1 in the first cross section SC in the first direction F1 is h11'. The third length of the cross section of the first slit KK1 in the first cross section SC in the second direction F2 is h21. The first angle β1' between the cross section of the first slit KK1 in the first cross section SC and the side wall of the first slit KK1 in the first direction F1.

Referring to fig. 14a to 14d, fig. 14a is a schematic top view of a semiconductor device according to an embodiment of the present application during a manufacturing process, fig. 14b is a schematic cross-sectional view along AA 'direction in fig. 14a, fig. 14c is a schematic cross-sectional view along BB' direction in fig. 14a, fig. 14d is a schematic cross-sectional view along CC 'direction in fig. 14a, and fig. 14e is a schematic cross-sectional view along DD' direction in fig. 14 a. Illustratively, the sidewalls of the first slit KK1 in the first direction F1 are etched using an angled reactive ion etching process or the like, such that a first angle between a cross section of the first slit KK1 in the first cross section SC and the sidewalls of the first slit KK1 in the first direction F1 is β1, and such that a cross section of the first slit KK1 in the first cross section SC increases from h11' to h11 along a first length h11 of the first direction F1, thereby making h11> h12. Further, h12 does not change, and therefore, the cross-sectional area of the first opening KK1 in the first cross-section SC can be increased from SKK' to SKK. I.e. implementation SKK1> SKK2. Further, when the sidewall of the first slit KK1 in the first direction F1 is etched by an inclined etching process such as an angled reactive ion etching process, the sidewall of the first slit KK1 in the first direction F1 may be translated so that β1 is substantially the same as β1', and β1 is substantially the same as β2, or the sidewall of the first slit KK1 in the first direction F1 may be inclined so that β1< β1', and β1< β2. By this arrangement, the length of the first slit KK1 is enlarged in the first direction, and the length of the first slit KK1 is not enlarged in the second direction, so that a short circuit between the first electrode 521 and the channel region 510 can be avoided.

Referring to fig. 2 a-2 d, a metal layer is deposited on the side of the first insulating layer 610 facing away from the dielectric layer 410, and fills the first opening KK1 with the metal layer, and covers the surface of the side of the first insulating layer 610 facing away from the BDI 550. Thereafter, the metal layer is planarized by a CMP process, and the metal layer covering the surface of the first insulating layer 610 facing away from the BDI550 is removed, exposing the first insulating layer 610, thereby forming the first connection portion 710 in the first slit KK 1. Or referring to fig. 3a and 3b, an interfacial layer is deposited on a side of the first insulating layer 610 facing away from the dielectric layer 410 such that the interfacial layer covers a surface of the first electrode in the first slit KK1 and covers a sidewall of the first slit KK 1. Thereafter, a metal layer is deposited on the side of the first insulating layer 610 facing away from the dielectric layer 410, and fills the first opening KK1 with the metal layer, and covers the surface of the side of the first insulating layer 610 facing away from the BDI 550. Thereafter, the metal layer is planarized by a CMP process, and the metal layer covering the surface of the first insulating layer 610 facing away from the BDI550 is removed, exposing the first insulating layer 610, thereby forming the first connection portion 710 in the first slit KK 1.

The embodiment of the application also provides electronic equipment, which comprises a circuit board (such as a printed circuit board) and any semiconductor device provided by the embodiment of the application, wherein the semiconductor device is connected with the circuit board. Since the principle of the electronic device for solving the problem is similar to that of the semiconductor device, the implementation of the electronic device can be referred to the implementation of the semiconductor device, and the repetition is omitted.

The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application.

Claims

1. A semiconductor device, comprising:

dielectric layer;

A device structure layer, wherein the dielectric layer is arranged on the device structure layer, a first opening and a second opening penetrating the dielectric layer are arranged in the dielectric layer, and the bottoms of the first opening and the second opening both lead to the device structure layer; at least one transistor is formed in the device structure layer, and the transistor includes a channel region, a first electrode and a second electrode, the first electrode and the second electrode are distributed and arranged at two ends of the channel region, and the first electrode is exposed in the first opening;

a first insulating layer, covering the dielectric layer, the first insulating layer covering and filling the second opening, and the first insulating layer bypassing the first opening;

a first connection portion filled in the first opening, and the first connection portion contacts the first electrode through the first opening, a cross-sectional area of the first opening in a first cross-section is larger than a cross-sectional area of the second opening in the first cross-section, the first cross-section is located between the upper surface and the lower surface of the dielectric layer; and a cross-sectional area of the first opening in the first cross-section is the same or gradually increases in a direction from the device structure layer to the dielectric layer;

A second insulating layer is arranged on a side of the device structure layer away from the dielectric layer, the second insulating layer is provided with a first contact hole penetrating the second insulating layer, the bottom of the first contact hole leads to the device structure layer, and the second electrode is exposed in the first contact hole;

The second connection portion is filled in the first contact hole, and the second connection portion is in contact with the second electrode through the first contact hole.

2. The semiconductor device as claimed in claim 1 is characterized in that a cross section of the first opening in the first cross section has a first length along a first direction, a cross section of the second opening in the first cross section has a second length along the first direction, the first length is greater than the second length, and the first direction is parallel to the first cross section.

3. The semiconductor device as described in claim 2 is characterized in that a first angle is formed between a cross section of the first opening in the first cross section and a side wall of the first opening in the first direction, a second angle is formed between a cross section of the second opening in the first cross section and a side wall of the second opening in the first direction, and the first angle is not greater than the second angle.

4. A semiconductor device as described in claim 2 or 3, characterized in that the cross-section of the first opening in the first cross-section has a third length along the second direction, the cross-section of the second opening in the first cross-section has a fourth length along the second direction, the third length is equal to the fourth length, the second direction is parallel to the first cross-section, and the second direction is perpendicular to the first direction.

5 . The semiconductor device according to claim 1 , further comprising: at least one interface layer, wherein the at least one interface layer is disposed between the first connecting portion and the first electrode.

The semiconductor device according to claim 5 , wherein the material of the interface layer is a semiconductor material.

7. The semiconductor device according to claim 6, wherein the interface layer comprises silicon and a dopant;

Alternatively, the interfacial layer comprises silicon, carbon and a dopant;

The dopant includes one or both of phosphorus and arsenic.

8 . The semiconductor device according to claim 5 , wherein the at least one interface layer is further disposed between the first connecting portion and a sidewall of the first opening.

9. The semiconductor device according to any one of claims 1 to 8, characterized in that a second contact hole penetrating the second insulating layer is further provided in the second insulating layer, the bottom of the second contact hole leads to the device structure layer, and the first electrode is exposed in the second contact hole;

The semiconductor device further includes a third connection portion filled in the second contact hole and contacting the first electrode through the second contact hole.

10. The semiconductor device according to any one of claims 1 to 9, characterized in that the channel region comprises: a first connection region, a second connection region, and an active region disposed between the first connection region and the second connection region, the first electrode contacts the first connection region, and the second electrode contacts the second connection region;

The transistor further includes a gate, the gate covers the active area via a gate insulating layer, and the second insulating layer is arranged on both sides of the gate.

11 . The semiconductor device according to claim 10 , wherein the channel region comprises: a plurality of stacked channel layers, wherein the plurality of channel layers are spaced apart from each other, and the gate surrounds an active region of each of the channel layers via the gate insulating layer.

12. An electronic device, comprising: a circuit board and a semiconductor device according to any one of claims 1 to 11, wherein the semiconductor device is connected to the circuit board.

13. A method for preparing a semiconductor device, comprising:

A dielectric layer, a device structure layer and a second insulating layer are formed on a semiconductor substrate; the dielectric layer is arranged on the device structure layer, a first opening and a second opening penetrating the dielectric layer are arranged in the dielectric layer, and the bottoms of the first opening and the second opening both lead to the device structure layer; at least one transistor is formed in the device structure layer, the transistor comprises a channel region, a first electrode and a second electrode, the first electrode and the second electrode are arranged at both ends of the channel region; the first electrode is exposed in the first opening; a substrate fin is provided between the second electrode of the transistor and the semiconductor substrate, the substrate fin fills the second opening, a sacrificial connection portion is filled in the first opening, and the sacrificial connection portion contacts the first electrode through the first opening; a second insulating layer is arranged on a side of the device structure layer away from the dielectric layer, a first contact hole penetrating the second insulating layer is arranged in the second insulating layer, the bottom of the first contact hole leads to the device structure layer, and the second electrode is exposed in the first contact hole;

Depositing a second connecting portion so that the second connecting portion fills the first contact hole and the second connecting portion contacts the second electrode through the first contact hole;

After etching away the substrate fin to expose a portion of the channel region facing the dielectric layer, a first insulating layer is deposited on a side of the dielectric layer away from the device structure layer, so that the first insulating layer covers and fills the second opening and bypasses the first opening, and the first insulating layer covers a surface of the dielectric layer away from the device structure layer;

Etching the sidewall of the first opening so that the cross-sectional area of the first opening in a first cross-section is larger than the cross-sectional area of the second opening in the first cross-section, the first cross-section is located between the upper surface and the lower surface of the dielectric layer; and the cross-sectional area of the first opening in the first cross-section is the same or gradually increases in a direction from the device structure layer to the dielectric layer;

A first connection portion is filled in the first opening, and the first connection portion is in contact with the first electrode through the first opening.

14 . The preparation method according to claim 13 , wherein an inclined etching process is used to etch the sidewall of the first opening in a first direction, and the first direction is parallel to the first cross section.

15 . The preparation method according to claim 14 , wherein the oblique etching process comprises an angled reactive ion etching process.

16. The preparation method according to any one of claims 13 to 15, characterized in that the preparation method further comprises:

After depositing the second connecting portion, forming an interconnection layer on a side of the semiconductor substrate having the transistor;

After bonding the semiconductor substrate with the transistor side to a carrier wafer, the semiconductor substrate is removed.