CN119521752B - Semiconductor devices and their fabrication methods - Google Patents
Semiconductor devices and their fabrication methodsInfo
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- CN119521752B CN119521752B CN202311020688.5A CN202311020688A CN119521752B CN 119521752 B CN119521752 B CN 119521752B CN 202311020688 A CN202311020688 A CN 202311020688A CN 119521752 B CN119521752 B CN 119521752B
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Abstract
A semiconductor device and a forming method thereof comprise the steps of providing a plurality of groups of wafers to be processed, wherein the wafers to be processed comprise a substrate and device structures formed on the substrate, gaps are formed among the device structures, sequentially processing the wafers to be processed based on the sequence of parameter groups in a preset parameter set, forming a deposition layer which completely covers the gaps on the wafers to be processed, wherein the parameter set comprises a plurality of parameter groups, one parameter group corresponds to one group of wafers to be processed, different parameter groups correspond to different states of deposition equipment, and a sacrificial layer is formed on the deposition layer. The scheme can improve the yield of the semiconductor device.
Description
Technical Field
The embodiment of the invention relates to the technical field of semiconductors, in particular to a semiconductor device and a forming method thereof.
Background
In the formation of semiconductor devices, it is necessary to form rugged device structures on a substrate, and thus, gaps of different sizes appear between device structures on the surface of the substrate. At this point, a deposition process is typically used to fill the gaps and further completely cover the device structures, thereby protecting and isolating the device structures.
However, in the prior art, the yield of semiconductor devices is to be improved.
Disclosure of Invention
The embodiment of the invention provides a semiconductor device and a forming method thereof, which are used for improving the yield of the semiconductor device.
To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor device, including:
providing a plurality of groups of wafers to be processed, wherein the wafers to be processed comprise a substrate and device structures formed on the substrate, and gaps are formed among the device structures;
Sequentially processing the wafers to be processed based on the sequence of parameter sets in a preset parameter set, and forming a deposition layer which completely covers the gap on the wafers to be processed, wherein the parameter set comprises a plurality of parameter sets, one parameter set corresponds to one group of wafers to be processed, and different parameter sets correspond to different states of deposition equipment;
A sacrificial layer is formed over the deposited layer.
Optionally, the parameter set in the parameter set is executed in a loop, and a device cleaning process is executed once.
Optionally, in the step of forming a deposition layer on the wafer to be processed, the deposition layer is formed by a deposition process, wherein the parameter set at least comprises a reaction gas flow;
in the parameter set, the flow rate of the reaction gas sequentially increases with the sequence of the parameter set.
Optionally, in the step of forming a deposition layer on the wafer to be processed, the deposition layer is formed by a deposition process, wherein the parameter set at least comprises bias power;
wherein, in the parameter set, the bias power sequentially becomes larger with the order of the parameter set.
Optionally, in the step of forming a deposition layer on the wafer to be processed, a deposition process is adopted to form the deposition layer, wherein the parameter set at least comprises deposition time;
wherein, in the parameter set, the deposition time period sequentially increases with the order of the parameter set.
Optionally, the number of parameter groups in the parameter set is 4-20.
Optionally, in the deposition process, the reaction gas is SIH 4, the side flow of the reaction gas is 6-15 sccm, the top flow of the reaction gas is 6-15 sccm, the bias power is 1200-2000 w, and the deposition duration is 110-200 s.
Optionally, after the step of forming a deposition layer on the wafer to be processed, the step of forming a sacrificial layer on the deposition layer further includes:
Forming a supplemental deposition layer over the deposition layer;
the step of forming a sacrificial layer on the deposition layer, specifically, forming a sacrificial layer on the complementary deposition layer.
Optionally, the device structure includes a gate structure protruding from the substrate, and source-drain structures located at two sides of the gate structure, where the source-drain structures are located in the substrate, and an isolation structure for isolating the device structures is further included between adjacent device structures.
The embodiment of the invention also provides a semiconductor device, which is formed by the method for forming the semiconductor device.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
The embodiment of the invention provides a semiconductor device and a forming method thereof, the forming method comprises the steps of providing a plurality of groups of wafers to be processed, wherein the wafers to be processed comprise substrates and device structures formed on the substrates, gaps are formed among the device structures, sequentially processing the wafers to be processed based on the sequence of parameter groups in a preset parameter set, forming a deposition layer which completely covers the gaps on the wafers to be processed, the parameter set comprises a plurality of parameter groups, one parameter set corresponds to one group of wafers to be processed, and different parameter groups correspond to different states of deposition equipment, and forming a sacrificial layer on the deposition layer.
It can be seen that in the method provided by the embodiment of the invention, by setting a plurality of parameter sets in the parameter set, and enabling different parameter sets to correspond to different states of the deposition device, and simultaneously, one parameter set corresponds to one group of wafers to be processed, after each group of wafers to be processed is processed, one-time parameter adjustment can be realized to adapt to state change of the deposition device, thereby ensuring surface quality of a deposition layer of each wafer to be processed, and improving yield of semiconductor devices.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present invention, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.
Fig. 1 to 3 are schematic structural views corresponding to steps in a method for forming a semiconductor device;
Fig. 4 to fig. 7 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor device according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram corresponding to another embodiment of a method for forming a semiconductor device according to the present invention.
Detailed Description
As described in the background art, the yield of semiconductor devices formed in the prior art needs to be improved.
Next, the cause of this problem is analyzed in combination with a method for forming an existing semiconductor device.
Referring to fig. 1 to 3, fig. 1 to 3 are schematic structural views corresponding to each step in a method for forming a semiconductor device.
Referring to fig. 1, a plurality of sets of wafers to be processed are provided, the wafers to be processed including a substrate 1, and device structures 2 (shown by dotted line boxes) formed on the substrate, wherein gaps (areas indicated by arrows L) are formed between the device structures.
Referring to fig. 2, a deposition layer 3 is formed on the wafer to be processed to entirely cover the gap;
Referring to fig. 3, a sacrificial layer 4 is formed on the deposited layer.
However, the inventors have found that the yield of semiconductor devices is not high in the above process flow. After further observation and analysis, it is considered that in the semiconductor device, the quality of the surface morphology of the deposition layer 3 presents certain regularity, that is, the surface morphology quality of the deposition layer is reduced to a certain extent every certain number of wafers, so that the yield of the semiconductor device is affected. After analysis, the inventor considers that the method is because, in the deposition process, after each preset number of wafers are processed, a device cleaning process is executed, so that the device is in a more ideal state, a deposition layer formed later is good in surface morphology quality, but after a certain number of wafers are processed, the state of the device changes, so that the surface morphology quality of the deposition layer of the rest wafers is reduced, and the yield of semiconductor devices is affected.
For example, in a wafer production process with a line width (i.e., the width of the gate) greater than 40nm, the wafer with low yield has a surface morphology of the deposited layer that is characterized by low quality in the outer ring region of the deposited layer. After a batch of 25 wafers is continuously processed, the wafers with lower yield rate show a rule that the wafers with the problems are 2 nd and 3 rd wafers in every 3 wafers, wherein the yield rate of the 2 nd wafer is reduced by about 6%, the yield rate of the 3 rd wafer is reduced by about 15%, and meanwhile, SEM (Scanning Electron Microscope ) analysis shows that the outer ring area of the deposition layer cannot completely cover the device structures, so that bridging problems among the device structures exist.
However, in the wafer processing process, too much time is spent in performing the equipment cleaning process once, which makes it impractical to perform the equipment cleaning process too frequently to ensure the wafer quality.
In view of the above, the embodiment of the invention provides a semiconductor device and a forming method thereof, wherein the method comprises the steps of providing a plurality of groups of wafers to be processed, wherein the wafers to be processed comprise a substrate and device structures formed on the substrate, gaps are formed among the device structures, sequentially processing the wafers to be processed based on the sequence of parameter groups in a preset parameter set, forming a deposition layer which completely covers the gaps on the wafers to be processed, the parameter set comprises a plurality of parameter groups, one parameter set corresponds to one group of wafers to be processed, and different parameter groups correspond to different states of deposition equipment, and forming a sacrificial layer on the deposition layer.
It can be seen that in the method provided by the embodiment of the invention, by setting a plurality of parameter sets in the parameter set, and enabling different parameter sets to correspond to different states of the deposition device, and simultaneously, one parameter set corresponds to one group of wafers to be processed, after each group of wafers to be processed is processed, one-time parameter adjustment can be realized to adapt to state change of the deposition device, thereby ensuring surface quality of a deposition layer of each wafer to be processed, and improving yield of semiconductor devices.
In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 4 to 7 are schematic structural views corresponding to each step in an embodiment of a method for forming a semiconductor device according to the present invention.
Referring to fig. 4, a plurality of sets of wafers to be processed are provided, the wafers to be processed including a substrate 100, and a device structure 200 (shown in dashed boxes) formed on the substrate, wherein a gap (shown by arrow L) is formed between the device structures.
The wafer to be processed may be understood as a wafer in a semi-finished product, which is used to provide a process basis for forming a semiconductor device, on which a corresponding device structure may be formed, and a gap L between the device structures is to be covered by a subsequent process.
In this embodiment, the substrate 100 may be silicon. In other embodiments, the material of the substrate 100 may be other semiconductor materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate 100 may be another type of substrate such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.
The substrate 100 may have a device structure 200 formed thereon, which may be a device structure of an active device, such as a PMOS transistor, CMOS transistor, NMOS transistor, resistor, capacitor, or inductor, for example. It will be appreciated that, on a wafer to be processed, the number of device structures is typically plural, and to ensure electrical isolation and interference between the device structures, the device structures are typically spatially isolated, so that gaps are formed between the device structures for achieving spatial isolation of the device structures.
In a specific example, the device structure is a MOS device structure, where the device structure 200 may include a gate structure 201 protruding from a substrate, and source-drain structures 202 located on two sides of the gate structure 201, where the source-drain structures 202 may be located in the substrate, and in the substrate, between adjacent device structures, an isolation structure 300 for isolating the device structures is further included.
On a wafer, the size of the gap between different device structures varies based on the layout design of the wafer, with smaller gap sizes corresponding to some device structures being closer together and larger gap sizes corresponding to some device structures being farther apart. It will be appreciated that the larger the gap, the greater the corresponding fill difficulty and, correspondingly, the higher the requirements on the deposition process.
In the embodiment of the invention, aiming at the problem of the yield of the semiconductor device, a plurality of groups of wafers to be processed are provided so as to ensure the yield of the plurality of groups of wafers to be processed at the same time. Wherein, a group of wafers to be processed is a wafer to be processed by the deposition equipment at a time, and the number of the wafers to be processed in the group of wafers to be processed can be one or more, for example, 2, 3 or 4, etc.
Referring to fig. 5, the wafers to be processed are sequentially processed based on the sequence of parameter sets in a predetermined parameter set, and a deposition layer 400 is formed on the wafers to be processed to completely cover the gap.
The parameter set comprises a plurality of parameter sets, one parameter set corresponds to a group of wafers to be processed, and different parameter sets correspond to different states of the deposition equipment.
By setting a plurality of parameter sets in the parameter set and enabling different parameter sets to correspond to different states of the deposition equipment, after each group of wafers to be processed are processed, adjustment of parameters can be realized once, so that the parameter set is suitable for state change of the deposition equipment, and surface quality of a subsequent group of wafers to be processed is ensured.
The sequence of the parameter sets in the parameter set is preset and corresponds to different states of the deposition equipment, so in the embodiment of the invention, the wafers to be processed need to be processed sequentially based on the sequence of the parameter sets in the preset parameter set. And, the parameter set may be preconfigured into the deposition apparatus such that the deposition apparatus achieves continuous, uninterrupted processing of the wafer to be processed directly based on the parameter set.
The parameter sets are correspondingly executed in a circulating way from the process after the deposition equipment finishes the cleaning process to the process before the next cleaning process, and each cycle of the parameter sets is executed for one round, so that the equipment cleaning process is executed once.
The deposited layer may be silicon oxide, in some alternative examples, silicon nitride, silicon oxynitride, or the like.
In an alternative example, the deposition layer may be formed by a deposition process, for example, HDP (high density plasma chemical vapor deposition) process, which has good filling capability, better deposited film characteristics and higher yield, so that the deposition layer covering the gap can be formed rapidly and efficiently.
In an alternative example, at least the flow rate of the reaction gas is included in the parameter set corresponding to the deposition process, and in the parameter set, the flow rate of the reaction gas sequentially increases with the order of the parameter set. The method is characterized in that the probability of occurrence of corresponding deposition pits is increased when the processing flow is more backward corresponding to a plurality of groups of wafers to be processed, and the flow rate of the reaction gas is adjusted to be increased, so that the reaction gas in the deposition equipment is increased, and the corresponding deposition reaction is increased, thereby reducing the probability of occurrence of deposition pits on the wafers to be processed in the subsequent flow. In a specific example, the reaction gas may be a SIH 4, the corresponding reaction gas flow may include a TOP flow (SIH 4 TOP) and a side flow (SIH 4 side), the side flow of the reaction gas may be 6-15 sccm, the TOP flow of the reaction gas may be 6-15 sccm, and specific parameters of the corresponding reaction gas flow may be selected in the range under the condition of ensuring the corresponding variation trend.
In a specific alternative example, in the parameter set, the side flow rate of the reaction gas of each parameter set may be 6Sccm,8Sccm,10Sccm,12Sccm, and 14Sccm in this order, and the top flow rate of the reaction gas of each parameter set may be 6Sccm,8Sccm,10Sccm,12Sccm, and 14Sccm in this order.
In a further alternative example, at least the bias power is included in a parameter set corresponding to the deposition process, and in the parameter set, the bias power sequentially increases with the order of the parameter set. This is because, corresponding to a plurality of groups of wafers to be processed, the more the processing flow is rearward, the larger the probability of occurrence of the corresponding deposition dishing, and by adjusting the bias power to be larger and larger, the deposition reaction in the deposition equipment is also more and more sufficient, so that the probability of occurrence of the deposition dishing of the wafers to be processed in the subsequent flow is reduced. In a specific example, the bias power may be 1200-2000 w, and specific parameters of the corresponding bias power may be selected within the range under the condition of ensuring the corresponding variation trend.
In a specific alternative example, the bias power of each parameter set may be 1200W,1400W, 630W and 2000W in order within the parameter set.
In a further alternative example, the parameter sets corresponding to the deposition process include at least a deposition time period, and in the parameter sets, the deposition time period sequentially increases with the order of the parameter sets. This is because, corresponding to a plurality of groups of wafers to be processed, the more the processing flow is rearward, the larger the probability of occurrence of the corresponding deposition dishing, and by adjusting the deposition time period to be longer and longer, the deposition reaction in the deposition equipment is also more and more sufficient, so that the probability of occurrence of the deposition dishing of the wafers to be processed in the subsequent flow is reduced. In a specific example, the deposition time period may be 110 to 200s, and specific parameters of the corresponding deposition time period may be selected within the range under the condition of ensuring the corresponding variation trend.
In a specific alternative example, the deposition time periods of the parameter sets may be 110S,130S,150S,170S, and 190S in this order within the parameter set.
It can be understood that, based on the embodiment of the present invention, the parameters can be adjusted based on the state of the device, so as to ensure the processing quality of the wafer to be processed to the greatest extent. In a specific example, the number of parameter sets in the parameter set may be 4 to 20, for example, 4, or 8, 12, or 16.
In a specific example, the reactant gas may further include O 2 and PH 3.
The flow rate of O 2 may be 40 to 80Sccm, and the flow rate of O 2 in each parameter set may be, for example, 40Sccm,50Sccm,60Sccm,70Sccm, and 80Sccm in this order, which is not particularly limited herein.
Wherein, the top flow of PH 3 can be 1.5-3 SCcm, and the side flow can be 1.5-3 SCcm. The corresponding parameter settings may be selected with reference to the above manner, and the invention is not particularly limited herein.
Referring to fig. 6, a sacrificial layer 500 is formed on the deposition layer.
The sacrificial layer is used for further protecting and isolating the device structure, wherein the sacrificial layer has a flat surface. The sacrificial layer may be formed by a deposition process, specifically, the deposition process may be PETEOS (plasma enhanced tetraethyl orthosilicate layer deposition), and correspondingly, the material of the sacrificial layer may be one or more of silicon oxide, silicon nitride, silicon oxynitride, and the like.
Specifically, in order to form the sacrificial layer into a flat surface, the process of forming the sacrificial layer may include:
Forming a sacrificial material layer on the deposition layer, wherein the thickness of the sacrificial material layer is larger than that of the sacrificial layer; and grinding to remove the sacrificial material layer with excessive thickness to form the sacrificial layer.
The sacrificial material layer provides a process basis for forming the sacrificial layer. Accordingly, the material of the sacrificial material layer is the same as the material of the sacrificial layer.
It will be appreciated that, based on the surface of the wafer to be processed having a device structure, the corresponding surface topography is manifested as roughness, and the deposited layer formed on the basis of this will not normally be perfectly planar, nor will the layer of sacrificial material formed on the basis of this be perfectly planar.
Therefore, in the embodiment of the invention, the thickness of the first formed sacrificial material layer is larger than the thickness of the subsequently formed sacrificial layer, so that part of the thickness of the sacrificial material layer can be removed based on the grinding process to form the sacrificial layer with a flat surface.
Wherein the redundant thickness refers to the difference between the thickness of the preset sacrificial layer and the thickness of the formed sacrificial material layer, and a flat surface can be formed based on the characteristics of the grinding process.
It can be seen that in the method provided by the embodiment of the invention, by setting a plurality of parameter sets in the parameter set, and enabling different parameter sets to correspond to different states of the deposition device, and simultaneously, one parameter set corresponds to one group of wafers to be processed, after each group of wafers to be processed is processed, one-time parameter adjustment can be realized to adapt to state change of the deposition device, thereby ensuring surface quality of a deposition layer of each wafer to be processed, and improving yield of semiconductor devices.
In the embodiment of the invention, even for the gap with the size larger than 40nm, good filling can be realized.
It will be appreciated that in HDP deposition processes, the film growth rate is slow, about 1800-4000A/min, and correspondingly, the wafer processing speed is slow, and the WPH (wafer per hour number of wafers processed) is relatively small, and in the process of producing a film thickness of about 5000A, WPH is generally less than 3.
In a further embodiment of the present invention, a complementary deposition layer is further formed on the deposition layer, so as to further protect and isolate the device structure, and improve the yield of the device structure. Specifically, in an embodiment of the present invention, after the step of forming a deposition layer on the wafer to be processed to completely cover the gap, the method further includes:
referring to fig. 7, a supplemental deposition layer 600 is formed on the deposition layer;
The additional deposition layer may be, for example, silicon oxide, and by further forming the additional deposition layer, defects such as recesses that may occur during the formation of the deposition layer are corrected. The material of the complementary deposition layer can be one or more of silicon oxide, silicon nitride, silicon oxynitride and the like.
Specifically, the complementary deposition layer may be formed by a deposition process, for example HARPTEOS (deposition of a high aspect ratio ethyl orthosilicate layer), and HARPTEOS has excellent filling capability and extensibility, so that better and more sufficient filling can be achieved in both larger-sized gaps and smaller-sized gaps.
Accordingly, in an example of forming a supplementary deposition layer, the step of forming a sacrificial layer on the deposition layer, and in particular, referring to fig. 8, a sacrificial layer 500 is formed on the supplementary deposition layer 600.
In another embodiment of the present invention, there is also provided a semiconductor device formed based on the method for forming a semiconductor device provided in the foregoing embodiment, wherein, referring to fig. 8, the semiconductor device includes:
A substrate 100, and device structures formed on the substrate, wherein gaps (indicated by arrows L in the figure) are formed between the device structures.
In this embodiment, the substrate 100 may be silicon. In other embodiments, the material of the substrate 100 may be other semiconductor materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate 100 may be another type of substrate such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.
The substrate 100 may have a device structure formed thereon, which may be a device structure of an active device, such as a PMOS transistor, a CMOS transistor, an NMOS transistor, a resistor, a capacitor, or an inductor, or the like. It will be appreciated that the number of device structures is typically plural, and that to ensure electrical isolation and interference between the device structures, the device structures are typically spatially isolated, such that gaps are formed between the device structures for achieving spatial isolation of the device structures.
In a specific example, the device structure is a MOS device structure, where the device structure may include a gate structure 201 protruding from a substrate, and source-drain structures 202 located on two sides of the gate structure 201, where the source-drain structures 202 may be located in the substrate, and an isolation structure 300 for isolating the device structure is further included between adjacent device structures in the substrate.
The size of the gap between different device structures varies based on the layout design of the wafer, with smaller gap sizes corresponding to some device structures being closer together and larger gap sizes corresponding to some device structures being farther apart. It will be appreciated that the larger the gap, the greater the corresponding fill difficulty and, correspondingly, the higher the requirements on the deposition process.
The semiconductor device further includes a deposition layer 400, which may be silicon oxide, which in some alternative examples may also be silicon nitride, silicon oxynitride, etc., that completely covers the gap.
The deposited layer 400 may further include a sacrificial layer 500 thereon, and the material of the sacrificial layer may be one or more of silicon oxide, silicon nitride, silicon oxynitride, and the like.
In some alternative examples, a supplemental deposition layer 600 may also be included on the deposition layer. The material of the complementary deposition layer can be one or more of silicon oxide, silicon nitride, silicon oxynitride and the like. In particular, the supplemental deposition layer is located between the deposition layer and the sacrificial layer.
It should be noted that, in the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described as different from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other. For the apparatus class embodiments, the description is relatively simple as it is substantially similar to the method embodiments, and reference is made to the description of the method embodiments for relevant points.
Although the embodiments of the present invention are disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (7)
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| CN107978523A (en) * | 2016-10-24 | 2018-05-01 | 中芯国际集成电路制造(上海)有限公司 | The control method of multizone differential etching |
| CN113933672A (en) * | 2021-09-18 | 2022-01-14 | 杭州广立微电子股份有限公司 | A method and system for judging the correlation of wafer test parameters |
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| JP5286701B2 (en) * | 2007-06-27 | 2013-09-11 | ソニー株式会社 | Semiconductor device and manufacturing method of semiconductor device |
| SG195494A1 (en) * | 2012-05-18 | 2013-12-30 | Novellus Systems Inc | Carbon deposition-etch-ash gap fill process |
| KR20180071695A (en) * | 2016-12-20 | 2018-06-28 | 주식회사 티씨케이 | Parts for semiconductor manufacturing with deposition layer covering boundary line between layers |
| US10269559B2 (en) * | 2017-09-13 | 2019-04-23 | Lam Research Corporation | Dielectric gapfill of high aspect ratio features utilizing a sacrificial etch cap layer |
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| CN107978523A (en) * | 2016-10-24 | 2018-05-01 | 中芯国际集成电路制造(上海)有限公司 | The control method of multizone differential etching |
| CN113933672A (en) * | 2021-09-18 | 2022-01-14 | 杭州广立微电子股份有限公司 | A method and system for judging the correlation of wafer test parameters |
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