CN119521659A

CN119521659A - Semiconductor structure and manufacturing method thereof

Info

Publication number: CN119521659A
Application number: CN202411596584.3A
Authority: CN
Inventors: 周厚宏; 徐大林; 黄晨; 全钟声
Original assignee: Changxin Technology Group Co ltd
Current assignee: Changxin Technology Group Co ltd
Priority date: 2024-11-08
Filing date: 2024-11-08
Publication date: 2025-02-25

Abstract

A semiconductor structure and a method for manufacturing the semiconductor structure, the semiconductor structure comprising: a substrate, the substrate having a word line groove extending from the top surface of the substrate toward the inside of the substrate, and the word line groove also extending along a first direction, the first direction being parallel to the plane where the top surface of the substrate is located; a buried word line structure located in the word line groove, the word line structure comprising a gate dielectric layer, a gate conductive layer and an insulating cap layer stacked in sequence, the gate dielectric layer covering the bottom and at least part of the sidewall of the word line groove, the gate conductive layer covering the surface of the gate dielectric layer located at the bottom of the word line groove and part of the sidewall region in contact with the bottom, and the insulating cap layer being located on the top surface of the gate conductive layer; wherein the gate conductive layer comprises a metal material conductive layer, a semiconductor material conductive layer and an air gap, the semiconductor material conductive layer and the air gap being embedded in and occupying part of the sidewall of the metal material conductive layer. The semiconductor structure has good electrical properties.

Description

Semiconductor structure and manufacturing method thereof

Technical Field

The embodiment of the disclosure relates to the technical field of semiconductors, in particular to a semiconductor structure and a manufacturing method thereof.

Background

A dynamic random access memory Device (DRAM) is a type of volatile memory. DRAM devices generally include a memory array region composed of memory cells, and a peripheral region composed of logic control circuits. A typical memory cell includes a switching structure (e.g., a transistor) and a memory structure (e.g., a capacitor). Logic control circuitry in the peripheral region may address each memory cell in the memory array region by passing through a plurality of columns of word lines (word lines) and a plurality of rows of bit lines (bit lines) of the memory array region and opening a switch structure to electrically connect with the memory structure to perform reading, writing or accessing of data.

However, due to the demands of mass storage and high integration, the size of the memory device is rapidly shrinking, and how to secure and improve the electrical performance of the word line structure in the memory array region is a technical problem to be solved.

Disclosure of Invention

According to a first aspect of the embodiment of the disclosure, a semiconductor structure is provided, which comprises a substrate, a word line structure and an air gap, wherein the substrate is provided with a word line groove extending from the top surface of the substrate towards the inside of the substrate, the word line groove also extends along a first direction, the first direction is parallel to a plane of the top surface of the substrate, the word line structure is arranged in the word line groove and comprises a gate dielectric layer, a gate conductive layer and an insulating cover layer which are sequentially stacked, the gate dielectric layer covers the bottom and at least part of the side wall of the word line groove, the gate conductive layer covers the surface of the gate dielectric layer on the bottom of the word line groove and the part of the side wall contacted with the bottom, the insulating cover layer is arranged on the top surface of the gate conductive layer, the gate conductive layer also comprises a metal material conductive layer and a semiconductor material conductive layer, and the word line structure further comprises the air gap, and the semiconductor material conductive layer and the air gap are embedded in and occupy part of the side wall of the metal material conductive layer.

In some embodiments, the air gap is located on top of, and in direct contact with, the conductive layer of semiconductor material.

In some embodiments, a ratio of a height of the air gap to a height of the conductive layer of semiconductor material is 1:3, the height direction being a direction perpendicular to the substrate surface.

In some embodiments, the sum of the height of the air gap and the height of the conductive layer of semiconductor material is in the range of 30-45 nm.

In some embodiments, the thickness of the air gap is greater than or equal to the thickness of the semiconductor material conductive layer, the thickness ranges from 2.5 nm to 4.5nm, and the thickness direction is parallel to the plane of the top surface of the substrate and perpendicular to the first direction.

In some embodiments, in the same word line trench, the number of the air gaps and the semiconductor material conductive layers is two, and the air gaps and the semiconductor material conductive layers are respectively located on two opposite side walls of the metal material conductive layer, and are disposed in a mirror symmetry manner with respect to a central axis surface of the metal material conductive layer, and the central axis surface is perpendicular to the top surface of the substrate and extends along the first direction.

In some embodiments, a portion of the sidewall of the metallic material conductive layer embedded and occupied by the semiconductor material conductive layer and the air gap is located in a region near the top of the metallic material conductive layer.

In some embodiments, the metal material conductive layer comprises a first sub-portion and a second sub-portion, the second sub-portion is located at the top of the first sub-portion, the semiconductor material conductive layer and the air gap are located at two sides of the second sub-portion, the sum of the heights of the semiconductor material conductive layer and the air gap is smaller than or equal to the height of the second sub-portion, the height direction is a direction perpendicular to the surface of the substrate, the average thickness of the second sub-portion is smaller than the maximum thickness of the first sub-portion, and the thickness direction is parallel to the plane of the top surface of the substrate and perpendicular to the first direction.

In some embodiments, the ratio of the heights of the second sub-portion and the first sub-portion ranges from 1:2 to 1:1, and the ratio of the average thickness of the second sub-portion to the maximum thickness of the first sub-portion ranges from 1:3 to 2:3.

In some embodiments, the substrate further includes an active region and an isolation structure, a plurality of the active regions are distributed in an array, the isolation structure is located between adjacent active regions, and the word line structure passes through the plurality of active regions and the isolation structure.

According to a second aspect of the embodiment of the disclosure, a manufacturing method of a semiconductor structure is provided, and the manufacturing method comprises the steps of providing a substrate, forming a word line groove extending from the top surface of the substrate towards the inside of the substrate on the surface of the substrate, wherein the word line groove also extends along a first direction, the first direction is parallel to a plane of the top surface of the substrate, forming a word line structure in the word line groove, forming a gate dielectric layer, a gate conductive layer and an insulating cover layer sequentially stacked in the word line groove, wherein the gate dielectric layer covers the bottom and at least part of side walls of the word line groove, the gate conductive layer covers the surface of the gate dielectric layer located on the bottom of the word line groove and part of side wall area contacted with the bottom, the insulating cover layer is formed on the top surface of the gate conductive layer, the gate conductive layer further comprises a metal material conductive layer and a semiconductor material conductive layer, and the word line structure further comprises an air gap, and the semiconductor material conductive layer and the air gap is embedded in and occupies part of the side walls of the metal material conductive layer.

In some embodiments, forming a gate dielectric layer, a gate conductive layer and an insulating cap layer in the word line trench sequentially comprises forming the gate dielectric layer at the bottom and at least part of the side wall of the word line trench, forming the metal material conductive layer on the surface of the gate dielectric layer, forming the semiconductor material conductive layer on part of the side wall of the metal material conductive layer, forming the insulating cap layer on the top surface of the metal material conductive layer, forming the air gap between the insulating cap layer and the semiconductor material conductive layer, wherein the air gap is positioned at the top of the semiconductor material conductive layer, and the air gap is in direct contact with the top of the semiconductor material conductive layer.

In some embodiments, the metal material conductive layer is formed on the surface of the gate dielectric layer, the semiconductor material conductive layer is formed on part of the side wall of the metal material conductive layer, the method comprises the steps of forming a first sub-portion of the metal material conductive layer on the surface of the gate dielectric layer, forming a second sub-portion of the semiconductor material conductive layer and the metal material conductive layer on the top of the first sub-portion, wherein the semiconductor material conductive layer and the air gap are located on two sides of the second sub-portion, the sum of the heights of the semiconductor material conductive layer and the air gap is smaller than or equal to the height of the second sub-portion, the height direction is the direction perpendicular to the surface of the substrate, the average thickness of the second sub-portion is smaller than the maximum thickness of the first sub-portion, and the thickness direction is parallel to the plane of the top surface of the substrate and perpendicular to the first direction.

In some embodiments, forming the metal material conductive layer on the surface of the gate dielectric layer and forming the semiconductor material conductive layer on a part of the side wall of the metal material conductive layer comprises forming an initial metal material conductive layer on the surface of the gate dielectric layer, etching a part of the side wall of the initial metal material conductive layer to form the metal material conductive layer comprising a first sub-portion and a second sub-portion, wherein the second sub-portion is positioned on the top of the first sub-portion, forming the semiconductor material conductive layer on the side wall of the second sub-portion, and the sum of the heights of the semiconductor material conductive layer and the air gap is smaller than or equal to the height of the second sub-portion, wherein the height direction is a direction perpendicular to the surface of the substrate, and the average thickness of the second sub-portion is smaller than the maximum thickness of the first sub-portion, and the thickness direction is parallel to the plane of the top surface of the substrate and perpendicular to the first direction.

In some embodiments, before forming the word line trench, forming an active region and an isolation structure on the surface of the substrate, wherein a plurality of the active regions are distributed in an array, the isolation structure is positioned between adjacent active regions, and after forming the word line trench, the word line trench passes through the plurality of active regions and the isolation structure.

Drawings

FIG. 1 is a schematic diagram of a semiconductor structure shown in accordance with an exemplary embodiment;

fig. 2 is a schematic diagram of a semiconductor structure shown in accordance with another exemplary embodiment;

FIG. 3 is a schematic diagram of a provided substrate shown according to an exemplary embodiment;

FIG. 4 is a schematic diagram illustrating the formation of isolation structures and active regions, according to an example embodiment;

FIG. 5 is a schematic diagram illustrating the formation of a word line structure in accordance with an exemplary embodiment;

FIG. 6 is a schematic diagram showing specific steps for forming a word line structure, according to one illustrative embodiment;

FIG. 7 is a schematic diagram illustrating specific steps for forming a word line structure according to a second exemplary embodiment;

FIG. 8 is a schematic diagram illustrating specific steps for forming a word line structure, according to a third exemplary embodiment;

FIG. 9 is a schematic diagram of a memory structure shown according to an example embodiment.

Detailed Description

The technical scheme of the present disclosure will be further elaborated with reference to the drawings and examples. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

The present disclosure is described more specifically in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become more fully apparent from the following description and appended claims. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the disclosure.

It is to be understood that the meaning of "on," "over," "above," and "above" of the present disclosure should be read in the broadest manner so that "on" means not only that it is "on" something and there is no intervening feature or layer therebetween (i.e., directly on something), but also that it is "on" and there is an intervening feature or layer therebetween.

In the presently disclosed embodiments, the terms "first," "second," "third," and the like are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order.

In the presently disclosed embodiments, the term "layer" refers to a portion of material that includes a region having a thickness. The layer may extend over the entirety of the underlying or overlying structure, or may have a range that is less than the range of the underlying or overlying structure. Further, the layer may be a region of homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure, or the layer may be between any horizontal facing at the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically and/or along an inclined surface. The layer may comprise a plurality of sub-layers.

The technical solutions described in the embodiments of the present disclosure may be arbitrarily combined without any conflict.

In the related art, a process flow of a Dynamic Random Access Memory (DRAM) structure generally requires forming a memory cell related structure such as a memory transistor, a memory capacitor, a bit line, a word line, etc. in a memory array region. The inventor of the present application has found that with the continuous demands of mass storage and high integration, the related electrical performance of the word line structure is severely slipped down after further miniaturization of the size, such as the problems of large Gate Induced Drain Leakage (GIDL), small saturation current (IDR), large word line impedance, etc., seriously affecting the transistor switch, the memory failure and the device reliability.

In view of the foregoing technical problems, the present disclosure provides a semiconductor structure and a method for manufacturing the same, and in particular, an exemplary semiconductor structure and a method for manufacturing the same will be described with reference to fig. 1 to 9. Fig. 1 to 2 are schematic views of a semiconductor structure shown according to various exemplary embodiments of the present disclosure, fig. 3 to 8 are schematic views of a method of manufacturing a semiconductor structure shown according to an exemplary embodiment of the present disclosure, and fig. 9 is a schematic view of a memory structure shown according to an exemplary embodiment of the present disclosure.

In an exemplary embodiment of the present disclosure, a semiconductor structure is provided, and referring to fig. 1,2 or 5, fig. 1 or 2 is shown as a schematic cross-sectional view along a plane of a third direction Z and a second direction Y, fig. 5 (a) is shown as a top view facing a top surface of a substrate 1 in a reverse direction of the third direction Z, and fig. 5 (b) is a schematic cross-sectional view along A-A' direction in fig. 5 (a). The semiconductor structure comprises a substrate 1, a word line structure 10 and an insulating cover layer 103, wherein the substrate 1 is provided with a word line groove 100 extending from the top surface of the substrate 1 towards the inside of the substrate 1, the word line groove 100 also extends along a first direction X, the first direction X is parallel to the plane of the top surface of the substrate 1, the word line structure 10 is arranged in the word line groove 100 and comprises a gate dielectric layer 101, a gate conductive layer 102 and an insulating cover layer 103 which are sequentially stacked, the gate dielectric layer 101 covers the bottom and at least part of the side wall of the word line groove 100, the gate conductive layer 102 covers the surface of the gate dielectric layer 101 on the bottom of the word line groove 100 and the part of the side wall contacted with the bottom, the insulating cover layer 103 is arranged on the top surface of the gate conductive layer 102, the word line structure 10 further comprises an air gap 104, the gate conductive layer 102 comprises a metal material conductive layer 1021 and a semiconductor material conductive layer 1022, and the semiconductor material conductive layer 1022 are embedded in and occupy part of the side wall of the metal material conductive layer 1021.

The material of the substrate 1 may be at least one of silicon, germanium, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), germanium-on-insulator (GeOI) and the like semiconductor material or group III-V material. In an exemplary embodiment of the present disclosure, the material of the substrate 1 is monocrystalline silicon.

The word line trench 100 is located in the substrate 1, extends from the top surface of the substrate 1 toward the inside of the substrate 1, i.e. the opening of the word line trench 100 is on the top surface of the substrate 1, and the depth direction of the trench is perpendicular to the plane of the top surface of the substrate 1 and toward the inside of the substrate 1, opposite to the third direction Z. The word line trenches 100 also extend in a first direction X on a plane parallel to the top surface of the substrate 1, and as can be seen in fig. 5 (a), the word line structures 10 located in the word line trenches 100 extend in the first direction X. In some embodiments, referring to fig. 1 or 2, the cross-sectional schematic view of the word line trench 100 is rectangular, i.e., the opening size of the word line trench 100 is substantially the same as the bottom size. In other embodiments, the cross-sectional schematic view of the word line trench 100 is trapezoidal, e.g., the opening size of the word line trench 100 is larger than the bottom size, or the bottom size of the word line trench 100 is larger than the opening size.

The gate dielectric layer 101 covers the bottom and at least a portion of the sidewalls of the word line trench 100. In some embodiments, as shown in fig. 1 or 2, gate dielectric layer 101 covers the bottom and all sidewalls of word line trench 100. In other embodiments, the gate dielectric layer 101 covers only the bottom of the word line trench 100 and the portion of the height of the sidewall (not shown) that is in contact with the bottom. The material of the gate dielectric layer 101 may be any one or a combination of silicon oxide, hafnium oxide, zirconium oxide, and aluminum oxide. In an exemplary embodiment of the present disclosure, silicon oxide is used as the material of gate dielectric layer 101.

The gate conductive layer 102 covers the surface of the gate dielectric layer 101 on the bottom of the wordline trench 100 and the portion of the sidewall in contact with the bottom. In some embodiments, the gate conductive layer 102 fills the bottom of the word line trench 100 and covers the gate dielectric layer 101 on a portion of the sidewalls of the depth of the word line trench 100 from the bottom up to 1/3-2/3. Specifically, in the word line trench 100, the top surface of the gate dielectric layer 101 is higher than the gate conductive layer 102.

The gate conductive layer 102 includes a metal material conductive layer 1021 and a semiconductor material conductive layer 1022. In some embodiments, the metal material conductive layer 1021 occupies a main portion of the gate conductive layer 1021, and the semiconductor material conductive layer 1022 is embedded in and occupies a portion of the sidewall of the metal material conductive layer 1021.

In some embodiments, the conductive layer 1021 of metal material includes a first sub-portion 1021a and a second sub-portion 1021b, the second sub-portion 1021b being located on top of the first sub-portion 1021 a. In some embodiments, in the same word line trench 100, the number of semiconductor material conductive layers 1022 is two, and the semiconductor material conductive layers 1022 are respectively located at two sides of the second sub-portion 1021b and are disposed in mirror symmetry with respect to the central axis of the metal material conductive layer 1021.

In some embodiments, the average thickness of the second sub-portion 1021b is less than the maximum thickness of the first sub-portion 1021 a. In some embodiments, the ratio of the heights of the second sub-portion 1021b and the first sub-portion 1021a ranges from 1:2 to 1:1, and the ratio of the average thickness of the second sub-portion 1021b to the maximum thickness of the first sub-portion 1021a ranges from 1:3 to 2:3. The thickness direction is parallel to the plane of the top surface of the substrate 1 and perpendicular to the first direction X, and the height direction is a direction perpendicular to the surface of the substrate 1, i.e., the same direction as the third direction Z.

In some embodiments, the material of the metal material conductive layer 1021 may be any one or more of tungsten, titanium, molybdenum, ruthenium, tungsten nitride, titanium nitride, molybdenum nitride, ruthenium nitride, and the material of the semiconductor material conductive layer 1022 may be any one or more of doped polysilicon, polysilicon germanium, or polysilicon germanium. In an exemplary embodiment of the present disclosure, the material of the metal material conductive layer 1021 is titanium nitride, and the semiconductor material conductive layer is doped polysilicon.

In some embodiments, the second sub-portion 1021b and the first sub-portion 1021a may be the same material, e.g., both titanium nitride. In other embodiments, the second sub-portion 1021b is of a different material than the first sub-portion 1021a, e.g., the material of the first sub-portion 1021a is titanium nitride and the material of the second sub-portion 1021b is tungsten.

In some embodiments, as shown in fig. 1, the second sub-portion 1021b and the first sub-portion 1021a may be formed separately for two separate portions. In yet other embodiments, as shown in fig. 2, the second sub-portion 1021b is integrally formed with the first sub-portion 1021 a. In fig. 2, the broken line is merely for illustrating the distinction between the first and second sub-portions 1021a and 1021b, and in an actual structure, there is no substantial dividing line or interface because they are integrally formed.

An insulating cap layer 103 is located on the top surface of the gate conductive layer 102. Specifically, the insulating cap layer 103 fills the word line trench 100 above the top surface of the second sub-portion 1021b of the metal material conductive layer 1021 of the gate conductive layer 102, and the lowest bottom surface of the insulating cap layer 103 is flush with the top surface of the second sub-portion 1021b or slightly below the top surface of the second sub-portion 1021 b. In some embodiments, gate dielectric layer 101 covers the bottom and all sidewalls of word line trench 100 and insulating cap layer 103 covers the surface of gate dielectric layer 101 at the sidewalls of the top region of word line trench 100. In other embodiments, gate dielectric layer 101 covers the bottom and a portion of the sidewalls of word line trench 100, i.e., the sidewalls other than the sidewalls of the top region of word line trench 100, and insulating cap layer 103 directly covers the sidewalls of the top region of word line trench 100 and is located on the top surface of gate dielectric layer 101 in direct contact with the top surface of gate dielectric layer 101. In some embodiments, the material of insulating cap layer 103 may be at least one of, or any combination of, silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride. In an exemplary embodiment of the present disclosure, the material of the insulating cap layer 103 is silicon nitride.

The word line structure 10 further includes an air gap 104, the air gap 104 being embedded in and occupying a portion of the sidewalls of the conductive layer 1021 of metal material. Specifically, the air gap 104 is surrounded by the top surface of the semiconductor material conductive layer 1022, a portion of the side surface of the second sub-portion 1021b, a portion of the surface of the gate dielectric layer 101, and the bottom surface of the insulating cap 103. In some embodiments, the air gap 104 is located on top of the conductive layer 1022 of semiconductor material and is in direct contact with the top of the conductive layer 1022 of semiconductor material.

In some embodiments, the ratio of the height of the air gap 104 to the height of the conductive layer 1022 of semiconductor material is 1:3. In an exemplary embodiment of the present disclosure, the sum of the height of the air gap 104 and the height of the semiconductor material conductive layer 1022 is in the range of 30-45 nm, for example, 30nm, 35nm, 40nm, 45nm may be used. In an exemplary embodiment of the present disclosure, the thickness of the air gap 104 is greater than or equal to the thickness of the semiconductor material conductive layer 1022, which may range from 2.5nm to 4.5nm, for example, 2.5nm, 3nm, 3.5nm, 4nm, 4.5nm. The height direction is a direction perpendicular to the surface of the substrate 1, i.e., the same direction as the third direction Z, and the thickness direction is parallel to the plane of the top surface of the substrate 1 and perpendicular to the first direction X.

In some embodiments, as shown in fig. 5, the substrate 1 further includes active regions 11 and isolation structures 12, the plurality of active regions 11 are distributed in an array, the isolation structures 12 are located between adjacent active regions 11, and the word line structures 10 pass through the plurality of active regions 11 and the isolation structures 12. Specifically, as shown in fig. 5 (a) and 5 (b), the isolation structure 12 is a Shallow Trench Isolation (STI) structure, dividing a surface portion of the substrate 1 into a plurality of active regions 11, the plurality of active regions 11 are arranged in an staggered array for subsequently forming source and drain regions and channel regions of a transistor, the plurality of word line structures 10 extend in the first direction X and are arranged at equal intervals in the second direction Y, and pass through the plurality of active regions 11 and the isolation structure 12, wherein the depth of the word line structures 10 or the word line trenches 100 is smaller than the depth of the isolation structure 12. In some embodiments, the same active region 11 is traversed by two adjacent word line structures 11, thereby subsequently forming two transistors in the active region 11 sharing one of the source-drain regions.

In some embodiments, the material of isolation structure 12 may be at least one of, or any combination of, silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride. In an exemplary embodiment of the present disclosure, the isolation structure 12 is made of silicon oxide. In some embodiments, the active region 11 may have a doping of an N-type or P-type element therein, specifically, the N-type element includes a group V element such as phosphorus, arsenic, antimony, or bismuth, and the P-type element includes a group III element such as boron, aluminum, gallium, or indium.

The semiconductor structure provided by the disclosure comprises a gate dielectric layer, a gate conductive layer, an insulating cover layer and an air gap which are sequentially stacked, wherein the gate conductive layer is made of a metal material and the semiconductor material is made of a metal material, the semiconductor material and the air gap are embedded into and occupy part of the side wall of the metal material, and the metal material is maintained to have a larger conduction area only by a proper thin thickness so as to reduce the impedance of a word line. On the one hand, the semiconductor material conductive layer has a lower work function than the metal material conductive layer, the semiconductor material conductive layer is embedded in part of the side wall of the metal material conductive layer and is positioned at the end part of a channel region in a transistor formed later, so that the problem of Gate Induced Drain Leakage (GIDL) can be effectively reduced, the higher height of the semiconductor material conductive layer is also used for effectively improving drain saturation current (IDR), on the other hand, the air gap has a lower dielectric constant and is configured to be embedded in part of the side wall of the metal material conductive layer, the coupling effect between adjacent word line structures or between the word line structures and other later forming devices (such as a bit line structure, a storage contact structure and the like) can be effectively reduced, crosstalk between the adjacent structures is avoided, and in addition, the air gap is positioned at the top of the semiconductor material conductive layer and is in direct contact with the top of the semiconductor material conductive layer, and the higher height of the air gap is used for further reducing the Gate Induced Drain Leakage (GIDL). By combining the characteristics, the word line structure with the height and thickness of the semiconductor material conductive layer and the air gap is properly adjusted, and the characteristics of high drain saturation current (IDR), low Gate Induced Drain Leakage (GIDL) and low word line impedance are considered, so that the working performance of the memory device is improved.

Based on the semiconductor structure, the present disclosure also provides a method for manufacturing the semiconductor structure, which comprises providing a substrate 1, as shown in fig. 3, wherein fig. 3 (a) is a top view facing the substrate in a direction opposite to the third direction Z, and fig. 3 (b) is a schematic cross-sectional view along a direction of a dashed line A-A 'in fig. 3 (a), and a cross-section along the direction of the dashed line A-A' is perpendicular to a top surface of the substrate 1.

Next, active regions 11 and isolation structures 12 are formed on the surface of the substrate 1, where the plurality of active regions 11 are distributed in an array, and the isolation structures 12 are located between adjacent active regions 11, as shown in fig. 4, where fig. 4 (a) is a top view facing the substrate in a direction opposite to the third direction Z, and fig. 4 (b) is a schematic cross-sectional view along a direction of a dashed line A-A 'in fig. 4 (a), and a cross-section along the direction of the dashed line A-A' is perpendicular to the top surface of the substrate 1. Specifically, shallow Trench Isolation (STI) is formed as an isolation structure 12 on the surface of the substrate 1 to divide a surface partial region of the substrate 1 into a plurality of active regions 11 arranged in an array. More specifically, the substrate 1 may be etched to form a shallow trench, where the shallow trench divides the surface of the substrate 1 into a plurality of active regions 11 arranged in an array, and then the shallow trench is filled with an isolation material to form an isolation structure 12. The first active region 11 may be doped with an N-type or P-type element before or after the isolation structure 12 is formed. In an exemplary embodiment of the present disclosure, as can be seen from fig. 4 (a), the top view of the active regions 11 is in a strip shape with rounded two ends, and the adjacent active regions 11 are arranged in a staggered manner. In other embodiments, the top view of the active regions 11 may be in a parallelogram shape, or a rectangular shape, and the adjacent active regions 11 may be arranged in a non-staggered manner.

In some embodiments, the surface of the substrate 1 may be etched using a photolithographic process to form shallow trenches. Specifically, a photoresist mask layer may be formed on the surface of the substrate 1, a pattern of the active region 11 is formed in the photoresist mask layer by exposure and development, and then dry etching is performed to etch the substrate 1 along the pattern to form a shallow trench. In some embodiments, before coating the photoresist mask layer, an anti-reflection layer and a hard mask layer (not shown) are further formed on the surface of the substrate 1, and are removed after forming the shallow trenches.

In some embodiments, the material of isolation structure 12 may be at least one of, or any combination of, silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride. In an exemplary embodiment of the present disclosure, the isolation structure 12 is made of silicon oxide. In some embodiments, the deposition method of the isolation material in the isolation structures 12 may employ at least one of a deposition method selected from a group consisting of Chemical Vapor Deposition (CVD), low Pressure Chemical Vapor Deposition (LPCVD), plasma Enhanced Chemical Vapor Deposition (PECVD), ultra High Vacuum Chemical Vapor Deposition (UHVCVD), flowable Chemical Vapor Deposition (FCVD), direct Liquid Injection Chemical Vapor Deposition (DLICVD), rapid Thermal Chemical Vapor Deposition (RTCVD), microwave plasma assisted chemical vapor deposition (MPCVD), metal Organic Chemical Vapor Deposition (MOCVD), atomic Layer Deposition (ALD), spin-on dielectric layer (SOD), and thermal oxidation growth.

In some embodiments, the active region 11 may have a doping of an N-type or P-type element therein, specifically, the N-type element includes a group V element such as phosphorus, arsenic, antimony, or bismuth, and the P-type element includes a group III element such as boron, aluminum, gallium, or indium. In some embodiments, the doping method in the active region 11 may include ion implantation.

Then, referring to FIG. 5, wherein FIG. 5 (a) is a top view of the substrate in the opposite direction of the third direction Z, FIG. 5 (b) is a schematic cross-sectional view in the direction of the dotted line A-A 'in FIG. 5 (a), the cross-section in the direction of the dotted line A-A' is perpendicular to the top surface of the substrate 1, a word line trench 100 extending from the top surface of the substrate 1 toward the inside of the substrate 1 is formed on the surface of the substrate 1, and the word line trench 100 also extends in the first direction X, the first direction X is parallel to the plane of the top surface of the substrate 1, a word line structure 10 is formed in the word line trench 100, comprising forming a gate dielectric layer 101, a gate conductive layer 102 and an insulating cap layer 103 in the word line trench 100, the gate dielectric layer 101 covering the bottom and at least a portion of the side wall of the word line trench 100, the insulating cap layer 103 covering the surface of the gate dielectric layer 101 on the bottom of the word line trench 100 and a portion of the side wall area in contact with the bottom, the gate conductive layer 102 is on the top surface of the gate conductive layer 102, the gate conductive layer 102 further comprises a metal material layer 1022, a semiconductor material layer 10 is formed in parallel to the plane of the top surface of the substrate 1, and an air gap material 104 is further comprises a metal material layer 1021, and an air conductive layer 104 is further formed in the air gap material 104, and occupies the air gap material 104.

In some embodiments, the substrate 1 surface may be etched using a photolithographic process to form the wordline trenches 100. Specifically, a photoresist mask layer may be formed on the surface of the substrate 1, a pattern of the word line structure 10 is formed in the photoresist mask layer by exposure and development, and then dry etching is performed, and the substrate 1 (including the active region 11 and the isolation structure 12) is etched along the pattern to form the word line trench 100, and the depth of the word line trench 100 is smaller than that of the isolation structure 12. . In some embodiments, before coating the photoresist mask layer, an anti-reflection layer and a hard mask layer (not shown) are further formed on the surface of the substrate 1, and are removed after forming the word line trenches 100.

In some embodiments, the material of the gate dielectric layer 101 may be at least one or a combination of silicon oxide (SiO 2), aluminum oxide (Al ₂O₃), zirconium oxide (ZrO ₂), hafnium oxide (HfO ₂), titanium oxide (TiO ₂), tantalum oxide (Ta ₂O₅), barium Strontium Titanate (BST), strontium Titanate (STO), lead titanate (PZT). In an exemplary embodiment of the present disclosure, silicon oxide is used as the material of the gate dielectric layer 101. In some embodiments, the material of the gate conductive layer 102 may be at least one or a combination of more of doped polysilicon, titanium nitride (TiN), silicon-doped titanium nitride (TiSiN), titanium (Ti), tungsten (W), tungsten nitride (WN), silicon-doped tungsten nitride (WSiN). In other embodiments, the material of the gate conductive layer 102 may also be at least one or more of molybdenum (Mo), ruthenium (Ru), tantalum (Ta), platinum (Pt), copper (Cu), and nitrides thereof. In an exemplary embodiment of the present disclosure, the material of the metal material conductive layer 1021 is titanium nitride, and the semiconductor material conductive layer 1022 is doped polysilicon. In some embodiments, the material of insulating cap layer 103 may be at least one of, or any combination of, silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride. In an exemplary embodiment of the present disclosure, the material of the insulating cap layer 103 is silicon nitride.

In some embodiments, the gate dielectric layer 101, the gate conductive layer 102, and the insulating cap layer 103 may be formed by at least one of a deposition method selected from a group consisting of Chemical Vapor Deposition (CVD), low Pressure Chemical Vapor Deposition (LPCVD), plasma Enhanced Chemical Vapor Deposition (PECVD), ultra High Vacuum Chemical Vapor Deposition (UHVCVD), flowable Chemical Vapor Deposition (FCVD), direct Liquid Injection Chemical Vapor Deposition (DLICVD), rapid Thermal Chemical Vapor Deposition (RTCVD), microwave plasma assisted chemical vapor deposition (MPCVD), metal Organic Chemical Vapor Deposition (MOCVD), atomic Layer Deposition (ALD), spin-on dielectric layer (SOD), in situ vapor growth (ISSG), and thermal oxidation growth. Note that, the gate dielectric layer 101 in the word line structure 10 may also be selectively formed only in the first active region 11.

In some embodiments, the N-type or P-type doping of the active region 11 is further included before forming the word line structure 10, and after forming the word line structure 10, the doped portions of the active region 11 located at two sides of the word line structure 10 serve as two source and drain electrodes, and the doped portions of the active region 11 located under the word line structure 10 serve as a channel region, and the gate conductive layer 102 in the word line structure 10 itself serves as a gate electrode to form a transistor structure. The gate conductive layer 102 serves as a gate of the transistor structure for providing a gate signal to control the turning on or off of the memory transistor structure. In an exemplary embodiment of the present disclosure, a single active region 11 is traversed by two adjacent word line structures 10 to form two transistor structures that share one of the source and drain electrodes.

In one exemplary embodiment of the present disclosure, as shown in fig. 6, fig. 6 (a) to 6 (h) are schematic views of specific steps of sequentially forming the word line structure 10, and are schematic cross-sectional views along any plane intersecting the word line structure 10. Comprising the following steps:

First, as shown in fig. 6 (a), a word line groove 100 extending from the top surface of the substrate 1 toward the inside of the substrate 1 is formed on the surface of the substrate 1, and the surface of the substrate 1 may be etched by a photolithography method. In some embodiments, the cross-sectional schematic view of the wordline trench 100 is rectangular, i.e. the opening size of the wordline trench 100 is substantially identical to the bottom size. In other embodiments, the cross-sectional schematic view of the word line trench 100 is trapezoidal, e.g., the opening size of the word line trench 100 is larger than the bottom size, or the bottom size of the word line trench 100 is larger than the opening size.

Next, as shown in fig. 6 (b), a gate dielectric layer 101 is formed on the bottom and at least part of the sidewalls of the word line trench 100, and may be formed by any method for forming the gate dielectric layer 101 in the foregoing embodiment. In some embodiments, the gate dielectric layer 101 covers the bottom and all sidewalls of the word line trench 100. While in some embodiments, the gate dielectric layer 101 covers the bottom and portions of the sidewalls in contact with the bottom of the word line trench 100.

Then, as shown in fig. 6 (c), a first sub-portion 1021a of the metal material conductive layer 1021 is formed in the word line trench 100, and the first sub-portion 1021a is located on the surface of the gate dielectric layer 101 and fills the bottom of the word line trench 100 and has a target height, and may be formed by any of the methods for forming the gate conductive layer 102 in the foregoing embodiments. In some embodiments, the first subsection 1021a of the target height may be formed by deposition followed by etching back. In other embodiments, the target height or thickness of the deposition may also be controlled by controlling the deposition time.

Next, referring to fig. 6 (d), an initial semiconductor material conductive layer 1022″ is formed in the word line trench 100, and the initial semiconductor material conductive layer 1022″ at least covers the top surface of the first sub-portion 1021a and the surface of the gate dielectric layer 101 remaining uncovered in the word line trench 100, and may be formed by any of the methods for forming the gate conductive layer 102 in the foregoing embodiments, wherein the thickness of the initial semiconductor material conductive layer 1022″ ranges from 2.5 nm to 4.5nm.

Next, referring to fig. 6 (e), the initial semiconductor material conductive layer 1022″ is etched back to obtain a temporary semiconductor material conductive layer 1022 'with a temporary height, so that the temporary semiconductor material conductive layer 1022' is only provided on the top surface of the first sub-portion 1021a in the vicinity of the sidewall in contact with the gate dielectric layer 101, and the region of the top surface of the first sub-portion 1021a far from the sidewall (near the middle) is exposed, and the etching back may be performed by a plasma dry etching, a gas phase chemical etching, or a wet chemical etching method. In some embodiments, the area of the top surface of the first subsection 1021a distal from the sidewall (near the middle) may be recessed due to over-etching.

Then, referring to fig. 6 (f), an initial second sub-portion 1021b ' of the metal material conductive layer 1021 is formed in the word line trench 100, the initial second sub-portion 1021b ' fills the space in the remaining word line trench 100 and covers the exposed surfaces of the first sub-portion 1021a, the temporary semiconductor material conductive layer 1022', and the gate dielectric layer 101, and may be formed using any of the forming methods of the gate conductive layer 102 in the previous embodiments.

Next, as shown in fig. 6 (g), the initial second sub-portion 1021b 'is etched back to obtain a second sub-portion 1021b of the target height, and the temporary semiconductor material conductive layer 1022' is etched back to obtain a semiconductor material conductive layer 1022 of the target height, and the etching back may be performed by a plasma dry etching method, a gas phase chemical etching method or a wet chemical etching method. In some embodiments, the ratio of the heights of the second sub-portion 1021b and the first sub-portion 1021a ranges from 1:2 to 1:1, and the ratio of the average thickness of the second sub-portion 1021b to the maximum thickness of the first sub-portion 1021a ranges from 1:3 to 2:3. In some embodiments, wet chemical etching may be used to reduce the thickness of sidewall gate dielectric layer 101, and finally the thickness of air gap 104 is greater than or equal to the thickness of semiconductor material conductive layer 1022.

Finally, referring to fig. 6 (h), an insulating cap layer 103 is formed in the word line trench 100, the insulating cap layer 103 covering the top surface of the second sub-portion 1021b of the metal material conductive layer 1021, while an air gap 104 is formed between the semiconductor material conductive layers 1022, the top surface of the insulating cap layer 103 being flush with the top surface of the substrate 1. In some embodiments, the air gap 104 is located on top of the semiconductor material conductive layer 1022 and is in direct contact with the top of the semiconductor material conductive layer 1022, the ratio of the height of the air gap 104 to the height of the semiconductor material conductive layer 1022 is 1:3, and the sum of the height of the air gap 104 and the height of the semiconductor material conductive layer 1033 ranges from 30 to 45nm. In some embodiments, the thickness of the air gap 104 is greater than or equal to the thickness of the conductive layer 1022 of semiconductor material. It should be noted that, the height direction is perpendicular to the surface of the substrate 1, and the thickness direction is parallel to the plane of the top surface of the substrate 1 and perpendicular to the first direction X.

In a second exemplary embodiment of the present disclosure, as shown in fig. 7, fig. 7 (a) to 7 (h) are schematic views of specific steps of sequentially forming the word line structure 10, and are schematic cross-sectional views along any plane intersecting the word line structure 10. Comprising the following steps:

First, the steps shown in fig. 7 (a) and 7 (b) are substantially identical to the steps 6 (a) and 6 (b) in the foregoing embodiment, and a repetitive description thereof will not be made herein.

Next, as shown in fig. 7 (c), a first sub-portion 1021a of a metal material conductive layer 1021 and an initial semiconductor material conductive layer 1022 "are formed in the word line trench 100, the first sub-portion 1021a is located on the surface of the gate dielectric layer 101 and fills the bottom of the word line trench 100 and has a target height, and the initial semiconductor material conductive layer 1022" is located on the top surface of the first sub-portion 1021a and fills the middle of the word line trench 100 and has an initial height, which may be formed by any of the forming methods of the gate conductive layer 102 in the foregoing embodiments. In some embodiments, the first sub-portion 1021a of the target height and the initial conductive layer 1022 of semiconductor material may be formed by deposition followed by etching back. In other embodiments, the target height or thickness of the deposition may also be controlled by controlling the deposition time.

Next, referring to fig. 7 (d), an initial first mask layer 105' is formed in the word line trench 100, wherein the initial first mask layer 105' at least covers the top surface of the initial semiconductor material conductive layer 1022″ and the remaining surface of the gate dielectric layer 101 in the word line trench 100, and the thickness of the initial first mask layer 105' ranges from 2.5 nm to 4.5nm. In some embodiments, the material of the initial first mask layer 105' may be at least one of, or any combination of, amorphous carbon (amorphous carbon), polysilicon, silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride. In an exemplary embodiment of the present disclosure, amorphous carbon is used as the material of the initial first mask layer 105'. In some embodiments, the initial first mask layer 105' may be formed by at least one of a deposition method including Chemical Vapor Deposition (CVD), low Pressure Chemical Vapor Deposition (LPCVD), plasma Enhanced Chemical Vapor Deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), flowable Chemical Vapor Deposition (FCVD), direct Liquid Injection Chemical Vapor Deposition (DLICVD), rapid Thermal Chemical Vapor Deposition (RTCVD), microwave plasma assisted chemical vapor deposition (MPCVD), metal Organic Chemical Vapor Deposition (MOCVD), atomic Layer Deposition (ALD), spin-on dielectric layer (SOD), in situ vapor growth (ISSG), thermal oxidation growth.

Then, as shown in fig. 7 (e), the initial first mask layer 105' is used as a mask to perform self-aligned etching on the initial conductive layer 1022 "of semiconductor material, so as to obtain a temporary conductive layer 1022' of semiconductor material, and the top surface of the first sub-portion 1021a only has the temporary conductive layer 1022' of semiconductor material in the vicinity of the sidewall in contact with the gate dielectric layer 101, and the region of the top surface of the first sub-portion 1021a far from the sidewall (near the middle) is exposed, which may be performed by using a plasma dry etching, a gas phase chemical etching or a wet chemical etching method. In some embodiments, the area of the top surface of the first subsection 1021a distal from the sidewall (near the middle) may be recessed due to over-etching. In some embodiments, the initial first mask layer 105 'is not completely etched and is left as the first mask layer 105 is on top of the temporary semiconductor material conductive layer 1022' and covers a portion of the surface of the gate dielectric layer 101. While in other embodiments the initial first mask layer 105' is completely consumed.

Immediately before the step shown in fig. 7 (f) is performed, the first mask layer 105 is removed, and the subsequent steps shown in fig. 7 (f) to 7 (h) are substantially identical to those shown in fig. 6 (f) to 6 (h) in the previous embodiment, and will not be repeated here.

In a third exemplary embodiment of the present disclosure, as shown in fig. 8, fig. 8 (a) to 8 (j) are schematic views of specific steps of sequentially forming the word line structure 10, and are schematic cross-sectional views along any plane intersecting the word line structure 10. Comprising the following steps:

First, the steps shown in fig. 8 (a) and 8 (b) are substantially identical to the steps 6 (a) and 6 (b) in the foregoing embodiment, and a repetitive description thereof will not be made herein.

Next, as shown in fig. 8 (c), an initial metal material conductive layer 1021 'is formed in the word line trench 100, and the initial metal material conductive layer 1021' is located on the surface of the gate dielectric layer 101 and fills the bottom of the word line trench 100 to have a target height, and may be formed by any of the methods for forming the gate conductive layer 102 in the foregoing embodiments. In some embodiments, the initial metallic material conductive layer 1021' of the target height may be formed by deposition followed by etching back. In other embodiments, the target height or thickness of the deposition may also be controlled by controlling the deposition time.

Then, referring to fig. 8 (d), an initial first mask layer 105 'is formed in the word line trench 100, the initial first mask layer 105' at least covers the top surface of the initial metal material conductive layer 1021 'and the remaining surface of the gate dielectric layer 101 that is not covered in the word line trench 100, and the thickness of the initial first mask layer 105' ranges from 2.5 nm to 4.5nm. The steps of forming the initial first mask layer 105' in fig. 8 (d) are substantially identical to those of fig. 7 (d) in the previous embodiment, and are not repeated here.

Next, referring to fig. 8 (e), self-aligned etching is performed using the initial first mask layer 105' as a mask, so as to obtain the first mask layer 105, and the initial metal material conductive layer 1021' has the first mask layer 105 only in the vicinity of the sidewall in contact with the gate dielectric layer 101 on the top surface, and the region far from the sidewall (near the middle) on the top surface of the initial metal material conductive layer 1021' is exposed, and the self-aligned etching may be performed by using a plasma dry etching, a gas phase chemical etching or a wet chemical etching method.

Then, as shown in fig. 8 (f), an initial second mask layer 106' is formed in the word line trench 100, the initial second mask layer 106' fills the space in the remaining word line trench 100 and covers the exposed surfaces of the initial metal material conductive layer 1021', the first mask layer 105, and the gate dielectric layer 101. In some embodiments, the material and forming method of the initial second mask layer 106 'may be the same as that of the initial first mask layer 105' in the previous embodiments, but the material of the initial second mask layer 106 'and the material of the initial first mask layer 105' need to be selected to be different to ensure that the subsequent etching has different etching selectivity ratios, in an exemplary embodiment of the present disclosure, amorphous carbon is used as the material of the initial first mask layer 105', and silicon nitride is used as the material of the initial second mask layer 106'.

Next, referring to fig. 8 (g), the self-aligned etching is performed using the initial second mask layer 106' and the first mask layer 105 as masks, and the etching rate of the first mask layer 105 is higher than that of the initial second mask layer 106', so that the sidewall portion of the initial metal material conductive layer 1021' near the top is etched away to form a gap, and the remaining initial second mask layer 106' as the second mask layer 106 protects the top of the initial metal material conductive layer 1021' from being etched, thereby obtaining the metal material conductive layer 1021, and the self-aligned etching may be performed by using a plasma dry etching, a gas phase chemical etching or a wet chemical etching method. The conductive layer 1021 of a metal material includes a first sub-portion 1021a and a second sub-portion 1021b located on top of the first sub-portion 1021a, with respect to the first sub-portion.

Next, as shown in fig. 8 (h), the second mask layer 106 on top of the conductive layer 1021 of the metal material is removed by selective dry etching, reactive ion etching, gas phase chemical etching or wet chemical etching.

Then, referring to fig. 8 (i), a semiconductor material conductive layer 1022 is formed in the gap formed in the foregoing step 8 (g), and the semiconductor material conductive layer 1022 has a target height, which may be formed by any of the methods for forming the gate conductive layer 102 in the foregoing embodiments. In some embodiments, the conductive layer 1022 of semiconductor material may be formed by deposition followed by etching back to a target height. In other embodiments, the target height or thickness of the deposition may also be controlled by controlling the deposition time. In some embodiments, wet chemical etching may be used to reduce the thickness of sidewall gate dielectric layer 101, and finally the thickness of air gap 104 is greater than or equal to the thickness of semiconductor material conductive layer 1022.

Finally, as shown in fig. 8 (j), an insulating cap layer 103 is formed in the word line trench 100, the insulating cap layer 103 covering the top surface of the second sub-portion 1021b of the metal material conductive layer 1021 while forming an air gap 104 with the semiconductor material conductive layer 1022, the top surface of the insulating cap layer 103 being flush with the top surface of the substrate 1. The description of forming the insulating cap layer 103 and the air gap 104 is substantially identical to that in the step shown in fig. 6 (h) in the foregoing embodiment, and a repeated description is not given here. The metal material conductive layer 1021 includes a first sub-portion 1021a and a second sub-portion 1021b located on the top surface of the first sub-portion 1021a, which is distinguished by a broken line as a boundary line (plane) in fig. 8 (j), and descriptions about the first sub-portion 1021a and the second sub-portion 1021b and their relationship with the semiconductor material conductive layer 1022 and the air gap 104 are also substantially identical to those in the foregoing embodiments, and are not repeated here.

In an exemplary embodiment of the present disclosure, a memory structure is further provided, as shown in fig. 9, including a memory cell array region and a peripheral device region with a dashed line C-C' as a boundary line/plane, where the memory cell array region includes, in addition to the substrate 1, the word line structure 10, the active region 11, and the isolation structure 12 in the above embodiment, a bit line structure 14 (including the first bit line conductive layer 141, the second bit line conductive layer 142, and the bit line insulating layer 143) formed later and connected to one source and drain electrode in the active region 11, a capacitor contact structure 15 (including the contact plug 151 and the landing pad 152) and connected to another source and drain electrode in the active region 11, a capacitor structure 17 (including the first electrode layer 171, the capacitor dielectric layer 172, and the second electrode layer 172) and connected to the capacitor contact structure 15, a supporting layer 161/162 for supporting the capacitor structure 17, a peripheral region including the peripheral active region 21, the peripheral isolation structure 22, and the peripheral device 23, and further including some interconnection structures such as the contact plug 19/241/243, the interconnection plug 151, the interconnection line 151, the interconnection layer 18, the interlayer dielectric layer 252, and the like.

It should be noted that the semiconductor structure or the memory structure in the embodiments of the present disclosure may be used to fabricate a DRAM device, and may also be used to fabricate other devices that need to form a capacitor structure or a conductive plate in different areas, which is not limited herein.

The various semiconductor structures shown in this embodiment mode can be used for an electronic device having a memory function. The electronic device may be a terminal device, such as a mobile phone, tablet computer, smart bracelet, or may be a personal computer (personal computer, PC), server, workstation, etc. The memory function in the electronic device may be implemented by a Dynamic Random Access Memory (DRAM), a Ferroelectric Random Access Memory (FRAM), a Phase Change Memory (PCM), a Magnetic Random Access Memory (MRAM), or a Resistive Random Access Memory (RRAM).

The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it is intended to cover the scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A semiconductor structure, comprising:

the substrate is provided with a word line groove extending from the top surface of the substrate towards the inside of the substrate, and the word line groove also extends along a first direction, wherein the first direction is parallel to the plane of the top surface of the substrate;

A word line structure in the word line trench, the word line structure comprising a gate dielectric layer, a gate conductive layer and an insulating cap layer stacked in sequence, the gate dielectric layer covering the bottom and at least part of the sidewall of the word line trench, the gate conductive layer covering the surface of the gate dielectric layer on the bottom of the word line trench and part of the sidewall in contact with the bottom, the insulating cap layer being on the top surface of the gate conductive layer;

The gate conductive layer further comprises a metal material conductive layer and a semiconductor material conductive layer, and the word line structure further comprises an air gap, wherein the semiconductor material conductive layer and the air gap are embedded in and occupy part of the side wall of the metal material conductive layer.

2. The semiconductor structure of claim 1, wherein the air gap is located on top of and in direct contact with the top of the conductive layer of semiconductor material.

3. The semiconductor structure of claim 1, wherein a ratio of a height of the air gap to a height of the conductive layer of semiconductor material is 1:3, the height direction being a direction perpendicular to the substrate surface.

4. The semiconductor structure of claim 3, wherein a sum of a height of the air gap and a height of the conductive layer of semiconductor material ranges from 30 nm to 45nm.

5. The semiconductor structure of claim 1, wherein the air gap has a thickness greater than or equal to a thickness of the conductive layer of semiconductor material, the thickness ranging from 2.5 nm to 4.5nm, the thickness direction being parallel to a plane of the top surface of the substrate and perpendicular to the first direction.

6. The semiconductor structure of claim 1, wherein in the same word line trench, the number of the air gaps and the semiconductor material conductive layers is two, and the air gaps and the semiconductor material conductive layers are respectively located on two opposite side walls of the metal material conductive layer, and are mirror symmetry disposed about a central axis of the metal material conductive layer, the central axis being perpendicular to the top surface of the substrate and extending along the first direction.

7. The semiconductor structure of claim 1, wherein a portion of the sidewall of the conductive layer of metallic material embedded and occupied by the conductive layer of semiconductor material and the air gap is located in a region proximate to a top of the conductive layer of metallic material.

8. The semiconductor structure of claim 1, wherein the conductive layer of metal material comprises a first sub-portion and a second sub-portion, the second sub-portion being located on top of the first sub-portion, the conductive layer of semiconductor material and the air gap being located on both sides of the second sub-portion;

the sum of the heights of the semiconductor material conducting layer and the air gap is smaller than or equal to the height of the second sub-part, the height direction is a direction perpendicular to the surface of the substrate, the average thickness of the second sub-part is smaller than the maximum thickness of the first sub-part, and the thickness direction is parallel to the plane of the top surface of the substrate and perpendicular to the first direction.

9. The semiconductor structure of claim 8, wherein a ratio of heights of the second sub-portion and the first sub-portion ranges from 1:2 to 1:1, and a ratio of an average thickness of the second sub-portion and a maximum thickness of the first sub-portion ranges from 1:3 to 2:3.

10. The semiconductor structure of claim 1, wherein the substrate further comprises an active region and an isolation structure, a plurality of the active regions being distributed in an array, the isolation structure being located between adjacent ones of the active regions, the word line structure passing through the plurality of active regions and the isolation structure.

11. A method of fabricating a semiconductor structure, comprising:

providing a substrate;

Forming word line grooves extending from the top surface of the substrate towards the inside of the substrate on the surface of the substrate, wherein the word line grooves also extend along a first direction, and the first direction is parallel to a plane where the top surface of the substrate is located;

Forming a word line structure in the word line groove, comprising forming a gate dielectric layer, a gate conductive layer and an insulating cover layer which are sequentially stacked in the word line groove, wherein the gate dielectric layer covers the bottom and at least part of the side wall of the word line groove, the gate conductive layer covers the surface of the gate dielectric layer on the bottom of the word line groove and part of the side wall area contacted with the bottom, and the insulating cover layer is formed on the top surface of the gate conductive layer;

12. The method of claim 11, wherein forming a gate dielectric layer, a gate conductive layer, and an insulating cap layer in the word line trench, sequentially comprises:

forming the grid dielectric layer at the bottom and at least part of the side wall of the word line groove;

forming the metal material conducting layer on the surface of the gate dielectric layer;

forming the semiconductor material conductive layer on a part of the side wall of the metal material conductive layer;

And forming the insulating cover layer on the top surface of the metal material conductive layer, wherein the air gap is formed between the insulating cover layer and the semiconductor material conductive layer, and is positioned on the top of the semiconductor material conductive layer and is in direct contact with the top of the semiconductor material conductive layer.

13. The method of claim 12, wherein forming the metal conductive layer on the surface of the gate dielectric layer and forming the semiconductor conductive layer on a portion of the sidewall of the metal conductive layer comprises:

Forming a first sub-part of the metal material conducting layer on the surface of the gate dielectric layer;

forming a second sub-portion of the semiconductor material conductive layer and the metal material conductive layer on top of the first sub-portion, the semiconductor material conductive layer and the air gap being located on both sides of the second sub-portion;

The sum of the heights of the semiconductor material conductive layer and the air gap is smaller than or equal to the height of the second sub-part, the height direction is a direction perpendicular to the surface of the substrate, the thickness of the air gap is larger than or equal to the thickness of the semiconductor material conductive layer, the average thickness of the second sub-part is smaller than the maximum thickness of the first sub-part, and the thickness direction is parallel to the plane of the top surface of the substrate and perpendicular to the first direction.

14. The method of claim 12, wherein forming the metal conductive layer on the surface of the gate dielectric layer and forming the semiconductor conductive layer on a portion of the sidewall of the metal conductive layer comprises:

Forming an initial metal material conducting layer on the surface of the gate dielectric layer;

etching a portion of a sidewall of the initial metallic material conductive layer to form the metallic material conductive layer including a first sub-portion and a second sub-portion, the second sub-portion being located on top of the first sub-portion;

Forming a conductive layer of the semiconductor material on a sidewall of the second sub-portion;

15. The method of fabricating a semiconductor structure according to any one of claims 11-14, further comprising, prior to forming the wordline trench:

Forming active areas and isolation structures on the surface of the substrate, wherein a plurality of the active areas are distributed in an array, and the isolation structures are positioned between adjacent active areas;

After forming the word line trench, the word line trench passes through a plurality of the active regions and the isolation structure.