CN119514458A - Method and device for adjusting signal line impedance in integrated circuit layout - Google Patents
Method and device for adjusting signal line impedance in integrated circuit layout Download PDFInfo
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
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- G06F30/30—Circuit design
- G06F30/36—Circuit design at the analogue level
- G06F30/373—Design optimisation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/36—Circuit design at the analogue level
- G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
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- G—PHYSICS
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- G06F2115/00—Details relating to the type of the circuit
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Abstract
本发明公开了一种集成电路版图中信号线阻抗的调整方法，针对现有的信号线阻抗通过手动测量长度和宽度计算粗略误差大的问题，初步完成集成电路版图后，根据信号线在电路图中的名称，生成信号线的GDSII文件；从GDSII文件中获取信号线中所有金属线及通孔的坐标信息，结合各层金属线和通孔的单位阻抗，计算信号线的总阻抗值；比较信号线的总阻抗值与预设的最大阻抗值的大小，若总阻抗值未超出最大阻抗值，则集成电路版图符合要求；若总阻抗值大于最大阻抗值，则修改集成电路版图，重新计算信号线阻抗。从而提高信号线的阻抗计算的准确性，进而提高集成电路版图设计的工作效率。
The present invention discloses a method for adjusting the impedance of a signal line in an integrated circuit layout. Aiming at the problem that the impedance of an existing signal line is roughly calculated by manually measuring the length and width and has a large error, after the integrated circuit layout is initially completed, a GDSII file of the signal line is generated according to the name of the signal line in the circuit diagram; the coordinate information of all metal lines and through holes in the signal line is obtained from the GDSII file, and the total impedance value of the signal line is calculated in combination with the unit impedance of each layer of metal lines and through holes; the total impedance value of the signal line is compared with the preset maximum impedance value, and if the total impedance value does not exceed the maximum impedance value, the integrated circuit layout meets the requirements; if the total impedance value is greater than the maximum impedance value, the integrated circuit layout is modified and the signal line impedance is recalculated. Thus, the accuracy of the impedance calculation of the signal line is improved, and the work efficiency of the integrated circuit layout design is further improved.
Description
Technical Field
The invention belongs to the technical field of chip design, and particularly relates to a method and a device for adjusting signal line impedance in an integrated circuit layout.
Background
In the chip design process, the problem of overlarge signal impedance value exists, and the problems have no influence in the design and production, but in the chip use process, the overlarge signal impedance value can lead to signal attenuation, thereby reducing the quality of signal transmission and influencing the stability of a circuit system and the performance of the whole chip. Therefore, in order to ensure the normal function of the chip during the chip design process, the circuit engineer may put impedance requirements on some signals, especially important analog signals.
In the prior art, after the integrated circuit layout is completed, impedance extraction and analysis can be performed on signals at a module level and a chiplet level through simulation software after the integrated circuit layout is completed. However, as the area of the chip becomes larger and the integration level becomes higher, the post-integrated circuit simulation software is unable to simulate and analyze the signal line at the chip level, and can only manually measure the length and width of the signal line and perform rough calculation according to the unit impedance of the metal line, where the impedance calculation formula of the metal line is r=rs (L/W), where L is the length of the metal line, W is the width of the metal line, and Rs is the unit impedance of the metal line.
Drawbacks of manual measurement and calculation:
The manual measurement itself may create various uncertainties;
with the increase of chip area, the increase of metal layers and the complexity and diversification of wiring, the manual measurement difficulty is greater and greater, and the error generated by the manual measurement is also greater and greater.
Disclosure of Invention
The invention aims to provide a method for adjusting the impedance of a signal wire in an integrated circuit layout, which can intuitively and accurately check the impedance value of the whole signal wire.
In order to solve the problems, the technical scheme of the invention is as follows:
a method for adjusting the impedance of a signal line in an integrated circuit layout comprises the following steps:
after the integrated circuit layout is initially completed, generating a GDSII file of the signal line according to the name of the signal line in the circuit diagram;
Acquiring coordinate information of all metal wires and through holes in a signal wire from a GDSII file, determining the serial-parallel connection relation of all metal wires and the length and width of the metal wires according to the coordinate information of the metal wires;
comparing the total impedance value of the signal line with a preset maximum impedance value, if the total impedance value does not exceed the maximum impedance value, the integrated circuit layout meets the requirements, and if the total impedance value is greater than the maximum impedance value, the integrated circuit layout is modified, and the impedance of the signal line is recalculated.
According to an embodiment of the present invention, the impedance value of the metal line is calculated according to the formula r=rs (L/W), where L is the length of the metal line, W is the width of the metal line, and Rs is the unit impedance of the metal line.
According to an embodiment of the present invention, determining the serial-parallel relationship of all the metal lines according to the coordinate information of the metal lines, and the length and width of the metal lines further includes:
Dividing the metal wire into a plurality of line segments with preset distances through SKILL or TCL languages, and obtaining the LENGTH and the WIDTH of each line segment through LENGTH and WIDTH;
Judging whether the two line segments are connected in parallel by a common starting point and a common ending point, if so, connecting the two line segments in parallel;
Judging whether the two line segments are connected end to end, if so, connecting the two line segments in series.
According to one embodiment of the invention, the impedance of the series line segment is calculated by the following formula:
R=Rs1*(L1/W1)+Rs2*(L2/W2)+Rs3*(L3/W3)+...+Rsn*(Ln/Wn)
The lengths of the n line segments are L1, L2 and L3..ln, the widths are W1, W2 and W3...wn, and the unit impedances of the metal lines of the n line segments are Rs1, rs2, rs3 and.. Rsn.
According to an embodiment of the present invention, the impedance of the parallel line segments is calculated by the following formula:
R = (R1*R2*R3*...*Rn) / (R1+R2+R3+...+Rn)
wherein r1=r1 (L1/W1)
R2=Rs2*(L2/W2)
Rn=Rsn*(Ln/Wn)
The lengths of the n line segments are L1, L2, and L3..ln, the widths are W1, W2, W3...wn, and the unit impedances of the metal lines of the n line segments are Rs1, rs2, rs3, rsn.
According to an embodiment of the present invention, the predetermined distance does not exceed a minimum grid point of the integrated circuit layout design software, so as to ensure that the metal line is divided into integer parts.
According to an embodiment of the invention, when modifying an integrated circuit layout, R=Rs (L/W) is calculated according to a metal line impedance calculation formula, wherein Rs is the unit impedance of the metal line, L is the length of the metal line, and W is the width of the metal line, the unit impedance Rs of the metal line is reduced, the length L of the metal line is reduced, or the width W of the metal line is increased.
According to an embodiment of the present invention, when the unit impedance of the metal line is reduced to reduce the total impedance value of the signal line, the metal line with the minimum unit impedance is selected, and the other metal lines are adjusted to be the metal lines with the minimum unit impedance.
According to the embodiment of the invention, when the width of the metal wire is increased to reduce the total impedance value of the signal wire, the metal layer is overlapped on the basis of the current metal wire under the condition that the metal wire is ensured to have no short circuit and the layout design rule is met.
An apparatus for adjusting signal line impedance in an integrated circuit layout, comprising:
The signal line extraction module is configured to generate a GDSII file of the signal line according to the name of the signal line in the circuit diagram after the integrated circuit layout is initially completed;
the impedance calculation module is configured to acquire coordinate information of all metal wires and through holes in the signal wire from the GDSII file, determine the serial-parallel connection relation of all metal wires, the length and the width of the metal wires and calculate the total impedance value of the signal wire by combining the unit impedance of each layer of metal wires according to the coordinate information of the metal wires;
The impedance correction module is configured to compare the total impedance value of the signal line with a preset maximum impedance value, if the total impedance value does not exceed the maximum impedance value, the integrated circuit layout meets the requirements, and if the total impedance value is greater than the maximum impedance value, the integrated circuit layout is modified, and the impedance of the signal line is recalculated.
According to an embodiment of the present invention, the impedance calculating module includes a data processing unit and a calculating unit;
The data processing unit is configured to divide a metal wire into a plurality of line segments with preset distances through SKILL or TCL language, and acquire the LENGTH and the WIDTH of each line segment through LENGTH and WIDTH;
The calculating unit calculates an impedance value of the metal wire according to a formula r=rs (L/W), wherein L is a length of the metal wire, W is a width of the metal wire, and Rs is a unit impedance of the metal wire.
By adopting the technical scheme, the invention has the following advantages and positive effects compared with the prior art:
The method for adjusting the impedance of the signal wire in the integrated circuit layout comprises the steps of generating a GDSII file of the signal wire according to the name of the signal wire in a circuit diagram after the integrated circuit layout is initially completed according to the problem that the rough error is calculated through manual measurement of the length and the width of the existing signal wire impedance, acquiring coordinate information of all metal wires and through holes in the signal wire from the GDSII file, calculating the total impedance value of the signal wire by combining unit impedance of each layer of metal wires and through holes, comparing the total impedance value of the signal wire with the preset maximum impedance value, if the total impedance value does not exceed the maximum impedance value, conforming the integrated circuit layout to requirements, and if the total impedance value is larger than the maximum impedance value, modifying the integrated circuit layout and recalculating the impedance of the signal wire. Thereby improving the accuracy of impedance calculation of the signal line and further improving the working efficiency of integrated circuit layout design.
Drawings
FIG. 1 is a flow chart of a method for adjusting signal line impedance in an integrated circuit layout according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a signal line according to an embodiment of the invention;
FIG. 3 is an equivalent schematic diagram of a signal line according to an embodiment of the present invention;
FIG. 4 is a schematic diagram illustrating a first modification of the signal lines according to an embodiment of the present invention;
FIG. 5 is a schematic diagram showing a second modification of the signal line according to an embodiment of the present invention;
FIG. 6 is a block diagram of an apparatus for adjusting signal line impedance in an integrated circuit layout according to an embodiment of the present invention.
Detailed Description
The invention provides a method and a device for adjusting the impedance of a signal line in an integrated circuit layout, which are further described in detail below with reference to the accompanying drawings and specific embodiments. Advantages and features of the invention will become more apparent from the following description and from the claims.
Referring to fig. 1, the present embodiment provides a method for adjusting the impedance of a signal line in an integrated circuit layout, which includes the following steps:
after the integrated circuit layout is initially completed, generating a GDSII file of the signal line according to the name of the signal line in the circuit diagram;
acquiring coordinate information of all metal wires and through holes in a signal wire from a GDSII file, and calculating the total impedance value of the signal wire by combining unit impedance of each layer of metal wires and through holes;
comparing the total impedance value of the signal line with a preset maximum impedance value, if the total impedance value does not exceed the maximum impedance value, the integrated circuit layout meets the requirements, and if the total impedance value is greater than the maximum impedance value, the integrated circuit layout is modified, and the impedance of the signal line is recalculated.
Specifically, in designing an integrated circuit layout, the layout design software virtuoso, ICC, encounter and the like can be used to realize that devices and signal lines are in one-to-one correspondence on a circuit diagram and the layout, so that corresponding metal lines and through holes can be found in the layout according to the names of the signal lines in the circuit diagram.
The GDSII files containing all metal wires and through holes in the signal wires are extracted, and the GDSII files corresponding to the layout can be extracted through the export function in virtuoso software. The GDSII file is a binary file containing coordinate information of all layers of corresponding graphics in the integrated circuit layout.
And acquiring the coordinate information of all the through holes and the coordinate information of all the metal wires in the whole GDSII file. In general, a through hole is required to connect two layers of metals on a circuit board, and if the same signal line is composed of different metal layers, filling the through hole is considered to not increase the impedance of the signal line additionally. Conversely, it is believed that the resistance of the metal line increases. Therefore, in calculating the impedance of the signal line, it is necessary to acquire coordinate information of all the through holes in addition to coordinate information of all the metal lines.
And determining the length and width of the metal wire according to the coordinate information of the metal wire, and determining the serial-parallel connection relation of the metal wire according to the coordinate information of the through hole. According to the unit impedance information of different metal wires in Foundry factory and the maximum impedance value A required by circuit engineers, calculating the impedance value of the signal wire by the formula R=Rs (L/W), and outputting the total impedance value B of all the metal wires. Wherein L is the length of the metal wire, W is the width of the metal wire, and Rs is the unit impedance of the metal wire. Comparing A with B, if A is larger than or equal to B, then designing signal line is not problematic, if A is smaller than B, then modifying layout is needed, and repeating the above operation after finishing layout modification until impedance of signal line meets requirement.
The method for adjusting the impedance of the signal line in the integrated circuit layout is described in an embodiment.
Referring to fig. 2, the signal lines in the drawing are composed of five layers of metal lines, the unit impedance of the first layer metal line (M1) is 0.18Ω, the unit impedance of the second to fourth layers of metal lines (M2 to M4) is 0.16Ω, and the unit impedance of the fifth layer metal line (M5) is 0.022 Ω. Circuit engineers require that the overall line impedance of the signal be less than 0.5 q.
Firstly, the impedance R1 of the second metal layer (M2) between the AB two points, the impedance R2 of the first metal layer (M1) between the BC two points, the impedance R3 of the third metal layer (M3) between the CD two points, the impedance R5 of the fifth metal layer (M5) R4 between the DE two points, the impedance R5 of the fourth metal layer (M4) between the EF two points, the impedance R6 of the second metal layer (M2) between the BF two points and the impedance R7 of the second metal layer (M2) between the FG need to be calculated.
According to the calculation formula of the series connection and the parallel connection of the metal wire impedance:
The lengths of the n line segments are L1, L2, L3..ln, the widths are W1, W2, W3...wn, respectively, and the unit impedances of the metal lines of the n line segments are Rs1, rs2, rs3,.. Rsn;
Series r=r1 (L1/W1) +r2 (L2/W2) +r3 (L3/W3) + Rsn (Ln/Wn)
Parallel connection r1=r1 (L1/W1)
R2=Rs2*(L2/W2)
Rn=Rsn*(Ln/Wn)
R = (R1*R2*R3*...*Rn) / (R1+R2+R3+...+Rn)
The connection impedance of the whole signal line can be obtained as follows:
R = R1+ R7+(R2+R3+R4+R5)* R6 /(R2+R3+R4+R5+R6)
From the above calculation formula, it can be seen that the manual measurement and calculation are difficult, and errors generated by the manual measurement and calculation are large.
In order to avoid the above problems, the present embodiment divides the metal wire into individual small metal wires according to the minimum GRID point (GRID) of the item by the language such as SKILL or TCL, so that it is ensured that the number of divided parts of the whole metal wire is an integer. The minimum GRID point (GRID) of this item is 0.1, so the signal wires are divided into wires with lengths of 0.1 μm, each of which is equivalent to a small resistance, and referring to fig. 3, fig. 3 is a simple illustration due to the number of divided wire segments.
And judging the series-parallel connection relation of the resistors according to a detection rule that the resistors are parallel with the starting point and the ending point and are connected end to end in series, and calculating the total resistance, namely the impedance R, according to a series-parallel connection formula. When the resistance values of the resistors are calculated, the LENGTH and the WIDTH of the resistors can be obtained through LENGTH and WIDTH functions.
According to the method, the total impedance R of the signal line is 1.2 omega and is larger than 0.5 omega which is required, so that the line design is not in line with the requirement, and the layout needs to be modified. By the calculation formula of the metal wire impedance, R=Rs (L/W), wherein Rs is the unit impedance of the metal wire, L is the length of the metal wire, and W is the width of the metal wire, three ideas can be seen for reducing the impedance:
1. the unit impedance Rs of the metal wire is reduced, and the metal wire can be replaced by a metal with small unit impedance under the condition of permitting;
2. reducing the length L of the metal wire;
3. The width W of the metal line is increased.
Which of these three methods is used specifically or a combination of the three methods is to be used according to the actual situation analysis of the project.
In this embodiment, the fifth layer metal (M5) is the highest layer metal and has the smallest unit impedance, and the metal line should be replaced with the fifth layer metal (M5) as much as possible, and other layer metal lines should be replaced with the fifth layer metal (M5) under the condition that the metal line is not shorted and the layout design rule is satisfied, please refer to fig. 4.
And calculating the impedance value R to be 0.6Ω through languages such as SKILL or TCL again, wherein the impedance value R is still larger than the required 0.5Ω, and the layout needs to be continuously modified. The third proposal is tried to overlap the metal layer on the basis of the original metal wire under the condition that the metal wire is ensured to have no short circuit and the layout design rule is satisfied.
Referring to fig. 5, a fourth metal layer is stacked on the fifth metal layer, and a third metal layer is stacked on the second metal layer. The impedance value R is calculated to be 0.43 omega by the languages such as SKILL or TCL, and the width of the metal wire is increased by the method, so that the layout design meets the impedance requirement.
By the method, the impedance value of the whole signal line can be visually and accurately checked, and the calculation accuracy and calculation efficiency of the impedance of the signal line are greatly improved.
Based on the same conception, the embodiment also provides a device for adjusting the impedance of the signal line in the integrated circuit layout, and the method for adjusting the impedance of the signal line in the integrated circuit layout is realized. Referring to fig. 6, the apparatus includes:
the signal line extraction module 1 is configured to generate a GDSII file of the signal line according to the name of the signal line in the circuit diagram after the integrated circuit layout is initially completed;
The impedance calculation module 2 is configured to acquire coordinate information of all metal wires and through holes in the signal wire from the GDSII file, determine the serial-parallel connection relation of all metal wires, the length and the width of the metal wires and calculate the total impedance value of the signal wire by combining the unit impedance of each layer of metal wires according to the coordinate information of the metal wires;
The impedance correction module 3 is configured to compare the total impedance value of the signal line with a preset maximum impedance value, if the total impedance value does not exceed the maximum impedance value, the integrated circuit layout meets the requirements, and if the total impedance value is greater than the maximum impedance value, the integrated circuit layout is modified, and the impedance of the signal line is recalculated.
The impedance calculation module 2 comprises a data processing unit and a calculation unit, wherein the data processing unit is configured to divide a metal wire into a plurality of line segments with preset distances through SKILL or TCL languages, acquire the LENGTH and the WIDTH of each line segment through LENGTH and WIDTH, judge whether the two line segments are connected in parallel or not by a common starting point and a common ending point if the two line segments are connected in parallel, and judge whether the two line segments are connected end to end if the two line segments are connected in series. The preset distance is not more than the minimum grid point of the integrated circuit layout design software so as to ensure that the metal wire is divided into integer parts.
The calculating unit calculates an impedance value of the metal line according to a formula r=rs (L/W), where L is a metal line length, W is a metal line width, and Rs is a unit impedance of the metal line. Specifically, the calculation unit calculates the impedance of the series line segment by the following formula:
R=Rs1*(L1/W1)+Rs2*(L2/W2)+Rs3*(L3/W3)+...+Rsn*(Ln/Wn)
The impedance of the parallel line segments is calculated by the following formula:
R = (R1*R2*R3*...*Rn) / (R1+R2+R3+...+Rn)
wherein r1=r1 (L1/W1)
R2=Rs2*(L2/W2)
Rn=Rsn*(Ln/Wn)
The lengths of the n line segments are L1, L2, and L3..ln, the widths are W1, W2, W3...wn, and the unit impedances of the metal lines of the n line segments are Rs1, rs2, rs3, rsn.
The device is used for realizing the method for adjusting the impedance of the signal line in the integrated circuit layout, and the implementation mode is similar and is not repeated here.
The embodiments of the present invention have been described in detail with reference to the drawings, but the present invention is not limited to the above embodiments. Even if various changes are made to the present invention, it is within the scope of the appended claims and their equivalents to fall within the scope of the invention.
Claims (10)
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| CN202411694640.7A CN119514458A (en) | 2024-11-25 | 2024-11-25 | Method and device for adjusting signal line impedance in integrated circuit layout |
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| CN202411694640.7A CN119514458A (en) | 2024-11-25 | 2024-11-25 | Method and device for adjusting signal line impedance in integrated circuit layout |
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