CN119512807A - Error correction method, memory storage device and memory control circuit unit - Google Patents
Error correction method, memory storage device and memory control circuit unit Download PDFInfo
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Abstract
The invention provides an error correction method, a memory storage device and a memory control circuit unit. The error correction method includes counting a first decoding rate of a first error correction procedure, wherein the first error correction procedure includes a plurality of decoding operations that are performed based on a first order, and switching the first error correction procedure to a second error correction procedure in response to the first decoding rate being less than a first threshold, wherein the second error correction procedure includes a plurality of decoding operations that are performed based on a second order, wherein a decoding capability of a first decoding operation indicated by the second order is superior to a decoding capability of a first decoding operation indicated by the first order.
Description
Technical Field
The present invention relates to memory management, and more particularly, to an error correction method, a memory storage device and a memory control circuit unit.
Background
Portable electronic devices such as mobile phones and notebook computers have grown very rapidly over the years, and consumer demand for storage media has also increased rapidly. Since a rewritable nonvolatile memory module (e.g., flash memory) has characteristics of nonvolatile data, power saving, small size, and no mechanical structure, it is very suitable for being built in the various portable electronic devices as exemplified above.
When the read data is not more positive, the memory storage device can execute the error correction process accordingly. In the conventional error correction process, the memory storage device performs the decoding operation with the shortest operation time, and if the decoding fails, sequentially performs the decoding operations with longer operation time and stronger decoding capability. When the number of error bits of the rewritable nonvolatile memory module is not high, the initial decoding operation with the shortest operation time can successfully decode most of the data. However, when the number of error bits of the rewritable nonvolatile memory module becomes high, most of the data is successfully decoded after a subsequent decoding operation with a high decoding capability. In this case, the conventional error correction procedure may result in a longer average decoding time, which may deteriorate the performance of the memory device.
Disclosure of Invention
The invention provides an error correction method, a memory storage device and a memory control circuit unit, which can select different error correction flows according to actual conditions so as to reduce time cost and improve the efficiency of the memory storage device.
An exemplary embodiment of the present invention provides an error correction method for a rewritable non-volatile memory module, the error correction method including counting a first decoding rate of a first error correction procedure, wherein the first error correction procedure includes a plurality of decoding operations performed based on a first order, and switching the first error correction procedure to a second error correction procedure in response to the first decoding rate being less than a first threshold, wherein the second error correction procedure includes a plurality of decoding operations performed based on a second order, wherein a decoding capability of a first decoding operation indicated by the second order is superior to a decoding capability of a first decoding operation indicated by the first order.
In an example embodiment of the present invention, the error correction method further includes counting a second decoding rate of the second error correction procedure, and switching the second error correction procedure to the first error correction procedure in response to the second decoding rate being not less than a second threshold.
In an example embodiment of the present invention, the first decoding rate is a success rate of the first decoding operation indicated by the first order.
In an example embodiment of the present invention, the second decoding rate is a success rate of each of the decoding operations in the second error correction procedure.
In an example embodiment of the present invention, the plurality of decoding operations included in the first error correction procedure is a first number, and the plurality of decoding operations included in the second error correction procedure is a second number, wherein the first number is greater than the second number.
In an exemplary embodiment of the invention, the error correction method further includes obtaining health status information of the rewritable nonvolatile memory module, and employing one of the first error correction procedure, the second error correction procedure and a third error correction procedure according to the health status information.
In an example embodiment of the present invention, the third error correction flow includes a plurality of decoding operations performed based on a third order, and a decoding capability of a first decoding operation indicated by the third order is superior to the decoding capability of the first decoding operation indicated by the second order.
The exemplary embodiments of the present invention further provide a memory storage device, which includes a connection interface unit, a rewritable nonvolatile memory module, and a memory control circuit unit. The connection interface unit is used for being coupled to a host system. The memory control circuit unit is coupled to the connection interface unit and the rewritable nonvolatile memory module. The memory control circuit unit is configured to count a first decoding rate of a first error correction procedure, wherein the first error correction procedure includes a plurality of decoding operations performed based on a first order. In response to the first decoding rate being less than a first threshold, the memory control circuit unit is further configured to switch the first error correction flow to a second error correction flow, wherein the second error correction flow includes a plurality of decoding operations performed based on a second order, wherein a decoding capability of a first decoding operation indicated by the second order is superior to a decoding capability of a first decoding operation indicated by the first order.
In an exemplary embodiment of the invention, the memory control circuit unit is further configured to count a second decoding rate of the second error correction procedure. In response to the second decoding rate not being less than a second threshold, the memory control circuit unit is further configured to switch the second error correction procedure to the first error correction procedure.
In an exemplary embodiment of the invention, the memory control circuit unit is further configured to obtain health status information of the rewritable nonvolatile memory module. The memory control circuit unit is further configured to employ one of the first error correction procedure, the second error correction procedure, and a third error correction procedure according to the health status information.
The exemplary embodiments of the present invention further provide a memory control circuit unit for controlling a rewritable nonvolatile memory module. The memory control circuit unit comprises a host interface, a memory interface and a memory management circuit. The host interface is configured to be coupled to a host system. The memory interface is configured to be coupled to the rewritable non-volatile memory module. The memory management circuit is coupled to the host interface and the memory interface. The memory management circuit is configured to count a first decoding rate of a first error correction procedure, wherein the first error correction procedure includes a plurality of decoding operations performed based on a first order. In response to the first decoding rate being less than a first threshold, the memory management circuit is further configured to switch the first error correction flow to a second error correction flow, wherein the second error correction flow includes a plurality of decoding operations performed based on a second order, wherein a decoding capability of a first decoding operation indicated by the second order is superior to a decoding capability of a first decoding operation indicated by the first order.
In an example embodiment of the present invention, the memory management circuit is further configured to count a second decoding rate of the second error correction procedure. In response to the second decoding rate not being less than a second threshold, the memory management circuit is further configured to switch the second error correction procedure to the first error correction procedure.
In an example embodiment of the present invention, the memory management circuit is further configured to obtain health status information of the rewritable nonvolatile memory module. The memory management circuit is further configured to employ one of the first error correction procedure, the second error correction procedure, and a third error correction procedure according to the health status information.
The exemplary embodiments of the present invention further provide a memory storage device, which includes a connection interface unit, a rewritable nonvolatile memory module, and a memory control circuit unit. The connection interface unit is used for being coupled to a host system. The memory control circuit unit is coupled to the connection interface unit and the rewritable nonvolatile memory module. The memory control circuit unit is used for executing a first error correction process or a second error correction process. The first error correction flow includes a plurality of decoding operations that are performed based on a first order, and the plurality of decoding operations included in the first error correction flow is a first number. The second error correction flow includes a plurality of decoding operations that are performed based on a second order, and the plurality of decoding operations included in the second error correction flow is a second number. At least one of the plurality of decoding operations included in the first error correction procedure is the same as at least one of the plurality of decoding operations included in the second error correction procedure. The decoding capability of the first decoding operation indicated by the second order is better than the decoding capability of the first decoding operation indicated by the first order, and the first number is greater than the second number.
In an example embodiment of the present invention, the memory control circuit unit is further configured to perform one of the first error correction procedure, the second error correction procedure, and a third error correction procedure, wherein the third error correction procedure includes a plurality of decoding operations performed based on a third order, and a decoding capability of a first decoding operation indicated by the third order is better than the decoding capability of the first decoding operation indicated by the second order.
In an example embodiment of the present invention, the at least one of the plurality of decoding operations included in the first error correction flow, the at least one of the plurality of decoding operations included in the second error correction flow, and the at least one of the plurality of decoding operations included in the third error correction flow are the same.
The exemplary embodiments of the present invention further provide a memory control circuit unit for controlling a rewritable nonvolatile memory module. The memory control circuit unit comprises a host interface, a memory interface and a memory management circuit. The host interface is configured to be coupled to a host system. The memory interface is configured to be coupled to the rewritable non-volatile memory module. The memory management circuit is coupled to the host interface and the memory interface. The memory management circuit is used for executing a first error correction process or a second error correction process. The first error correction flow includes a plurality of decoding operations that are performed based on a first order, and the plurality of decoding operations included in the first error correction flow is a first number. The second error correction flow includes a plurality of decoding operations that are performed based on a second order, and the plurality of decoding operations included in the second error correction flow is a second number. At least one of the plurality of decoding operations included in the first error correction procedure is the same as at least one of the plurality of decoding operations included in the second error correction procedure. The decoding capability of the first decoding operation indicated by the second order is better than the decoding capability of the first decoding operation indicated by the first order, and the first number is greater than the second number.
In an example embodiment of the present invention, the memory management circuit is further configured to perform one of the first error correction procedure, the second error correction procedure, and a third error correction procedure, wherein the third error correction procedure includes a plurality of decoding operations performed based on a third order, and a decoding capability of a first decoding operation indicated by the third order is better than the decoding capability of the first decoding operation indicated by the second order.
Based on the above, the error correction method, the memory storage device and the memory control circuit unit of the present invention can select a proper error correction process according to the decoding rate of the current error correction process or the health status information of the rewritable nonvolatile memory module, so as to reduce the decoding time and improve the performance of the memory storage device.
In order to make the above features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device, according to an example embodiment of the invention;
FIG. 2 is a schematic diagram of a host system, a memory storage device, and an I/O device according to an example embodiment of the invention;
FIG. 3 is a schematic diagram of a host system and a memory storage device according to an example embodiment of the invention;
FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention;
FIG. 5 is a schematic block diagram of a memory control circuit unit according to an example embodiment of the invention;
FIG. 6 is a schematic diagram illustrating managing a rewritable non-volatile memory module according to an example embodiment of the present invention;
FIG. 7 is a schematic diagram of a different type of error correction flow shown in accordance with an exemplary embodiment of the present invention;
FIG. 8 is a flowchart of an error correction method according to an exemplary embodiment of the present invention;
FIG. 9 is a flowchart of an error correction method according to an exemplary embodiment of the present invention;
FIG. 10 is a flowchart of an error correction method according to an exemplary embodiment of the present invention.
Detailed Description
Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.
Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable nonvolatile memory module (rewritable non-volatile memory module) and a controller (also referred to as a control circuit). The memory storage device may be used with a host system such that the host system may write data to or read data from the memory storage device.
FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the invention. FIG. 2 is a schematic diagram of a host system, a memory storage device, and an I/O device according to an example embodiment of the invention.
Referring to fig. 1 and 2, the host system 11 may include a processor 111, a random access memory (random access memory, RAM) 112, a Read Only Memory (ROM) 113, and a data transfer interface 114. The processor 111, the random access memory 112, the read only memory 113, and the data transfer interface 114 may be connected to a system bus 110.
In an example embodiment, host system 11 may be coupled to memory storage device 10 via data transfer interface 114. For example, host system 11 may store data to memory storage device 10 or read data from memory storage device 10 via data transfer interface 114. In addition, host system 11 may be connected to I/O device 12 via system bus 110. For example, host system 11 may transmit output signals to I/O device 12 or receive input signals from I/O device 12 via system bus 110.
In an exemplary embodiment, the processor 111, the ram 112, the rom 113, and the data transfer interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. The motherboard 20 may be connected to the memory storage device 10 via a wired or wireless connection via the data transmission interface 114.
In an exemplary embodiment, the memory storage device 10 may be, for example, a usb flash disk 201, a memory card 202, a Solid state disk (Solid STATE DRIVE, SSD) 203, or a wireless memory storage device 204. The wireless memory storage 204 may be, for example, a Near Field Communication (NFC) memory storage, a wireless facsimile (WiFi) memory storage, a Bluetooth (Bluetooth) memory storage, or a Bluetooth low energy memory storage (iBeacon) or the like based on a wide variety of wireless Communication technologies. In addition, the motherboard 20 may also be connected to various I/O devices such as a global positioning system (Global Positioning System, GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, a speaker 210, etc. through the system bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 through the wireless transmission device 207.
In an example embodiment, host system 11 is a computer system. In an example embodiment, host system 11 may be any system that may substantially cooperate with a memory storage device to store data. In an example embodiment, the memory storage device 10 and the host system 11 may include the memory storage device 30 and the host system 31 of fig. 3, respectively.
FIG. 3 is a schematic diagram of a host system and a memory storage device according to an example embodiment of the invention. Referring to fig. 3, the memory storage device 30 may be used with the host system 31 to store data. For example, the host system 31 may be a system such as a digital camera, video camera, communication device, audio player, video player, or tablet computer. For example, the memory storage device 30 may be a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded memory device 34 used by a host system 31. The embedded storage 34 includes embedded storage devices of various types such as embedded multimedia card (embedded Multi MEDIA CARD, EMMC) 341 and/or embedded Multi-chip package (embedded Multi CHIP PACKAGE, EMCP) 342 that directly connect the memory module to the substrate of the host system.
Fig. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention. Referring to fig. 4, the memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42, and a rewritable nonvolatile memory module 43.
The connection interface unit 41 is used for connecting to the host system 11. The memory storage device 10 may communicate with the host system 11 via the connection interface unit 41. In an exemplary embodiment, connection interface unit 41 is compatible with the high speed peripheral component interconnect (PERIPHERAL COMPONENT INTERCONNECT EXPRESS, PCI Express) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 41 may be a serial advanced technology attachment (SERIAL ADVANCED Technology Attachment, SATA) standard, a parallel advanced technology attachment (PARALLEL ADVANCED Technology Attachment, PATA) standard, an Institute of electrical and Electronics engineers (ELECTRICAL AND Electronic Engineers, IEEE) 1394 standard, a universal serial bus (Universal Serial Bus, USB) standard, an SD interface standard, a Ultra-high speed generation (Ultra HIGH SPEED-I, UHS-I) interface standard, a Ultra-high speed second generation (Ultra HIGH SPEED-II, UHS-II) interface standard, a Memory Stick (MS) interface standard, an MCP interface standard, an MMC interface standard, an eMMC interface standard, a universal flash Memory (Universal Flash Storage, UFS) interface standard, an eMCP interface standard, a CF interface standard, an integrated drive Electronics (INTEGRATED DEVICE Electronics, IDE) standard, or other suitable standard. The connection interface unit 41 may be packaged in one chip with the memory control circuit unit 42, or the connection interface unit 41 may be disposed outside a chip including the memory control circuit unit 42.
The memory control circuit unit 42 is connected to the connection interface unit 41 and the rewritable nonvolatile memory module 43. The memory control circuit unit 42 is used for executing a plurality of logic gates or control instructions implemented in hardware or firmware and performing operations of writing, reading and erasing data in the rewritable nonvolatile memory module 43 according to the instructions of the host system 11.
The rewritable nonvolatile memory module 43 is used for storing data written by the host system 11. The rewritable nonvolatile memory module 43 may include a single-level memory cell (SINGLE LEVEL CELL, SLC) NAND type flash memory module (i.e., a flash memory module that can store 1 bit in one memory cell), a second-level memory cell (Multi LEVEL CELL, MLC) NAND type flash memory module (i.e., a flash memory module that can store 2 bits in one memory cell), a third-level memory cell (TRIPLE LEVEL CELL, TLC) NAND type flash memory module (i.e., a flash memory module that can store 3 bits in one memory cell), a fourth-level memory cell (Quad LEVEL CELL, QLC) NAND type flash memory module (i.e., a flash memory module that can store 4 bits in one memory cell), other flash memory modules, or other memory modules having the same characteristics.
Each memory cell in the rewritable nonvolatile memory module 43 stores one or more bits with a change in voltage (hereinafter also referred to as a threshold voltage). Specifically, there is a charge trapping layer between the control gate (control gate) and the channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming" the memory cell. As the threshold voltage changes, each memory cell in the rewritable nonvolatile memory module 43 has a plurality of memory states. By applying a read voltage, it is possible to determine which memory state a memory cell belongs to, and thereby obtain one or more bits stored in the memory cell.
In an exemplary embodiment, the memory cells of the rewritable nonvolatile memory module 43 may constitute a plurality of physical program units, and the physical program units may constitute a plurality of physical erase units. Specifically, memory cells on the same word line may constitute one or more physical programming units. If each memory cell can store more than 2 bits, the physical programming units on the same word line can be categorized into at least a lower physical programming unit and an upper physical programming unit. For example, the least significant Bit (LEAST SIGNIFICANT Bit, LSB) of a memory cell is that belonging to the lower physical programming cell, and the most significant Bit (Most Significant Bit, MSB) of a memory cell is that belonging to the upper physical programming cell. In general, in MLC NAND-type flash memory, the writing speed of the lower physical programming unit is greater than the writing speed of the upper physical programming unit, and/or the reliability of the lower physical programming unit is higher than the reliability of the upper physical programming unit.
In an exemplary embodiment, the physical programming unit is a minimum unit of programming. That is, the physical programming unit is the smallest unit of write data. For example, the physical programming unit may be a physical page (page) or a physical sector (sector). If the physical programming units are physical pages, the physical programming units may include data bits and redundancy bits. The data bit area includes a plurality of physical sectors for storing user data, and the redundant bit area is used for storing system data (e.g., management data such as error correction codes). In an exemplary embodiment, the data bit area includes 32 physical sectors, and a physical sector has a size of 512 bytes (B). However, in other exemplary embodiments, 8, 16 or a greater or lesser number of physical fans may be included in the data bit zone, and the size of each physical fan may be greater or lesser. On the other hand, a physical erase unit is the minimum unit of erase. That is, each physically erased cell contains a minimum number of memory cells that are erased together. For example, the physical erased cells are physical blocks (blocks).
Fig. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention. Referring to fig. 5, the memory control circuit unit 42 includes a memory management circuit 51, a host interface 52 and a memory interface 53.
The memory management circuit 51 is used for controlling the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has a plurality of control commands, and when the memory storage device 10 is operated, the control commands are executed to perform operations such as writing, reading and erasing data. The operation of the memory management circuit 51 is explained as follows, which is equivalent to the explanation of the operation of the memory control circuit unit 42.
In an example embodiment, the control instructions of the memory management circuit 51 are implemented in firmware. For example, the memory management circuit 51 has a microprocessor unit (not shown) and a read-only memory (not shown), and the control instructions are burned into the read-only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading and erasing data.
In an exemplary embodiment, the control instructions of the memory management circuit 51 may also be stored in a program code format in a specific area of the rewritable nonvolatile memory module 43 (e.g., a system area dedicated to storing system data in the memory module). In addition, the memory management circuit 51 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the rom has a boot code (boot code), and when the memory control circuit unit 42 is enabled, the microprocessor unit executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 43 into the ram of the memory management circuit 51. Then, the microprocessor unit operates the control instructions to perform operations such as writing, reading and erasing of data.
In an exemplary embodiment, the control instructions of the memory management circuit 51 may also be implemented in a hardware type. For example, the memory management circuit 51 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, the memory write circuit, the memory read circuit, the memory erase circuit and the data processing circuit are connected to the microcontroller. The memory cell management circuit is used to manage the memory cells or groups of memory cells of the rewritable nonvolatile memory module 43. The memory write circuit is used for issuing a write instruction sequence to the rewritable nonvolatile memory module 43 to write data into the rewritable nonvolatile memory module 43. The memory read circuit is used for issuing a read instruction sequence to the rewritable nonvolatile memory module 43 to read data from the rewritable nonvolatile memory module 43. The memory erase circuit is used for issuing an erase command sequence to the rewritable nonvolatile memory module 43 to erase data from the rewritable nonvolatile memory module 43. The data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 43 and data read from the rewritable nonvolatile memory module 43. The write command sequence, the read command sequence, and the erase command sequence may each include one or more program codes or command codes and are used to instruct the rewritable nonvolatile memory module 43 to perform corresponding writing, reading, and erasing operations. In an example embodiment, the memory management circuit 51 may also issue other types of instruction sequences to the rewritable nonvolatile memory module 43 to instruct the corresponding operations to be performed.
The host interface 52 is connected to the memory management circuit 51. Memory management circuitry 51 may communicate with host system 11 through host interface 52. The host interface 52 may be used to obtain and identify instructions and data of the host system 11. For example, instructions and data of host system 11 may be transferred to memory management circuitry 51 through host interface 52. In addition, the memory management circuitry 51 may communicate data to the host system 11 through the host interface 52. In the present example embodiment, host interface 52 is compatible with the PCI Express standard. However, it should be understood that the present invention is not limited thereto, and the host interface 52 may also be compatible with SATA standards, PATA standards, IEEE 1394 standards, USB standards, SD standards, UHS-I standards, UHS-II standards, MS standards, MMC standards, eMMC standards, UFS standards, CF standards, IDE standards, or other suitable data transfer standards.
The memory interface 53 is connected to the memory management circuit 51 and is used to access the rewritable nonvolatile memory module 43. For example, the memory management circuit 51 may access the rewritable nonvolatile memory module 43 through the memory interface 53. That is, the data to be written into the rewritable nonvolatile memory module 43 is converted into a format acceptable to the rewritable nonvolatile memory module 43 through the memory interface 53. Specifically, if the memory management circuit 51 is to access the rewritable nonvolatile memory module 43, the memory interface 53 transmits the corresponding instruction sequence. For example, the instruction sequences may include a write instruction sequence that indicates write data, a read instruction sequence that indicates read data, an erase instruction sequence that indicates erase data, and corresponding instruction sequences to indicate various memory operations (e.g., changing read voltage levels or performing garbage collection (Garbage Collection, GC) operations, etc.). These sequences of instructions are, for example, generated by the memory management circuit 51 and transferred to the rewritable non-volatile memory module 43 via the memory interface 53. These instruction sequences may include one or more signals, or data, on a bus. Such signals or data may include instruction code or program code. For example, the read instruction sequence may include information such as a read identification code and a memory address.
In an exemplary embodiment, the memory control circuit unit 42 further includes an error checking and correction circuit 54, a buffer memory 55, and a power management circuit 56.
The error checking and correcting circuit 54 is connected to the memory management circuit 51 and is used for performing error checking and correcting operations to ensure the correctness of the data. Specifically, when the memory management circuit 51 obtains the write command from the host system 11, the error checking and correcting circuit 54 generates a corresponding error correction code (error correcting code, ECC) and/or error check code (error detecting code, EDC) for the data corresponding to the write command, and the memory management circuit 51 writes the data corresponding to the write command and the corresponding error correction code and/or error check code into the rewritable nonvolatile memory module 43. Then, when the memory management circuit 51 reads data from the rewritable nonvolatile memory module 43, the error correction code and/or the error check code corresponding to the data are read at the same time, and the error check and correction circuit 54 performs an error check and correction operation on the read data according to the error correction code and/or the error check code.
The buffer memory 55 is connected to the memory management circuit 51 and is used for buffering data. The power management circuit 56 is connected to the memory management circuit 51 and is used to control the power of the memory storage device 10.
In an example embodiment, the rewritable non-volatile memory module 43 of fig. 4 may include a flash memory module. In an example embodiment, the memory control circuit unit 42 of fig. 4 may include a flash memory controller. In an example embodiment, the memory management circuit 51 of fig. 5 may include a flash memory management circuit.
FIG. 6 is a schematic diagram illustrating managing a rewritable non-volatile memory module according to an example embodiment of the present invention. Referring to FIG. 6, the memory management circuit 51 can logically group the physical units 610 (0) -610 (B) in the rewritable nonvolatile memory module 43 into a memory area 601 and a spare (spare) area 602.
In an exemplary embodiment, a physical unit refers to a physical address or a physical programming unit. In an exemplary embodiment, a physical unit may also be composed of a plurality of consecutive or non-consecutive physical addresses. In an exemplary embodiment, a physical unit may also be referred to as a Virtual Block (VB). A virtual block may include multiple physical addresses or multiple physical programming units. In an example embodiment, a dummy block may include one or more physical erase units.
The entity units 610 (0) -610 (a) in the storage area 601 are used to store user data (e.g., user data from the host system 11 of fig. 1). For example, the entity units 610 (0) -610 (A) in the storage area 601 may store valid (valid) data and invalid (invalid) data. The physical units 610 (A+1) -610 (B) in the free area 602 do not store data (e.g., valid data). For example, if a physical unit does not store valid data, the physical unit may be associated (or added) to the idle area 602. In addition, the physical cells in the free area 602 (or the physical cells that do not store valid data) may be erased. When writing new data, one or more physical units may be extracted from the spare area 602 to store the new data. In an exemplary embodiment, the free area 602 is also referred to as a free pool (free pool).
The memory management circuit 51 may configure the logic units 612 (0) -612 (C) to map the physical units 610 (0) -610 (A) in the memory area 601. In an exemplary embodiment, each logical unit corresponds to a logical address. For example, a logical address may include one or more logical block addresses (Logical Block Address, LBAs) or other logical management units. In an exemplary embodiment, a logic unit may also correspond to a logic programming unit or be composed of a plurality of consecutive or non-consecutive logic addresses.
It should be noted that a logical unit may be mapped to one or more physical units. If a certain entity unit is currently mapped by a certain logic unit, the data currently stored in the entity unit includes valid data. Otherwise, if a certain entity unit is not mapped by any logic unit, the data stored in the entity unit is invalid.
The memory management circuit 51 may record management data (also referred to as logic-to-entity mapping information) describing a mapping relationship between the logic units and the entity units in at least one logic-to-entity mapping table. When the host system 11 wants to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 51 can access the rewritable nonvolatile memory module 43 according to the information in the logical-to-physical mapping table.
In an exemplary embodiment, the memory storage device 10 supports error correction (error handling), and the data is encoded by the error checking and correcting circuit 54 and then stored in the rewritable nonvolatile memory module 43. When a physical cell (also referred to as a target physical cell) is to be read, the memory management circuit 51 performs a first read operation INITIAL READ, and may first use a predetermined (or previous) read voltage level to read the memory cells in the target physical cell to obtain a verification bit (e.g., bit 0 or bit 1) of the memory cells. The error checking and correction circuit 54 performs a decoding operation according to the verification bits of the memory cells to generate a plurality of decoded bits. These decoded bits may constitute one decoded data (i.e., codeword). In an exemplary embodiment, if the error checking and correcting circuit 54 fails to decode, the error checking and correcting circuit 54 responds to the decoding failure (i.e. the memory cells store too many error bits), and the memory management circuit 51 performs an error correction process.
FIG. 7 is a schematic diagram illustrating a different type of error correction procedure according to an example embodiment of the present invention. Referring to fig. 7, the memory storage device 10 may support, for example, a first error correction process EHP1, a second error correction process EHP2, and a third error correction process EHP3 as shown in fig. 7. When the error checking and correcting circuit 54 cannot successfully decode, the memory management circuit 51 may execute the first error correcting process EHP1, the second error correcting process EHP2 or the third error correcting process EHP3.
In an exemplary embodiment, the memory management circuit 51 may determine the error correction procedure to be performed according to the decoding rate. In an exemplary embodiment, the memory management circuit 51 may determine the error correction procedure to be performed according to the health status information of the rewritable nonvolatile memory module 43. In an exemplary embodiment, the memory management circuit 51 may determine the error correction procedure to be performed according to an instruction from the host system 11. In an exemplary embodiment, the memory management circuit 51 may determine the error correction procedure to be performed according to the actual use situation.
In an example embodiment, the first error correction flow EHP1 includes a plurality of decoding operations that are performed based on a first order. The first error correction process EHP1 may include, for example, but not limited to, a retry read (RETRY READ) operation OP11, an Optimal read voltage level search (Optimal READ LEVEL SEARCH) operation OP12, and an interference compensation read (INTERFERENCE COMPENSATION READ) operation OP13, which are performed according to a first order. In an example embodiment, the second error correction flow EHP2 includes a plurality of decoding operations that are performed based on the second order. The second error correction process EHP2 may include, for example, but is not limited to, an optimum read voltage level search operation OP21 and an interference compensation read operation OP22 performed according to the second order. In an example embodiment, the third error correction process EHP3 includes a plurality of decoding operations that are performed based on a third order. The third error correction process EHP3 may include, for example, but is not limited to, a retry read and disturb compensation read operation OP31 and an optimal read voltage level search operation OP32 performed according to a third order.
In an example embodiment, at least one decoding operation of the plurality of decoding operations included in the first error correction flow EHP1 is the same as at least one decoding operation of the plurality of decoding operations included in the second error correction flow EHP 2. For example, the first error correction process EHP1 and the second error correction process EHP2 both include the same optimum read voltage level searching operations OP12, OP21 and the disturbance compensating read operations OP13, OP22. In an example embodiment, at least one of the plurality of decoding operations included in the first error correction flow EHP1, at least one of the plurality of decoding operations included in the second error correction flow EHP2, and at least one of the plurality of decoding operations included in the third error correction flow EHP3 are the same. For example, the first error correction process EHP1, the second error correction process EHP2 and the third error correction process EHP3 each include the optimum read voltage level searching operations OP12, OP21 and OP32.
In an exemplary embodiment, when the memory management circuit 51 executes the first error correction process EHP1 (or the second error correction process EHP2 and the third error correction process EHP 3), if one of the decoding operations of the first error correction process EHP1 (or the second error correction process EHP2 and the third error correction process EHP 3) is successful and the codeword is obtained, the memory management circuit 51 may end the first error correction process EHP1 (or the second error correction process EHP2 and the third error correction process EHP 3). If all decoding operations in the first error correction process EHP1 (or the second error correction process EHP2 and the third error correction process EHP 3) fail, the memory management circuit 51 obtains a result that decoding cannot be performed, and ends the first error correction process EHP1 (or the second error correction process EHP2 and the third error correction process EHP 3).
In an exemplary embodiment, the retry read operation OP11 may, for example, retrieve another read voltage level from the memory management circuit 51 to read the memory cell of the target physical cell, retrieve the verification bit of the memory cell, and perform the decoding operation according to the retrieved verification bits by the error checking and correction circuit 54. When the error bits are too many, the verification bits of some memory cells in the target physical cell can be changed by adopting another read voltage level to retrieve the verification bits, so that the decoding result of the decoding operation can be changed.
In an exemplary embodiment, the optimum read voltage level searching operations OP12, OP21, OP32 may be, for example, the memory management circuit 51 re-acquiring the read voltage level different from the previous read voltage level to read the memory cell of the target physical cell to re-acquire the verification bit of the memory cell, and the error checking and correcting circuit 54 performs the decoding operation according to the re-acquired verification bits to acquire another data composed of the decoded bits. If the decoding fails again (i.e., the number of error bits of the retrieved plurality of verification bits is too large), another read voltage level is retrieved again by the memory management circuit 51 to attempt decoding until the decoding is successful or the preset number of attempted decoding times has been exceeded.
In an exemplary embodiment, the interference compensation read operations OP13 and OP22 may be, for example, when the memory management circuit 51 re-reads the memory cells of the target physical unit, also read the memory cells of the neighboring physical units that may cause interference to the target physical unit, so as to perform the decoding operation by the verification bits obtained from the memory cells of the target physical unit and the verification bits obtained from the memory cells of the neighboring physical units, so as to improve the success rate of the decoding operation.
In an exemplary embodiment, the retry read and disturbance offset read operations OP31, as the name implies, are a combination of the retry read operation OP11 and the disturbance offset read operations OP13, OP22. The retry read and disturb compensating read operation OP31 may, for example, retrieve another read voltage level from the memory management circuit 51 to read the target physical unit and read the memory cells of the neighboring physical units that may disturb the target physical unit, so as to obtain a plurality of verification bits from the obtained target physical unit and the neighboring physical units, and perform the decoding operation according to the obtained verification bits, thereby improving the success rate of the decoding operation. In another exemplary embodiment, after the error correction procedure is adjusted, the first read operation is performed on the target physical unit, and the disturbance compensation read operations OP13 and OP22 are also performed, that is, the first read operation and the disturbance compensation read operations OP13 and OP22 are combined.
In an example embodiment, the first error correction flow EHP1 includes a first number (e.g., 3) of decoding operations, and the second error correction flow EHP2 includes a second number (e.g., 2) of decoding operations. The first number is greater than the second number. In an example embodiment, the first error correction flow EHP1 includes a first number (e.g., 3) of decoding operations, and the third error correction flow EHP3 includes a third number (e.g., 2) of decoding operations. The first number is greater than the third number.
In an exemplary embodiment, the decoding capability of the first decoding operation (i.e., the optimal read voltage level searching operation OP 21) indicated by the second order is better than the decoding capability of the first decoding operation (i.e., the retry read operation OP 11) indicated by the first order, and a better decoding capability indicates a higher probability of successful decoding. In an example embodiment, the decoding capability of the first decoding operation indicated by the third order (i.e., the retry read and interference compensation read operation OP 31) is better than the decoding capability of the first decoding operation indicated by the second order.
In an exemplary embodiment, the first error correction process EHP1 is a predetermined error correction process. That is, the memory storage device 10 is preset to employ the first error correction flow EHP1. The first error correction flow EHP1 includes a plurality of operations that are performed based on a first order, wherein the first order may be used to indicate a decoding capability (or operation time) of the plurality of operations. For example, the memory management circuit 51 may perform operations with weaker decoding capability according to the first order, and then sequentially perform other operations according to the decoding capability. For example, the memory management circuit 51 may perform operations with shorter operation time according to the first order, and then sequentially perform other operations according to the operation time.
That is, the decoding capability of the retry read operation OP11 is lower than that of the optimum read voltage level search operation OP12, and the decoding capability of the optimum read voltage level search operation OP12 is lower than that of the disturbance compensation read operation OP 13. In other words, the operation time of the retry read operation OP11 is smaller than the operation time of the optimum read voltage level search operation OP12, and the operation time of the optimum read voltage level search operation OP12 is smaller than the operation time of the disturbance compensation read operation OP 13.
In an example embodiment, the memory management circuit 51 may count the first decoding rate of the first error correction process EHP 1. For example, the memory management circuit 51 may periodically count the first decoding rate of the first error correction flow EHP 1. For example, the memory management circuit 51 may count the first decoding rate of the first error correction process EHP1 every time interval. For example, after the rewritable nonvolatile memory module 43 receives a certain number of read command sequences, the memory management circuit 51 may count the first decoding rate of the first error correction process EHP 1. For example, the memory management circuit 51 may set a read count value, and when the read count value reaches the count threshold, the memory management circuit 51 may count the first decoding rate of the first error correction process EHP1 and re-count the read count value. In an example embodiment, the first decoding rate is a success rate of a first decoding operation (i.e., retry read operation OP 11) indicated by the first order.
In an example embodiment, the memory management circuit 51 may switch the first error correction process EHP1 to the second error correction process EHP2 when the first decoding rate is smaller than the first threshold. Specifically, a first decoding rate smaller than the first threshold value indicates that the retry read operation OP11 is insufficient in decoding capability. Therefore, the memory management circuit 51 can switch the first error correction process EHP1 to the second error correction process EHP2 having the first decoding operation (i.e., the optimal read voltage level searching operation OP 21) with relatively strong decoding capability, so as to reduce the decoding time.
In an example embodiment, the memory management circuit 51 may count the second decoding rate of the second error correction process EHP 2. For example, the memory management circuit 51 may periodically count the second decoding rate of the second error correction flow EHP 2. For example, the memory management circuit 51 may count the second decoding rate of the second error correction process EHP2 every time interval. For example, after the rewritable nonvolatile memory module 43 receives a certain number of read command sequences, the memory management circuit 51 may count the second decoding rate of the second error correction process EHP 2. For example, the memory management circuit 51 may set a read count value, and when the read count value reaches the count threshold, the memory management circuit 51 may count the second decoding rate of the second error correction process EHP2 and re-count the read count value. In an exemplary embodiment, the second decoding rate is the success rate of each decoding operation (i.e., the best read voltage level searching operation OP21 and the disturbance compensating read operation OP 22) in the second error correction flow EHP 2. In another exemplary embodiment, the second decoding rate is the success rate of the first decoding operation (i.e., the best read voltage level searching operation OP 21) indicated by the second order.
In an example embodiment, the memory management circuit 51 may switch the second error correction process EHP2 to the first error correction process EHP1 when the second decoding rate is not less than the second threshold. That is, when the success rate of the optimum read voltage level searching operation OP21 and/or the success rate of the disturbance compensating read operation OP22 is not less than the second threshold, the memory management circuit 51 can restore the second error correction process EHP2 to the preset first error correction process EHP1. Specifically, the second decoding rate not being smaller than the second threshold value indicates that the success rate of reading the target entity unit from the rewritable nonvolatile memory module 43 is high. Therefore, the memory management circuit 51 may restore the second error correction flow EHP2 to the first error correction flow EHP1 of the first decoding operation (i.e., the retry read operation OP 11) having a relatively short operation time, so as to reduce the decoding time.
In an example embodiment, the memory management circuit 51 may switch the second error correction process EHP2 to the third error correction process EHP3 when the second decoding rate is smaller than the third threshold. Specifically, the second decoding rate being smaller than the third threshold value indicates that the decoding capability of the optimum read voltage level searching operation OP21 and the interference compensating operation OP22 is insufficient. Therefore, the memory management circuit 51 can switch the second error correction process EHP2 to the third error correction process EHP3 having the first decoding operation (i.e. the retry read and disturbance compensation read operation OP 31) with relatively strong decoding capability, so as to reduce the decoding time.
In an example embodiment, the memory management circuit 51 may count a third decoding rate of the third error correction process EHP 3. Details of the implementation of the third decoding rate statistics may refer to the foregoing implementation of the first decoding rate statistics and the second decoding rate statistics, and will not be repeated herein. In an exemplary embodiment, the third decoding rate is the success rate of each decoding operation (i.e., the retry read and disturb compensating read operation OP31 and the best read voltage level searching operation OP 32) in the third error correction flow EHP 3. In another example embodiment, the third decoding rate is the success rate of the first decoding operation (i.e., the retry read and interference compensation read operation OP 31) indicated by the third order.
In an example embodiment, when the third decoding rate is not less than the fourth threshold, the memory management circuit 51 may switch the third error correction process EHP3 to the second error correction process EHP2 (or the first error correction process EHP 1). That is, when the success rate of the retry read and disturbance compensation read operation OP31 and/or the success rate of the optimum read voltage level search operation OP32 is not less than the fourth threshold, the memory management circuit 51 may switch the third error correction process EHP3 to the second error correction process EHP2 (or the first error correction process EHP 1) having the first decoding operation (i.e., the optimum read voltage level search operation OP21 or the retry read operation OP 11) with the relatively shorter operation time, so as to reduce the decoding time. In another exemplary embodiment, the fourth decoding rate of the initial read operation may also be counted, and details of the counting of the fourth decoding rate may be referred to the foregoing counting of the first decoding rate and the counting of the second decoding rate, which are not repeated here. In an exemplary embodiment, the fourth decoding rate is a success rate of a plurality of initial read operations, wherein each read instruction sequence has one initial read operation. The memory management circuit 51 may switch the error correction procedure according to the fourth decoding rate, for example, when the fourth decoding rate is lower, the error correction procedure with relatively stronger decoding capability may be changed, for example, when the fourth decoding rate is higher, the error correction procedure with relatively weaker decoding capability may be changed, and the details of the implementation of the switching the error correction procedure may be referred to the above, so that they will not be repeated here.
In an example embodiment, the memory management circuit 51 may obtain health information of the rewritable nonvolatile memory module 43. The health status information may include, but is not limited to, at least one of a temperature, a read count, an erase count, a write count, a fourth decoding rate, and a number of error bits of the rewritable nonvolatile memory module 43. Next, the memory management circuit 51 may employ the first error correction process EHP1, the second error correction process EHP2 or the third error correction process EHP3 according to the health status information. For example, the memory management circuit 51 may determine that the rewritable nonvolatile memory module 43 is good according to the health status information, and accordingly employ the first error correction process EHP1. For example, the memory management circuit 51 may determine that the rewritable nonvolatile memory module 43 is medium according to the health status information, and accordingly employ the second error correction procedure EHP2. For example, the memory management circuit 51 may determine that the rewritable nonvolatile memory module 43 is bad according to the health status information, and accordingly employ the third error correction procedure EHP3.
According to the above, the memory management circuit 51 can select an appropriate error correction procedure according to the health status information to enhance the performance of the memory storage device 10.
FIG. 8 is a flowchart of an error correction method according to an exemplary embodiment of the present invention. Referring to fig. 8, in step S801, a first decoding rate of the first error correction flow EHP1 is counted. In step S802, it is determined whether the first decoding rate is less than a first threshold. If the first decoding rate is not less than the first threshold, the process returns to step S801. If the first decoding rate is smaller than the first threshold, step S803 is continuously performed. In step S803, the first error correction flow EHP1 is switched to the second error correction flow EHP2. In step S804, a second decoding rate of the second error correction flow EHP2 is counted. In step S805, it is determined whether the second decoding rate is less than a second threshold. If the second decoding rate is smaller than the second threshold, the process returns to step S804. If the second decoding rate is not less than the second threshold, step S806 is performed successively. In step S806, the second error correction flow EHP2 is switched to the first error correction flow EHP1. After the execution of step S806, the process may return to step S801 to re-execute the error correction method of fig. 8.
FIG. 9 is a flowchart of an error correction method according to an exemplary embodiment of the present invention. Referring to fig. 9, in step S901, health status information of the rewritable nonvolatile memory module 43 is obtained. In step S902, the first error correction flow EHP1, the second error correction flow EHP2, or the third error correction flow EHP3 is employed according to the health status information.
FIG. 10 is a flowchart of an error correction method according to an exemplary embodiment of the present invention. Referring to fig. 10, in step S1001, a first decoding rate of a first error correction flow EHP1 is counted, wherein the first error correction flow EHP1 includes a plurality of decoding operations performed based on a first order. In step S1002, responsive to the first decoding rate being less than the first threshold, the first error correction flow EHP1 is switched to a second error correction flow EHP2, wherein the second error correction flow EHP2 includes a plurality of decoding operations that are performed based on a second order, wherein a decoding capability of a first decoding operation indicated by the second order is superior to a decoding capability of a first decoding operation indicated by the first order.
The steps in fig. 8 to 10 are described in detail above and will not be repeated here. It should be noted that each step in fig. 8 to 10 may be implemented as a plurality of program codes or circuits, which is not limited by the present invention. In addition, the methods of fig. 8 to 10 may be used with the above exemplary embodiments, or may be used alone, and the present invention is not limited thereto.
In summary, the error correction method, the memory storage device and the memory control circuit unit according to the embodiments of the present invention provide a plurality of different error correction processes, and can select a proper error correction process according to the decoding rate of the current error correction process or the health status information of the rewritable nonvolatile memory module, so as to reduce the average decoding time, thereby improving the performance of the memory storage device.
It should be noted that the above embodiments are merely for illustrating the technical solution of the present invention and not for limiting the same, and although the present invention has been described in detail with reference to the above embodiments, it should be understood by those skilled in the art that the technical solution described in the above embodiments may be modified or some or all of the technical features may be equivalently replaced, and these modifications or substitutions do not make the essence of the corresponding technical solution deviate from the scope of the technical solution of the embodiments of the present invention.
Claims (27)
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